; -------------------------------------------------------------------------------- ; @Title: LS10xx On-Chip Peripherals ; @Props: Released ; @Author: SEB, MKK, GAJ, ADP, KOL, MRO, BCA, DPR, DOR, STY, JUS, DAM ; @Changelog: 2016-09-06 ADP ; 2018-01-12 KOL ; 2018-07-27 BCA ; 2019-06-13 KMB ; 2020-03-06 DAM ; @Manufacturer: FREESCALE - Freescale Semiconductor, Inc. ; @Doc: LS1043A Rev C Reference Manual.pdf (Rev. C, 2015-07) ; LS1046A Reference Manual_RevA (Rev. A, 2016-02) ; LS1088A Reference Manual_revB (Rev. B, 2016-01) ; LS1043A_ReferenceManual_rev3.pdf (Rev. 3, 2017-02) ; LS1043A_SecurityReferenceManuel_rev1.pdf (Rev. 1, 2017-07) ; QEIWRM.pdf (Rev. 8, 2016-05) ; LS1043ADPAARM.pdf (Rev. 0, 2016-04) ; 201710LS1046ARM.pdf (Rev. 1, 2017-10) ; 201705LS1046ASECRM.pdf (Rev. 0, 2017-05) ; 201703LS1046ADPAARM.pdf (Rev. 0, 2017-10) ; T4240RM DPAAAP RevD.pdf (Rev. D, 2013-10) ; LS1012A Reference Manual_rev0.pdf (Rev. 0, 2017-01) ; LS1012A_SecurityReferenceManual_rev1.pdf (Rev. 1, 2017-07) ; LS1046ASECRM.pdf (Rev. 0, 2017-05) ; LS1088A_DataSheet.pdf (Rev. 1, 2019-02) ; LS1046ARM.pdf (Rev. 2, 2018-11) ; LS1046ADPAARMAD.pdf (Rev. 0.1, 2018-01) ; LS1012ARM.pdf (Rev. 2, 2019-02) ; LS1012A.pdf (Rev. 2, 2019-01) ; LS1043A.pdf (Rev. 4.1 2019-08) ; LS1043A_Auto.pdf (Rev. 2, 2019-08) ; LS1043ARM.pdf (Rev. 5, 2019-04) ; LS1088ARM.pdf (Rev. 0, 2018-02) ; QEIWRM.pdf (Rev. 9, 2018-05) ; LS1046A.pdf (Rev. 3, 2019-07) ; @Core: Cortex-A72, Cortex-A53 ; @Chip: LS1046A, LS1026A, LS1043A, LS1023A, LS1088A, LS1048A, LS1084A, LS1044A ; LS1012A ; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perls10xx.per 17622 2024-03-12 15:04:23Z kwisniewski $ ; Known problems: ; MODULE REGISTER DESCRIPTION ; QuadSPI No base address for AHB Bus Registers ; RST CRSTSR Data sheet indicates there are 12 registers of this type for LS1088, even though ; this MCU has only 8 cores (1 reg per core) ; I2C Module is not described in LS1046A Reference Manual_revA.pdf, however it appears in memory map ; SERDES MDIO registers MDIO registers use relative addressing, therefore they have not been implemented yet. ; Implemented as they are at ls208x family ; qDMA Memory map absolute address and submodules offsets are not consistent. ; Module might not work properly for certain MCUs. For LS10?6* implemented base address from address map ; instead of base from qdma memory map ; CLK CLKCCSR Incorrect bits description (201710LS1046ARM.pdf) ; TZC-380 REGION_ATTRIBUTES_0/A Wrong/missleading description for "A" incrementation rule (LS1012A) ; SCFG G0MSIIR/G0MSIRN Fields in G0MSIIR count MSIR0-3 but G0MSIRN register count MSIR1-4 ; QUICC CEISER Access and description says that all fields are W1C but Figure 4-10 shows it RO ; QUICC CMXUCR1 Location of bits HBM1 and HBM2 are not described in LS10?3 Refference Manual ; SFP All Newest revisions of documentations contain only reference to User Guide which couldn't be found config 16. 8. sif (cpuis("LS1012*")||cpuis("LS1023*")||cpuis("LS1043*")) tree "Core Registers (Cortex-A53)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.long 0x0 "MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field" newline bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.quad SPR:0x30006++0x0 line.long 0x0 "REVIDR_EL1,Revision ID Register" rgroup.quad SPR:0x30014++0x00 line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30015++0x00 line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad SPR:0x30016++0x00 line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad SPR:0x30017++0x00 line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" endif rgroup.quad SPR:0x30020++0x00 line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad SPR:0x30021++0x00 line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30022++0x00 line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30023++0x00 line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30024++0x00 line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30025++0x00 line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" endif rgroup.quad SPR:0x30010++0x00 line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30011++0x00 line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" endif if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" endif rgroup.quad SPR:0x30013++0x00 line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad SPR:0x31007++0x00 line.long 0x00 "AIDR_EL1,Auxiliary ID Register" rgroup.quad SPR:0x33007++0x00 line.long 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad SPR:0x30100++0x0 line.long 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x34100++0x0 line.long 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x36100++0x0 line.long 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad SPR:0x30101++0x0 line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad SPR:0x34101++0x0 line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x30102++0x00 line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..." bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped" group.quad SPR:0x36110++0x0 line.long 0x0 "SCR_EL3,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (CORENAME()=="CORTEXA57") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif elif (CORENAME()=="CORTEXA53") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External," newline hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif endif tree.end newline if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad SPR:0x30C10++0x00 line.long 0x00 "ISR_EL1,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad SPR:0x36C02++0x00 line.long 0x00 "RMR_EL3,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]" endif group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad SPR:0x34300++0x00 line.long 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif rgroup.quad SPR:0x30510++0x00 line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" rgroup.quad SPR:0x34510++0x00 line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" rgroup.quad SPR:0x36510++0x00 line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" rgroup.quad SPR:0x30511++0x00 line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" rgroup.quad SPR:0x34511++0x00 line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" rgroup.quad SPR:0x36511++0x00 line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" rgroup.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" rgroup.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" rgroup.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad SPR:0x30D01++0x00 line.long 0x0 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad SPR:0x34000++0x0 line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register" if (CORENAME()=="CORTEXA57") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" endif group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" endif group.quad SPR:0x34112++0x00 line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x36131++0x00 line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad SPR:0x36112++0x00 line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x34113++0x00 line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" rgroup.quad SPR:0x34117++0x00 line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..." bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif group.quad SPR:0x32000++0x0 line.long 0x0 "CSSELR_EL1,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..." endif tree "Level 1 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x30F10++0x00 line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad SPR:0x30F11++0x00 line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad SPR:0x30F12++0x00 line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad SPR:0x30F13++0x00 line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad SPR:0x30F00++0x00 line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad SPR:0x30F01++0x00 line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad SPR:0x30F02++0x00 line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad SPR:0x30F03++0x00 line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" newline bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" newline bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" newline bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" newline bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" newline bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" endif if (CORENAME()=="CORTEXA57") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" endif tree.end tree "Level 2 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..." bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" newline bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" newline bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" newline bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" newline bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3" bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled" newline bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.quad SPR:0x339C0++0x00 line.long 0x0 "PMCR_EL0,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad SPR:0x339C1++0x00 line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad SPR:0x339C2++0x00 line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad SPR:0x339C3++0x00 line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad SPR:0x339C4++0x00 line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" newline bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" newline bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" newline bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" newline bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" newline bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad SPR:0x339C5++0x00 line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" newline bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" newline bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" endif rgroup.quad SPR:0x339C7++0x0 line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad SPR:0x339D1++0x00 line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad SPR:0x339D2++0x00 line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad SPR:0x339E0++0x00 line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad SPR:0x309E1++0x00 line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad SPR:0x309E2++0x00 line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad SPR:0x339E3++0x00 line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad SPR:(0x33E80+0x0)++0x00 line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad SPR:(0x33EC0+0x0)++0x00 line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x1)++0x00 line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad SPR:(0x33EC0+0x1)++0x00 line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x2)++0x00 line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad SPR:(0x33EC0+0x2)++0x00 line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x3)++0x00 line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad SPR:(0x33EC0+0x3)++0x00 line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x4)++0x00 line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad SPR:(0x33EC0+0x4)++0x00 line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x5)++0x00 line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad SPR:(0x33EC0+0x5)++0x00 line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:0x33EF7++0x00 line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad SPR:0x33E00++0x00 line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad SPR:0x30E10++0x00 line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x33E20++0x00 line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad SPR:0x33E21++0x00 line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad SPR:0x33E30++0x00 line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad SPR:0x33E31++0x00 line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad SPR:0x34E10++0x00 line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x34E20++0x00 line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad SPR:0x34E21++0x00 line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad SPR:0x37E20++0x00 line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad SPR:0x37E21++0x00 line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad SPR:0x30CC6++0x00 line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x30CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x36CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad SPR:0x30460++0x00 line.long 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad SPR:0x30CB3++0x00 line.long 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad SPR:0x30CC5++0x00 line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x34C95++0x00 line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x36CC5++0x00 line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad SPR:0x34C80++0x00 line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34C90++0x00 line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" endif tree.end newline rgroup.quad SPR:0x34CB3++0x00 line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad SPR:0x34CB5++0x00 line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad SPR:0x34CB0++0x00 line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad SPR:0x34CB2++0x00 line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad SPR:0x34CB7++0x00 line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad SPR:0x34C94++0x00 line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad SPR:0x34CB1++0x00 line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad SPR:0x23010++0x00 line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad SPR:0x20020++0x00 line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad SPR:0x24070++0x00 line.long 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad SPR:0x20002++0x00 line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20022++0x00 line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled" group.quad SPR:0x20032++0x00 line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20062++0x00 line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad SPR:0x20104++0x00 line.long 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad SPR:0x20114++0x00 line.long 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad SPR:0x20134++0x00 line.long 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad SPR:0x20144++0x00 line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad SPR:0x20786++0x00 line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad SPR:0x20796++0x00 line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad SPR:0x207E6++0x00 line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" group.quad SPR:0x33450++0x00 line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x0)++0x0 line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x10)++0x0 line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x20)++0x0 line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x30)++0x0 line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x40)++0x0 line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x50)++0x0 line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0" line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1" line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2" line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3" line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if corename()=="CORTEXA57" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" endif if corename()=="CORTEXA57" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4" elif corename()=="CORTEXA53" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if corename()=="CORTEXA57" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif group.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" if corename()=="CORTEXA57" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" elif corename()=="CORTEXA53" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" newline bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" newline bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" newline bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" newline bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" newline bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" newline bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" endif if corename()=="CORTEXA57" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes" newline bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" elif corename()=="CORTEXA53" group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full" endif group.long c15:0x0011++0x0 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" if corename()=="CORTEXA57" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" elif corename()=="CORTEXA53" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" endif rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif endif if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if corename()=="CORTEXA57" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]" elif corename()=="CORTEXA53" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]" endif group.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" if corename()=="CORTEXA57" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) // MPIDR[31]==1 case is missing here for TTBR0 and TTBR1 group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" endif if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif endif if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" else group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline endif tree.end newline if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" if corename()=="CORTEXA57" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" elif corename()=="CORTEXA53" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" endif group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..." newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..." newline hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13" bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT" newline bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if corename()=="CORTEXA57" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." endif rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" if corename()=="CORTEXA57" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" elif corename()=="CORTEXA53" rgroup.long c15:0x300F++0x00 line.long 0x00 "CDBGDR0,Cache Debug Data Register 0" rgroup.long c15:0x310F++0x00 line.long 0x00 "CDBGDR1,Cache Debug Data Register 1" rgroup.long c15:0x320F++0x00 line.long 0x00 "CDBGDR2,Cache Debug Data Register 2" rgroup.long c15:0x330F++0x00 line.long 0x00 "CDBGDR3,Cache Debug Data Register 3" wgroup.long c15:0x302F++0x00 line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register" endif tree.end tree "Level 2 memory system" if corename()=="CORTEXA57" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" newline rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present" newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" newline bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" newline bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" newline bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" newline bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif corename()=="CORTEXA53" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" newline rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled" eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled" eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled" eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled" eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow" eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow" eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow" eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow" newline eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow" eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow" eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow" eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow" eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow" newline eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow" eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow" eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow" eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow" eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow" newline eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow" eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow" eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow" eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow" eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow" newline eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow" eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow" eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow" eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow" eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow" newline eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" newline eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" newline bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" newline bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" newline bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" newline bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" newline bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.l(c15:0x4CC))&0x3800)==0x00) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" elif (((per.l(c15:0x4CC))&0x3800)==0x800) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" if corename()=="CORTEXA53" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" endif group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA57" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" elif corename()=="CORTEXA53" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" newline bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" group.long c14:0x0141++0x0 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" group.long c14:0x0151++0x0 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-400)" width 17. width 17. base AD:0x01410000 tree "Distributor Interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(AD:0x01410000) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" if PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0080) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)" else group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0084)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0088)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x008C)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0090)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0094)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0098)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x009C)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A0)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A4)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A8)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00AC)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B0)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B4)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B8)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00BC)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C0)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C4)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C8)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00CC)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D0)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D4)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D8)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00DC)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E0)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x0E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E4)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E8)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00EC)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F0)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x0F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F4)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F8)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00FC)) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else rgroup.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else rgroup.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Not pending,Pending" else rgroup.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(AD:0x01410000+0x08))&0xFF000000)==(0x0000000||0x1000000)) rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x037C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else rgroup.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" rgroup.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" rgroup.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" rgroup.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" rgroup.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" rgroup.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" rgroup.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(AD:0x01410000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" rgroup.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else rgroup.long 0x0D60++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xFD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" rgroup.byte 0xFD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" rgroup.byte 0xFDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end width 0x0B base AD:0x1420000 width 17. tree "CPU Interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " else if PER.ADDRESS.isSECUREEX(AD:0x1420000) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Secure access)" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " endif endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(AD:0x1420000+0x0008) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif hgroup.long 0x0020++0x003 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) wgroup.long 0x0024++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" else hgroup.long 0x0024++0x03 hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hgroup.long 0x0028++0x03 hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" endif group.long 0x00D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) group.long 0x00E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" else hgroup.long 0x00E0++0x03 hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end sif CPU.FEATURE(hypervisor) base AD:0x1440000 width 12. tree "Virtual CPU Control Interface" group.long 0x0000++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x008++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1" bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1" textline " " bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1" bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1" bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1" rgroup.long 0x0010++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt" rgroup.long 0x020++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x0030++0x03 line.long 0x00 "GICH_ELSR0,Empty List register Status Register" bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty" bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty" bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty" textline " " bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty" group.long 0x00F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" if (((per.l(AD:0x1440000+0x100))&0x80000000)==0x80000000) group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x104))&0x80000000)==0x80000000) group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x108))&0x80000000)==0x80000000) group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x10C))&0x80000000)==0x80000000) group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif tree.end base AD:0x1460000 width 12. tree "Virtual CPU Interface" group.long 0x0000++0x03 line.long 0x00 "GICV_CTLR,Virtual Machine Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs" textline " " bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x0004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x000C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICV_EOIR,VM End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x001C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x0020++0x03 hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" in wgroup.long 0x0024++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x00D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" rgroup.long 0x00FC++0x03 line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end endif width 0x0B tree.end tree.end elif (cpuis("LS1026*")||cpuis("LS1046*")) tree "Core Registers (Cortex-A72)" AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.quad spr:0x33001++0x0 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" rgroup.quad spr:0x30006++0x0 line.quad 0x00 "REVIDR_EL1,Revision ID Register" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,2 levels,?..." bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,ID_MMFR4_EL1" bitfld.quad 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2, SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1, SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,Support for the GIC System register interface" "Not supported,GICv3 supported,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,Implemented,?..." rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,PMUv3,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug v8-A,?..." rgroup.quad spr:0x339C6++0x0 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "DA,Bus access" "Not implemented,Implemented" newline bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.quad 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Thread Pointer/ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Thread Pointer/ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Thread Pointer/ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Thread Pointer/ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Thread Pointer/ID Register" tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enables snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.quad spr:0x34101++0x0 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x36101++0x0 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register" bitfld.quad 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.quad 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.quad 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap EL0/EL1,Trap EL0,Trap EL0/EL1,No trap" group.quad spr:0x36110++0x0 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort and SError Interrupt Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 2. "FIQ,Physical FIQ Routing" "Not to EL3,To EL3" bitfld.quad 0x00 1. "IRQ,Physical IRQ Routing" "Not to EL3,To EL3" newline bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers 1 (EL3)" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.quad 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.quad 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.quad 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.quad.tbyte 0x00 0.--23. 1. "IS,Additional information about the SError interrupt" elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif tree.end newline if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Base address of the exception vectors for exceptions taken in this exception level" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.quad 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.quad 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID registers" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID registers" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID registers" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID registers" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.quad 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianess" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,Reserved,Reserved" newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,Reserved,Reserved,Reserved,Reserved,Reserved" newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,16 KB,Reserved" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associatedwith translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memoryregion addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.quad 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.quad 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device,?..." newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000))) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--43. 0x1000 "PA[43:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x1000 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st level,Synchronous parity error on memory access on translation table walk/2nd level,Synchronous parity error on memory access on translation table walk/3rd level,Reserved,Alignment fault,Debug event,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" tree.end newline group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad spr:0x34000++0x0 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.quad 0x00 28. "TDZ,Traps DC ZVA instruction" "Disabled,Enabled" bitfld.quad 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.quad 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.quad 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.quad 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort" "Not aborted,Aborted" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" newline bitfld.quad 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.quad 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.quad 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.quad 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.quad 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpointregisters disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.quad 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 16. "TTEE,Trap T32EE" "Disabled,Enabled" bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" newline bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.quad 0x00 4. "T4,Trap to Hypervisor mode Non-secure priv 4" "No effect,Trap" newline bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" newline bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (((per.q(spr:0x34212))&0xC000)==0x0000) group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 2,Level 1,Level 0,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,16 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Outer Shareable,Inner Shareable,?..." newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Normal/Non-cacheable,Normal/Write-Back Write-Allocate,Normal/Write-Through,Normal/Write-Back no Write-Allocate" bitfld.quad 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "Level 3,Level 2,Level 1,?..." newline bitfld.quad 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting intermediate physical address" tree.end tree "Cache Control and Configuration" rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,CTR_EL0" bitfld.quad 0x0 29.--31. "FORMAT,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." group.quad spr:0x32000++0x0 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" rgroup.quad spr:0x31001++0x0 line.quad 0x00 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.quad 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.quad 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.quad 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.quad 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." rgroup.quad spr:0x31000++0x0 line.quad 0x00 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32bytes,64 bytes,128 bytes,?..." tree "Level 1 memory system" group.quad spr:0x30F10++0x00 line.quad 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad spr:0x30F11++0x00 line.quad 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad spr:0x30F12++0x00 line.quad 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad spr:0x30F13++0x00 line.quad 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad spr:0x30F14++0x00 line.quad 0x00 "DL1DATA4_EL1,Data L1 Data 3 Register" group.quad spr:0x30F00++0x00 line.quad 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad spr:0x30F01++0x00 line.quad 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad spr:0x30F02++0x00 line.quad 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad spr:0x30F03++0x00 line.quad 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" tree.end tree "Level 2 memory system" group.quad spr:0x31B02++0x0 line.quad 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.quad 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.quad 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.quad 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.quad 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.quad 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.quad 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.quad 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.quad 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.quad 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.quad 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.quad 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.quad 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.quad 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.quad spr:0x31B03++0x0 line.quad 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.quad 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.quad 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.quad 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad spr:0x31F00++0x00 line.quad 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.quad 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.quad 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.quad 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.quad 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.quad 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.quad 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.quad 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.quad 0x00 23. "DACPMUWLUT,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.quad 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.quad 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.quad 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.quad 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.quad 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.quad 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.quad 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.quad 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.quad 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.quad 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.quad 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.quad 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.quad 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.quad 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.quad 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.quad 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.quad 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.quad 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.quad 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.quad 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitor Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.quad 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register " bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR enable" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.quad 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register" bitfld.quad 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.quad 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.quad 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.quad 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.quad 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.quad 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,%d..." tree.open "Common Event Identification Registers" group.quad spr:0x339c6++0x00 line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.quad 0x00 30. "CH,Chain" "Not implemented,Implemented" newline bitfld.quad 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.quad 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.quad 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.quad 0x00 25. "BA,Bus access" "Not implemented,Implemented" bitfld.quad 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.quad 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.quad 0x00 19. "MA,Data memory access" "Not implemented,Implemented" bitfld.quad 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.quad 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.quad 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.quad 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.quad 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.quad 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.quad 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.quad 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.quad 0x00 9. "ET,Exception taken" "Not implemented,Implemented" newline bitfld.quad 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.quad 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.quad 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.quad 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" newline bitfld.quad 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad spr:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad spr:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad spr:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad spr:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad spr:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad spr:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad spr:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.quad 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.quad 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.quad 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" bitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,Supported" bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interruptidentifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,Special values" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1" bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1" bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed" bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.quad 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Register 0-0" rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((per.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad spr:0x34C94++0x00 line.quad 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" hexmask.quad.long 0x00 32.--63. 1. "HW,HighWord - Write/read DTRRX/DTRTX value without changing RXfull/TXfull" hexmask.quad.long 0x00 0.--31. 1. "LW,LowWord - Write/read DTRTX/DTRRX value without changing TXfull/RXfull" hgroup.quad spr:0x23050++0x00 hide.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" in wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad spr:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" if (((per.q(spr:0x20114)&0x02)==0x00)) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" newline bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" newline bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "Disabled,Enabled" newline bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--43. 0x10 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.q(spr:0x207e6))&0xAA)==0xAA) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA8) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0xA2) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0xA0) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x8A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x88) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x82) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x80) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x2A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x28) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x22) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x20) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x0A) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x08) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.q(spr:0x207e6))&0xAA)==0x02) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.q(spr:0x207e6))&0xAA)==0x00) rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x0)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x0))&0x400000)==0x400000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0x800000)==0x800000) group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x0 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 1" if (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x10)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x10))&0x400000)==0x400000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0x800000)==0x800000) group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x0 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 2" if (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x20)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x20))&0x400000)==0x400000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0x800000)==0x800000) group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x0 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 3" if (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x30)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x30))&0x400000)==0x400000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0x800000)==0x800000) group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x0 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 4" if (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x40)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x40))&0x400000)==0x400000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0x800000)==0x800000) group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x0 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 5" if (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x000000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x800000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" elif (((per.q(spr:(0x20005+0x50)))&0xA00000)==0x200000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" else group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif if (((per.q(spr:0x20005+0x50))&0x400000)==0x400000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,Reserved,Reserved" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0x800000)==0x800000) group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Reserved" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x0 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.quad 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.quad 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.quad 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" endif tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" bitfld.long 0x00 0. "NU,Not Unified. Indicates whether the implementation has a unified TLB" "Unified," rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largery independent,Very interdependent" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,ACTLR/AIFSR/ADFSR,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Not supported,Supported,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline rgroup.long c15:0x6C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "CH,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BC,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "TW,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "IS,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "ME,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "BA,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "DC2W,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "DC2R,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "DC2A,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "DC1W,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "IC1A,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "MA,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "BP,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "CC,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "BM,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "UL,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "BR,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "BI,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "PW,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CW,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "ER,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "ET,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "IA,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "ST,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "LD,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "DT1R,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "DC1A,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "DC1R,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "IT1R,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "IC1R,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "SI,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPMRCGEA,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 62. "FPNMRCGEA,Force processor non-memory-system RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 61. "FPDIERCGEA,Force processor Decode and Integer Execute idle RCG enables active" "Not forced,Forced" bitfld.quad 0x00 60. "FPDRCGEA,Force processor Dispatch idle RCG enables active" "Not forced,Forced" newline bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/st and DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" newline bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" newline bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "ECDAFEMP,Enable contention detection and fast exclusive monitor path" "Disabled,Enabled" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" newline bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" newline bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 46. "DML1DTLBM,Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss" "No,Yes" newline bitfld.quad 0x00 45. "Dl1DCWT,Disable L1-DCache way tracker" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 43. "DVABHWPREF,Disable the Load/Store hardware prefetcher from using VA to cross page boundaries" "No,Yes" bitfld.quad 0x00 42. "DPREFREQRUT,Disable prefetch requests from ReadUnique transactions" "No,Yes" newline bitfld.quad 0x00 41. "ESHWSHAEP,Enable snoop hazard while waiting for second half of atomic exclusive pair" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 requests,1 request,2 requests,3 requests" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "16 requests,18 requests,20 requests,22 requests" bitfld.quad 0x00 6. "SMPEN,Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the first memory error" group.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 28. "TRCDIS,Disable CP14 access to trace registers" "No," newline bitfld.long 0x00 22.--23. "CP11,Coprocesor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" group.long c15:0x0011++0x00 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" rgroup.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" rgroup.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External abort type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status bits" "Address size/0th level,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Short,Long" newline bitfld.long 0x00 0.--3. 10. "FS[3:0],Fault Status bits" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity/on memory access,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[43:32],Periphbase[43:32]" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x00 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,ThumbEE Enable" "Not implemented," bitfld.long 0x00 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x02)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0002))&0x02)==0x00)) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB0,Translation table base 0 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x02)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base 1 Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" newline bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0102))&0x02)==0x00)) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base 1 address" bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base 0 address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base 0 address" endif if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR0/TTBR1 ASID field" "TTBR0,TTBR1" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Outer Non-cacheable,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0, ,Inner cacheability attribute, Normal memory" "Inner Non-cacheable,Inner Write-Back Write-Allocate Cacheable,Inner Write-Through Cacheable,Inner Write-Back no Write-Allocate Cacheable" hexmask.long.byte 0x00 0.--2. 0x1 "T0SZ, ,Size offset of the memory region addressed by HTTBR" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" bitfld.long 0x00 7. "SH,Shareable attribute for the region" "No,Yes" newline bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Strongly-ordered,Reserved,Device,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" newline bitfld.long 0x00 1. "SS,Supersection" "Disabled,Enabled" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline newline newline bitfld.long 0x00 6. "FS[5],Fault status bit - External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 1.--5. "FS[0:4],Fault status bit - Fault source" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external abort/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external abort on translation table walk/1st level,Permission/1st level,Sync. external abort on translation table walk/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external abort,Reserved,Async. parity error on memory access,Sync. parity error on memory access,Reserved,Reserved,Sync. parity error on translation table walk/1st level,Reserved,Sync. parity error on translation table walk/2nd level,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address/0th level,Address/1st level,Address/2nd level,Address/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. ext. abort,Async. external abort,Reserved,Reserved,Sync. ext. abort/0th level,Sync. ext. abort/1st level,Sync. ext. abort/2nd level,Sync. ext. abort/3rd level,Sync. parity error on memory access,Async. parity error on memory access,Reserved,Reserved,Reserved,Sync. parity error on translation table walk/0th level,Sync. parity error on translation table walk/1st level,Sync. parity error on translation table walk/2nd level,Sync. parity error on translation table walk/3rd level,Reserved,Alignment,Debug event,?..." newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)==0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)==0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)==0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x002A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x002A))&0xF00000)!=0x000000)&&(((per.l(c15:0x002A))&0xF000)!=0x0000)&&(((per.l(c15:0x002A))&0xF0)!=0x00)) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)==0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)==0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)==0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x012A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x012A))&0xF00000)!=0x000000)&&(((per.l(c15:0x012A))&0xF000)!=0x0000)&&(((per.l(c15:0x012A))&0xF0)!=0x00)) group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x012A++0x00 hide.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)==0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)==0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)==0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x402A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x402A))&0xF00000)!=0x000000)&&(((per.l(c15:0x402A))&0xF000)!=0x0000)&&(((per.l(c15:0x402A))&0xF0)!=0x00)) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x402A++0x00 hide.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" endif if ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)==0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)==0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)==0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)==0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "nGnRnE,,,,nGnRE,,,,nGRE,,,,GRE,?..." newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" elif ((((per.l(c15:0x0202))&0x80000000)==0x0x80000000)&&(((per.l(c15:0x412A))&0xF0000000)!=0x00000000)&&(((per.l(c15:0x412A))&0xF00000)!=0x000000)&&(((per.l(c15:0x412A))&0xF000)!=0x0000)&&(((per.l(c15:0x412A))&0xF0)!=0x00)) group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR3[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0[7:4],The memory attribute encoding for an AttrIndx[2:0] bits [7:4]" "Device,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Write-through transient,Normal/Outer Non-Cacheable,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-back transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-through non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient,Normal/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0[3:0],The memory attribute encoding for an AttrIndx[2:0] bits [3:0]" "Device,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Write-through transient,Normal/Inner Non-Cacheable,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-back transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-through non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient,Normal/Inner Write-back non-transient" else hgroup.long c15:0x412A++0x00 hide.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x00 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Non-shareable,Shareable" bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Non-shareable,Shareable" newline bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Non-shareable,Shareable" bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Non-shareable,Shareable" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x00 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-back allocate,Write-through,Write-back no allocate" newline group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" else hgroup.long c15:0x002A++0x00 hide.long 0x00 "PRRR,Primary Region Remap Register" hgroup.long c15:0x012A++0x00 hide.long 0x00 "NMRR,Normal Memory Remap Register" group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,AArch32 CP15 barrier enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU enable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR access control" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x00 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x00 20. "TTA,Trap Trace Access" "Not supported," newline bitfld.long 0x00 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" newline bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" newline bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" newline bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if (((per.l(c15:0x4202))&0x07)==0x00) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x01) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x02) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x03) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x04) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x05) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4202))&0x07)==0x06) group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" if (((per.l(c15:0x4212))&0x0F)==0x00) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 5.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x01) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x02) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 12.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x03) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 11.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x04) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 10.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x05) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 9.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x06) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 8.--47. 0x1 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x07) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 7.--47. 0x80 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x08) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 22.--47. 0x40 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x09) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 21.--47. 0x20 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0A) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 20.--47. 0x10 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0B) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 19.--47. 0x8 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0C) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 18.--47. 0x4 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0D) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 17.--47. 0x2 "BADDR,Translation table base address" elif (((per.l(c15:0x4212))&0x0F)==0x0E) group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad.long 0x00 16.--47. 0x1 "BADDR,Translation table base address" else group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 15.--47. 0x80 "BADDR,Translation table base address" endif group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "2nd level,1st level,," newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x54000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.l(c15:0x4025))&0xFC000000)==0x60000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" newline bitfld.long 0x00 17.--19. "OP2,Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OP1,Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0800000||0xB0800000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.l(c15:0x4025))&0xFC800000)==(0xA0000000||0xB0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.l(c15:0x4025))&0xFD000000)==0xBD000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 15. "UNASE,Unattributable System Error" "Attributable,Unattributable" newline bitfld.long 0x00 14. "UNCSE,Uncontainable System Error" "Containable,Uncontainable" bitfld.long 0x00 0.--1. "SES,System Error Source" "Decode,ECC,Slave," elif (((per.l(c15:0x4025))&0xFD000000)==0xBC000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((per.l(c15:0x4025))&0xFC000000)==(0xC0000000||0xC4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xC8000000||0xCC000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xD0000000||0xD4000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((per.l(c15:0x4025))&0xFC000000)==(0xE0000000||0xF0000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA,Bits [39:12] of the faulting intermediate physical address" group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,Reserved,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." newline bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." newline bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported," bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x041F++0x00 line.long 0x00 "DL1DATA4,Data L1 Data 4 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM identifier" bitfld.long 0x00 18.--21. "WAY,Indicates the way of the RAM that is being accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. "INDEX,Indicates the index address of the RAM that is being accessed" tree.end tree "Level 2 memory system" group.long c15:0x1209++0x00 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "Reset,No reset" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 23. "L2CP,L2 cache ECC protection" "Not supported,Supported" newline rbitfld.long 0x00 22. "L1CECCPP,L1 Cache ECC and Parity protection" "Not supported,Supported" bitfld.long 0x00 21. "ECCPPEN,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" newline rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1 present,2 present,?..." newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" newline bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,6 cycles,6 cycles" group.long c15:0x1309++0x00 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2PLRUIP,Select the L2 PLRU insertion point" "MRU/LRU,MRU,3/4 LRU,LRU" bitfld.long 0x00 29. "L2RPLCPOL,Select the L2 cache replacement policy" "PLRU,Pseudo random" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Force L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enable single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 24. "L2PLRUMD,Disable PLRU dynamic insertion and update policy" "No,Yes" bitfld.long 0x00 23. "DACPMUWLU,Disable ACP MakeUnique and WriteLineUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enable UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" newline bitfld.long 0x00 12. "DPSHO,Disable set hazard optimization against prefetch entries" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 9. "DWHOBBRRQ,Disable set/way hazard optimization on back to back reads from the same CPU targeting the same set" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" newline bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" bitfld.long 0x00 5. "DSWHOWWM,Disables set/way hazard optimization for WBNA/WT memory" "No,Yes" bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disable clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline eventfld.long 0x00 5. "P5,Event Counter 5 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Event Counter 2 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,PMN5 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,PMN4 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,PMN3 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,PMN2 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,PMN1 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,PMN0 overflow [Read/Write]" "No overflow/No effect,Overflow/Clear" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" bitfld.long 0x00 5. "EVENT[5],Value of 5 event counter" "0,1" bitfld.long 0x00 4. "EVENT[4],Value of 4 event counter" "0,1" bitfld.long 0x00 3. "EVENT[3],Value of 3 event counter" "0,1" newline bitfld.long 0x00 2. "EVENT[2],Value of 2 event counter" "0,1" bitfld.long 0x00 1. "EVENT[1],Value of 1 event counter" "0,1" bitfld.long 0x00 0. "EVENT[0],Value of 0 event counter" "0,1" newline group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Prioity Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Prioity Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt" hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Interrupt Controller Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Register 0-0" bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Register 1-0" bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1" bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1" bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1" bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1" newline bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1" bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1" bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1" bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1" newline bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1" bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1" bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1" bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1" bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1" bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1" bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1" newline bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1" bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1" bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1" bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1" newline bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1" bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1" bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1" bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1" bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1" bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1" bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1" newline bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1" bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1" bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1" bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..." newline bitfld.long 0x0 16.--19. "VERSION,Debug Architecture Version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..." bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" hgroup.long c14:0x0050++0x0 hide.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" in group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 22.--23. "INTDIS,Used for save/restore of EDSCR.INTdis" "0,1,2,3" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" if (((per.l(c14:0x06E7))&0xAA)==0xAA) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA8) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0xA2) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0xA0) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x8A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x88) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x82) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x80) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x2A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x28) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x22) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x20) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x0A) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x08) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" elif (((per.l(c14:0x06E7))&0xAA)==0x02) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" elif (((per.l(c14:0x06E7))&0xAA)==0x00) rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" endif rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" ",,No offset,?..." rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" ",Supported,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--47. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 0.--1. "VALID,ROM table address valid" "Not valid,,,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Power down,Emulate" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x0)++0x0 hide.long 0x00 "DBGBVR0,Breakpoint Value Register" else group.long c14:(0x0400+0x0)++0x0 line.long 0x00 "DBGBVR0,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 1" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x10)++0x0 hide.long 0x00 "DBGBVR1,Breakpoint Value Register" else group.long c14:(0x0400+0x10)++0x0 line.long 0x00 "DBGBVR1,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 2" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x20)++0x0 hide.long 0x00 "DBGBVR2,Breakpoint Value Register" else group.long c14:(0x0400+0x20)++0x0 line.long 0x00 "DBGBVR2,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 3" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x30)++0x0 hide.long 0x00 "DBGBVR3,Breakpoint Value Register" else group.long c14:(0x0400+0x30)++0x0 line.long 0x00 "DBGBVR3,Breakpoint ContextID Register" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 4" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x40)++0x0 hide.long 0x00 "DBGBVR4,Breakpoint Value Register" else group.long c14:(0x0400+0x40)++0x0 line.long 0x00 "DBGBVR4,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x40)))&0x800000)==0x800000) group.long c14:(0x0101+0x40)++0x0 line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x40)++0x0 hide.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 5" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) hgroup.long c14:(0x0400+0x50)++0x0 hide.long 0x00 "DBGBVR5,Breakpoint Value Register" else group.long c14:(0x0400+0x50)++0x0 line.long 0x00 "DBGBVR5,Breakpoint ContextID Register" endif if (((per.l(c14:(0x500+0x50)))&0x800000)==0x800000) group.long c14:(0x0101+0x50)++0x0 line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VAMID,VMID value for comparison" else hgroup.long c14:(0x0101+0x50)++0x0 hide.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,?..." bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree.end tree "Watchpoint Control Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked,Linked" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP0,BRP1,BRP2,BRP3,BRP4,BRP5,?..." newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hyp Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end tree.end AUTOINDENT.OFF tree.open "Interrupt Controller (GIC-400)" width 17. width 17. base AD:0x01410000 tree "Distributor Interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(AD:0x01410000) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" if PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0080) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)" else group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0084)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0088)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x008C)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0090)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0094)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x0098)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x009C)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A0)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A4)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00A8)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00AC)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B0)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B4)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00B8)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00BC)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C0)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C4)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00C8)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00CC)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D0)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D4)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00D8)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00DC)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E0)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x0E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E4)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00E8)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00EC)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F0)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x0F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F4)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00F8)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(AD:0x01410000+0x00FC)) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else rgroup.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else rgroup.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Not pending,Pending" else rgroup.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(AD:0x01410000+0x08))&0xFF000000)==(0x0000000||0x1000000)) rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x037C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else rgroup.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" rgroup.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" rgroup.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" rgroup.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" rgroup.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" rgroup.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" rgroup.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(AD:0x01410000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" rgroup.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else rgroup.long 0x0D60++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(AD:0x01410000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xFD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" rgroup.byte 0xFD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" rgroup.byte 0xFDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end width 0x0B base AD:0x1420000 width 17. tree "CPU Interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " else if PER.ADDRESS.isSECUREEX(AD:0x1420000) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Secure access)" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,When the signaling of IRQs by the CPU interface is disabled this bit partly controls whether the bypass IRQ signal is signaled to the processor" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,When the signaling of FIQs by the CPU interface is disabled this bit partly controls whether the bypass FIQ signal is signaled to the processor" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " endif endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(AD:0x1420000+0x0008) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif hgroup.long 0x0020++0x003 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) wgroup.long 0x0024++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" else hgroup.long 0x0024++0x03 hide.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hgroup.long 0x0028++0x03 hide.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" endif group.long 0x00D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" if (((per.l(AD:0x01410000+0x04))&0x400)==0x400) group.long 0x00E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" else hgroup.long 0x00E0++0x03 hide.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end sif CPU.FEATURE(hypervisor) base AD:0x1440000 width 12. tree "Virtual CPU Control Interface" group.long 0x0000++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Disable Group 1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Enable Group 1 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " VGRP0DIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " VGRP0EIE ,VM Disable Group 0 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x008++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" bitfld.long 0x00 27.--31. " VMPRIMASK ,Alias of GICV_PMR.Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. " VMBP ,Alias of GICV_BPR.Binary point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VMABP ,Alias of GICV_ABPR.Binary point" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9. " VEM ,Alias of GICV_CTLR.EOImode" "0,1" bitfld.long 0x00 4. " VMCBPR ,Alias of GICV_CTLR.CBPR" "0,1" bitfld.long 0x00 3. " VMFIQEN ,Alias of GICV_CTLR.FIQEn" "0,1" textline " " bitfld.long 0x00 2. " VMACKCTL ,Alias of GICV_CTLR.AckCtl" "0,1" bitfld.long 0x00 1. " VMGRP1EN ,Alias of GICV_CTLR.EnableGrp1" "0,1" bitfld.long 0x00 0. " VMGRP0EN ,Alias of GICV_CTLR.EnableGrp0" "0,1" rgroup.long 0x0010++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,Disabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VGRP1E ,Enabled Group 1 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. " VGRP0D ,Disabled Group 0 maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " VGRP0E ,Enabled Group 0 maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "No interrupt,Interrupt" rgroup.long 0x020++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x0030++0x03 line.long 0x00 "GICH_ELSR0,Empty List register Status Register" bitfld.long 0x00 3. " STATUS3 ,Emptiness status bit for List register 3" "Not empty,Empty" bitfld.long 0x00 2. " STATUS2 ,Emptiness status bit for List register 2" "Not empty,Empty" bitfld.long 0x00 1. " STATUS1 ,Emptiness status bit for List register 1" "Not empty,Empty" textline " " bitfld.long 0x00 0. " STATUS0 ,Emptiness status bit for List register 0" "Not empty,Empty" group.long 0x00F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" if (((per.l(AD:0x1440000+0x100))&0x80000000)==0x80000000) group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x104))&0x80000000)==0x80000000) group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x108))&0x80000000)==0x80000000) group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif if (((per.l(AD:0x1440000+0x10C))&0x80000000)==0x80000000) group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Indicates the physical interrupt ID that the hypervisor forwards to the Distributor" hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" else group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GRP1 ,Indicates whether this virtual interrupt is a Group 1 virtual interrupt" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Invalid,Pending,Active,Pending and active" textline " " bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " EOI ,Indicates whether this interrupt triggers an EOI maintenance interrupt" "Not asserted,Asserted" bitfld.long 0x00 10.--12. " CPUID ,If the interrupt has the VirtualID for an SGI that is 0-15 this field shows the requesting CPU ID" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,This ID is returned to the Guest OS when the interrupt is acknowledged through the VM Interrupt Acknowledge register, GICV_IAR" endif tree.end base AD:0x1460000 width 12. tree "Virtual CPU Interface" group.long 0x0000++0x03 line.long 0x00 "GICV_CTLR,Virtual Machine Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior associated with the GICV_EOIR GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate,Priority drop" bitfld.long 0x00 4. " CBPR ,Controls whether the GICV_BPR controls both Group 0 and Group 1 virtual interrupts" "BPR/ABPR split,BPR common" bitfld.long 0x00 3. " FIQEN ,Controls whether interrupts marked as Group 0 are presented as virtual FIQs" "IRQs,FIQs" textline " " bitfld.long 0x00 2. " ACKCTL ,Acknowledge Control" "ID 1022 interrupt,Corresponding interrupt" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x0004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" bitfld.long 0x00 3.--7. " PRIORITY ,Priority mask level for CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x000C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICV_EOIR,VM End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the Virtual CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x001C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" hgroup.long 0x0020++0x03 hide.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" in wgroup.long 0x0024++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0028++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" group.long 0x00D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" bitfld.long 0x00 31. " APB31 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 30. " APB30 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 29. " APB29 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 28. " APB28 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 27. " APB27 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 26. " APB26 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 25. " APB25 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 24. " APB24 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 23. " APB23 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 22. " APB22 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 21. " APB21 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 20. " APB20 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 19. " APB19 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 18. " APB18 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 17. " APB17 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 16. " APB16 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 15. " APB15 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 14. " APB14 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 13. " APB13 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 12. " APB12 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 11. " APB11 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 10. " APB10 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 9. " APB9 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 8. " APB8 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 7. " APB7 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 6. " APB6 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 5. " APB5 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 4. " APB4 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 3. " APB3 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 2. " APB2 ,Determines whether the corresponding preemption level is active" "Not active,Active" textline " " bitfld.long 0x00 1. " APB1 ,Determines whether the corresponding preemption level is active" "Not active,Active" bitfld.long 0x00 0. " APB0 ,Determines whether the corresponding preemption level is active" "Not active,Active" rgroup.long 0x00FC++0x03 line.long 0x00 "GICV_IIDR,VM CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation this field identifies the processor that requested the interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " INTID ,The interrupt ID" tree.end endif width 0x0B tree.end tree.end elif (cpuis("LS1044*")||cpuis("LS1048*")||cpuis("LS1084*")||cpuis("LS1088*")) tree "Core Registers (Cortex-A53)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x0 line.long 0x0 "MIDR_EL1,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" newline hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30005++0x00 line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field" newline bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" newline hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.quad SPR:0x30006++0x0 line.long 0x0 "REVIDR_EL1,Revision ID Register" rgroup.quad SPR:0x30014++0x00 line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30015++0x00 line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad SPR:0x30016++0x00 line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad SPR:0x30017++0x00 line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" endif rgroup.quad SPR:0x30020++0x00 line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad SPR:0x30021++0x00 line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30022++0x00 line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30023++0x00 line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30024++0x00 line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad SPR:0x30025++0x00 line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" endif rgroup.quad SPR:0x30010++0x00 line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.quad SPR:0x30011++0x00 line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..." endif if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" endif if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x30012++0x00 line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..." if (CORENAME()=="CORTEXA53") rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" endif rgroup.quad SPR:0x30013++0x00 line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad SPR:0x31007++0x00 line.long 0x00 "AIDR_EL1,Auxiliary ID Register" rgroup.quad SPR:0x33007++0x00 line.long 0x00 "DCZID_EL0,Data Cache Zero ID" bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited" bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" group.quad SPR:0x30100++0x0 line.long 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x34100++0x0 line.long 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad SPR:0x36100++0x0 line.long 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad SPR:0x30101++0x0 line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad SPR:0x34101++0x0 line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x36101++0x0 line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" group.quad SPR:0x30102++0x00 line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register" bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..." bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped" group.quad SPR:0x36110++0x0 line.long 0x0 "SCR_EL3,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled" bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (CORENAME()=="CORTEXA57") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif elif (CORENAME()=="CORTEXA53") if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External," newline hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x30520++0x00 line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..." elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x34520++0x00 line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3" bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined" elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt" elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000) group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value" else group.quad SPR:0x36520++0x00 line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif endif tree.end newline if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address" rgroup.quad SPR:0x30C10++0x00 line.long 0x00 "ISR_EL1,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.quad SPR:0x36C02++0x00 line.long 0x00 "RMR_EL3,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]" elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register" hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]" endif group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register" tree.end tree "Memory Management Unit" group.quad spr:0x30100++0x0 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes" bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x36100++0x0 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB" newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..." newline bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB" bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored" bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad SPR:0x34300++0x00 line.long 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (CORENAME()=="CORTEXA57") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif (CORENAME()=="CORTEXA53") if (((per.q(spr:0x34501))&0x200)==0x200) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long" newline bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif rgroup.quad SPR:0x30510++0x00 line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" rgroup.quad SPR:0x34510++0x00 line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" rgroup.quad SPR:0x36510++0x00 line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" rgroup.quad SPR:0x30511++0x00 line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" rgroup.quad SPR:0x34511++0x00 line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" rgroup.quad SPR:0x36511++0x00 line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..." newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read" newline hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" newline bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate" rgroup.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)" rgroup.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)" rgroup.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)" tree.end newline group.quad SPR:0x30D01++0x00 line.long 0x0 "CONTEXTIDR_EL1,Context ID Register" tree.end tree "Virtualization Extensions" group.quad SPR:0x34000++0x0 line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register" if (CORENAME()=="CORTEXA57") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1" elif (CORENAME()=="CORTEXA53") group.quad spr:0x34005++0x00 line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" endif group.quad spr:0x34100++0x0 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" newline bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled" bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled" newline bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending" bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34111++0x00 line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6" endif group.quad SPR:0x34112++0x00 line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x36131++0x00 line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes" bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" group.quad SPR:0x36112++0x00 line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped" group.quad SPR:0x34113++0x00 line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..." bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped" bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped" newline bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped" bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped" bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped" newline bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped" bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped" bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped" newline bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped" bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped" bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped" newline bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped" bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped" bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped" rgroup.quad SPR:0x34117++0x00 line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" if (CORENAME()=="CORTEXA57") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..." bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x34212++0x00 line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..." bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..." bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits" tree.end tree "Cache Control and Configuration" if (CORENAME()=="CORTEXA57") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad spr:0x33001++0x0 line.long 0x0 "CTR_EL0,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif group.quad SPR:0x32000++0x0 line.long 0x0 "CSSELR_EL1,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x31001++0x0 line.long 0x0 "CLIDR_EL1,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." rgroup.quad SPR:0x31000++0x0 line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..." endif tree "Level 1 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x30F10++0x00 line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register" group.quad SPR:0x30F11++0x00 line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register" group.quad SPR:0x30F12++0x00 line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register" group.quad SPR:0x30F13++0x00 line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register" group.quad SPR:0x30F00++0x00 line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register" group.quad SPR:0x30F01++0x00 line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register" group.quad SPR:0x30F02++0x00 line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register" group.quad SPR:0x30F03++0x00 line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register" group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" newline bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" newline bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" newline bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" newline bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" newline bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" newline bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" newline bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..." elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F20++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" newline bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" newline bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8" bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled" group.quad spr:0x31F21++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" endif if (CORENAME()=="CORTEXA57") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" elif (CORENAME()=="CORTEXA53") group.quad spr:0x31F22++0x00 line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" endif tree.end tree "Level 2 memory system" if (CORENAME()=="CORTEXA57") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..." bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" newline bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" newline bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" newline bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" newline bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" newline bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif (CORENAME()=="CORTEXA53") group.quad SPR:0x31B02++0x0 line.long 0x00 "L2CTLR_EL1,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.quad SPR:0x31B03++0x0 line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad SPR:0x31F00++0x00 line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3" bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled" bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled" newline bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad spr:0x31F23++0x00 line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" newline bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.quad SPR:0x339C0++0x00 line.long 0x0 "PMCR_EL0,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad SPR:0x339C1++0x00 line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.quad SPR:0x339C2++0x00 line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.quad SPR:0x339C3++0x00 line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register" bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled" wgroup.quad SPR:0x339C4++0x00 line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" newline bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" newline bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" newline bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" newline bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" newline bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" newline bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.quad SPR:0x339C5++0x00 line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" if (CORENAME()=="CORTEXA57") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" newline bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" newline bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" newline bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" newline bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" newline bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" newline bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA53") rgroup.quad SPR:0x339C6++0x0 line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" newline bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" newline bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" endif rgroup.quad SPR:0x339C7++0x0 line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register" group.quad SPR:0x339D1++0x00 line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register" group.quad SPR:0x339D2++0x00 line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register" group.quad SPR:0x339E0++0x00 line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.quad SPR:0x309E1++0x00 line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad SPR:0x309E2++0x00 line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.quad SPR:0x339E3++0x00 line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register" group.quad SPR:(0x33E80+0x0)++0x00 line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad SPR:(0x33EC0+0x0)++0x00 line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x1)++0x00 line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad SPR:(0x33EC0+0x1)++0x00 line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x2)++0x00 line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad SPR:(0x33EC0+0x2)++0x00 line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x3)++0x00 line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad SPR:(0x33EC0+0x3)++0x00 line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x4)++0x00 line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad SPR:(0x33EC0+0x4)++0x00 line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:(0x33E80+0x5)++0x00 line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad SPR:(0x33EC0+0x5)++0x00 line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.quad SPR:0x33EF7++0x00 line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad SPR:0x33E00++0x00 line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register" group.quad SPR:0x30E10++0x00 line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x33E20++0x00 line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad SPR:0x33E21++0x00 line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad SPR:0x33E30++0x00 line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register" group.quad SPR:0x33E31++0x00 line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register" group.quad SPR:0x34E10++0x00 line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.quad SPR:0x34E20++0x00 line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register" group.quad SPR:0x34E21++0x00 line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register" group.quad SPR:0x37E20++0x00 line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register" group.quad SPR:0x37E21++0x00 line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported" rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register" if (((per.q(spr:0x30CC4))&0x3800)==0x00) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" elif (((per.q(spr:0x30CC4))&0x3800)==0x800) wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level" endif hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad SPR:0x30CC6++0x00 line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x30CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)" bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad SPR:0x36CC7++0x00 line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad SPR:0x30460++0x00 line.long 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad SPR:0x30CB3++0x00 line.long 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad SPR:0x30CC5++0x00 line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x34C95++0x00 line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.quad SPR:0x36CC5++0x00 line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad SPR:0x34C80++0x00 line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" if (CORENAME()=="CORTEXA53") group.quad SPR:0x34C90++0x00 line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" endif tree.end newline rgroup.quad SPR:0x34CB3++0x00 line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.quad SPR:0x34CB5++0x00 line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.quad SPR:0x34CB0++0x00 line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..." bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" endif rgroup.quad SPR:0x34CB2++0x00 line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.quad SPR:0x34CB7++0x00 line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.quad SPR:0x34C94++0x00 line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register" rgroup.quad SPR:0x34CB1++0x00 line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" rgroup.quad SPR:0x23010++0x00 line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad SPR:0x20020++0x00 line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad SPR:0x23050++0x00 line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad SPR:0x24070++0x00 line.long 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High" newline bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High" bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High" bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High" newline bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High" bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High" bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High" group.quad SPR:0x20002++0x00 line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20022++0x00 line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High" bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High" newline bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High" newline bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High" bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled" group.quad SPR:0x20032++0x00 line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad SPR:0x20062++0x00 line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad SPR:0x20104++0x00 line.long 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad SPR:0x20114++0x00 line.long 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..." group.quad SPR:0x20134++0x00 line.long 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad SPR:0x20144++0x00 line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes" group.quad SPR:0x20786++0x00 line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad SPR:0x20796++0x00 line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad SPR:0x207E6++0x00 line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" group.quad SPR:0x33450++0x00 line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" tree.end tree "Breakpoint Registers" if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0" line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x0)++0x0 line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1" line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x10)++0x0 line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2" line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x20)++0x0 line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3" line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x30)++0x0 line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4" line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x40)++0x0 line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000)) group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000)) else group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5" line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID" endif group.quad SPR:(0x20005+0x50)++0x0 line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0" line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1" line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2" line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3" line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0000++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8" newline hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number" bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA57") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." elif (CORENAME()=="CORTEXA53") rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." endif if corename()=="CORTEXA57" rgroup.long c15:0x0300++0x0 line.long 0x0 "TLBTR,TLB Type Register" endif if corename()=="CORTEXA57" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4" elif corename()=="CORTEXA53" rgroup.long c15:0x0500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..." hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field" newline hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field" endif rgroup.long c15:0x0600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,ID_MMFR4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved" rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." if corename()=="CORTEXA57" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif group.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" if corename()=="CORTEXA57" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" elif corename()=="CORTEXA53" rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented" newline bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented" bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented" bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented" newline bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass unaligned load or store" "Not implemented,Implemented" newline bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" newline bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented" newline bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" rgroup.long c15:0x7C9++0x0 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" tree.end tree "System Control and Configuration" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" else group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" endif group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced" bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes" newline bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes" bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled" newline bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes" bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes" newline bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled" bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled" newline bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes" bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes" newline bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes" bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes" newline bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes" bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes" newline bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled" bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes" newline bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced" bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes" newline bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced" bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes" newline bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes" bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes" newline bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled" bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced" newline bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled" bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" newline bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled" newline bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced" bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced" newline bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes" bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes" newline bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes" bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes" newline bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes" bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled" newline bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced" bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced" newline bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled" bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled" newline bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled" bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced" newline bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes" bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled" newline bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled" bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled" newline bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes" bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes" newline bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes" bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes" bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" newline bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" newline bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled" bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled" newline bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes" bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes" newline bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes" bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes" newline bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams" bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled" newline bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled" bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" newline bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.quad c15:0x120F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7" newline hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address" group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" endif if corename()=="CORTEXA57" group.long c15:0x0201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes" newline bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full" elif corename()=="CORTEXA53" group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full" newline bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full" endif group.long c15:0x0011++0x0 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped" bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" if corename()=="CORTEXA57" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" elif corename()=="CORTEXA53" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" endif rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" newline bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable" bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable" newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..." endif endif if corename()=="CORTEXA57" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif elif corename()=="CORTEXA53" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if corename()=="CORTEXA57" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]" elif corename()=="CORTEXA53" rgroup.long c15:0x103F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]" hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]" endif group.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE Process ID register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" tree.end tree "Memory Management Unit" if corename()=="CORTEXA57" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) // MPIDR[31]==1 case is missing here for TTBR0 and TTBR1 group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address" bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner" newline bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. "IMP,Implementation" "Low,High" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" endif if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif elif corename()=="CORTEXA53" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes" bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes" newline bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes" newline bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled" bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" else group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address" bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" endif endif if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if (((per.l(c15:0x202))&0x80000000)==0x80000000) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" else group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" newline bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" newline endif tree.end newline if (((per.l(c15:0x202))&0x80000000)==0x00000000) group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier" endif tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x0 line.long 0x00 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced" newline bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes" bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled" newline bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled" newline bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled" bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled" bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled" newline bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled" if corename()=="CORTEXA57" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" newline bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" newline bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" newline bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted" newline bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed" newline bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" elif corename()=="CORTEXA53" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes" newline bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled" newline bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" newline bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" newline bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled" newline bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled" bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" newline bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" newline bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" newline bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3" bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" newline bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted" bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override" newline bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override" newline bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" newline bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled" endif group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid" newline bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid" newline bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..." newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..." newline hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13" bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" if corename()=="CORTEXA57" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address" elif corename()=="CORTEXA53" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" endif group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3" bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3" newline bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3" bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3" newline bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High" bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT" newline bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if corename()=="CORTEXA57" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..." newline bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." elif corename()=="CORTEXA53" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..." endif rgroup.long c15:0x1700++0x0 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" tree "Level 1 memory system" if corename()=="CORTEXA57" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x030F++0x00 line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register" wgroup.long c15:0x04F++0x00 line.long 0x00 "RAMINDEX,RAM Index Operation Register" elif corename()=="CORTEXA53" rgroup.long c15:0x300F++0x00 line.long 0x00 "CDBGDR0,Cache Debug Data Register 0" rgroup.long c15:0x310F++0x00 line.long 0x00 "CDBGDR1,Cache Debug Data Register 1" rgroup.long c15:0x320F++0x00 line.long 0x00 "CDBGDR2,Cache Debug Data Register 2" rgroup.long c15:0x330F++0x00 line.long 0x00 "CDBGDR3,Cache Debug Data Register 3" wgroup.long c15:0x302F++0x00 line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register" wgroup.long c15:0x312F++0x00 line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register" wgroup.long c15:0x304F++0x00 line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register" wgroup.long c15:0x314F++0x00 line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register" wgroup.long c15:0x324F++0x00 line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register" endif tree.end tree "Level 2 memory system" if corename()=="CORTEXA57" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" newline rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported" bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" newline bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled" rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present" newline rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present" rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present" newline bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" newline rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle" bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled" bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled" newline bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced" bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled" newline bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes" bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes" newline bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled" bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit" newline bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes" bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled" newline bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes" bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes" newline bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes" bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes" newline bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes" newline bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled" bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" newline bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited" bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled" newline bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes" group.quad c15:0x130F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index" elif corename()=="CORTEXA53" group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4" bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled" newline rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled" rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle" newline rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles" group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error" newline bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3" bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled" newline bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes" group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count" newline hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count" bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid" newline hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier" bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." newline hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address" endif tree.end tree.end tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled" bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled" bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled" bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled" bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled" bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled" bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled" bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled" bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled" bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled" bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled" bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled" bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled" bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled" bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled" bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled" bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled" bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled" bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled" bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled" eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled" eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled" eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled" eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled" eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled" eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled" eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled" eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled" eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled" eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled" eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow" eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow" eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow" eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow" newline eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow" eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow" eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow" eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow" eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow" newline eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow" eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow" eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow" eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow" eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow" newline eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow" eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow" eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow" eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow" eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow" newline eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow" eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow" eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow" eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow" eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow" newline eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" newline eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment" bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment" bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment" bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment" bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment" newline bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment" bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment" bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment" bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment" bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment" newline bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment" bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment" bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment" bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment" bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment" newline bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment" bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment" bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment" bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment" bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment" newline bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment" bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment" bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment" bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment" bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment" newline bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment" bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment" newline bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled" eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled" newline eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x40)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x40)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x40)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x40)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x40)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x40)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" newline bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported" rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported" newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register" if (((per.l(c15:0x4CC))&0x3800)==0x00) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" elif (((per.l(c15:0x4CC))&0x3800)==0x800) wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" endif hgroup.long c15:0x008C++0x00 hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" in hgroup.long c15:0x00CC++0x00 hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" in group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" wgroup.quad c15:0x100C0++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" if corename()=="CORTEXA53" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" endif group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x459C++0x00 line.long 0x00 "ICH_SRE,Hypervisor System Register" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt" bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported" newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA57" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" elif corename()=="CORTEXA53" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version" bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High" bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported" newline bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number" newline hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled" newline bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled" bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." wgroup.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" group.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)" group.long c14:0x0687++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented" newline bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1" newline bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1" rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..." bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..." newline bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..." bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented" newline bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address" hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address" bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid" newline bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else hgroup.long c14:0x0260++0x00 hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register" bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High" tree.end tree "Breakpoint Registers" if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0" line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x0)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1" line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x10)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2" line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x20)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3" line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x30)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4" line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x40)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000)) group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)" hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison" elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000)) hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)" else group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5" line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)" endif group.long c14:(0x0500+0x50)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" newline bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled" group.long c14:0x0141++0x0 line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" group.long c14:0x0151++0x0 line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5" hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value" tree.end tree "Watchpoint Control Registers" group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0" line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1" line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2" line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3" line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "DA,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match" bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" newline bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled" hexmask.long.byte 0x0 5.--12. "BAS,Byte address select" newline bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-500)" base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register" endif width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Implementation Defined Test Registers" rgroup.long 0xC000++0x03 line.long 0x00 "GICD_ESTATUSR,GICD_ESTATUSR" bitfld.long 0x00 31. " SRWP ,Super Register Write Pending" "Not pending,Pending" wgroup.long 0xC004++0x03 line.long 0x00 "GICD_ERRTESTR,Error Test Register" bitfld.long 0x00 1. " AXIM_ERR ,Drives the axim_err pin to 0b1 for 1 cycle" "Low,High" bitfld.long 0x00 0. " ECC_FATAL ,Drives the ecc_fatal pin to 0b1 for 1 cycle" "Low,High" textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) rgroup.long 0xC084++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " SPIS63 ,SPI Status Bit 63" "Low,High" bitfld.long 0x00 30. " SPIS62 ,SPI Status Bit 62" "Low,High" bitfld.long 0x00 29. " SPIS61 ,SPI Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " SPIS60 ,SPI Status Bit 60" "Low,High" bitfld.long 0x00 27. " SPIS59 ,SPI Status Bit 59" "Low,High" bitfld.long 0x00 26. " SPIS58 ,SPI Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " SPIS57 ,SPI Status Bit 57" "Low,High" bitfld.long 0x00 24. " SPIS56 ,SPI Status Bit 56" "Low,High" bitfld.long 0x00 23. " SPIS55 ,SPI Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " SPIS54 ,SPI Status Bit 54" "Low,High" bitfld.long 0x00 21. " SPIS53 ,SPI Status Bit 53" "Low,High" bitfld.long 0x00 20. " SPIS52 ,SPI Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " SPIS51 ,SPI Status Bit 51" "Low,High" bitfld.long 0x00 18. " SPIS50 ,SPI Status Bit 50" "Low,High" bitfld.long 0x00 17. " SPIS49 ,SPI Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " SPIS48 ,SPI Status Bit 48" "Low,High" bitfld.long 0x00 15. " SPIS47 ,SPI Status Bit 47" "Low,High" bitfld.long 0x00 14. " SPIS46 ,SPI Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " SPIS45 ,SPI Status Bit 45" "Low,High" bitfld.long 0x00 12. " SPIS44 ,SPI Status Bit 44" "Low,High" bitfld.long 0x00 11. " SPIS43 ,SPI Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " SPIS42 ,SPI Status Bit 42" "Low,High" bitfld.long 0x00 9. " SPIS41 ,SPI Status Bit 41" "Low,High" bitfld.long 0x00 8. " SPIS40 ,SPI Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " SPIS39 ,SPI Status Bit 39" "Low,High" bitfld.long 0x00 6. " SPIS38 ,SPI Status Bit 38" "Low,High" bitfld.long 0x00 5. " SPIS37 ,SPI Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " SPIS36 ,SPI Status Bit 36" "Low,High" bitfld.long 0x00 3. " SPIS35 ,SPI Status Bit 35" "Low,High" bitfld.long 0x00 2. " SPIS34 ,SPI Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " SPIS33 ,SPI Status Bit 33" "Low,High" bitfld.long 0x00 0. " SPIS32 ,SPI Status Bit 32" "Low,High" else hgroup.long 0xC084++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) rgroup.long 0xC088++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " SPIS95 ,SPI Status Bit 95" "Low,High" bitfld.long 0x00 30. " SPIS94 ,SPI Status Bit 94" "Low,High" bitfld.long 0x00 29. " SPIS93 ,SPI Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " SPIS92 ,SPI Status Bit 92" "Low,High" bitfld.long 0x00 27. " SPIS91 ,SPI Status Bit 91" "Low,High" bitfld.long 0x00 26. " SPIS90 ,SPI Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " SPIS89 ,SPI Status Bit 89" "Low,High" bitfld.long 0x00 24. " SPIS88 ,SPI Status Bit 88" "Low,High" bitfld.long 0x00 23. " SPIS87 ,SPI Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " SPIS86 ,SPI Status Bit 86" "Low,High" bitfld.long 0x00 21. " SPIS85 ,SPI Status Bit 85" "Low,High" bitfld.long 0x00 20. " SPIS84 ,SPI Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " SPIS83 ,SPI Status Bit 83" "Low,High" bitfld.long 0x00 18. " SPIS82 ,SPI Status Bit 82" "Low,High" bitfld.long 0x00 17. " SPIS81 ,SPI Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " SPIS80 ,SPI Status Bit 80" "Low,High" bitfld.long 0x00 15. " SPIS79 ,SPI Status Bit 79" "Low,High" bitfld.long 0x00 14. " SPIS78 ,SPI Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " SPIS77 ,SPI Status Bit 77" "Low,High" bitfld.long 0x00 12. " SPIS76 ,SPI Status Bit 76" "Low,High" bitfld.long 0x00 11. " SPIS75 ,SPI Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " SPIS74 ,SPI Status Bit 74" "Low,High" bitfld.long 0x00 9. " SPIS73 ,SPI Status Bit 73" "Low,High" bitfld.long 0x00 8. " SPIS72 ,SPI Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " SPIS71 ,SPI Status Bit 71" "Low,High" bitfld.long 0x00 6. " SPIS70 ,SPI Status Bit 70" "Low,High" bitfld.long 0x00 5. " SPIS69 ,SPI Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " SPIS68 ,SPI Status Bit 68" "Low,High" bitfld.long 0x00 3. " SPIS67 ,SPI Status Bit 67" "Low,High" bitfld.long 0x00 2. " SPIS66 ,SPI Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " SPIS65 ,SPI Status Bit 65" "Low,High" bitfld.long 0x00 0. " SPIS64 ,SPI Status Bit 64" "Low,High" else hgroup.long 0xC088++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) rgroup.long 0xC08C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " SPIS127 ,SPI Status Bit 127" "Low,High" bitfld.long 0x00 30. " SPIS126 ,SPI Status Bit 126" "Low,High" bitfld.long 0x00 29. " SPIS125 ,SPI Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " SPIS124 ,SPI Status Bit 124" "Low,High" bitfld.long 0x00 27. " SPIS123 ,SPI Status Bit 123" "Low,High" bitfld.long 0x00 26. " SPIS122 ,SPI Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " SPIS121 ,SPI Status Bit 121" "Low,High" bitfld.long 0x00 24. " SPIS120 ,SPI Status Bit 120" "Low,High" bitfld.long 0x00 23. " SPIS119 ,SPI Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " SPIS118 ,SPI Status Bit 118" "Low,High" bitfld.long 0x00 21. " SPIS117 ,SPI Status Bit 117" "Low,High" bitfld.long 0x00 20. " SPIS116 ,SPI Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " SPIS115 ,SPI Status Bit 115" "Low,High" bitfld.long 0x00 18. " SPIS114 ,SPI Status Bit 114" "Low,High" bitfld.long 0x00 17. " SPIS113 ,SPI Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " SPIS112 ,SPI Status Bit 112" "Low,High" bitfld.long 0x00 15. " SPIS111 ,SPI Status Bit 111" "Low,High" bitfld.long 0x00 14. " SPIS110 ,SPI Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " SPIS109 ,SPI Status Bit 109" "Low,High" bitfld.long 0x00 12. " SPIS108 ,SPI Status Bit 108" "Low,High" bitfld.long 0x00 11. " SPIS107 ,SPI Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " SPIS106 ,SPI Status Bit 106" "Low,High" bitfld.long 0x00 9. " SPIS105 ,SPI Status Bit 105" "Low,High" bitfld.long 0x00 8. " SPIS104 ,SPI Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " SPIS103 ,SPI Status Bit 103" "Low,High" bitfld.long 0x00 6. " SPIS102 ,SPI Status Bit 102" "Low,High" bitfld.long 0x00 5. " SPIS101 ,SPI Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " SPIS100 ,SPI Status Bit 100" "Low,High" bitfld.long 0x00 3. " SPIS99 ,SPI Status Bit 99" "Low,High" bitfld.long 0x00 2. " SPIS98 ,SPI Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " SPIS97 ,SPI Status Bit 97" "Low,High" bitfld.long 0x00 0. " SPIS96 ,SPI Status Bit 96" "Low,High" else hgroup.long 0xC08C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) rgroup.long 0xC090++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " SPIS159 ,SPI Status Bit 159" "Low,High" bitfld.long 0x00 30. " SPIS158 ,SPI Status Bit 158" "Low,High" bitfld.long 0x00 29. " SPIS157 ,SPI Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " SPIS156 ,SPI Status Bit 156" "Low,High" bitfld.long 0x00 27. " SPIS155 ,SPI Status Bit 155" "Low,High" bitfld.long 0x00 26. " SPIS154 ,SPI Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " SPIS153 ,SPI Status Bit 153" "Low,High" bitfld.long 0x00 24. " SPIS152 ,SPI Status Bit 152" "Low,High" bitfld.long 0x00 23. " SPIS151 ,SPI Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " SPIS150 ,SPI Status Bit 150" "Low,High" bitfld.long 0x00 21. " SPIS149 ,SPI Status Bit 149" "Low,High" bitfld.long 0x00 20. " SPIS148 ,SPI Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " SPIS147 ,SPI Status Bit 147" "Low,High" bitfld.long 0x00 18. " SPIS146 ,SPI Status Bit 146" "Low,High" bitfld.long 0x00 17. " SPIS145 ,SPI Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " SPIS144 ,SPI Status Bit 144" "Low,High" bitfld.long 0x00 15. " SPIS143 ,SPI Status Bit 143" "Low,High" bitfld.long 0x00 14. " SPIS142 ,SPI Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " SPIS141 ,SPI Status Bit 141" "Low,High" bitfld.long 0x00 12. " SPIS140 ,SPI Status Bit 140" "Low,High" bitfld.long 0x00 11. " SPIS139 ,SPI Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " SPIS138 ,SPI Status Bit 138" "Low,High" bitfld.long 0x00 9. " SPIS137 ,SPI Status Bit 137" "Low,High" bitfld.long 0x00 8. " SPIS136 ,SPI Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " SPIS135 ,SPI Status Bit 135" "Low,High" bitfld.long 0x00 6. " SPIS134 ,SPI Status Bit 134" "Low,High" bitfld.long 0x00 5. " SPIS133 ,SPI Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " SPIS132 ,SPI Status Bit 132" "Low,High" bitfld.long 0x00 3. " SPIS131 ,SPI Status Bit 131" "Low,High" bitfld.long 0x00 2. " SPIS130 ,SPI Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " SPIS129 ,SPI Status Bit 129" "Low,High" bitfld.long 0x00 0. " SPIS128 ,SPI Status Bit 128" "Low,High" else hgroup.long 0xC090++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) rgroup.long 0xC094++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " SPIS191 ,SPI Status Bit 191" "Low,High" bitfld.long 0x00 30. " SPIS190 ,SPI Status Bit 190" "Low,High" bitfld.long 0x00 29. " SPIS189 ,SPI Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " SPIS188 ,SPI Status Bit 188" "Low,High" bitfld.long 0x00 27. " SPIS187 ,SPI Status Bit 187" "Low,High" bitfld.long 0x00 26. " SPIS186 ,SPI Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " SPIS185 ,SPI Status Bit 185" "Low,High" bitfld.long 0x00 24. " SPIS184 ,SPI Status Bit 184" "Low,High" bitfld.long 0x00 23. " SPIS183 ,SPI Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " SPIS182 ,SPI Status Bit 182" "Low,High" bitfld.long 0x00 21. " SPIS181 ,SPI Status Bit 181" "Low,High" bitfld.long 0x00 20. " SPIS180 ,SPI Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " SPIS179 ,SPI Status Bit 179" "Low,High" bitfld.long 0x00 18. " SPIS178 ,SPI Status Bit 178" "Low,High" bitfld.long 0x00 17. " SPIS177 ,SPI Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " SPIS176 ,SPI Status Bit 176" "Low,High" bitfld.long 0x00 15. " SPIS175 ,SPI Status Bit 175" "Low,High" bitfld.long 0x00 14. " SPIS174 ,SPI Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " SPIS173 ,SPI Status Bit 173" "Low,High" bitfld.long 0x00 12. " SPIS172 ,SPI Status Bit 172" "Low,High" bitfld.long 0x00 11. " SPIS171 ,SPI Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " SPIS170 ,SPI Status Bit 170" "Low,High" bitfld.long 0x00 9. " SPIS169 ,SPI Status Bit 169" "Low,High" bitfld.long 0x00 8. " SPIS168 ,SPI Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " SPIS167 ,SPI Status Bit 167" "Low,High" bitfld.long 0x00 6. " SPIS166 ,SPI Status Bit 166" "Low,High" bitfld.long 0x00 5. " SPIS165 ,SPI Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " SPIS164 ,SPI Status Bit 164" "Low,High" bitfld.long 0x00 3. " SPIS163 ,SPI Status Bit 163" "Low,High" bitfld.long 0x00 2. " SPIS162 ,SPI Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " SPIS161 ,SPI Status Bit 161" "Low,High" bitfld.long 0x00 0. " SPIS160 ,SPI Status Bit 160" "Low,High" else hgroup.long 0xC094++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) rgroup.long 0xC098++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " SPIS223 ,SPI Status Bit 223" "Low,High" bitfld.long 0x00 30. " SPIS222 ,SPI Status Bit 222" "Low,High" bitfld.long 0x00 29. " SPIS221 ,SPI Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " SPIS220 ,SPI Status Bit 220" "Low,High" bitfld.long 0x00 27. " SPIS219 ,SPI Status Bit 219" "Low,High" bitfld.long 0x00 26. " SPIS218 ,SPI Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " SPIS217 ,SPI Status Bit 217" "Low,High" bitfld.long 0x00 24. " SPIS216 ,SPI Status Bit 216" "Low,High" bitfld.long 0x00 23. " SPIS215 ,SPI Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " SPIS214 ,SPI Status Bit 214" "Low,High" bitfld.long 0x00 21. " SPIS213 ,SPI Status Bit 213" "Low,High" bitfld.long 0x00 20. " SPIS212 ,SPI Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " SPIS211 ,SPI Status Bit 211" "Low,High" bitfld.long 0x00 18. " SPIS210 ,SPI Status Bit 210" "Low,High" bitfld.long 0x00 17. " SPIS209 ,SPI Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " SPIS208 ,SPI Status Bit 208" "Low,High" bitfld.long 0x00 15. " SPIS207 ,SPI Status Bit 207" "Low,High" bitfld.long 0x00 14. " SPIS206 ,SPI Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " SPIS205 ,SPI Status Bit 205" "Low,High" bitfld.long 0x00 12. " SPIS204 ,SPI Status Bit 204" "Low,High" bitfld.long 0x00 11. " SPIS203 ,SPI Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " SPIS202 ,SPI Status Bit 202" "Low,High" bitfld.long 0x00 9. " SPIS201 ,SPI Status Bit 201" "Low,High" bitfld.long 0x00 8. " SPIS200 ,SPI Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " SPIS199 ,SPI Status Bit 199" "Low,High" bitfld.long 0x00 6. " SPIS198 ,SPI Status Bit 198" "Low,High" bitfld.long 0x00 5. " SPIS197 ,SPI Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " SPIS196 ,SPI Status Bit 196" "Low,High" bitfld.long 0x00 3. " SPIS195 ,SPI Status Bit 195" "Low,High" bitfld.long 0x00 2. " SPIS194 ,SPI Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " SPIS193 ,SPI Status Bit 193" "Low,High" bitfld.long 0x00 0. " SPIS192 ,SPI Status Bit 192" "Low,High" else hgroup.long 0xC098++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) rgroup.long 0xC09C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " SPIS255 ,SPI Status Bit 255" "Low,High" bitfld.long 0x00 30. " SPIS254 ,SPI Status Bit 254" "Low,High" bitfld.long 0x00 29. " SPIS253 ,SPI Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " SPIS252 ,SPI Status Bit 252" "Low,High" bitfld.long 0x00 27. " SPIS251 ,SPI Status Bit 251" "Low,High" bitfld.long 0x00 26. " SPIS250 ,SPI Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " SPIS249 ,SPI Status Bit 249" "Low,High" bitfld.long 0x00 24. " SPIS248 ,SPI Status Bit 248" "Low,High" bitfld.long 0x00 23. " SPIS247 ,SPI Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " SPIS246 ,SPI Status Bit 246" "Low,High" bitfld.long 0x00 21. " SPIS245 ,SPI Status Bit 245" "Low,High" bitfld.long 0x00 20. " SPIS244 ,SPI Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " SPIS243 ,SPI Status Bit 243" "Low,High" bitfld.long 0x00 18. " SPIS242 ,SPI Status Bit 242" "Low,High" bitfld.long 0x00 17. " SPIS241 ,SPI Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " SPIS240 ,SPI Status Bit 240" "Low,High" bitfld.long 0x00 15. " SPIS239 ,SPI Status Bit 239" "Low,High" bitfld.long 0x00 14. " SPIS238 ,SPI Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " SPIS237 ,SPI Status Bit 237" "Low,High" bitfld.long 0x00 12. " SPIS236 ,SPI Status Bit 236" "Low,High" bitfld.long 0x00 11. " SPIS235 ,SPI Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " SPIS234 ,SPI Status Bit 234" "Low,High" bitfld.long 0x00 9. " SPIS233 ,SPI Status Bit 233" "Low,High" bitfld.long 0x00 8. " SPIS232 ,SPI Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " SPIS231 ,SPI Status Bit 231" "Low,High" bitfld.long 0x00 6. " SPIS230 ,SPI Status Bit 230" "Low,High" bitfld.long 0x00 5. " SPIS229 ,SPI Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " SPIS228 ,SPI Status Bit 228" "Low,High" bitfld.long 0x00 3. " SPIS227 ,SPI Status Bit 227" "Low,High" bitfld.long 0x00 2. " SPIS226 ,SPI Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " SPIS225 ,SPI Status Bit 225" "Low,High" bitfld.long 0x00 0. " SPIS224 ,SPI Status Bit 224" "Low,High" else hgroup.long 0xC09C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) rgroup.long 0xC0A0++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " SPIS287 ,SPI Status Bit 287" "Low,High" bitfld.long 0x00 30. " SPIS286 ,SPI Status Bit 286" "Low,High" bitfld.long 0x00 29. " SPIS285 ,SPI Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " SPIS284 ,SPI Status Bit 284" "Low,High" bitfld.long 0x00 27. " SPIS283 ,SPI Status Bit 283" "Low,High" bitfld.long 0x00 26. " SPIS282 ,SPI Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " SPIS281 ,SPI Status Bit 281" "Low,High" bitfld.long 0x00 24. " SPIS280 ,SPI Status Bit 280" "Low,High" bitfld.long 0x00 23. " SPIS279 ,SPI Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " SPIS278 ,SPI Status Bit 278" "Low,High" bitfld.long 0x00 21. " SPIS277 ,SPI Status Bit 277" "Low,High" bitfld.long 0x00 20. " SPIS276 ,SPI Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " SPIS275 ,SPI Status Bit 275" "Low,High" bitfld.long 0x00 18. " SPIS274 ,SPI Status Bit 274" "Low,High" bitfld.long 0x00 17. " SPIS273 ,SPI Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " SPIS272 ,SPI Status Bit 272" "Low,High" bitfld.long 0x00 15. " SPIS271 ,SPI Status Bit 271" "Low,High" bitfld.long 0x00 14. " SPIS270 ,SPI Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " SPIS269 ,SPI Status Bit 269" "Low,High" bitfld.long 0x00 12. " SPIS268 ,SPI Status Bit 268" "Low,High" bitfld.long 0x00 11. " SPIS267 ,SPI Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " SPIS266 ,SPI Status Bit 266" "Low,High" bitfld.long 0x00 9. " SPIS265 ,SPI Status Bit 265" "Low,High" bitfld.long 0x00 8. " SPIS264 ,SPI Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " SPIS263 ,SPI Status Bit 263" "Low,High" bitfld.long 0x00 6. " SPIS262 ,SPI Status Bit 262" "Low,High" bitfld.long 0x00 5. " SPIS261 ,SPI Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " SPIS260 ,SPI Status Bit 260" "Low,High" bitfld.long 0x00 3. " SPIS259 ,SPI Status Bit 259" "Low,High" bitfld.long 0x00 2. " SPIS258 ,SPI Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " SPIS257 ,SPI Status Bit 257" "Low,High" bitfld.long 0x00 0. " SPIS256 ,SPI Status Bit 256" "Low,High" else hgroup.long 0xC0A0++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) rgroup.long 0xC0A4++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " SPIS319 ,SPI Status Bit 319" "Low,High" bitfld.long 0x00 30. " SPIS318 ,SPI Status Bit 318" "Low,High" bitfld.long 0x00 29. " SPIS317 ,SPI Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " SPIS316 ,SPI Status Bit 316" "Low,High" bitfld.long 0x00 27. " SPIS315 ,SPI Status Bit 315" "Low,High" bitfld.long 0x00 26. " SPIS314 ,SPI Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " SPIS313 ,SPI Status Bit 313" "Low,High" bitfld.long 0x00 24. " SPIS312 ,SPI Status Bit 312" "Low,High" bitfld.long 0x00 23. " SPIS311 ,SPI Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " SPIS310 ,SPI Status Bit 310" "Low,High" bitfld.long 0x00 21. " SPIS309 ,SPI Status Bit 309" "Low,High" bitfld.long 0x00 20. " SPIS308 ,SPI Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " SPIS307 ,SPI Status Bit 307" "Low,High" bitfld.long 0x00 18. " SPIS306 ,SPI Status Bit 306" "Low,High" bitfld.long 0x00 17. " SPIS305 ,SPI Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " SPIS304 ,SPI Status Bit 304" "Low,High" bitfld.long 0x00 15. " SPIS303 ,SPI Status Bit 303" "Low,High" bitfld.long 0x00 14. " SPIS302 ,SPI Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " SPIS301 ,SPI Status Bit 301" "Low,High" bitfld.long 0x00 12. " SPIS300 ,SPI Status Bit 300" "Low,High" bitfld.long 0x00 11. " SPIS299 ,SPI Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " SPIS298 ,SPI Status Bit 298" "Low,High" bitfld.long 0x00 9. " SPIS297 ,SPI Status Bit 297" "Low,High" bitfld.long 0x00 8. " SPIS296 ,SPI Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " SPIS295 ,SPI Status Bit 295" "Low,High" bitfld.long 0x00 6. " SPIS294 ,SPI Status Bit 294" "Low,High" bitfld.long 0x00 5. " SPIS293 ,SPI Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " SPIS292 ,SPI Status Bit 292" "Low,High" bitfld.long 0x00 3. " SPIS291 ,SPI Status Bit 291" "Low,High" bitfld.long 0x00 2. " SPIS290 ,SPI Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " SPIS289 ,SPI Status Bit 289" "Low,High" bitfld.long 0x00 0. " SPIS288 ,SPI Status Bit 288" "Low,High" else hgroup.long 0xC0A4++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) rgroup.long 0xC0A8++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " SPIS351 ,SPI Status Bit 351" "Low,High" bitfld.long 0x00 30. " SPIS350 ,SPI Status Bit 350" "Low,High" bitfld.long 0x00 29. " SPIS349 ,SPI Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " SPIS348 ,SPI Status Bit 348" "Low,High" bitfld.long 0x00 27. " SPIS347 ,SPI Status Bit 347" "Low,High" bitfld.long 0x00 26. " SPIS346 ,SPI Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " SPIS345 ,SPI Status Bit 345" "Low,High" bitfld.long 0x00 24. " SPIS344 ,SPI Status Bit 344" "Low,High" bitfld.long 0x00 23. " SPIS343 ,SPI Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " SPIS342 ,SPI Status Bit 342" "Low,High" bitfld.long 0x00 21. " SPIS341 ,SPI Status Bit 341" "Low,High" bitfld.long 0x00 20. " SPIS340 ,SPI Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " SPIS339 ,SPI Status Bit 339" "Low,High" bitfld.long 0x00 18. " SPIS338 ,SPI Status Bit 338" "Low,High" bitfld.long 0x00 17. " SPIS337 ,SPI Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " SPIS336 ,SPI Status Bit 336" "Low,High" bitfld.long 0x00 15. " SPIS335 ,SPI Status Bit 335" "Low,High" bitfld.long 0x00 14. " SPIS334 ,SPI Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " SPIS333 ,SPI Status Bit 333" "Low,High" bitfld.long 0x00 12. " SPIS332 ,SPI Status Bit 332" "Low,High" bitfld.long 0x00 11. " SPIS331 ,SPI Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " SPIS330 ,SPI Status Bit 330" "Low,High" bitfld.long 0x00 9. " SPIS329 ,SPI Status Bit 329" "Low,High" bitfld.long 0x00 8. " SPIS328 ,SPI Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " SPIS327 ,SPI Status Bit 327" "Low,High" bitfld.long 0x00 6. " SPIS326 ,SPI Status Bit 326" "Low,High" bitfld.long 0x00 5. " SPIS325 ,SPI Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " SPIS324 ,SPI Status Bit 324" "Low,High" bitfld.long 0x00 3. " SPIS323 ,SPI Status Bit 323" "Low,High" bitfld.long 0x00 2. " SPIS322 ,SPI Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " SPIS321 ,SPI Status Bit 321" "Low,High" bitfld.long 0x00 0. " SPIS320 ,SPI Status Bit 320" "Low,High" else hgroup.long 0xC0A8++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) rgroup.long 0xC0AC++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " SPIS383 ,SPI Status Bit 383" "Low,High" bitfld.long 0x00 30. " SPIS382 ,SPI Status Bit 382" "Low,High" bitfld.long 0x00 29. " SPIS381 ,SPI Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " SPIS380 ,SPI Status Bit 380" "Low,High" bitfld.long 0x00 27. " SPIS379 ,SPI Status Bit 379" "Low,High" bitfld.long 0x00 26. " SPIS378 ,SPI Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " SPIS377 ,SPI Status Bit 377" "Low,High" bitfld.long 0x00 24. " SPIS376 ,SPI Status Bit 376" "Low,High" bitfld.long 0x00 23. " SPIS375 ,SPI Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " SPIS374 ,SPI Status Bit 374" "Low,High" bitfld.long 0x00 21. " SPIS373 ,SPI Status Bit 373" "Low,High" bitfld.long 0x00 20. " SPIS372 ,SPI Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " SPIS371 ,SPI Status Bit 371" "Low,High" bitfld.long 0x00 18. " SPIS370 ,SPI Status Bit 370" "Low,High" bitfld.long 0x00 17. " SPIS369 ,SPI Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " SPIS368 ,SPI Status Bit 368" "Low,High" bitfld.long 0x00 15. " SPIS367 ,SPI Status Bit 367" "Low,High" bitfld.long 0x00 14. " SPIS366 ,SPI Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " SPIS365 ,SPI Status Bit 365" "Low,High" bitfld.long 0x00 12. " SPIS364 ,SPI Status Bit 364" "Low,High" bitfld.long 0x00 11. " SPIS363 ,SPI Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " SPIS362 ,SPI Status Bit 362" "Low,High" bitfld.long 0x00 9. " SPIS361 ,SPI Status Bit 361" "Low,High" bitfld.long 0x00 8. " SPIS360 ,SPI Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " SPIS359 ,SPI Status Bit 359" "Low,High" bitfld.long 0x00 6. " SPIS358 ,SPI Status Bit 358" "Low,High" bitfld.long 0x00 5. " SPIS357 ,SPI Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " SPIS356 ,SPI Status Bit 356" "Low,High" bitfld.long 0x00 3. " SPIS355 ,SPI Status Bit 355" "Low,High" bitfld.long 0x00 2. " SPIS354 ,SPI Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " SPIS353 ,SPI Status Bit 353" "Low,High" bitfld.long 0x00 0. " SPIS352 ,SPI Status Bit 352" "Low,High" else hgroup.long 0xC0AC++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) rgroup.long 0xC0B0++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " SPIS415 ,SPI Status Bit 415" "Low,High" bitfld.long 0x00 30. " SPIS414 ,SPI Status Bit 414" "Low,High" bitfld.long 0x00 29. " SPIS413 ,SPI Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " SPIS412 ,SPI Status Bit 412" "Low,High" bitfld.long 0x00 27. " SPIS411 ,SPI Status Bit 411" "Low,High" bitfld.long 0x00 26. " SPIS410 ,SPI Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " SPIS409 ,SPI Status Bit 409" "Low,High" bitfld.long 0x00 24. " SPIS408 ,SPI Status Bit 408" "Low,High" bitfld.long 0x00 23. " SPIS407 ,SPI Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " SPIS406 ,SPI Status Bit 406" "Low,High" bitfld.long 0x00 21. " SPIS405 ,SPI Status Bit 405" "Low,High" bitfld.long 0x00 20. " SPIS404 ,SPI Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " SPIS403 ,SPI Status Bit 403" "Low,High" bitfld.long 0x00 18. " SPIS402 ,SPI Status Bit 402" "Low,High" bitfld.long 0x00 17. " SPIS401 ,SPI Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " SPIS400 ,SPI Status Bit 400" "Low,High" bitfld.long 0x00 15. " SPIS399 ,SPI Status Bit 399" "Low,High" bitfld.long 0x00 14. " SPIS398 ,SPI Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " SPIS397 ,SPI Status Bit 397" "Low,High" bitfld.long 0x00 12. " SPIS396 ,SPI Status Bit 396" "Low,High" bitfld.long 0x00 11. " SPIS395 ,SPI Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " SPIS394 ,SPI Status Bit 394" "Low,High" bitfld.long 0x00 9. " SPIS393 ,SPI Status Bit 393" "Low,High" bitfld.long 0x00 8. " SPIS392 ,SPI Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " SPIS391 ,SPI Status Bit 391" "Low,High" bitfld.long 0x00 6. " SPIS390 ,SPI Status Bit 390" "Low,High" bitfld.long 0x00 5. " SPIS389 ,SPI Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " SPIS388 ,SPI Status Bit 388" "Low,High" bitfld.long 0x00 3. " SPIS387 ,SPI Status Bit 387" "Low,High" bitfld.long 0x00 2. " SPIS386 ,SPI Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " SPIS385 ,SPI Status Bit 385" "Low,High" bitfld.long 0x00 0. " SPIS384 ,SPI Status Bit 384" "Low,High" else hgroup.long 0xC0B0++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) rgroup.long 0xC0B4++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " SPIS447 ,SPI Status Bit 447" "Low,High" bitfld.long 0x00 30. " SPIS446 ,SPI Status Bit 446" "Low,High" bitfld.long 0x00 29. " SPIS445 ,SPI Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " SPIS444 ,SPI Status Bit 444" "Low,High" bitfld.long 0x00 27. " SPIS443 ,SPI Status Bit 443" "Low,High" bitfld.long 0x00 26. " SPIS442 ,SPI Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " SPIS441 ,SPI Status Bit 441" "Low,High" bitfld.long 0x00 24. " SPIS440 ,SPI Status Bit 440" "Low,High" bitfld.long 0x00 23. " SPIS439 ,SPI Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " SPIS438 ,SPI Status Bit 438" "Low,High" bitfld.long 0x00 21. " SPIS437 ,SPI Status Bit 437" "Low,High" bitfld.long 0x00 20. " SPIS436 ,SPI Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " SPIS435 ,SPI Status Bit 435" "Low,High" bitfld.long 0x00 18. " SPIS434 ,SPI Status Bit 434" "Low,High" bitfld.long 0x00 17. " SPIS433 ,SPI Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " SPIS432 ,SPI Status Bit 432" "Low,High" bitfld.long 0x00 15. " SPIS431 ,SPI Status Bit 431" "Low,High" bitfld.long 0x00 14. " SPIS430 ,SPI Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " SPIS429 ,SPI Status Bit 429" "Low,High" bitfld.long 0x00 12. " SPIS428 ,SPI Status Bit 428" "Low,High" bitfld.long 0x00 11. " SPIS427 ,SPI Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " SPIS426 ,SPI Status Bit 426" "Low,High" bitfld.long 0x00 9. " SPIS425 ,SPI Status Bit 425" "Low,High" bitfld.long 0x00 8. " SPIS424 ,SPI Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " SPIS423 ,SPI Status Bit 423" "Low,High" bitfld.long 0x00 6. " SPIS422 ,SPI Status Bit 422" "Low,High" bitfld.long 0x00 5. " SPIS421 ,SPI Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " SPIS420 ,SPI Status Bit 420" "Low,High" bitfld.long 0x00 3. " SPIS419 ,SPI Status Bit 419" "Low,High" bitfld.long 0x00 2. " SPIS418 ,SPI Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " SPIS417 ,SPI Status Bit 417" "Low,High" bitfld.long 0x00 0. " SPIS416 ,SPI Status Bit 416" "Low,High" else hgroup.long 0xC0B4++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) rgroup.long 0xC0B8++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " SPIS479 ,SPI Status Bit 479" "Low,High" bitfld.long 0x00 30. " SPIS478 ,SPI Status Bit 478" "Low,High" bitfld.long 0x00 29. " SPIS477 ,SPI Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " SPIS476 ,SPI Status Bit 476" "Low,High" bitfld.long 0x00 27. " SPIS475 ,SPI Status Bit 475" "Low,High" bitfld.long 0x00 26. " SPIS474 ,SPI Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " SPIS473 ,SPI Status Bit 473" "Low,High" bitfld.long 0x00 24. " SPIS472 ,SPI Status Bit 472" "Low,High" bitfld.long 0x00 23. " SPIS471 ,SPI Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " SPIS470 ,SPI Status Bit 470" "Low,High" bitfld.long 0x00 21. " SPIS469 ,SPI Status Bit 469" "Low,High" bitfld.long 0x00 20. " SPIS468 ,SPI Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " SPIS467 ,SPI Status Bit 467" "Low,High" bitfld.long 0x00 18. " SPIS466 ,SPI Status Bit 466" "Low,High" bitfld.long 0x00 17. " SPIS465 ,SPI Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " SPIS464 ,SPI Status Bit 464" "Low,High" bitfld.long 0x00 15. " SPIS463 ,SPI Status Bit 463" "Low,High" bitfld.long 0x00 14. " SPIS462 ,SPI Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " SPIS461 ,SPI Status Bit 461" "Low,High" bitfld.long 0x00 12. " SPIS460 ,SPI Status Bit 460" "Low,High" bitfld.long 0x00 11. " SPIS459 ,SPI Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " SPIS458 ,SPI Status Bit 458" "Low,High" bitfld.long 0x00 9. " SPIS457 ,SPI Status Bit 457" "Low,High" bitfld.long 0x00 8. " SPIS456 ,SPI Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " SPIS455 ,SPI Status Bit 455" "Low,High" bitfld.long 0x00 6. " SPIS454 ,SPI Status Bit 454" "Low,High" bitfld.long 0x00 5. " SPIS453 ,SPI Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " SPIS452 ,SPI Status Bit 452" "Low,High" bitfld.long 0x00 3. " SPIS451 ,SPI Status Bit 451" "Low,High" bitfld.long 0x00 2. " SPIS450 ,SPI Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " SPIS449 ,SPI Status Bit 449" "Low,High" bitfld.long 0x00 0. " SPIS448 ,SPI Status Bit 448" "Low,High" else hgroup.long 0xC0B8++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) rgroup.long 0xC0BC++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " SPIS511 ,SPI Status Bit 511" "Low,High" bitfld.long 0x00 30. " SPIS510 ,SPI Status Bit 510" "Low,High" bitfld.long 0x00 29. " SPIS509 ,SPI Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " SPIS508 ,SPI Status Bit 508" "Low,High" bitfld.long 0x00 27. " SPIS507 ,SPI Status Bit 507" "Low,High" bitfld.long 0x00 26. " SPIS506 ,SPI Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " SPIS505 ,SPI Status Bit 505" "Low,High" bitfld.long 0x00 24. " SPIS504 ,SPI Status Bit 504" "Low,High" bitfld.long 0x00 23. " SPIS503 ,SPI Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " SPIS502 ,SPI Status Bit 502" "Low,High" bitfld.long 0x00 21. " SPIS501 ,SPI Status Bit 501" "Low,High" bitfld.long 0x00 20. " SPIS500 ,SPI Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " SPIS499 ,SPI Status Bit 499" "Low,High" bitfld.long 0x00 18. " SPIS498 ,SPI Status Bit 498" "Low,High" bitfld.long 0x00 17. " SPIS497 ,SPI Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " SPIS496 ,SPI Status Bit 496" "Low,High" bitfld.long 0x00 15. " SPIS495 ,SPI Status Bit 495" "Low,High" bitfld.long 0x00 14. " SPIS494 ,SPI Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " SPIS493 ,SPI Status Bit 493" "Low,High" bitfld.long 0x00 12. " SPIS492 ,SPI Status Bit 492" "Low,High" bitfld.long 0x00 11. " SPIS491 ,SPI Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " SPIS490 ,SPI Status Bit 490" "Low,High" bitfld.long 0x00 9. " SPIS489 ,SPI Status Bit 489" "Low,High" bitfld.long 0x00 8. " SPIS488 ,SPI Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " SPIS487 ,SPI Status Bit 487" "Low,High" bitfld.long 0x00 6. " SPIS486 ,SPI Status Bit 486" "Low,High" bitfld.long 0x00 5. " SPIS485 ,SPI Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " SPIS484 ,SPI Status Bit 484" "Low,High" bitfld.long 0x00 3. " SPIS483 ,SPI Status Bit 483" "Low,High" bitfld.long 0x00 2. " SPIS482 ,SPI Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " SPIS481 ,SPI Status Bit 481" "Low,High" bitfld.long 0x00 0. " SPIS480 ,SPI Status Bit 480" "Low,High" else hgroup.long 0xC0BC++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) rgroup.long 0xC0C0++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " SPIS543 ,SPI Status Bit 543" "Low,High" bitfld.long 0x00 30. " SPIS542 ,SPI Status Bit 542" "Low,High" bitfld.long 0x00 29. " SPIS541 ,SPI Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " SPIS540 ,SPI Status Bit 540" "Low,High" bitfld.long 0x00 27. " SPIS539 ,SPI Status Bit 539" "Low,High" bitfld.long 0x00 26. " SPIS538 ,SPI Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " SPIS537 ,SPI Status Bit 537" "Low,High" bitfld.long 0x00 24. " SPIS536 ,SPI Status Bit 536" "Low,High" bitfld.long 0x00 23. " SPIS535 ,SPI Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " SPIS534 ,SPI Status Bit 534" "Low,High" bitfld.long 0x00 21. " SPIS533 ,SPI Status Bit 533" "Low,High" bitfld.long 0x00 20. " SPIS532 ,SPI Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " SPIS531 ,SPI Status Bit 531" "Low,High" bitfld.long 0x00 18. " SPIS530 ,SPI Status Bit 530" "Low,High" bitfld.long 0x00 17. " SPIS529 ,SPI Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " SPIS528 ,SPI Status Bit 528" "Low,High" bitfld.long 0x00 15. " SPIS527 ,SPI Status Bit 527" "Low,High" bitfld.long 0x00 14. " SPIS526 ,SPI Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " SPIS525 ,SPI Status Bit 525" "Low,High" bitfld.long 0x00 12. " SPIS524 ,SPI Status Bit 524" "Low,High" bitfld.long 0x00 11. " SPIS523 ,SPI Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " SPIS522 ,SPI Status Bit 522" "Low,High" bitfld.long 0x00 9. " SPIS521 ,SPI Status Bit 521" "Low,High" bitfld.long 0x00 8. " SPIS520 ,SPI Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " SPIS519 ,SPI Status Bit 519" "Low,High" bitfld.long 0x00 6. " SPIS518 ,SPI Status Bit 518" "Low,High" bitfld.long 0x00 5. " SPIS517 ,SPI Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " SPIS516 ,SPI Status Bit 516" "Low,High" bitfld.long 0x00 3. " SPIS515 ,SPI Status Bit 515" "Low,High" bitfld.long 0x00 2. " SPIS514 ,SPI Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " SPIS513 ,SPI Status Bit 513" "Low,High" bitfld.long 0x00 0. " SPIS512 ,SPI Status Bit 512" "Low,High" else hgroup.long 0xC0C0++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) rgroup.long 0xC0C4++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " SPIS575 ,SPI Status Bit 575" "Low,High" bitfld.long 0x00 30. " SPIS574 ,SPI Status Bit 574" "Low,High" bitfld.long 0x00 29. " SPIS573 ,SPI Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " SPIS572 ,SPI Status Bit 572" "Low,High" bitfld.long 0x00 27. " SPIS571 ,SPI Status Bit 571" "Low,High" bitfld.long 0x00 26. " SPIS570 ,SPI Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " SPIS569 ,SPI Status Bit 569" "Low,High" bitfld.long 0x00 24. " SPIS568 ,SPI Status Bit 568" "Low,High" bitfld.long 0x00 23. " SPIS567 ,SPI Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " SPIS566 ,SPI Status Bit 566" "Low,High" bitfld.long 0x00 21. " SPIS565 ,SPI Status Bit 565" "Low,High" bitfld.long 0x00 20. " SPIS564 ,SPI Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " SPIS563 ,SPI Status Bit 563" "Low,High" bitfld.long 0x00 18. " SPIS562 ,SPI Status Bit 562" "Low,High" bitfld.long 0x00 17. " SPIS561 ,SPI Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " SPIS560 ,SPI Status Bit 560" "Low,High" bitfld.long 0x00 15. " SPIS559 ,SPI Status Bit 559" "Low,High" bitfld.long 0x00 14. " SPIS558 ,SPI Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " SPIS557 ,SPI Status Bit 557" "Low,High" bitfld.long 0x00 12. " SPIS556 ,SPI Status Bit 556" "Low,High" bitfld.long 0x00 11. " SPIS555 ,SPI Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " SPIS554 ,SPI Status Bit 554" "Low,High" bitfld.long 0x00 9. " SPIS553 ,SPI Status Bit 553" "Low,High" bitfld.long 0x00 8. " SPIS552 ,SPI Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " SPIS551 ,SPI Status Bit 551" "Low,High" bitfld.long 0x00 6. " SPIS550 ,SPI Status Bit 550" "Low,High" bitfld.long 0x00 5. " SPIS549 ,SPI Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " SPIS548 ,SPI Status Bit 548" "Low,High" bitfld.long 0x00 3. " SPIS547 ,SPI Status Bit 547" "Low,High" bitfld.long 0x00 2. " SPIS546 ,SPI Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " SPIS545 ,SPI Status Bit 545" "Low,High" bitfld.long 0x00 0. " SPIS544 ,SPI Status Bit 544" "Low,High" else hgroup.long 0xC0C4++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) rgroup.long 0xC0C8++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " SPIS607 ,SPI Status Bit 607" "Low,High" bitfld.long 0x00 30. " SPIS606 ,SPI Status Bit 606" "Low,High" bitfld.long 0x00 29. " SPIS605 ,SPI Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " SPIS604 ,SPI Status Bit 604" "Low,High" bitfld.long 0x00 27. " SPIS603 ,SPI Status Bit 603" "Low,High" bitfld.long 0x00 26. " SPIS602 ,SPI Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " SPIS601 ,SPI Status Bit 601" "Low,High" bitfld.long 0x00 24. " SPIS600 ,SPI Status Bit 600" "Low,High" bitfld.long 0x00 23. " SPIS599 ,SPI Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " SPIS598 ,SPI Status Bit 598" "Low,High" bitfld.long 0x00 21. " SPIS597 ,SPI Status Bit 597" "Low,High" bitfld.long 0x00 20. " SPIS596 ,SPI Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " SPIS595 ,SPI Status Bit 595" "Low,High" bitfld.long 0x00 18. " SPIS594 ,SPI Status Bit 594" "Low,High" bitfld.long 0x00 17. " SPIS593 ,SPI Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " SPIS592 ,SPI Status Bit 592" "Low,High" bitfld.long 0x00 15. " SPIS591 ,SPI Status Bit 591" "Low,High" bitfld.long 0x00 14. " SPIS590 ,SPI Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " SPIS589 ,SPI Status Bit 589" "Low,High" bitfld.long 0x00 12. " SPIS588 ,SPI Status Bit 588" "Low,High" bitfld.long 0x00 11. " SPIS587 ,SPI Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " SPIS586 ,SPI Status Bit 586" "Low,High" bitfld.long 0x00 9. " SPIS585 ,SPI Status Bit 585" "Low,High" bitfld.long 0x00 8. " SPIS584 ,SPI Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " SPIS583 ,SPI Status Bit 583" "Low,High" bitfld.long 0x00 6. " SPIS582 ,SPI Status Bit 582" "Low,High" bitfld.long 0x00 5. " SPIS581 ,SPI Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " SPIS580 ,SPI Status Bit 580" "Low,High" bitfld.long 0x00 3. " SPIS579 ,SPI Status Bit 579" "Low,High" bitfld.long 0x00 2. " SPIS578 ,SPI Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " SPIS577 ,SPI Status Bit 577" "Low,High" bitfld.long 0x00 0. " SPIS576 ,SPI Status Bit 576" "Low,High" else hgroup.long 0xC0C8++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) rgroup.long 0xC0CC++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " SPIS639 ,SPI Status Bit 639" "Low,High" bitfld.long 0x00 30. " SPIS638 ,SPI Status Bit 638" "Low,High" bitfld.long 0x00 29. " SPIS637 ,SPI Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " SPIS636 ,SPI Status Bit 636" "Low,High" bitfld.long 0x00 27. " SPIS635 ,SPI Status Bit 635" "Low,High" bitfld.long 0x00 26. " SPIS634 ,SPI Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " SPIS633 ,SPI Status Bit 633" "Low,High" bitfld.long 0x00 24. " SPIS632 ,SPI Status Bit 632" "Low,High" bitfld.long 0x00 23. " SPIS631 ,SPI Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " SPIS630 ,SPI Status Bit 630" "Low,High" bitfld.long 0x00 21. " SPIS629 ,SPI Status Bit 629" "Low,High" bitfld.long 0x00 20. " SPIS628 ,SPI Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " SPIS627 ,SPI Status Bit 627" "Low,High" bitfld.long 0x00 18. " SPIS626 ,SPI Status Bit 626" "Low,High" bitfld.long 0x00 17. " SPIS625 ,SPI Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " SPIS624 ,SPI Status Bit 624" "Low,High" bitfld.long 0x00 15. " SPIS623 ,SPI Status Bit 623" "Low,High" bitfld.long 0x00 14. " SPIS622 ,SPI Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " SPIS621 ,SPI Status Bit 621" "Low,High" bitfld.long 0x00 12. " SPIS620 ,SPI Status Bit 620" "Low,High" bitfld.long 0x00 11. " SPIS619 ,SPI Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " SPIS618 ,SPI Status Bit 618" "Low,High" bitfld.long 0x00 9. " SPIS617 ,SPI Status Bit 617" "Low,High" bitfld.long 0x00 8. " SPIS616 ,SPI Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " SPIS615 ,SPI Status Bit 615" "Low,High" bitfld.long 0x00 6. " SPIS614 ,SPI Status Bit 614" "Low,High" bitfld.long 0x00 5. " SPIS613 ,SPI Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " SPIS612 ,SPI Status Bit 612" "Low,High" bitfld.long 0x00 3. " SPIS611 ,SPI Status Bit 611" "Low,High" bitfld.long 0x00 2. " SPIS610 ,SPI Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " SPIS609 ,SPI Status Bit 609" "Low,High" bitfld.long 0x00 0. " SPIS608 ,SPI Status Bit 608" "Low,High" else hgroup.long 0xC0CC++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) rgroup.long 0xC0D0++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " SPIS671 ,SPI Status Bit 671" "Low,High" bitfld.long 0x00 30. " SPIS670 ,SPI Status Bit 670" "Low,High" bitfld.long 0x00 29. " SPIS669 ,SPI Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " SPIS668 ,SPI Status Bit 668" "Low,High" bitfld.long 0x00 27. " SPIS667 ,SPI Status Bit 667" "Low,High" bitfld.long 0x00 26. " SPIS666 ,SPI Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " SPIS665 ,SPI Status Bit 665" "Low,High" bitfld.long 0x00 24. " SPIS664 ,SPI Status Bit 664" "Low,High" bitfld.long 0x00 23. " SPIS663 ,SPI Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " SPIS662 ,SPI Status Bit 662" "Low,High" bitfld.long 0x00 21. " SPIS661 ,SPI Status Bit 661" "Low,High" bitfld.long 0x00 20. " SPIS660 ,SPI Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " SPIS659 ,SPI Status Bit 659" "Low,High" bitfld.long 0x00 18. " SPIS658 ,SPI Status Bit 658" "Low,High" bitfld.long 0x00 17. " SPIS657 ,SPI Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " SPIS656 ,SPI Status Bit 656" "Low,High" bitfld.long 0x00 15. " SPIS655 ,SPI Status Bit 655" "Low,High" bitfld.long 0x00 14. " SPIS654 ,SPI Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " SPIS653 ,SPI Status Bit 653" "Low,High" bitfld.long 0x00 12. " SPIS652 ,SPI Status Bit 652" "Low,High" bitfld.long 0x00 11. " SPIS651 ,SPI Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " SPIS650 ,SPI Status Bit 650" "Low,High" bitfld.long 0x00 9. " SPIS649 ,SPI Status Bit 649" "Low,High" bitfld.long 0x00 8. " SPIS648 ,SPI Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " SPIS647 ,SPI Status Bit 647" "Low,High" bitfld.long 0x00 6. " SPIS646 ,SPI Status Bit 646" "Low,High" bitfld.long 0x00 5. " SPIS645 ,SPI Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " SPIS644 ,SPI Status Bit 644" "Low,High" bitfld.long 0x00 3. " SPIS643 ,SPI Status Bit 643" "Low,High" bitfld.long 0x00 2. " SPIS642 ,SPI Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " SPIS641 ,SPI Status Bit 641" "Low,High" bitfld.long 0x00 0. " SPIS640 ,SPI Status Bit 640" "Low,High" else hgroup.long 0xC0D0++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) rgroup.long 0xC0D4++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " SPIS703 ,SPI Status Bit 703" "Low,High" bitfld.long 0x00 30. " SPIS702 ,SPI Status Bit 702" "Low,High" bitfld.long 0x00 29. " SPIS701 ,SPI Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " SPIS700 ,SPI Status Bit 700" "Low,High" bitfld.long 0x00 27. " SPIS699 ,SPI Status Bit 699" "Low,High" bitfld.long 0x00 26. " SPIS698 ,SPI Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " SPIS697 ,SPI Status Bit 697" "Low,High" bitfld.long 0x00 24. " SPIS696 ,SPI Status Bit 696" "Low,High" bitfld.long 0x00 23. " SPIS695 ,SPI Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " SPIS694 ,SPI Status Bit 694" "Low,High" bitfld.long 0x00 21. " SPIS693 ,SPI Status Bit 693" "Low,High" bitfld.long 0x00 20. " SPIS692 ,SPI Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " SPIS691 ,SPI Status Bit 691" "Low,High" bitfld.long 0x00 18. " SPIS690 ,SPI Status Bit 690" "Low,High" bitfld.long 0x00 17. " SPIS689 ,SPI Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " SPIS688 ,SPI Status Bit 688" "Low,High" bitfld.long 0x00 15. " SPIS687 ,SPI Status Bit 687" "Low,High" bitfld.long 0x00 14. " SPIS686 ,SPI Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " SPIS685 ,SPI Status Bit 685" "Low,High" bitfld.long 0x00 12. " SPIS684 ,SPI Status Bit 684" "Low,High" bitfld.long 0x00 11. " SPIS683 ,SPI Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " SPIS682 ,SPI Status Bit 682" "Low,High" bitfld.long 0x00 9. " SPIS681 ,SPI Status Bit 681" "Low,High" bitfld.long 0x00 8. " SPIS680 ,SPI Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " SPIS679 ,SPI Status Bit 679" "Low,High" bitfld.long 0x00 6. " SPIS678 ,SPI Status Bit 678" "Low,High" bitfld.long 0x00 5. " SPIS677 ,SPI Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " SPIS676 ,SPI Status Bit 676" "Low,High" bitfld.long 0x00 3. " SPIS675 ,SPI Status Bit 675" "Low,High" bitfld.long 0x00 2. " SPIS674 ,SPI Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " SPIS673 ,SPI Status Bit 673" "Low,High" bitfld.long 0x00 0. " SPIS672 ,SPI Status Bit 672" "Low,High" else hgroup.long 0xC0D4++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) rgroup.long 0xC0D8++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " SPIS735 ,SPI Status Bit 735" "Low,High" bitfld.long 0x00 30. " SPIS734 ,SPI Status Bit 734" "Low,High" bitfld.long 0x00 29. " SPIS733 ,SPI Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " SPIS732 ,SPI Status Bit 732" "Low,High" bitfld.long 0x00 27. " SPIS731 ,SPI Status Bit 731" "Low,High" bitfld.long 0x00 26. " SPIS730 ,SPI Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " SPIS729 ,SPI Status Bit 729" "Low,High" bitfld.long 0x00 24. " SPIS728 ,SPI Status Bit 728" "Low,High" bitfld.long 0x00 23. " SPIS727 ,SPI Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " SPIS726 ,SPI Status Bit 726" "Low,High" bitfld.long 0x00 21. " SPIS725 ,SPI Status Bit 725" "Low,High" bitfld.long 0x00 20. " SPIS724 ,SPI Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " SPIS723 ,SPI Status Bit 723" "Low,High" bitfld.long 0x00 18. " SPIS722 ,SPI Status Bit 722" "Low,High" bitfld.long 0x00 17. " SPIS721 ,SPI Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " SPIS720 ,SPI Status Bit 720" "Low,High" bitfld.long 0x00 15. " SPIS719 ,SPI Status Bit 719" "Low,High" bitfld.long 0x00 14. " SPIS718 ,SPI Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " SPIS717 ,SPI Status Bit 717" "Low,High" bitfld.long 0x00 12. " SPIS716 ,SPI Status Bit 716" "Low,High" bitfld.long 0x00 11. " SPIS715 ,SPI Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " SPIS714 ,SPI Status Bit 714" "Low,High" bitfld.long 0x00 9. " SPIS713 ,SPI Status Bit 713" "Low,High" bitfld.long 0x00 8. " SPIS712 ,SPI Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " SPIS711 ,SPI Status Bit 711" "Low,High" bitfld.long 0x00 6. " SPIS710 ,SPI Status Bit 710" "Low,High" bitfld.long 0x00 5. " SPIS709 ,SPI Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " SPIS708 ,SPI Status Bit 708" "Low,High" bitfld.long 0x00 3. " SPIS707 ,SPI Status Bit 707" "Low,High" bitfld.long 0x00 2. " SPIS706 ,SPI Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " SPIS705 ,SPI Status Bit 705" "Low,High" bitfld.long 0x00 0. " SPIS704 ,SPI Status Bit 704" "Low,High" else hgroup.long 0xC0D8++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) rgroup.long 0xC0DC++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " SPIS767 ,SPI Status Bit 767" "Low,High" bitfld.long 0x00 30. " SPIS766 ,SPI Status Bit 766" "Low,High" bitfld.long 0x00 29. " SPIS765 ,SPI Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " SPIS764 ,SPI Status Bit 764" "Low,High" bitfld.long 0x00 27. " SPIS763 ,SPI Status Bit 763" "Low,High" bitfld.long 0x00 26. " SPIS762 ,SPI Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " SPIS761 ,SPI Status Bit 761" "Low,High" bitfld.long 0x00 24. " SPIS760 ,SPI Status Bit 760" "Low,High" bitfld.long 0x00 23. " SPIS759 ,SPI Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " SPIS758 ,SPI Status Bit 758" "Low,High" bitfld.long 0x00 21. " SPIS757 ,SPI Status Bit 757" "Low,High" bitfld.long 0x00 20. " SPIS756 ,SPI Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " SPIS755 ,SPI Status Bit 755" "Low,High" bitfld.long 0x00 18. " SPIS754 ,SPI Status Bit 754" "Low,High" bitfld.long 0x00 17. " SPIS753 ,SPI Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " SPIS752 ,SPI Status Bit 752" "Low,High" bitfld.long 0x00 15. " SPIS751 ,SPI Status Bit 751" "Low,High" bitfld.long 0x00 14. " SPIS750 ,SPI Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " SPIS749 ,SPI Status Bit 749" "Low,High" bitfld.long 0x00 12. " SPIS748 ,SPI Status Bit 748" "Low,High" bitfld.long 0x00 11. " SPIS747 ,SPI Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " SPIS746 ,SPI Status Bit 746" "Low,High" bitfld.long 0x00 9. " SPIS745 ,SPI Status Bit 745" "Low,High" bitfld.long 0x00 8. " SPIS744 ,SPI Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " SPIS743 ,SPI Status Bit 743" "Low,High" bitfld.long 0x00 6. " SPIS742 ,SPI Status Bit 742" "Low,High" bitfld.long 0x00 5. " SPIS741 ,SPI Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " SPIS740 ,SPI Status Bit 740" "Low,High" bitfld.long 0x00 3. " SPIS739 ,SPI Status Bit 739" "Low,High" bitfld.long 0x00 2. " SPIS738 ,SPI Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " SPIS737 ,SPI Status Bit 737" "Low,High" bitfld.long 0x00 0. " SPIS736 ,SPI Status Bit 736" "Low,High" else hgroup.long 0xC0DC++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) rgroup.long 0xC0E0++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " SPIS799 ,SPI Status Bit 799" "Low,High" bitfld.long 0x00 30. " SPIS798 ,SPI Status Bit 798" "Low,High" bitfld.long 0x00 29. " SPIS797 ,SPI Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " SPIS796 ,SPI Status Bit 796" "Low,High" bitfld.long 0x00 27. " SPIS795 ,SPI Status Bit 795" "Low,High" bitfld.long 0x00 26. " SPIS794 ,SPI Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " SPIS793 ,SPI Status Bit 793" "Low,High" bitfld.long 0x00 24. " SPIS792 ,SPI Status Bit 792" "Low,High" bitfld.long 0x00 23. " SPIS791 ,SPI Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " SPIS790 ,SPI Status Bit 790" "Low,High" bitfld.long 0x00 21. " SPIS789 ,SPI Status Bit 789" "Low,High" bitfld.long 0x00 20. " SPIS788 ,SPI Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " SPIS787 ,SPI Status Bit 787" "Low,High" bitfld.long 0x00 18. " SPIS786 ,SPI Status Bit 786" "Low,High" bitfld.long 0x00 17. " SPIS785 ,SPI Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " SPIS784 ,SPI Status Bit 784" "Low,High" bitfld.long 0x00 15. " SPIS783 ,SPI Status Bit 783" "Low,High" bitfld.long 0x00 14. " SPIS782 ,SPI Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " SPIS781 ,SPI Status Bit 781" "Low,High" bitfld.long 0x00 12. " SPIS780 ,SPI Status Bit 780" "Low,High" bitfld.long 0x00 11. " SPIS779 ,SPI Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " SPIS778 ,SPI Status Bit 778" "Low,High" bitfld.long 0x00 9. " SPIS777 ,SPI Status Bit 777" "Low,High" bitfld.long 0x00 8. " SPIS776 ,SPI Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " SPIS775 ,SPI Status Bit 775" "Low,High" bitfld.long 0x00 6. " SPIS774 ,SPI Status Bit 774" "Low,High" bitfld.long 0x00 5. " SPIS773 ,SPI Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " SPIS772 ,SPI Status Bit 772" "Low,High" bitfld.long 0x00 3. " SPIS771 ,SPI Status Bit 771" "Low,High" bitfld.long 0x00 2. " SPIS770 ,SPI Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " SPIS769 ,SPI Status Bit 769" "Low,High" bitfld.long 0x00 0. " SPIS768 ,SPI Status Bit 768" "Low,High" else hgroup.long 0xC0E0++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) rgroup.long 0xC0E4++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " SPIS831 ,SPI Status Bit 831" "Low,High" bitfld.long 0x00 30. " SPIS830 ,SPI Status Bit 830" "Low,High" bitfld.long 0x00 29. " SPIS829 ,SPI Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " SPIS828 ,SPI Status Bit 828" "Low,High" bitfld.long 0x00 27. " SPIS827 ,SPI Status Bit 827" "Low,High" bitfld.long 0x00 26. " SPIS826 ,SPI Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " SPIS825 ,SPI Status Bit 825" "Low,High" bitfld.long 0x00 24. " SPIS824 ,SPI Status Bit 824" "Low,High" bitfld.long 0x00 23. " SPIS823 ,SPI Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " SPIS822 ,SPI Status Bit 822" "Low,High" bitfld.long 0x00 21. " SPIS821 ,SPI Status Bit 821" "Low,High" bitfld.long 0x00 20. " SPIS820 ,SPI Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " SPIS819 ,SPI Status Bit 819" "Low,High" bitfld.long 0x00 18. " SPIS818 ,SPI Status Bit 818" "Low,High" bitfld.long 0x00 17. " SPIS817 ,SPI Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " SPIS816 ,SPI Status Bit 816" "Low,High" bitfld.long 0x00 15. " SPIS815 ,SPI Status Bit 815" "Low,High" bitfld.long 0x00 14. " SPIS814 ,SPI Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " SPIS813 ,SPI Status Bit 813" "Low,High" bitfld.long 0x00 12. " SPIS812 ,SPI Status Bit 812" "Low,High" bitfld.long 0x00 11. " SPIS811 ,SPI Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " SPIS810 ,SPI Status Bit 810" "Low,High" bitfld.long 0x00 9. " SPIS809 ,SPI Status Bit 809" "Low,High" bitfld.long 0x00 8. " SPIS808 ,SPI Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " SPIS807 ,SPI Status Bit 807" "Low,High" bitfld.long 0x00 6. " SPIS806 ,SPI Status Bit 806" "Low,High" bitfld.long 0x00 5. " SPIS805 ,SPI Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " SPIS804 ,SPI Status Bit 804" "Low,High" bitfld.long 0x00 3. " SPIS803 ,SPI Status Bit 803" "Low,High" bitfld.long 0x00 2. " SPIS802 ,SPI Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " SPIS801 ,SPI Status Bit 801" "Low,High" bitfld.long 0x00 0. " SPIS800 ,SPI Status Bit 800" "Low,High" else hgroup.long 0xC0E4++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) rgroup.long 0xC0E8++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " SPIS863 ,SPI Status Bit 863" "Low,High" bitfld.long 0x00 30. " SPIS862 ,SPI Status Bit 862" "Low,High" bitfld.long 0x00 29. " SPIS861 ,SPI Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " SPIS860 ,SPI Status Bit 860" "Low,High" bitfld.long 0x00 27. " SPIS859 ,SPI Status Bit 859" "Low,High" bitfld.long 0x00 26. " SPIS858 ,SPI Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " SPIS857 ,SPI Status Bit 857" "Low,High" bitfld.long 0x00 24. " SPIS856 ,SPI Status Bit 856" "Low,High" bitfld.long 0x00 23. " SPIS855 ,SPI Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " SPIS854 ,SPI Status Bit 854" "Low,High" bitfld.long 0x00 21. " SPIS853 ,SPI Status Bit 853" "Low,High" bitfld.long 0x00 20. " SPIS852 ,SPI Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " SPIS851 ,SPI Status Bit 851" "Low,High" bitfld.long 0x00 18. " SPIS850 ,SPI Status Bit 850" "Low,High" bitfld.long 0x00 17. " SPIS849 ,SPI Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " SPIS848 ,SPI Status Bit 848" "Low,High" bitfld.long 0x00 15. " SPIS847 ,SPI Status Bit 847" "Low,High" bitfld.long 0x00 14. " SPIS846 ,SPI Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " SPIS845 ,SPI Status Bit 845" "Low,High" bitfld.long 0x00 12. " SPIS844 ,SPI Status Bit 844" "Low,High" bitfld.long 0x00 11. " SPIS843 ,SPI Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " SPIS842 ,SPI Status Bit 842" "Low,High" bitfld.long 0x00 9. " SPIS841 ,SPI Status Bit 841" "Low,High" bitfld.long 0x00 8. " SPIS840 ,SPI Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " SPIS839 ,SPI Status Bit 839" "Low,High" bitfld.long 0x00 6. " SPIS838 ,SPI Status Bit 838" "Low,High" bitfld.long 0x00 5. " SPIS837 ,SPI Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " SPIS836 ,SPI Status Bit 836" "Low,High" bitfld.long 0x00 3. " SPIS835 ,SPI Status Bit 835" "Low,High" bitfld.long 0x00 2. " SPIS834 ,SPI Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " SPIS833 ,SPI Status Bit 833" "Low,High" bitfld.long 0x00 0. " SPIS832 ,SPI Status Bit 832" "Low,High" else hgroup.long 0xC0E8++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) rgroup.long 0xC0EC++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " SPIS895 ,SPI Status Bit 895" "Low,High" bitfld.long 0x00 30. " SPIS894 ,SPI Status Bit 894" "Low,High" bitfld.long 0x00 29. " SPIS893 ,SPI Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " SPIS892 ,SPI Status Bit 892" "Low,High" bitfld.long 0x00 27. " SPIS891 ,SPI Status Bit 891" "Low,High" bitfld.long 0x00 26. " SPIS890 ,SPI Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " SPIS889 ,SPI Status Bit 889" "Low,High" bitfld.long 0x00 24. " SPIS888 ,SPI Status Bit 888" "Low,High" bitfld.long 0x00 23. " SPIS887 ,SPI Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " SPIS886 ,SPI Status Bit 886" "Low,High" bitfld.long 0x00 21. " SPIS885 ,SPI Status Bit 885" "Low,High" bitfld.long 0x00 20. " SPIS884 ,SPI Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " SPIS883 ,SPI Status Bit 883" "Low,High" bitfld.long 0x00 18. " SPIS882 ,SPI Status Bit 882" "Low,High" bitfld.long 0x00 17. " SPIS881 ,SPI Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " SPIS880 ,SPI Status Bit 880" "Low,High" bitfld.long 0x00 15. " SPIS879 ,SPI Status Bit 879" "Low,High" bitfld.long 0x00 14. " SPIS878 ,SPI Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " SPIS877 ,SPI Status Bit 877" "Low,High" bitfld.long 0x00 12. " SPIS876 ,SPI Status Bit 876" "Low,High" bitfld.long 0x00 11. " SPIS875 ,SPI Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " SPIS874 ,SPI Status Bit 874" "Low,High" bitfld.long 0x00 9. " SPIS873 ,SPI Status Bit 873" "Low,High" bitfld.long 0x00 8. " SPIS872 ,SPI Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " SPIS871 ,SPI Status Bit 871" "Low,High" bitfld.long 0x00 6. " SPIS870 ,SPI Status Bit 870" "Low,High" bitfld.long 0x00 5. " SPIS869 ,SPI Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " SPIS868 ,SPI Status Bit 868" "Low,High" bitfld.long 0x00 3. " SPIS867 ,SPI Status Bit 867" "Low,High" bitfld.long 0x00 2. " SPIS866 ,SPI Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " SPIS865 ,SPI Status Bit 865" "Low,High" bitfld.long 0x00 0. " SPIS864 ,SPI Status Bit 864" "Low,High" else hgroup.long 0xC0EC++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) rgroup.long 0xC0F0++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " SPIS927 ,SPI Status Bit 927" "Low,High" bitfld.long 0x00 30. " SPIS926 ,SPI Status Bit 926" "Low,High" bitfld.long 0x00 29. " SPIS925 ,SPI Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " SPIS924 ,SPI Status Bit 924" "Low,High" bitfld.long 0x00 27. " SPIS923 ,SPI Status Bit 923" "Low,High" bitfld.long 0x00 26. " SPIS922 ,SPI Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " SPIS921 ,SPI Status Bit 921" "Low,High" bitfld.long 0x00 24. " SPIS920 ,SPI Status Bit 920" "Low,High" bitfld.long 0x00 23. " SPIS919 ,SPI Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " SPIS918 ,SPI Status Bit 918" "Low,High" bitfld.long 0x00 21. " SPIS917 ,SPI Status Bit 917" "Low,High" bitfld.long 0x00 20. " SPIS916 ,SPI Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " SPIS915 ,SPI Status Bit 915" "Low,High" bitfld.long 0x00 18. " SPIS914 ,SPI Status Bit 914" "Low,High" bitfld.long 0x00 17. " SPIS913 ,SPI Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " SPIS912 ,SPI Status Bit 912" "Low,High" bitfld.long 0x00 15. " SPIS911 ,SPI Status Bit 911" "Low,High" bitfld.long 0x00 14. " SPIS910 ,SPI Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " SPIS909 ,SPI Status Bit 909" "Low,High" bitfld.long 0x00 12. " SPIS908 ,SPI Status Bit 908" "Low,High" bitfld.long 0x00 11. " SPIS907 ,SPI Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " SPIS906 ,SPI Status Bit 906" "Low,High" bitfld.long 0x00 9. " SPIS905 ,SPI Status Bit 905" "Low,High" bitfld.long 0x00 8. " SPIS904 ,SPI Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " SPIS903 ,SPI Status Bit 903" "Low,High" bitfld.long 0x00 6. " SPIS902 ,SPI Status Bit 902" "Low,High" bitfld.long 0x00 5. " SPIS901 ,SPI Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " SPIS900 ,SPI Status Bit 900" "Low,High" bitfld.long 0x00 3. " SPIS899 ,SPI Status Bit 899" "Low,High" bitfld.long 0x00 2. " SPIS898 ,SPI Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " SPIS897 ,SPI Status Bit 897" "Low,High" bitfld.long 0x00 0. " SPIS896 ,SPI Status Bit 896" "Low,High" else hgroup.long 0xC0F0++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) rgroup.long 0xC0F4++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " SPIS959 ,SPI Status Bit 959" "Low,High" bitfld.long 0x00 30. " SPIS958 ,SPI Status Bit 958" "Low,High" bitfld.long 0x00 29. " SPIS957 ,SPI Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " SPIS956 ,SPI Status Bit 956" "Low,High" bitfld.long 0x00 27. " SPIS955 ,SPI Status Bit 955" "Low,High" bitfld.long 0x00 26. " SPIS954 ,SPI Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " SPIS953 ,SPI Status Bit 953" "Low,High" bitfld.long 0x00 24. " SPIS952 ,SPI Status Bit 952" "Low,High" bitfld.long 0x00 23. " SPIS951 ,SPI Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " SPIS950 ,SPI Status Bit 950" "Low,High" bitfld.long 0x00 21. " SPIS949 ,SPI Status Bit 949" "Low,High" bitfld.long 0x00 20. " SPIS948 ,SPI Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " SPIS947 ,SPI Status Bit 947" "Low,High" bitfld.long 0x00 18. " SPIS946 ,SPI Status Bit 946" "Low,High" bitfld.long 0x00 17. " SPIS945 ,SPI Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " SPIS944 ,SPI Status Bit 944" "Low,High" bitfld.long 0x00 15. " SPIS943 ,SPI Status Bit 943" "Low,High" bitfld.long 0x00 14. " SPIS942 ,SPI Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " SPIS941 ,SPI Status Bit 941" "Low,High" bitfld.long 0x00 12. " SPIS940 ,SPI Status Bit 940" "Low,High" bitfld.long 0x00 11. " SPIS939 ,SPI Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " SPIS938 ,SPI Status Bit 938" "Low,High" bitfld.long 0x00 9. " SPIS937 ,SPI Status Bit 937" "Low,High" bitfld.long 0x00 8. " SPIS936 ,SPI Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " SPIS935 ,SPI Status Bit 935" "Low,High" bitfld.long 0x00 6. " SPIS934 ,SPI Status Bit 934" "Low,High" bitfld.long 0x00 5. " SPIS933 ,SPI Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " SPIS932 ,SPI Status Bit 932" "Low,High" bitfld.long 0x00 3. " SPIS931 ,SPI Status Bit 931" "Low,High" bitfld.long 0x00 2. " SPIS930 ,SPI Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " SPIS929 ,SPI Status Bit 929" "Low,High" bitfld.long 0x00 0. " SPIS928 ,SPI Status Bit 928" "Low,High" else hgroup.long 0xC0F4++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) rgroup.long 0xC0F8++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " SPIS991 ,SPI Status Bit 991" "Low,High" bitfld.long 0x00 30. " SPIS990 ,SPI Status Bit 990" "Low,High" bitfld.long 0x00 29. " SPIS989 ,SPI Status Bit 989" "Low,High" textline " " bitfld.long 0x00 28. " SPIS988 ,SPI Status Bit 988" "Low,High" bitfld.long 0x00 27. " SPIS987 ,SPI Status Bit 987" "Low,High" bitfld.long 0x00 26. " SPIS986 ,SPI Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " SPIS985 ,SPI Status Bit 985" "Low,High" bitfld.long 0x00 24. " SPIS984 ,SPI Status Bit 984" "Low,High" bitfld.long 0x00 23. " SPIS983 ,SPI Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " SPIS982 ,SPI Status Bit 982" "Low,High" bitfld.long 0x00 21. " SPIS981 ,SPI Status Bit 981" "Low,High" bitfld.long 0x00 20. " SPIS980 ,SPI Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " SPIS979 ,SPI Status Bit 979" "Low,High" bitfld.long 0x00 18. " SPIS978 ,SPI Status Bit 978" "Low,High" bitfld.long 0x00 17. " SPIS977 ,SPI Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " SPIS976 ,SPI Status Bit 976" "Low,High" bitfld.long 0x00 15. " SPIS975 ,SPI Status Bit 975" "Low,High" bitfld.long 0x00 14. " SPIS974 ,SPI Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " SPIS973 ,SPI Status Bit 973" "Low,High" bitfld.long 0x00 12. " SPIS972 ,SPI Status Bit 972" "Low,High" bitfld.long 0x00 11. " SPIS971 ,SPI Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " SPIS970 ,SPI Status Bit 970" "Low,High" bitfld.long 0x00 9. " SPIS969 ,SPI Status Bit 969" "Low,High" bitfld.long 0x00 8. " SPIS968 ,SPI Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " SPIS967 ,SPI Status Bit 967" "Low,High" bitfld.long 0x00 6. " SPIS966 ,SPI Status Bit 966" "Low,High" bitfld.long 0x00 5. " SPIS965 ,SPI Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " SPIS964 ,SPI Status Bit 964" "Low,High" bitfld.long 0x00 3. " SPIS963 ,SPI Status Bit 963" "Low,High" bitfld.long 0x00 2. " SPIS962 ,SPI Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " SPIS961 ,SPI Status Bit 961" "Low,High" bitfld.long 0x00 0. " SPIS960 ,SPI Status Bit 960" "Low,High" else hgroup.long 0xC0F8++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) width 24. tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" textline " " bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" textline " " bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "16-bit,GITS_TYPER.CIDBITS value" textline " " hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "GICR_TYPER.PROCESSOR_NUMBER value,Base physical address" textline " " bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x20000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" textline " " bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." textline " " bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif textline " " wgroup.long 0xC000++0x03 line.long 0x00 "GITS_TRKCTLR,Tracking Control Register" bitfld.long 0x00 1. " LPI_TRACK ,Write 0b1 to capture information about the next interrupt that the ITS generated or failed to generate because of misprogramming" "No effect,Capture" bitfld.long 0x00 0. " CACHE_COUNT_RESET ,Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR" "No effect,Reset" if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x1F)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 6. " PID_OUT_OF_RANGE ,Indicates that the LPI PID is larger than that allowed by the IDbits field in the GICR_PROPBASER" "0,1" bitfld.long 0x00 5. " TARGET_OUT_OF_RANGE ,Indicates that target collection has not been successfully mapped using MAPC or that the target core does not have LPIs enabled in GICR_CTLR" "0,1" textline " " bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0xF)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 4. " NO_TRANSLATION ,Indicates that no valid MAPI or MAPVI has successfully been performed for this combination of input ID and Device ID" "0,1" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" textline " " bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 3. " INPUT_ID_OUT_OF_RANGE ,Indicates that the input ID is larger than that allowed for that Device ID which is set during the MAPD command or it is larger than 65535" "0,1" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" textline " " bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" elif (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x3)==0x01) rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 2. " DEVICE_ID_UNMAPPED ,Indicates that no valid MAPD has successfully been performed for this Device ID" "0,1" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" textline " " bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" else rgroup.long 0xC004++0x03 line.long 0x00 "GITS_TRKR,Tracking Status Register" bitfld.long 0x00 1. " DEVICE_ID_OUT_OF_RANGE ,Indicates that the Device ID is larger than that allowed by the Size and Page Size in GITS_BASER0 or larger than the number of Device IDs configured" "0,1" bitfld.long 0x00 0. " LPI_TRACKED ,Indicates that the LPI tracking initiated by the LPI track bit in the GITS_TRKCTLR register is completed and the contents of the Debug Tracked registers are valid" "Not valid,Valid" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC008++0x03 line.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" hexmask.long.tbyte 0x00 0.--19. 1. " LPI_DID ,The Device ID for the interrupt that was tracked" else hgroup.long 0xC008++0x03 hide.long 0x00 "GITS_TRKDIDR,Debug Tracked DID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC00C++0x03 line.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_PID ,The ID after translation for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC00C++0x03 hide.long 0x00 "GITS_TRKPIDR,Debug Tracked PID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x01)==0x01) rgroup.long 0xC010++0x03 line.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" hexmask.long.word 0x00 0.--15. 1. " LPI_ID ,The ID before translation of the interrupt that was tracked" else hgroup.long 0xC010++0x03 hide.long 0x00 "GITS_TRKVIDR,Debug Tracked ID Register" endif if (((per.l((COMP.BASE("GICD",-1.)+0x20000)+0xC004))&0x7F)==0x01) rgroup.long 0xC014++0x03 line.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" hexmask.long.byte 0x00 0.--6. 1. " LPI_TARGET_CORE ,The target core for an interrupt that was tracked and generated an LPI successfully" else hgroup.long 0xC014++0x03 hide.long 0x00 "GITS_TRKTGTR,Debug Tracked Target Register" endif rgroup.long 0xC018++0x03 line.long 0x00 "GITS_TRKICR,Debug ITE Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " ITE_CACHE_HITS ,Number of hits in the ITE cache" hexmask.long.word 0x00 0.--15. 1. " ITE_CACHE_MISSES ,Number of misses in the ITE cache" rgroup.long 0xC01C++0x03 line.long 0x00 "GITS_TRKLCR,Debug LPI Cache Statistics" hexmask.long.word 0x00 16.--31. 1. " LPI_CACHE_HITS ,Number of hits in the LPI cache" hexmask.long.word 0x00 0.--15. 1. " LPI_CACHE_MISSES ,Number of misses in the LPI cache" rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" textline " " bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " base (COMP.BASE("GICD",-1.)+0x20000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x20000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end width 0x0B base COMP.BASE("GICR",-1.) width 17. tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" textline " " bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" textline " " hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "All levels,AFF3,AFF3/AFF2,AFF3/AFF2/AFF1" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" textline " " bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" textline " " bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-500 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" textline " " bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-500 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" textline " " else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" textline " " bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.quad 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" textline " " hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." textline " " bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" textline " " tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif textline " " width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" textline " " bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" textline " " bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" textline " " bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" textline " " bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" textline " " bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" textline " " bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" textline " " bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" textline " " bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" textline " " bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" textline " " bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" textline " " else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." textline " " bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." textline " " else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" textline " " bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" textline " " bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" textline " " bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" textline " " bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" textline " " bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-500 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B tree.end tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "Reset" base ad:0x01E60000 width 17. group.long 0x00++0x07 line.long 0x00 "RSTCR,Reset Control Register" bitfld.long 0x00 1. " RESET_REQ ,Hardware reset request" "Not requested,Requested" line.long 0x04 "RSTCRSP,Service Processor Reset Control Register" bitfld.long 0x04 1. " RESET_REQ ,Hardware reset request" "Not requested,Requested" group.long 0x10++0x03 line.long 0x00 "RSTRQMR1,Reset Request Mask Register" bitfld.long 0x00 20. " SRDS_RST_MSK ,SerDes reset request event mask" "Not masked,Masked" bitfld.long 0x00 19. " RPTOE_MSK ,RCPM time out reset request event mask" "Not masked,Masked" newline bitfld.long 0x00 17. " MBEE_MSK ,Multi-bit ECC error reset request mask" "Not masked,Masked" bitfld.long 0x00 16. " SDC_MSK ,Security debug controller error reset request mask" "Not masked,Masked" newline bitfld.long 0x00 14. " SFP_MSK ,Security fuse processor error during POR fuse process reset mask" "Not masked,Masked" bitfld.long 0x00 13. " SP_MSK ,Service processor error reset mask" "Not masked,Masked" newline bitfld.long 0x00 0. " MC_MSK ,Management complex debug reset request mask" "Not masked,Masked" group.long 0x18++0x03 line.long 0x00 "RSTRQSR1,Reset Request Status Register" eventfld.long 0x00 23. " MC_WDT_RR ,MC processor reset request" "Not requested,Requested" eventfld.long 0x00 22. " TZONE_WDT_RR ,Trust zone WDOG reset request" "Not active,Active" newline eventfld.long 0x00 21. " SP_WDT_RR ,Service processor WDOG reset request" "Not active,Active" eventfld.long 0x00 20. " SRDS_RST_RR ,SerDes reset event" "Not active,Active" newline eventfld.long 0x00 19. " RPTOE_RR ,RCPM time out reset request event" "Not active,Active" eventfld.long 0x00 18. " PBSTE_RR ,POR BIST error reset request" "Not active,Active" newline eventfld.long 0x00 17. " MBEE_RR ,Multi-bit ECC reset request" "Not active,Active" eventfld.long 0x00 16. " SDC_RR ,Security debug controller reset request" "Not active,Active" newline eventfld.long 0x00 15. " SECM_RR ,Security monitor error during POR fuse process caused reset request" "Not active,Active" eventfld.long 0x00 14. " SFP_RR ,Security fuse processor error during POR fuse process caused reset request" "Not active,Active" newline eventfld.long 0x00 13. " SP_RR ,Service processor reset request" "No request,Request" eventfld.long 0x00 11. " SW_RR ,Software settable reset requested" "Not active,Active" newline eventfld.long 0x00 10. " WDT_RR ,WDT reset request requires device level" "Not active,Active" eventfld.long 0x00 9. " IFC_RR ,IFC reset request requires device level" "Not active,Active" newline rbitfld.long 0x00 0. " MC_RR ,Management complex debug reset request" "Not active,Active" group.long 0x20++0x03 line.long 0x00 "RSTRQWDTMRL,Reset Request WDT Mask Register" bitfld.long 0x00 7. " WDT_MSK7 ,Thread 7 WDT reset request mask" "Not masked,Masked" bitfld.long 0x00 6. " WDT_MSK6 ,Thread 6 WDT reset request mask" "Not masked,Masked" newline bitfld.long 0x00 5. " WDT_MSK5 ,Thread 5 WDT reset request mask" "Not masked,Masked" bitfld.long 0x00 4. " WDT_MSK4 ,Thread 4 WDT reset request mask" "Not masked,Masked" newline bitfld.long 0x00 3. " WDT_MSK3 ,Thread 3 WDT reset request mask" "Not masked,Masked" bitfld.long 0x00 2. " WDT_MSK2 ,Thread 2 WDT reset request mask" "Not masked,Masked" newline bitfld.long 0x00 1. " WDT_MSK1 ,Thread 1 WDT reset request mask" "Not masked,Masked" bitfld.long 0x00 0. " WDT_MSK0 ,Thread 0 WDT reset request mask" "Not masked,Masked" group.long 0x30++0x03 line.long 0x00 "RSTRQWDTSRL,Reset Request WDT Status Register" eventfld.long 0x00 7. " WDT_RR7 ,Thread 7 WDT reset request status" "Not requested,Requested" eventfld.long 0x00 6. " WDT_RR6 ,Thread 6 WDT reset request status" "Not requested,Requested" newline eventfld.long 0x00 5. " WDT_RR5 ,Thread 5 WDT reset request status" "Not requested,Requested" eventfld.long 0x00 4. " WDT_RR4 ,Thread 4 WDT reset request status" "Not requested,Requested" newline eventfld.long 0x00 3. " WDT_RR3 ,Thread 3 WDT reset request status" "Not requested,Requested" eventfld.long 0x00 2. " WDT_RR2 ,Thread 2 WDT reset request status" "Not requested,Requested" newline eventfld.long 0x00 1. " WDT_RR1 ,Thread 1 WDT reset request status" "Not requested,Requested" eventfld.long 0x00 0. " WDT_RR0 ,Thread 0 WDT reset request status" "Not requested,Requested" group.long 0x60++0x03 line.long 0x00 "BRR,Boot Release Register" bitfld.long 0x00 11. " CR11 ,Core 11 release for booting" "Not released,Released" bitfld.long 0x00 10. " CR10 ,Core 10 release for booting" "Not released,Released" newline bitfld.long 0x00 9. " CR9 ,Core 9 release for booting" "Not released,Released" bitfld.long 0x00 8. " CR8 ,Core 8 release for booting" "Not released,Released" newline bitfld.long 0x00 7. " CR7 ,Core 7 release for booting" "Not released,Released" bitfld.long 0x00 6. " CR6 ,Core 6 release for booting" "Not released,Released" newline bitfld.long 0x00 5. " CR5 ,Core 5 release for booting" "Not released,Released" bitfld.long 0x00 4. " CR4 ,Core 4 release for booting" "Not released,Released" newline bitfld.long 0x00 3. " CR3 ,Core 3 release for booting" "Not released,Released" bitfld.long 0x00 2. " CR2 ,Core 2 release for booting" "Not released,Released" newline bitfld.long 0x00 1. " CR1 ,Core 1 release for booting" "Not released,Released" bitfld.long 0x00 0. " CR0 ,Core 0 release for booting" "Not released,Released" rgroup.long 0x90++0x03 line.long 0x00 "BRCORENBR,Core Enable Boot Release Status Register" bitfld.long 0x00 0.--5. " CORE_NBR ,Designates which core will begin booting out of reset" "Core 0,Core 1,Core 2,Core 3,Core 4,Core 5,Core 6,Core 7,Core 8,Core 9,Core 10,Core 11,?..." rgroup.long 0x100++0x03 line.long 0x00 "RCW_REQR,RCW Request Register" bitfld.long 0x00 0. " RQ ,Service processor was requested for RCW loading" "Not requested,Requested" group.long 0x104++0x03 line.long 0x00 "RCW_COMPLETIONR,RCW Completion Register" hexmask.long.byte 0x00 16.--23. 1. " ERR_CODE ,RCW error code" bitfld.long 0x00 0. " DONE ,RCW done bit" "Not done,Done" rgroup.long 0x110++0x03 line.long 0x00 "PBI_REQR,PBI Request Register" bitfld.long 0x00 0. " RQ ,Service processor was requested for PBI phase" "Not requested,Requested" group.long 0x114++0x03 line.long 0x00 "PBI_COMPLETIONR,PBI Completion Register" hexmask.long.byte 0x00 16.--23. 1. " ERR_CODE ,PBI error code" bitfld.long 0x00 0. " DONE ,PBI done bit" "Not done,Done" group.long 0x400++0x03 line.long 0x00 "CRSTSR0,Core Reset Status Register 0" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x404++0x03 line.long 0x00 "CRSTSR1,Core Reset Status Register 1" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x408++0x03 line.long 0x00 "CRSTSR2,Core Reset Status Register 2" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x40C++0x03 line.long 0x00 "CRSTSR3,Core Reset Status Register 3" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x410++0x03 line.long 0x00 "CRSTSR4,Core Reset Status Register 4" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x414++0x03 line.long 0x00 "CRSTSR5,Core Reset Status Register 5" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x418++0x03 line.long 0x00 "CRSTSR6,Core Reset Status Register 6" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x41C++0x03 line.long 0x00 "CRSTSR7,Core Reset Status Register 7" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x420++0x03 line.long 0x00 "CRSTSR8,Core Reset Status Register 8" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x424++0x03 line.long 0x00 "CRSTSR9,Core Reset Status Register 9" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x428++0x03 line.long 0x00 "CRSTSR10,Core Reset Status Register 10" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x42C++0x03 line.long 0x00 "CRSTSR11,Core Reset Status Register 11" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" newline eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0xA00++0x03 line.long 0x00 "QMBM_WARMRST,QMBM Warm Reset Control Register" bitfld.long 0x00 0. " BMQM_WARMRST ,Bman warm reset" "No reset,Reset" rgroup.long 0xBF8++0x07 line.long 0x00 "IP_REV1,IP Block Revision Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,Block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" newline hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "IP_REV2,IP Block Revision Register 2" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,Block ID" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,IP block configuration ID" width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "Clocking" base ad:0x01300000 width 10. tree "CGU CGA Registers" group.long 0x10++0x03 line.long 0x00 "HWA1CSR,HWA 1 Clock Control / Status Register" bitfld.long 0x00 27.--30. " HWACLKSEL ,HWA clock mux clock frequency selection" "Sync,A/B PLL1 / 1,A/B PLL1 / 2,A/B PLL1 / 3,A/B PLL1 / 4,HWAMUX1 ext clk src,PLL2 / 2 or 3,?..." group.long 0x30++0x03 line.long 0x00 "HWA2CSR,HWA 2 Clock Control / Status Register" bitfld.long 0x00 27.--30. " HWACLKSEL ,HWA clock mux clock frequency selection" "Sync,A/B PLL2 / 1,A/B PLL2 / 2,A/B PLL2 / 3,A/B PLL2 / 4,HWAMUX2 ext clk src,PLL1 / 2 or 3,?..." group.long 0x50++0x03 line.long 0x00 "HWA3CSR,HWA 3 Clock Control / Status Register" bitfld.long 0x00 27.--30. " HWACLKSEL ,HWA clock mux clock frequency selection" "Sync,,,,,HWAMUX3 ext clk src,PLL2 / 2 or 3,?..." tree.end base ad:0x1360000 tree "Platform GCU Registers" group.long 0x00++0x03 line.long 0x00 "CLKCSR,Platform Clock Control / Status Register" bitfld.long 0x00 16. " CLKOEN1 ,CLKOUT1 pad enable" "Disabled,Enabled" bitfld.long 0x00 11.--15. " CLKODIV1[1:0] ,Signal for observation selection" ",,,,,,,,,,,,,,,,,,,,,,,,pll_clk_out_div8,pll_clk_out_div6,pll_clk_out_div4,pll_clk_out_div2,pll_clk_out,pll_vco_bufout,pll_fdbk_bufout,pll_sys_bufout" bitfld.long 0x00 9.--10. " CLKODIV1[1:0] ,Division setting for clockout mux output" ",/2,/4,/8" tree.end base ad:0x1380000 tree "CGU DDR CCSR Registers" group.long 0x00++0x03 line.long 0x00 "CLKCSR,DDR Clock Control / Status Register" bitfld.long 0x00 27.--30. " CLKSEL ,CGU feed forward divider selection" "Disabled,/2,?..." tree.end base ad:0x1370000 tree "CCU Registers" group.long 0x0++0x03 line.long 0x00 "CLKC1CSR,Core Cluster 1 Clock Control / Status Register" bitfld.long 0x00 27.--30. " CLKSEL ,Clock source for this clock domain selection" "PLL1,PLL1/2,PLL1/4 or 2,,PLL2,PLL2/2,PLL2/4,?..." group.long 0x20++0x03 line.long 0x00 "CLKC2CSR,Core Cluster 2 Clock Control / Status Register" bitfld.long 0x00 27.--30. " CLKSEL ,Clock source for this clock domain selection" "PLL1,PLL1/2,PLL1/4 or 2,,PLL2,PLL2/2,PLL2/4,?..." tree.end width 0x0B tree.end else tree "Clocking" base ad:0x01EE1000 width 23. endian.be group.long 0x00++0x03 line.long 0x00 "CLOCKING_CLKC1CSR,Core 1 Clock Control/Status Register" sif cpuis("LS1012A") bitfld.long 0x00 27.--30. " CLKSEL ,Clock select" "PLL1,,PLL1 /2,?..." elif cpuis("LS10?3A") bitfld.long 0x00 27.--30. " CLKSEL ,Clock select" "PLL1,PLL1 /2,,,PLL2,PLL2 /2,?..." elif cpuis("LS10?6A") bitfld.long 0x00 27.--30. " CLKSEL ,Clock select" "PLL1,,PLL1 /2,,PLL2,,PLL2 /2,?..." endif sif !cpuis("LS1012A") group.long 0x10++0x03 line.long 0x00 "CLOCKING_CLKCG1HWACSR,Clock Generator n Hardware Accelerator Control/Status Register 1" sif cpuis("LS10?6*") bitfld.long 0x00 27.--30. " HWACLKSEL ,Hardware accelerator clock select" ",,PLL1 /2,PLL1 /3 or 4,,Platform freq.,PLL2 /2,PLL2 /3,?..." elif cpuis("LS10?3*") bitfld.long 0x00 27.--30. " HWACLKSEL ,Hardware accelerator clock select" ",,PLL1 /2,PLL1 /3,,,PLL2 /2,PLL2 /3,?..." endif group.long 0x30++0x03 line.long 0x00 "CLOCKING_CLKCG2HWACSR,Clock Generator n Hardware Accelerator Control/Status Register 2" sif cpuis("LS10?6A") bitfld.long 0x00 27.--30. " HWACLKSEL ,Hardware accelerator clock select" ",PLL2,PLL2 /2,PLL2 /3,,,PLL1 /2,?..." elif cpuis("LS10?3A") bitfld.long 0x00 27.--30. " HWACLKSEL ,Hardware accelerator clock select" ",PLL2,,PLL2 /3,?..." endif endif group.long 0x800++0x03 line.long 0x00 "CLOCKING_PLLC1GSR,PLL Cluster 1 General Status Register" bitfld.long 0x00 31. " KILL ,Writing a 1 to this bit disables the PLL" "No,Yes" hexmask.long.word 0x00 1.--8. 1. " CFG ,Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL" sif !cpuis("LS1012A") group.long 0x820++0x03 line.long 0x00 "CLOCKING_PLLC2GSR,PLL Cluster 2 General Status Register" bitfld.long 0x00 31. " KILL ,Writing a 1 to this bit disables the PLL" "No,Yes" hexmask.long.word 0x00 1.--8. 1. " CFG ,Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL" endif group.long 0xA00++0x03 line.long 0x00 "CLOCKING_CLKPCSR,Platform Clock Domain Control/status Register" bitfld.long 0x00 16. " CLKOEN ,CLK_OUT pad enable" "Disabled,Enabled" sif !cpuis("LS1012A") bitfld.long 0x00 11.--15. " CLKOSEL ,Selects core related clock signal for observation on CLK_OUT pad" ",,,,,,,,,,,,,,,,,,,,,,,,,,,Platform clk /2,,,Platform feedback clk,SYSCLK" else bitfld.long 0x00 11.--15. " CLKOSEL ,Selects core related clock signal for observation on CLK_OUT pad" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,125 MHz SYSCLK" endif bitfld.long 0x00 9.--10. " CLKODIV ,Selects division setting for clock-out mux output to reduce the frequency of the signal" "/1,/2,/4,/8" group.long 0xC00++0x03 line.long 0x00 "CLOCKING_PLLPGSR,Platform PLL General Status Register" bitfld.long 0x00 1.--6. " CFG ,Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("LS1012A") group.long 0xC20++0x03 line.long 0x00 "CLOCKING_PLLDGSR,DDR PLL General Status Register" bitfld.long 0x00 31. " KILL ,Writing a 1 to this bit disables the PLL" "No,Yes" hexmask.long.word 0x00 1.--8. 1. " CFG ,Reflects the current PLL multiplier configuration. Indicates the frequency for this PLL" endif endian.le width 0x0B tree.end endif sif cpuis("LS10?6*")||cpuis("LS1012A") tree "System Counter" base ad:0x02B00000 width 25. endian.be group.long 0x00++0x03 "SECURE_SYSTEM_COUNTER" line.long 0x00 "SYS_COUNTER_CNTCR,Control Register" bitfld.long 0x00 0. " EN ,Enables the counter" "Disabled,Enabled" if (((per.l.be(ad:0x02B00000))&0x00000001)==0x00) group.long 0x08++0x03 line.long 0x00 "SYS_COUNTER_CNTCV1,LSB Of Counter Count Value" group.long 0x0C++0x03 line.long 0x00 "SYS_COUNTER_CNTCV2,MSB Of Counter Count Value" else rgroup.long 0x08++0x03 line.long 0x00 "SYS_COUNTER_CNTCV1,LSB Of Counter Count Value" rgroup.long 0x0C++0x03 line.long 0x00 "SYS_COUNTER_CNTCV2,MSB Of Counter Count Value" endif group.long 0x20++0x03 line.long 0x00 "SYS_COUNTER_CNTFID0,Counter Frequency Mode Table Base Frequency Register" rgroup.long 0x10000++0x07 "NON-SECURE_SYS_COUNTER" line.long 0x00 "NSYS_COUNTER_CNCTV_RO1,LSB Of Counter Count Value" line.long 0x04 "NSYS_COUNTER_CNCTV2_RO2,MSB Of Counter Count Value" endian.le width 0x0B tree.end elif cpuis("LS10?3*") tree "System Counter" base ad:0x02B00000 width 25. group.long 0x00++0x03 "SECURE_SYSTEM_COUNTER" line.long 0x00 "SYS_COUNTER_CNTCR,Control Register" bitfld.long 0x00 0. " EN ,Enables the counter" "Disabled,Enabled" if (((per.l(ad:0x02B00000))&0x00000001)==0x00) group.long 0x08++0x03 line.long 0x00 "SYS_COUNTER_CNTCV1,LSB Of Counter Count Value" group.long 0x0C++0x03 line.long 0x00 "SYS_COUNTER_CNTCV2,MSB Of Counter Count Value" else rgroup.long 0x08++0x03 line.long 0x00 "SYS_COUNTER_CNTCV1,LSB Of Counter Count Value" rgroup.long 0x0C++0x03 line.long 0x00 "SYS_COUNTER_CNTCV2,MSB Of Counter Count Value" endif group.long 0x20++0x07 line.long 0x00 "SYS_COUNTER_CNTFID0,Counter Frequency Mode Table Base Frequency Register" line.long 0x04 "SYS_COUNTER_CNTFID1,Counter Frequency Mode Table End Frequency Register" rgroup.long 0x10000++0x07 "NON-SECURE_SYS_COUNTER" line.long 0x00 "NSYS_COUNTER_CNCTV_RO1,LSB Of Counter Count Value" line.long 0x04 "NSYS_COUNTER_CNCTV2_RO2,MSB Of Counter Count Value" width 0x0B tree.end endif sif cpuis("LS10?3*") tree "IF (Interconnect Fabric)" base ad:0x02CA0200 width 28. group.long 0x688++0x13 "QDMA READ" line.long 0x00 "PRIO_QDMA_READ_ONLY,Priority QDMA (Read only)" rbitfld.long 0x00 31. " MARK ,Backward compatibility marker when 0" "0,1" bitfld.long 0x00 8.--10. " P1 ,Priority 1 level select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P0 ,Priority 0 level select" "0,1,2,3,4,5,6,7" line.long 0x04 "MOD_QDMA_READ_ONLY,Mode QDMA (Read only)" bitfld.long 0x04 0.--1. " MODE ,Functional mode" "Programmable,Limiter,Bypass,Regulator" line.long 0x08 "BW_QDMA_READ_ONLY,Bandwidth QDMA (Read only)" hexmask.long.word 0x08 0.--12. 1. " BANDWIDTH ,Bandwidth threshold in 1/256th-byte-per-cycle units" line.long 0x0C "SAT_QDMA_READ_ONLY,Saturation QDMA (Read only)" hexmask.long.word 0x0C 0.--9. 1. " SATURATION ,Defines the size of the bandwidth counter" line.long 0x10 "EXT_CNTRL_QDMA_READ_ONLY,ExtControl QDMA (Read only)" bitfld.long 0x10 2. " INTCLKEN ,Replace the External reference by the local clock" "Not replaced,Replaced" bitfld.long 0x10 1. " EXTTHREN ,ExtThr input controls Low/High priority instead of bandwidth threshold" "Bandwidth threshold,Low/High priority" bitfld.long 0x10 0. " SOCKETQOSEN ,Combines the socket QoS with regulator QoS" "Disabled,Enabled" group.long 0x708++0x13 "QDMA WRITE" line.long 0x00 "PRIO_QDMA_WRITE_ONLY,Priority QDMA (Write only)" rbitfld.long 0x00 31. " MARK ,Backward compatibility marker when 0" "0,1" bitfld.long 0x00 8.--10. " P1 ,Priority 1 level select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P0 ,Priority 0 level select" "0,1,2,3,4,5,6,7" line.long 0x04 "MOD_QDMA_WRITE_ONLY,Mode QDMA (Write only)" bitfld.long 0x04 0.--1. " MODE ,Functional mode" "Programmable,Limiter,Bypass,Regulator" line.long 0x08 "BW_QDMA_WRITE_ONLY,Bandwidth QDMA (Write only)" hexmask.long.word 0x08 0.--12. 1. " BANDWIDTH ,Bandwidth threshold in 1/256th-byte-per-cycle units" line.long 0x0C "SAT_QDMA_WRITE_ONLY,Saturation QDMA (Write only)" hexmask.long.word 0x0C 0.--9. 1. " SATURATION ,Defines the size of the bandwidth counter" line.long 0x10 "EXT_CNTRL_QDMA_WRITE_ONLY,ExtControl QDMA (Write only)" bitfld.long 0x10 2. " INTCLKEN ,Replace the External reference by the local clock" "Not replaced,Replaced" bitfld.long 0x10 1. " EXTTHREN ,ExtThr input controls Low/High priority instead of bandwidth threshold" "Bandwidth threshold,Low/High priority" bitfld.long 0x10 0. " SOCKETQOSEN ,Combines the socket QoS with regulator QoS" "Disabled,Enabled" group.long 0x788++0x13 "PEX READ" line.long 0x00 "PRIO_PEX_READ_ONLY,Priority PEX (Read only)" rbitfld.long 0x00 31. " MARK ,Backward compatibility marker when 0" "0,1" bitfld.long 0x00 8.--10. " P1 ,Priority 1 level select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P0 ,Priority 0 level select" "0,1,2,3,4,5,6,7" line.long 0x04 "MOD_PEX_READ_ONLY,Mode PEX (Read only)" bitfld.long 0x04 0.--1. " MODE ,Functional mode" "Programmable,Limiter,Bypass,Regulator" line.long 0x08 "BW_PEX_READ_ONLY,Bandwidth PEX (Read only)" hexmask.long.word 0x08 0.--12. 1. " BANDWIDTH ,Bandwidth threshold in 1/256th-byte-per-cycle units" line.long 0x0C "SAT_PEX_READ_ONLY,Saturation PEX (Read only)" hexmask.long.word 0x0C 0.--9. 1. " SATURATION ,Defines the size of the bandwidth counter" line.long 0x10 "EXT_CNTRL_PEX_READ_ONLY,ExtControl PEX (Read only)" bitfld.long 0x10 2. " INTCLKEN ,Replace the External reference by the local clock" "Not replaced,Replaced" bitfld.long 0x10 1. " EXTTHREN ,ExtThr input controls Low/High priority instead of bandwidth threshold" "Bandwidth threshold,Low/High priority" bitfld.long 0x10 0. " SOCKETQOSEN ,Combines the socket QoS with regulator QoS" "Disabled,Enabled" group.long 0x808++0x13 "PEX WRITE" line.long 0x00 "PRIO_PEX_WRITE_ONLY,Priority PEX (Write only)" rbitfld.long 0x00 31. " MARK ,Backward compatibility marker when 0" "0,1" bitfld.long 0x00 8.--10. " P1 ,Priority 1 level select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P0 ,Priority 0 level select" "0,1,2,3,4,5,6,7" line.long 0x04 "MOD_PEX_WRITE_ONLY,Mode PEX (Write only)" bitfld.long 0x04 0.--1. " MODE ,Functional mode" "Programmable,Limiter,Bypass,Regulator" line.long 0x08 "BW_PEX_WRITE_ONLY,Bandwidth PEX (Write only)" hexmask.long.word 0x08 0.--12. 1. " BANDWIDTH ,Bandwidth threshold in 1/256th-byte-per-cycle units" line.long 0x0C "SAT_PEX_WRITE_ONLY,Saturation PEX (Write only)" hexmask.long.word 0x0C 0.--9. 1. " SATURATION ,Defines the size of the bandwidth counter" line.long 0x10 "EXT_CNTRL_PEX_WRITE_ONLY,ExtControl PEX (Write only)" bitfld.long 0x10 2. " INTCLKEN ,Replace the External reference by the local clock" "Not replaced,Replaced" bitfld.long 0x10 1. " EXTTHREN ,ExtThr input controls Low/High priority instead of bandwidth threshold" "Bandwidth threshold,Low/High priority" bitfld.long 0x10 0. " SOCKETQOSEN ,Combines the socket QoS with regulator QoS" "Disabled,Enabled" width 0x0B tree.end endif tree "CCI-400 (Cache Coherent Interconnect)" base ad:0x01180000 width 23. group.long 0x00++0x0B line.long 0x00 "CONTROL_OVERRIDE,Control Override Register" bitfld.long 0x00 5. " DISABLE_RETRY_REDUCTION_BUFFERS ,Disable retry reduction buffers for speculative fetches" "No,Yes" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) bitfld.long 0x00 4. " DISABLE_PRIORITY_PROMOTION ,ARQOSARBS inputs are ignored" "No,Yes" endif newline bitfld.long 0x00 3. " TERMINATE_BARRIERS ,Terminate barriers" "According to inputs,All interfaces" bitfld.long 0x00 2. " DISABLE_SPECULATIVE_FETCHES ,Disable speculative fetches" "No,Yes" newline bitfld.long 0x00 1. " DVM_MESSAGE_DISABLE ,DVM message disable" "No,Yes" bitfld.long 0x00 0. " SNOOP_DISABLE ,Snoop disable" "No,Yes" line.long 0x04 "SPECULATION_CONTROL,Speculation Control Register" bitfld.long 0x04 20. " DISABLE_SPECULATIVE_FETCHES_S4 ,Disable speculative fetches from slave" "No,Yes" bitfld.long 0x04 19. " DISABLE_SPECULATIVE_FETCHES_S3 ,Disable speculative fetches from slave" "No,Yes" newline bitfld.long 0x04 18. " DISABLE_SPECULATIVE_FETCHES_S2 ,Disable speculative fetches from slave" "No,Yes" bitfld.long 0x04 17. " DISABLE_SPECULATIVE_FETCHES_S1 ,Disable speculative fetches from slave" "No,Yes" newline bitfld.long 0x04 16. " DISABLE_SPECULATIVE_FETCHES_S0 ,Disable speculative fetches from slave" "No,Yes" bitfld.long 0x04 2. " DISABLE_SPECULATIVE_FETCHES_M2 ,Disable speculative fetches from master" "No,Yes" newline bitfld.long 0x04 1. " DISABLE_SPECULATIVE_FETCHES_M1 ,Disable speculative fetches from master" "No,Yes" bitfld.long 0x04 0. " DISABLE_SPECULATIVE_FETCHES_M0 ,Disable speculative fetches from master" "No,Yes" line.long 0x08 "SECURE_ACCESS,Secure Access Register" bitfld.long 0x08 0. " SECURE_ACCESS_CONTROL ,Secure access control" "Disabled,Enabled" newline rgroup.long 0x0C++0x03 line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 0. " CCI_STATUS ,CCI_Status" "Not pending,Pending" group.long 0x10++0x03 line.long 0x00 "IMPRECISE_ERROR,Imprecise Error Register" bitfld.long 0x00 20. " IMP_ERR_S4 ,Imprecise error indicator for slave interface S4" "No error,Error" bitfld.long 0x00 19. " IMP_ERR_S3 ,Imprecise error indicator for slave interface S3" "No error,Error" bitfld.long 0x00 18. " IMP_ERR_S2 ,Imprecise error indicator for slave interface S2" "No error,Error" newline bitfld.long 0x00 17. " IMP_ERR_S1 ,Imprecise error indicator for slave interface S1" "No error,Error" bitfld.long 0x00 16. " IMP_ERR_S0 ,Imprecise error indicator for slave interface S0" "No error,Error" newline bitfld.long 0x00 2. " IMP_ERR_M2 ,Imprecise error indicator for master interface M2" "No error,Error" bitfld.long 0x00 1. " IMP_ERR_M1 ,Imprecise error indicator for master interface M1" "No error,Error" bitfld.long 0x00 0. " IMP_ERR_M0 ,Imprecise error indicator for master interface M0" "No error,Error" group.long 0x1000++0x07 "Slave 0" line.long 0x00 "SNOOP_CONTROL_S0,Snoop Controls Register 0" rbitfld.long 0x00 31. " SUPPORT_DVMS ,Slave interface supports DVM messages" "Not supported,Supported" rbitfld.long 0x00 30. " SUPPORT_SNOOPS ,Slave interface supports snoops" "Not supported,Supported" bitfld.long 0x00 1. " ENABLE_DVMS ,Enable DVMs" "Disabled,Enabled" line.long 0x04 "SHAREABLE_OVERRIDE_S0,Shareable Overrides Register 0" bitfld.long 0x04 0.--1. " AXDOMAIN_OVERRIDE ,AxDOMAIN override" "Not overridden,Not overridden,Overridden to 0b00,Overridden to 0b01" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) group.long (0x1000+0x100)++0x07 line.long 0x00 "READ_QOS_OVERRIDE_S0,Read Channel QoS Value Override Register 0" rbitfld.long 0x00 8.--11. " ARQOS_OVERRIDE_READBACK ,ARQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARQOS_VALUE ,ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WRITE_QOS_OVERRIDE_S0,Write Qos Override Register 0" rbitfld.long 0x04 8.--11. " AWQOS_OVERRIDE_READBACK ,AWQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " AWQOS_VALUE ,AWQOS value for slave interface S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1000+0x10C)++0x07 line.long 0x00 "QOS_CONTROL_S0,Qos Control Register 0" rbitfld.long 0x00 31. " QOS_REGULATION_DISABLED ,QoS regulation disabled" "No,Yes" bitfld.long 0x00 21. " BANDWIDTH_REGULATION_MODE ,Bandwidth regulation mode" "Normal,Quiesce High" bitfld.long 0x00 20. " ARQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for read transactions" "Latency,Period" newline bitfld.long 0x00 16. " AWQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for write transaction" "Latency,Period" bitfld.long 0x00 3. " AR_OT_REGULATION ,Enable regulation of outstanding read transactions for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 2. " AW_OT_REGULATION ,Enable regulation of outstanding write transactions for slave interfaces" "Disabled,Enabled" newline bitfld.long 0x00 1. " ARQOS_REGULATION_READ ,Enable QoS value regulation on reads for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 0. " AWQOS_REGULATION_WRITE ,Enable QoS value regulation on writes for slave interfaces" "Disabled,Enabled" line.long 0x04 "MAX_OT_S0,Max OTs Register 0" bitfld.long 0x04 24.--29. " INT_OT_AR ,Integer part of the maximum outstanding AR addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 16.--23. 0x01 " FRAC_OT_AR ,Fractional part of the maximum outstanding AR addresses S0" newline bitfld.long 0x04 8.--13. " INT_OT_AW ,Integer part of the maximum outstanding AW addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 0x01 " FRAC_OT_AW ,Fractional part of the maximum outstanding AW addresses S0" group.long (0x1000+0x130)++0x03 line.long 0x00 "TARGET_LATENCY_S0,Regulator Targets Register 0" hexmask.long.word 0x00 16.--27. 1. " AR_LAT ,AR channel target latency" hexmask.long.word 0x00 0.--11. 1. " AW_LAT ,AW channel target latency" group.long (0x1000+0x138)++0x03 line.long 0x00 "QOS_RANGE_S0,QoS Range Register 0" bitfld.long 0x00 24.--27. " MAX_ARQOS ,Maximum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MIN_ARQOS ,Minimum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " MAX_AWQOS ,Maximum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MIN_AWQOS ,Minimum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1000+0x1268)++0x03 line.long 0x00 "LATENCY_REGULATION_S0,QoS Regulator Scale Factors Register 0" bitfld.long 0x00 8.--10. " AR_SCALE_FACT ,ARQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" bitfld.long 0x00 0.--2. " AW_SCALE_FACT ,AWQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" endif group.long 0x2000++0x07 "Slave 1" line.long 0x00 "SNOOP_CONTROL_S1,Snoop Controls Register 1" rbitfld.long 0x00 31. " SUPPORT_DVMS ,Slave interface supports DVM messages" "Not supported,Supported" rbitfld.long 0x00 30. " SUPPORT_SNOOPS ,Slave interface supports snoops" "Not supported,Supported" bitfld.long 0x00 1. " ENABLE_DVMS ,Enable DVMs" "Disabled,Enabled" line.long 0x04 "SHAREABLE_OVERRIDE_S1,Shareable Overrides Register 1" bitfld.long 0x04 0.--1. " AXDOMAIN_OVERRIDE ,AxDOMAIN override" "Not overridden,Not overridden,Overridden to 0b00,Overridden to 0b01" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) group.long (0x2000+0x100)++0x07 line.long 0x00 "READ_QOS_OVERRIDE_S1,Read Channel QoS Value Override Register 1" rbitfld.long 0x00 8.--11. " ARQOS_OVERRIDE_READBACK ,ARQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARQOS_VALUE ,ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WRITE_QOS_OVERRIDE_S1,Write Qos Override Register 1" rbitfld.long 0x04 8.--11. " AWQOS_OVERRIDE_READBACK ,AWQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " AWQOS_VALUE ,AWQOS value for slave interface S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2000+0x10C)++0x07 line.long 0x00 "QOS_CONTROL_S1,Qos Control Register 1" rbitfld.long 0x00 31. " QOS_REGULATION_DISABLED ,QoS regulation disabled" "No,Yes" bitfld.long 0x00 21. " BANDWIDTH_REGULATION_MODE ,Bandwidth regulation mode" "Normal,Quiesce High" bitfld.long 0x00 20. " ARQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for read transactions" "Latency,Period" newline bitfld.long 0x00 16. " AWQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for write transaction" "Latency,Period" bitfld.long 0x00 3. " AR_OT_REGULATION ,Enable regulation of outstanding read transactions for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 2. " AW_OT_REGULATION ,Enable regulation of outstanding write transactions for slave interfaces" "Disabled,Enabled" newline bitfld.long 0x00 1. " ARQOS_REGULATION_READ ,Enable QoS value regulation on reads for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 0. " AWQOS_REGULATION_WRITE ,Enable QoS value regulation on writes for slave interfaces" "Disabled,Enabled" line.long 0x04 "MAX_OT_S1,Max OTs Register 1" bitfld.long 0x04 24.--29. " INT_OT_AR ,Integer part of the maximum outstanding AR addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 16.--23. 0x01 " FRAC_OT_AR ,Fractional part of the maximum outstanding AR addresses S0" newline bitfld.long 0x04 8.--13. " INT_OT_AW ,Integer part of the maximum outstanding AW addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 0x01 " FRAC_OT_AW ,Fractional part of the maximum outstanding AW addresses S0" group.long (0x2000+0x130)++0x03 line.long 0x00 "TARGET_LATENCY_S1,Regulator Targets Register 1" hexmask.long.word 0x00 16.--27. 1. " AR_LAT ,AR channel target latency" hexmask.long.word 0x00 0.--11. 1. " AW_LAT ,AW channel target latency" group.long (0x2000+0x138)++0x03 line.long 0x00 "QOS_RANGE_S1,QoS Range Register 1" bitfld.long 0x00 24.--27. " MAX_ARQOS ,Maximum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MIN_ARQOS ,Minimum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " MAX_AWQOS ,Maximum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MIN_AWQOS ,Minimum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2000+0x1268)++0x03 line.long 0x00 "LATENCY_REGULATION_S1,QoS Regulator Scale Factors Register 1" bitfld.long 0x00 8.--10. " AR_SCALE_FACT ,ARQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" bitfld.long 0x00 0.--2. " AW_SCALE_FACT ,AWQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" endif group.long 0x3000++0x07 "Slave 2" line.long 0x00 "SNOOP_CONTROL_S2,Snoop Controls Register 2" rbitfld.long 0x00 31. " SUPPORT_DVMS ,Slave interface supports DVM messages" "Not supported,Supported" rbitfld.long 0x00 30. " SUPPORT_SNOOPS ,Slave interface supports snoops" "Not supported,Supported" bitfld.long 0x00 1. " ENABLE_DVMS ,Enable DVMs" "Disabled,Enabled" line.long 0x04 "SHAREABLE_OVERRIDE_S2,Shareable Overrides Register 2" bitfld.long 0x04 0.--1. " AXDOMAIN_OVERRIDE ,AxDOMAIN override" "Not overridden,Not overridden,Overridden to 0b00,Overridden to 0b01" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) group.long (0x3000+0x100)++0x07 line.long 0x00 "READ_QOS_OVERRIDE_S2,Read Channel QoS Value Override Register 2" rbitfld.long 0x00 8.--11. " ARQOS_OVERRIDE_READBACK ,ARQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARQOS_VALUE ,ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WRITE_QOS_OVERRIDE_S2,Write Qos Override Register 2" rbitfld.long 0x04 8.--11. " AWQOS_OVERRIDE_READBACK ,AWQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " AWQOS_VALUE ,AWQOS value for slave interface S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x3000+0x10C)++0x07 line.long 0x00 "QOS_CONTROL_S2,Qos Control Register 2" rbitfld.long 0x00 31. " QOS_REGULATION_DISABLED ,QoS regulation disabled" "No,Yes" bitfld.long 0x00 21. " BANDWIDTH_REGULATION_MODE ,Bandwidth regulation mode" "Normal,Quiesce High" bitfld.long 0x00 20. " ARQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for read transactions" "Latency,Period" newline bitfld.long 0x00 16. " AWQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for write transaction" "Latency,Period" bitfld.long 0x00 3. " AR_OT_REGULATION ,Enable regulation of outstanding read transactions for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 2. " AW_OT_REGULATION ,Enable regulation of outstanding write transactions for slave interfaces" "Disabled,Enabled" newline bitfld.long 0x00 1. " ARQOS_REGULATION_READ ,Enable QoS value regulation on reads for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 0. " AWQOS_REGULATION_WRITE ,Enable QoS value regulation on writes for slave interfaces" "Disabled,Enabled" line.long 0x04 "MAX_OT_S2,Max OTs Register 2" bitfld.long 0x04 24.--29. " INT_OT_AR ,Integer part of the maximum outstanding AR addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 16.--23. 0x01 " FRAC_OT_AR ,Fractional part of the maximum outstanding AR addresses S0" newline bitfld.long 0x04 8.--13. " INT_OT_AW ,Integer part of the maximum outstanding AW addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 0x01 " FRAC_OT_AW ,Fractional part of the maximum outstanding AW addresses S0" group.long (0x3000+0x130)++0x03 line.long 0x00 "TARGET_LATENCY_S2,Regulator Targets Register 2" hexmask.long.word 0x00 16.--27. 1. " AR_LAT ,AR channel target latency" hexmask.long.word 0x00 0.--11. 1. " AW_LAT ,AW channel target latency" group.long (0x3000+0x138)++0x03 line.long 0x00 "QOS_RANGE_S2,QoS Range Register 2" bitfld.long 0x00 24.--27. " MAX_ARQOS ,Maximum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MIN_ARQOS ,Minimum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " MAX_AWQOS ,Maximum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MIN_AWQOS ,Minimum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x3000+0x1268)++0x03 line.long 0x00 "LATENCY_REGULATION_S2,QoS Regulator Scale Factors Register 2" bitfld.long 0x00 8.--10. " AR_SCALE_FACT ,ARQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" bitfld.long 0x00 0.--2. " AW_SCALE_FACT ,AWQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" endif group.long 0x4000++0x07 "Slave 3" line.long 0x00 "SNOOP_CONTROL_S3,Snoop Controls Register 3" rbitfld.long 0x00 31. " SUPPORT_DVMS ,Slave interface supports DVM messages" "Not supported,Supported" rbitfld.long 0x00 30. " SUPPORT_SNOOPS ,Slave interface supports snoops" "Not supported,Supported" bitfld.long 0x00 1. " ENABLE_DVMS ,Enable DVMs" "Disabled,Enabled" line.long 0x04 "SHAREABLE_OVERRIDE_S3,Shareable Overrides Register 3" bitfld.long 0x04 0.--1. " AXDOMAIN_OVERRIDE ,AxDOMAIN override" "Not overridden,Not overridden,Overridden to 0b00,Overridden to 0b01" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) group.long (0x4000+0x100)++0x07 line.long 0x00 "READ_QOS_OVERRIDE_S3,Read Channel QoS Value Override Register 3" rbitfld.long 0x00 8.--11. " ARQOS_OVERRIDE_READBACK ,ARQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARQOS_VALUE ,ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WRITE_QOS_OVERRIDE_S3,Write Qos Override Register 3" rbitfld.long 0x04 8.--11. " AWQOS_OVERRIDE_READBACK ,AWQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " AWQOS_VALUE ,AWQOS value for slave interface S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x4000+0x10C)++0x07 line.long 0x00 "QOS_CONTROL_S3,Qos Control Register 3" rbitfld.long 0x00 31. " QOS_REGULATION_DISABLED ,QoS regulation disabled" "No,Yes" bitfld.long 0x00 21. " BANDWIDTH_REGULATION_MODE ,Bandwidth regulation mode" "Normal,Quiesce High" bitfld.long 0x00 20. " ARQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for read transactions" "Latency,Period" newline bitfld.long 0x00 16. " AWQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for write transaction" "Latency,Period" bitfld.long 0x00 3. " AR_OT_REGULATION ,Enable regulation of outstanding read transactions for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 2. " AW_OT_REGULATION ,Enable regulation of outstanding write transactions for slave interfaces" "Disabled,Enabled" newline bitfld.long 0x00 1. " ARQOS_REGULATION_READ ,Enable QoS value regulation on reads for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 0. " AWQOS_REGULATION_WRITE ,Enable QoS value regulation on writes for slave interfaces" "Disabled,Enabled" line.long 0x04 "MAX_OT_S3,Max OTs Register 3" bitfld.long 0x04 24.--29. " INT_OT_AR ,Integer part of the maximum outstanding AR addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 16.--23. 0x01 " FRAC_OT_AR ,Fractional part of the maximum outstanding AR addresses S0" newline bitfld.long 0x04 8.--13. " INT_OT_AW ,Integer part of the maximum outstanding AW addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 0x01 " FRAC_OT_AW ,Fractional part of the maximum outstanding AW addresses S0" group.long (0x4000+0x130)++0x03 line.long 0x00 "TARGET_LATENCY_S3,Regulator Targets Register 3" hexmask.long.word 0x00 16.--27. 1. " AR_LAT ,AR channel target latency" hexmask.long.word 0x00 0.--11. 1. " AW_LAT ,AW channel target latency" group.long (0x4000+0x138)++0x03 line.long 0x00 "QOS_RANGE_S3,QoS Range Register 3" bitfld.long 0x00 24.--27. " MAX_ARQOS ,Maximum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MIN_ARQOS ,Minimum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " MAX_AWQOS ,Maximum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MIN_AWQOS ,Minimum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x4000+0x1268)++0x03 line.long 0x00 "LATENCY_REGULATION_S3,QoS Regulator Scale Factors Register 3" bitfld.long 0x00 8.--10. " AR_SCALE_FACT ,ARQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" bitfld.long 0x00 0.--2. " AW_SCALE_FACT ,AWQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" endif group.long 0x5000++0x07 "Slave 4" line.long 0x00 "SNOOP_CONTROL_S4,Snoop Controls Register 4" rbitfld.long 0x00 31. " SUPPORT_DVMS ,Slave interface supports DVM messages" "Not supported,Supported" rbitfld.long 0x00 30. " SUPPORT_SNOOPS ,Slave interface supports snoops" "Not supported,Supported" bitfld.long 0x00 1. " ENABLE_DVMS ,Enable DVMs" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENABLE_SNOOP ,Enable issuing of snoop requests from this slave interface" "Disabled,Enabled" line.long 0x04 "SHAREABLE_OVERRIDE_S4,Shareable Overrides Register 4" bitfld.long 0x04 0.--1. " AXDOMAIN_OVERRIDE ,AxDOMAIN override" "Not overridden,Not overridden,Overridden to 0b00,Overridden to 0b01" sif !(cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")) group.long (0x5000+0x100)++0x07 line.long 0x00 "READ_QOS_OVERRIDE_S4,Read Channel QoS Value Override Register 4" rbitfld.long 0x00 8.--11. " ARQOS_OVERRIDE_READBACK ,ARQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARQOS_VALUE ,ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WRITE_QOS_OVERRIDE_S4,Write Qos Override Register 4" rbitfld.long 0x04 8.--11. " AWQOS_OVERRIDE_READBACK ,AWQOS override readback" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " AWQOS_VALUE ,AWQOS value for slave interface S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x5000+0x10C)++0x07 line.long 0x00 "QOS_CONTROL_S4,Qos Control Register 4" rbitfld.long 0x00 31. " QOS_REGULATION_DISABLED ,QoS regulation disabled" "No,Yes" bitfld.long 0x00 21. " BANDWIDTH_REGULATION_MODE ,Bandwidth regulation mode" "Normal,Quiesce High" bitfld.long 0x00 20. " ARQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for read transactions" "Latency,Period" newline bitfld.long 0x00 16. " AWQOS_REGULATION_MODE ,Configures the mode of the QoS value regulator for write transaction" "Latency,Period" bitfld.long 0x00 3. " AR_OT_REGULATION ,Enable regulation of outstanding read transactions for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 2. " AW_OT_REGULATION ,Enable regulation of outstanding write transactions for slave interfaces" "Disabled,Enabled" newline bitfld.long 0x00 1. " ARQOS_REGULATION_READ ,Enable QoS value regulation on reads for slave interfaces" "Disabled,Enabled" bitfld.long 0x00 0. " AWQOS_REGULATION_WRITE ,Enable QoS value regulation on writes for slave interfaces" "Disabled,Enabled" line.long 0x04 "MAX_OT_S4,Max OTs Register 4" bitfld.long 0x04 24.--29. " INT_OT_AR ,Integer part of the maximum outstanding AR addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 16.--23. 0x01 " FRAC_OT_AR ,Fractional part of the maximum outstanding AR addresses S0" newline bitfld.long 0x04 8.--13. " INT_OT_AW ,Integer part of the maximum outstanding AW addresses S0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 0.--7. 0x01 " FRAC_OT_AW ,Fractional part of the maximum outstanding AW addresses S0" group.long (0x5000+0x130)++0x03 line.long 0x00 "TARGET_LATENCY_S4,Regulator Targets Register 4" hexmask.long.word 0x00 16.--27. 1. " AR_LAT ,AR channel target latency" hexmask.long.word 0x00 0.--11. 1. " AW_LAT ,AW channel target latency" group.long (0x5000+0x138)++0x03 line.long 0x00 "QOS_RANGE_S4,QoS Range Register 4" bitfld.long 0x00 24.--27. " MAX_ARQOS ,Maximum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MIN_ARQOS ,Minimum ARQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " MAX_AWQOS ,Maximum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MIN_AWQOS ,Minimum AWQOS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x5000+0x1268)++0x03 line.long 0x00 "LATENCY_REGULATION_S4,QoS Regulator Scale Factors Register 4" bitfld.long 0x00 8.--10. " AR_SCALE_FACT ,ARQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" bitfld.long 0x00 0.--2. " AW_SCALE_FACT ,AWQOS scale factor" "2^-5,2^-6,2^-7,2^-8,2^-9,2^-10,2^-11,2^-12" endif width 0x0B tree.end sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "TZC-400 (TrustZone Address Space Controller)" base ad:0x01100000 width 23. rgroup.long 0x00++0x03 line.long 0x00 "BUILD_CONFIG,Build Configuration Register" bitfld.long 0x00 24.--25. " NO_OF_FILTERS ,Defines the number of filter units in the design implementation" "One,Two,,Four" bitfld.long 0x00 8.--13. " ADDRESS_WIDTH ,Defines the width of the ACE-lite address bus" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32 bits,,,,36 bits,,,,40 bits,,,,,,,,48 bits,,,,,,,,,,,,,,,,64 bits" bitfld.long 0x00 0.--4. " NO_OF_REGIONS ,Defines the number of regions that the TZC-400 provides" ",,,,,,,,9,?..." group.long 0x04++0x0B line.long 0x00 "ACTION,Action Register" bitfld.long 0x00 0.--1. " REACTION_VALUE ,Controls how the TZC-400 uses BRESPS[1:0] RRESPS[1:0] and TZCINT signals" "LOW/OKAY,LOW/DECERR,HIGH/OKAY,HIGH/DECERR" line.long 0x04 "GATE_KEEPER,Gate Keeper Register" sif cpuis("LS10?6A") bitfld.long 0x04 16. " OPEN_STATUS ,The current state of the gate keeper in each filter unit" "Closed,Open" else rbitfld.long 0x04 16. " OPEN_STATUS ,The current state of the gate keeper in each filter unit" "Closed,Open" endif bitfld.long 0x04 0. " OPEN_REQUEST ,Requests the gate to be opened or closed" "Close request,Open request" line.long 0x08 "SPECULATION_CTRL,Speculation Control Register" bitfld.long 0x08 1. " WRITE_SPEC_DISABLE ,Write access speculation disable" "No,Yes" bitfld.long 0x08 0. " READ_SPEC_DISABLE ,Read access speculation disable" "No,Yes" rgroup.long 0x10++0x03 line.long 0x00 "INT_STATUS,Interrupt Status Register" bitfld.long 0x00 16. " OVERLAP ,Indicates a violation of the overlap region configuration rules for associated filter unit" "Not overlapped,Overlapped" bitfld.long 0x00 8. " OVERRUN ,Indicates the occurrence of two or more region permission or region overlapping failures at associated filter unit" "No overrun,Overrun" bitfld.long 0x00 0. " STATUS ,Indicates the status of the interrupt from each filter unit" "Not asserted,Asserted" wgroup.long 0x14++0x03 line.long 0x00 "INT_CLEAR,Interrupt Clear Register" bitfld.long 0x00 0. " CLEAR ,Contains the control bit to clear interrupt" "No effect,Clear" rgroup.long 0x20++0x0F line.long 0x00 "FAIL_ADDRESS_LOW_0,Fail Address Low Register 0" line.long 0x04 "FAIL_ADDRESS_HIGH_0,Fail Address High Register 0" hexmask.long.byte 0x04 0.--7. 0x01 " ADDR_STATUS_HIGH ,Fail address high bits" line.long 0x08 "FAIL_CONTROL_0,Fail Control Register 0" bitfld.long 0x08 24. " DIRECTION ,Indicates whether the failed access was a read or write access attempt" "Read,Write" bitfld.long 0x08 21. " NON_SECURE ,Indicates whether permission check fail or region overlap was secure or non-secure access attempt" "Secure,Non-secure" bitfld.long 0x08 20. " PRIVILEGED ,Indicates whether permission check fail or region overlap was unprivileged or privileged access attempt" "Unprivileged,Privileged" line.long 0x0C "FAIL_ID_0,Fail ID Register 0" bitfld.long 0x0C 24.--27. " VNET ,This field returns the VN number of the first failed access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.word 0x0C 0.--11. 1. " ID ,This field returns the ACE-Lite ID values of the first failed access" else hexmask.long.word 0x0C 0.--10. 1. " ID ,This field returns the ACE-Lite ID values of the first failed access" endif tree "Region 0 registers" rgroup.long 0x100++0x0F line.long 0x00 "REGION_BASE_LOW_0,Region Base Address Low Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW0 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_0,Region Base Address High Register 0" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_0 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH0 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_0,Region Top Address Low Register 0" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW0 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_0,Region Top Address High Register 0" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH0 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH0 ,Controls the region top address bits" endif group.long 0x110++0x07 line.long 0x00 "REGION_ATTRIBUTES_0,Region Attributes Register" bitfld.long 0x00 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x00 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FILTER_EN ,Independent region enable for each filter unit" ",Enabled" line.long 0x04 "REGION_ID_ACCESS_0,Region ID Access Register" bitfld.long 0x04 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x04 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x04 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x04 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x04 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x04 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x04 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x04 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 1 registers" group.long (0x120+0x0)++0x17 line.long 0x00 "REGION_BASE_LOW_1,Region Base Address Low Register 1" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_1 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_1,Region Base Address High Register 1" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_1 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_1 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_1,Region Top Address Low Register 1" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_1 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_1,Region Top Address High Register 1" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_1 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_1 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_1,Region Attributes Register 1" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_1,Region ID Access Register 1" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 2 registers" group.long (0x120+0x20)++0x17 line.long 0x00 "REGION_BASE_LOW_2,Region Base Address Low Register 2" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_2 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_2,Region Base Address High Register 2" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_2 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_2 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_2,Region Top Address Low Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_2 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_2,Region Top Address High Register 2" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_2 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_2 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_2,Region Attributes Register 2" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_2,Region ID Access Register 2" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 3 registers" group.long (0x120+0x40)++0x17 line.long 0x00 "REGION_BASE_LOW_3,Region Base Address Low Register 3" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_3 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_3,Region Base Address High Register 3" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_3 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_3 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_3,Region Top Address Low Register 3" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_3 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_3,Region Top Address High Register 3" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_3 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_3 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_3,Region Attributes Register 3" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_3,Region ID Access Register 3" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 4 registers" group.long (0x120+0x60)++0x17 line.long 0x00 "REGION_BASE_LOW_4,Region Base Address Low Register 4" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_4 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_4,Region Base Address High Register 4" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_4 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_4 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_4,Region Top Address Low Register 4" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_4 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_4,Region Top Address High Register 4" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_4 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_4 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_4,Region Attributes Register 4" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_4,Region ID Access Register 4" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 5 registers" group.long (0x120+0x80)++0x17 line.long 0x00 "REGION_BASE_LOW_5,Region Base Address Low Register 5" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_5 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_5,Region Base Address High Register 5" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_5 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_5 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_5,Region Top Address Low Register 5" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_5 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_5,Region Top Address High Register 5" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_5 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_5 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_5,Region Attributes Register 5" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_5,Region ID Access Register 5" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 6 registers" group.long (0x120+0xA0)++0x17 line.long 0x00 "REGION_BASE_LOW_6,Region Base Address Low Register 6" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_6 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_6,Region Base Address High Register 6" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_6 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_6 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_6,Region Top Address Low Register 6" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_6 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_6,Region Top Address High Register 6" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_6 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_6 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_6,Region Attributes Register 6" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_6,Region ID Access Register 6" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 7 registers" group.long (0x120+0xC0)++0x17 line.long 0x00 "REGION_BASE_LOW_7,Region Base Address Low Register 7" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_7 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_7,Region Base Address High Register 7" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_7 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_7 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_7,Region Top Address Low Register 7" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_7 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_7,Region Top Address High Register 7" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_7 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_7 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_7,Region Attributes Register 7" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_7,Region ID Access Register 7" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 8 registers" group.long (0x120+0xE0)++0x17 line.long 0x00 "REGION_BASE_LOW_8,Region Base Address Low Register 8" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_8 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_8,Region Base Address High Register 8" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_8 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_8 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_8,Region Top Address Low Register 8" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_8 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_8,Region Top Address High Register 8" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_8 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_8 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_8,Region Attributes Register 8" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_8,Region ID Access Register 8" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end newline rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral ID 4 Register" bitfld.long 0x00 4.--7. " 4KB_COUNT ,Number of 4KB address blocks required to access the registers" "1 block,?..." bitfld.long 0x00 0.--3. " JEP106_C_CODE ,Represents how many 0x7F continuation characters occur in the manufacturer identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.long 0xFD4++0x03 line.long 0x00 "PID5,Peripheral ID 5 Register" group.long 0xFD8++0x03 line.long 0x00 "PID6,Peripheral ID 6 Register" group.long 0xFDC++0x03 line.long 0x00 "PID7,Peripheral ID 7 Register" endif rgroup.long 0xFE0++0x1F line.long 0x00 "PID0,Peripheral ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Part number" line.long 0x04 "PID1,Peripheral ID 1 Register" bitfld.long 0x04 4.--7. " JEP106_ID_3_0 ,Identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") bitfld.long 0x04 0.--3. " PART_NUMBER_0 ,Part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 0.--3. " PART_NUMBER_1 ,Part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.long 0x08 "PID2,Peripheral ID 2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision of the TZC-400" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " JEDEC_USED ,Indicates that TZC-400 uses a manufacturer identity code that was allocated by JEDEC according to JEP106" "0,1" bitfld.long 0x08 0.--2. " JEP106_ID_6_4 ,Identity code" "0,1,2,3,4,5,6,7" line.long 0x0C "PID3,Peripheral ID 3 Register" bitfld.long 0x0C 4.--7. " REVAND ,Revision of the silicon" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " MOD_NUMBER ,This is set to 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "CID0,Component ID 0 Register" hexmask.long.byte 0x10 0.--7. 1. " COMP_ID_0 ,Component ID 0 field" line.long 0x14 "CID1,Component ID 1 Register" hexmask.long.byte 0x14 0.--7. 1. " COMP_ID_1 ,Component ID 1 field" line.long 0x18 "CID2,Component ID 2 Register" hexmask.long.byte 0x18 0.--7. 1. " COMP_ID_2 ,Component ID 2 field" line.long 0x1C "CID3,Component ID 3 Register" hexmask.long.byte 0x1C 0.--7. 1. " COMP_ID_3 ,Component ID 3 field" width 0x0B tree.end elif cpuis("LS10?6A") tree "TZC-400 (TrustZone Address Space Controller)" base ad:0x01500000 width 23. rgroup.long 0x00++0x03 line.long 0x00 "BUILD_CONFIG,Build Configuration Register" bitfld.long 0x00 24.--25. " NO_OF_FILTERS ,Defines the number of filter units in the design implementation" "One,Two,,Four" bitfld.long 0x00 8.--13. " ADDRESS_WIDTH ,Defines the width of the ACE-lite address bus" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32 bits,,,,36 bits,,,,40 bits,,,,,,,,48 bits,,,,,,,,,,,,,,,,64 bits" bitfld.long 0x00 0.--4. " NO_OF_REGIONS ,Defines the number of regions that the TZC-400 provides" ",,,,,,,,9,?..." group.long 0x04++0x0B line.long 0x00 "ACTION,Action Register" bitfld.long 0x00 0.--1. " REACTION_VALUE ,Controls how the TZC-400 uses BRESPS[1:0] RRESPS[1:0] and TZCINT signals" "LOW/OKAY,LOW/DECERR,HIGH/OKAY,HIGH/DECERR" line.long 0x04 "GATE_KEEPER,Gate Keeper Register" sif cpuis("LS10?6A") bitfld.long 0x04 16. " OPEN_STATUS ,The current state of the gate keeper in each filter unit" "Closed,Open" else rbitfld.long 0x04 16. " OPEN_STATUS ,The current state of the gate keeper in each filter unit" "Closed,Open" endif bitfld.long 0x04 0. " OPEN_REQUEST ,Requests the gate to be opened or closed" "Close request,Open request" line.long 0x08 "SPECULATION_CTRL,Speculation Control Register" bitfld.long 0x08 1. " WRITE_SPEC_DISABLE ,Write access speculation disable" "No,Yes" bitfld.long 0x08 0. " READ_SPEC_DISABLE ,Read access speculation disable" "No,Yes" rgroup.long 0x10++0x03 line.long 0x00 "INT_STATUS,Interrupt Status Register" bitfld.long 0x00 16. " OVERLAP ,Indicates a violation of the overlap region configuration rules for associated filter unit" "Not overlapped,Overlapped" bitfld.long 0x00 8. " OVERRUN ,Indicates the occurrence of two or more region permission or region overlapping failures at associated filter unit" "No overrun,Overrun" bitfld.long 0x00 0. " STATUS ,Indicates the status of the interrupt from each filter unit" "Not asserted,Asserted" wgroup.long 0x14++0x03 line.long 0x00 "INT_CLEAR,Interrupt Clear Register" bitfld.long 0x00 0. " CLEAR ,Contains the control bit to clear interrupt" "No effect,Clear" rgroup.long 0x20++0x0F line.long 0x00 "FAIL_ADDRESS_LOW_0,Fail Address Low Register 0" line.long 0x04 "FAIL_ADDRESS_HIGH_0,Fail Address High Register 0" hexmask.long.byte 0x04 0.--7. 0x01 " ADDR_STATUS_HIGH ,Fail address high bits" line.long 0x08 "FAIL_CONTROL_0,Fail Control Register 0" bitfld.long 0x08 24. " DIRECTION ,Indicates whether the failed access was a read or write access attempt" "Read,Write" bitfld.long 0x08 21. " NON_SECURE ,Indicates whether permission check fail or region overlap was secure or non-secure access attempt" "Secure,Non-secure" bitfld.long 0x08 20. " PRIVILEGED ,Indicates whether permission check fail or region overlap was unprivileged or privileged access attempt" "Unprivileged,Privileged" line.long 0x0C "FAIL_ID_0,Fail ID Register 0" bitfld.long 0x0C 24.--27. " VNET ,This field returns the VN number of the first failed access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.word 0x0C 0.--11. 1. " ID ,This field returns the ACE-Lite ID values of the first failed access" else hexmask.long.word 0x0C 0.--10. 1. " ID ,This field returns the ACE-Lite ID values of the first failed access" endif tree "Region 0 registers" rgroup.long 0x100++0x0F line.long 0x00 "REGION_BASE_LOW_0,Region Base Address Low Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW0 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_0,Region Base Address High Register 0" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_0 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH0 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_0,Region Top Address Low Register 0" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW0 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_0,Region Top Address High Register 0" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH0 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH0 ,Controls the region top address bits" endif group.long 0x110++0x07 line.long 0x00 "REGION_ATTRIBUTES_0,Region Attributes Register" bitfld.long 0x00 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x00 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FILTER_EN ,Independent region enable for each filter unit" ",Enabled" line.long 0x04 "REGION_ID_ACCESS_0,Region ID Access Register" bitfld.long 0x04 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x04 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x04 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x04 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x04 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x04 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x04 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x04 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x04 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x04 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x04 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x04 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x04 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 1 registers" group.long (0x120+0x0)++0x17 line.long 0x00 "REGION_BASE_LOW_1,Region Base Address Low Register 1" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_1 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_1,Region Base Address High Register 1" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_1 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_1 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_1,Region Top Address Low Register 1" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_1 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_1,Region Top Address High Register 1" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_1 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_1 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_1,Region Attributes Register 1" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_1,Region ID Access Register 1" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 2 registers" group.long (0x120+0x20)++0x17 line.long 0x00 "REGION_BASE_LOW_2,Region Base Address Low Register 2" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_2 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_2,Region Base Address High Register 2" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_2 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_2 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_2,Region Top Address Low Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_2 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_2,Region Top Address High Register 2" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_2 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_2 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_2,Region Attributes Register 2" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_2,Region ID Access Register 2" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 3 registers" group.long (0x120+0x40)++0x17 line.long 0x00 "REGION_BASE_LOW_3,Region Base Address Low Register 3" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_3 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_3,Region Base Address High Register 3" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_3 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_3 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_3,Region Top Address Low Register 3" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_3 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_3,Region Top Address High Register 3" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_3 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_3 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_3,Region Attributes Register 3" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_3,Region ID Access Register 3" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 4 registers" group.long (0x120+0x60)++0x17 line.long 0x00 "REGION_BASE_LOW_4,Region Base Address Low Register 4" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_4 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_4,Region Base Address High Register 4" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_4 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_4 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_4,Region Top Address Low Register 4" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_4 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_4,Region Top Address High Register 4" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_4 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_4 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_4,Region Attributes Register 4" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_4,Region ID Access Register 4" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 5 registers" group.long (0x120+0x80)++0x17 line.long 0x00 "REGION_BASE_LOW_5,Region Base Address Low Register 5" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_5 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_5,Region Base Address High Register 5" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_5 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_5 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_5,Region Top Address Low Register 5" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_5 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_5,Region Top Address High Register 5" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_5 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_5 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_5,Region Attributes Register 5" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_5,Region ID Access Register 5" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 6 registers" group.long (0x120+0xA0)++0x17 line.long 0x00 "REGION_BASE_LOW_6,Region Base Address Low Register 6" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_6 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_6,Region Base Address High Register 6" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_6 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_6 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_6,Region Top Address Low Register 6" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_6 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_6,Region Top Address High Register 6" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_6 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_6 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_6,Region Attributes Register 6" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_6,Region ID Access Register 6" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 7 registers" group.long (0x120+0xC0)++0x17 line.long 0x00 "REGION_BASE_LOW_7,Region Base Address Low Register 7" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_7 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_7,Region Base Address High Register 7" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_7 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_7 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_7,Region Top Address Low Register 7" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_7 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_7,Region Top Address High Register 7" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_7 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_7 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_7,Region Attributes Register 7" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_7,Region ID Access Register 7" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end tree "Region 8 registers" group.long (0x120+0xE0)++0x17 line.long 0x00 "REGION_BASE_LOW_8,Region Base Address Low Register 8" hexmask.long.tbyte 0x00 12.--31. 0x10 " BASE_ADDRESS_LOW_8 ,Controls the base address bits" line.long 0x04 "REGION_BASE_HIGH_8,Region Base Address High Register 8" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x04 0.--7. 0x01 " BASE_ADDRESS_HIGH_8 ,Controls the base address bits" else hexmask.long.byte 0x04 0.--6. 0x01 " BASE_ADDRESS_HIGH_8 ,Controls the base address bits" endif line.long 0x08 "REGION_TOP_LOW_8,Region Top Address Low Register 8" hexmask.long.tbyte 0x08 12.--31. 0x10 " TOP_ADDRESS_LOW_8 ,Controls the region top address bits" line.long 0x0C "REGION_TOP_HIGH_8,Region Top Address High Register 8" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") hexmask.long.byte 0x0C 0.--7. 0x01 " TOP_ADDRESS_HIGH_8 ,Controls the region top address bits" else hexmask.long.byte 0x0C 0.--6. 0x01 " TOP_ADDRESS_HIGH_8 ,Controls the region top address bits" endif line.long 0x10 "REGION_ATTRIBUTES_8,Region Attributes Register 8" bitfld.long 0x10 31. " S_WR_EN ,Secure global write enable" "Disabled,Enabled" bitfld.long 0x10 30. " S_RD_EN ,Secure global read enable" "Disabled,Enabled" bitfld.long 0x10 0. " FILTER_EN ,Independent region enable for each filter unit" "Disabled,Enabled" line.long 0x14 "REGION_ID_ACCESS_8,Region ID Access Register 8" bitfld.long 0x14 31. " NSAID_WR_EN[15] ,NSAID[15] write enable" "Disabled,Enabled" bitfld.long 0x14 30. " [14] ,NSAID[14] write enable" "Disabled,Enabled" bitfld.long 0x14 29. " [13] ,NSAID[13] write enable" "Disabled,Enabled" newline bitfld.long 0x14 28. " [12] ,NSAID[12] write enable" "Disabled,Enabled" bitfld.long 0x14 27. " [11] ,NSAID[11] write enable" "Disabled,Enabled" bitfld.long 0x14 26. " [10] ,NSAID[10] write enable" "Disabled,Enabled" newline bitfld.long 0x14 25. " [9] ,NSAID[9] write enable" "Disabled,Enabled" bitfld.long 0x14 24. " [8] ,NSAID[8] write enable" "Disabled,Enabled" bitfld.long 0x14 23. " [7] ,NSAID[7] write enable" "Disabled,Enabled" newline bitfld.long 0x14 22. " [6] ,NSAID[6] write enable" "Disabled,Enabled" bitfld.long 0x14 21. " [5] ,NSAID[5] write enable" "Disabled,Enabled" bitfld.long 0x14 20. " [4] ,NSAID[4] write enable" "Disabled,Enabled" newline bitfld.long 0x14 19. " [3] ,NSAID[3] write enable" "Disabled,Enabled" bitfld.long 0x14 18. " [2] ,NSAID[2] write enable" "Disabled,Enabled" newline bitfld.long 0x14 17. " [1] ,NSAID[1] write enable" "Disabled,Enabled" bitfld.long 0x14 16. " [0] ,NSAID[0] write enable" "Disabled,Enabled" newline bitfld.long 0x14 15. " NSAID_RD_EN[15] ,NSAID[15] read enable" "Disabled,Enabled" bitfld.long 0x14 14. " [14] ,NSAID[14] read enable" "Disabled,Enabled" bitfld.long 0x14 13. " [13] ,NSAID[13] read enable" "Disabled,Enabled" newline bitfld.long 0x14 12. " [12] ,NSAID[12] read enable" "Disabled,Enabled" bitfld.long 0x14 11. " [11] ,NSAID[11] read enable" "Disabled,Enabled" bitfld.long 0x14 10. " [10] ,NSAID[10] read enable" "Disabled,Enabled" newline bitfld.long 0x14 9. " [9] ,NSAID[9] read enable" "Disabled,Enabled" bitfld.long 0x14 8. " [8] ,NSAID[8] read enable" "Disabled,Enabled" bitfld.long 0x14 7. " [7] ,NSAID[7] read enable" "Disabled,Enabled" newline bitfld.long 0x14 6. " [6] ,NSAID[6] read enable" "Disabled,Enabled" bitfld.long 0x14 5. " [5] ,NSAID[5] read enable" "Disabled,Enabled" bitfld.long 0x14 4. " [4] ,NSAID[4] read enable" "Disabled,Enabled" newline bitfld.long 0x14 3. " [3] ,NSAID[3] read enable" "Disabled,Enabled" bitfld.long 0x14 2. " [2] ,NSAID[2] read enable" "Disabled,Enabled" newline bitfld.long 0x14 1. " [1] ,NSAID[1] read enable" "Disabled,Enabled" bitfld.long 0x14 0. " [0] ,NSAID[0] read enable" "Disabled,Enabled" tree.end newline rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral ID 4 Register" bitfld.long 0x00 4.--7. " 4KB_COUNT ,Number of 4KB address blocks required to access the registers" "1 block,?..." bitfld.long 0x00 0.--3. " JEP106_C_CODE ,Represents how many 0x7F continuation characters occur in the manufacturer identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.long 0xFD4++0x03 line.long 0x00 "PID5,Peripheral ID 5 Register" group.long 0xFD8++0x03 line.long 0x00 "PID6,Peripheral ID 6 Register" group.long 0xFDC++0x03 line.long 0x00 "PID7,Peripheral ID 7 Register" endif rgroup.long 0xFE0++0x1F line.long 0x00 "PID0,Peripheral ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Part number" line.long 0x04 "PID1,Peripheral ID 1 Register" bitfld.long 0x04 4.--7. " JEP106_ID_3_0 ,Identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") bitfld.long 0x04 0.--3. " PART_NUMBER_0 ,Part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 0.--3. " PART_NUMBER_1 ,Part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.long 0x08 "PID2,Peripheral ID 2 Register" bitfld.long 0x08 4.--7. " REVISION ,Revision of the TZC-400" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " JEDEC_USED ,Indicates that TZC-400 uses a manufacturer identity code that was allocated by JEDEC according to JEP106" "0,1" bitfld.long 0x08 0.--2. " JEP106_ID_6_4 ,Identity code" "0,1,2,3,4,5,6,7" line.long 0x0C "PID3,Peripheral ID 3 Register" bitfld.long 0x0C 4.--7. " REVAND ,Revision of the silicon" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " MOD_NUMBER ,This is set to 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "CID0,Component ID 0 Register" hexmask.long.byte 0x10 0.--7. 1. " COMP_ID_0 ,Component ID 0 field" line.long 0x14 "CID1,Component ID 1 Register" hexmask.long.byte 0x14 0.--7. 1. " COMP_ID_1 ,Component ID 1 field" line.long 0x18 "CID2,Component ID 2 Register" hexmask.long.byte 0x18 0.--7. 1. " COMP_ID_2 ,Component ID 2 field" line.long 0x1C "CID3,Component ID 3 Register" hexmask.long.byte 0x1C 0.--7. 1. " COMP_ID_3 ,Component ID 3 field" width 0x0B tree.end elif cpuis("LS1012A")||cpuis("LS10?3A") tree "TZC-380 (TrustZone Address Space Controller)" base ad:0x01500000 width 23. rgroup.long 0x00++0x03 line.long 0x00 "CONFIGURATION,Configuration Register" bitfld.long 0x00 8.--13. " ADDRESS_WIDTH ,Defines the width of the ACE-Lite address bus" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32-bit,33-bit,34-bit,35-bit,36-bit,37-bit,38-bit,39-bit,40-bit,41-bit,42-bit,43-bit,44-bit,45-bit,46-bit,47-bit,48-bit,49-bit,50-bit,51-bit,52-bit,53-bit,54-bit,55-bit,56-bit,57-bit,58-bit,59-bit,60-bit,61-bit,62-bit,63-bit,64-bit" bitfld.long 0x00 0.--3. " NO_OF_REGIONS ,Defines the number of regions that the TZC-380 provides" ",2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x04++0x03 line.long 0x00 "ACTION,Action Register" bitfld.long 0x00 0.--1. " REACTION_VALUE ,Controls how the TZC-380 uses BRESPS[1:0] RRESPS[1:0] and TZCINT signals" "LOW/OKAY,LOW/DECERR,HIGH/OKAY,HIGH/DECERR" if (((per.l(ad:0x01500000+0x0C))&0x01)==0x00) group.long 0x08++0x03 line.long 0x00 "LOCKDOWN_RANGE,Lockdown Range Register" bitfld.long 0x00 31. " ENABLE ,lockdown_regions field enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LOCKDOWN_REGIONS ,Control the number of regions to lockdown" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else rgroup.long 0x08++0x03 line.long 0x00 "LOCKDOWN_RANGE,Lockdown Range Register" bitfld.long 0x00 31. " ENABLE ,lockdown_regions field enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " LOCKDOWN_REGIONS ,Control the number of regions to lockdown" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif group.long 0x0C++0x03 line.long 0x00 "LOCKDOWN_SELECT,Lockdown Select Register" bitfld.long 0x00 2. " ACC_SPECULATION_CNTL ,Modifies the access type of the speculation_control Register" "RW,RO" bitfld.long 0x00 1. " SECURITY_INV ,Modifies the access type of the security_inversion_en Register" "RW,RO" bitfld.long 0x00 0. " REGION_REGISTER ,Modifies the access type of the lockdown_range Register" "RW,RO" rgroup.long 0x10++0x03 line.long 0x00 "INT_STATUS,Interrupt Status Register" bitfld.long 0x00 1. " OVERRUN ,Indicates the occurrence of two or more region permission or region permission failures since the interrupt was last cleared" "No overrun,Overrun" bitfld.long 0x00 0. " STATUS ,Returns the status of the interrupt" "Inactive,Active" wgroup.long 0x14++0x03 line.long 0x00 "INT_CLEAR,Interrupt Clear Register" rgroup.long 0x20++0x0F line.long 0x00 "FAIL_ADDRESS_LOW_0,Fail Address Low Register" line.long 0x04 "FAIL_ADDRESS_HIGH_0,Fail Address High Register" line.long 0x08 "FAIL_CONTROL,Fail Control Register" bitfld.long 0x08 24. " STKY_WRITE_REG ,Indicates whether the failed access was a read or write access attempt" "Read,Write" bitfld.long 0x08 21. " NON_SECURE ,Indicates whether the first access to fail a region permission check was non-secure" "Secure,Non-secure" bitfld.long 0x08 20. " PRIVILEGED ,Indicates whether permission check fail or region overlap was unprivileged or privileged access attempt" "Unprivileged,Privileged" line.long 0x0C "FAIL_ID,Fail ID Register" hexmask.long.word 0x0C 0.--11. 1. " FAIL_ID ,Returns the master AXI ID of the first access to fail a region permission check after the interrupt was cleared" if (((per.l(ad:0x01500000+0x0C))&0x04)==0x00) group.long 0x30++0x03 line.long 0x0 "SPECULATION_CONTROL,Speculation Control Register" bitfld.long 0x0 1. " WRITE_SPECULATION ,Controls the write access speculation" "Enabled,Disabled" bitfld.long 0x0 0. " READ_SPECULATION ,Controls the read access speculation" "Enabled,Disabled" else rgroup.long 0x30++0x03 line.long 0x00 "SPECULATION_CONTROL,Speculation Control Register" bitfld.long 0x00 1. " WRITE_SPECULATION ,Controls the write access speculation" "Enabled,Disabled" bitfld.long 0x00 0. " READ_SPECULATION ,Controls the read access speculation" "Enabled,Disabled" endif if (((per.l(ad:0x01500000+0x0C))&0x02)==0x00) group.long 0x34++0x03 line.long 0x00 "SECURITY_INVERSION_EN,Security Inversion Register" bitfld.long 0x00 0. " SECURITY_INVERSION_EN ,Controls whether the TZASC permits security inversion to occur" "Not permitted,Permitted" else rgroup.long 0x34++0x03 line.long 0x00 "SECURITY_INVERSION_EN,Security Inversion Register" bitfld.long 0x00 0. " SECURITY_INVERSION_EN ,Controls whether the TZASC permits security inversion to occur" "Not permitted,Permitted" endif rgroup.long 0x100++0x07 "REGION 0" line.long 0x00 "REGION_SETUP_LOW_0,Region Setup Low 0" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_0,Region Setup High 0" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_0,Region Top Address Low Register 0" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x110++0x07 "REGION 1" line.long 0x00 "REGION_SETUP_LOW_1,Region Setup Low 1" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_1,Region Setup High 1" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_1,Region Top Address Low Register 1" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x120++0x07 "REGION 2" line.long 0x00 "REGION_SETUP_LOW_2,Region Setup Low 2" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_2,Region Setup High 2" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_2,Region Top Address Low Register 2" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x130++0x07 "REGION 3" line.long 0x00 "REGION_SETUP_LOW_3,Region Setup Low 3" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_3,Region Setup High 3" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_3,Region Top Address Low Register 3" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x140++0x07 "REGION 4" line.long 0x00 "REGION_SETUP_LOW_4,Region Setup Low 4" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_4,Region Setup High 4" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_4,Region Top Address Low Register 4" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x150++0x07 "REGION 5" line.long 0x00 "REGION_SETUP_LOW_5,Region Setup Low 5" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_5,Region Setup High 5" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_5,Region Top Address Low Register 5" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x160++0x07 "REGION 6" line.long 0x00 "REGION_SETUP_LOW_6,Region Setup Low 6" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_6,Region Setup High 6" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_6,Region Top Address Low Register 6" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x170++0x07 "REGION 7" line.long 0x00 "REGION_SETUP_LOW_7,Region Setup Low 7" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_7,Region Setup High 7" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_7,Region Top Address Low Register 7" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x180++0x07 "REGION 8" line.long 0x00 "REGION_SETUP_LOW_8,Region Setup Low 8" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_8,Region Setup High 8" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_8,Region Top Address Low Register 8" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x190++0x07 "REGION 9" line.long 0x00 "REGION_SETUP_LOW_9,Region Setup Low 9" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_9,Region Setup High 9" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_9,Region Top Address Low Register 9" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1A0++0x07 "REGION 10" line.long 0x00 "REGION_SETUP_LOW_10,Region Setup Low 10" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_10,Region Setup High 10" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_10,Region Top Address Low Register 10" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1B0++0x07 "REGION 11" line.long 0x00 "REGION_SETUP_LOW_11,Region Setup Low 11" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_11,Region Setup High 11" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_11,Region Top Address Low Register 11" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1C0++0x07 "REGION 12" line.long 0x00 "REGION_SETUP_LOW_12,Region Setup Low 12" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_12,Region Setup High 12" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_12,Region Top Address Low Register 12" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1D0++0x07 "REGION 13" line.long 0x00 "REGION_SETUP_LOW_13,Region Setup Low 13" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_13,Region Setup High 13" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_13,Region Top Address Low Register 13" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1E0++0x07 "REGION 14" line.long 0x00 "REGION_SETUP_LOW_14,Region Setup Low 14" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_14,Region Setup High 14" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_14,Region Top Address Low Register 14" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" rgroup.long 0x1F0++0x07 "REGION 15" line.long 0x00 "REGION_SETUP_LOW_15,Region Setup Low 15" hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS_LOW0 ,Controls the base address of region n" line.long 0x04 "REGION_SETUP_HIGH_15,Region Setup High 15" group.long 0x08++0x03 line.long 0x00 "REGION_ATTRIBUTES_15,Region Top Address Low Register 15" bitfld.long 0x00 28.--31. " SP0 ,Permission setting for region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " SUBREGION_DISABLE[7] ,Subregion 7 disable" "Enabled,Disabled" bitfld.long 0x00 14. " [6] ,Subregion 6 disable" "Enabled,Disabled" bitfld.long 0x00 13. " [5] ,Subregion 5 disable" "Enabled,Disabled" bitfld.long 0x00 12. " [4] ,Subregion 4 disable" "Enabled,Disabled" newline bitfld.long 0x00 11. " [3] ,Subregion 3 disable" "Enabled,Disabled" bitfld.long 0x00 10. " [2] ,Subregion 2 disable" "Enabled,Disabled" bitfld.long 0x00 9. " [1] ,Subregion 1 disable" "Enabled,Disabled" bitfld.long 0x00 8. " [0] ,Subregion 0 disable" "Enabled,Disabled" newline bitfld.long 0x00 1.--6. " SIZE1 ,Size of region n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. " EN1 ,Region n enable" "Disabled,Enabled" group.long 0xE00++0x03 "INTEGRATION" line.long 0x00 "ITCRG,Integration Test Control Register" bitfld.long 0x00 0. " INT_TEST_EN ,Integration test logic enable" "Disabled,Enabled" rgroup.long 0xE04++0x03 line.long 0x00 "ITIP,Integration Test Input Register" bitfld.long 0x00 0. " ITIP_SECURE_BOOT_LOCK ,Integration test input secure boot lock" "Unlocked,Locked" group.long 0xE08++0x03 line.long 0x00 "ITOP,Integration Test Output Register" bitfld.long 0x00 0. " ITOP_INT ,Sets value of tzasc_int" "Low,High" width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "TZPC (TrustZone Protection Controller)" base ad:0x02200000 width 26. group.long 0x00++0x03 line.long 0x00 "TZPCR0SIZE,Secure RAM Region Size Register" hexmask.long.word 0x00 0.--9. 1. " R0SIZE ,Secure RAM region size in 4KB steps" group.long 0x800++0x03 line.long 0x00 "TZDECPROT0STAT_SET/CLR,Decode Protection 0 Status Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DDRC ,DDRC configuration registers lock" "Locked,Unlocked" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DCFG_RESET ,Registers needing protection against non-secure accesses accessibility" "Only NS=0,All" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DSPI ,DSPI security" "Secure,Non-secure" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " I2C_1 ,I2C 1 security" "Secure,Non-secure" group.long 0x80C++0x03 line.long 0x00 "TZDECPROT1STAT_SET/CLR,Decode Protection 1 Status Register" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TZ_WDT_CTL ,TZ WDOG timer halt in debug halted state / any device reset request blockade by RSTRQ_DIS allowance" "Not halted/Not allowed,Halted/Allowed" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SPIDEN ,Global secure privileged invasive debug" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SPNIDEN ,Global secure privileged non-invasive debug" "Disabled,Enabled" rgroup.long 0xFE0++0x0F line.long 0x00 "TZPCPERIPHID0,TZPC Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,Partnumber0" line.long 0x04 "TZPCPERIPHID1,TZPC Peripheral Identification Register 1" hexmask.long.byte 0x04 4.--7. 1. " DESIGNER0 ,Designer0" hexmask.long.byte 0x04 0.--3. 1. " PARTNUMBER1 ,Partnumber1" line.long 0x08 "TZPCPERIPHID2,TZPC Peripheral Identification Register 2" hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision" hexmask.long.byte 0x08 0.--3. 1. " DESIGNER1 ,Designer1" line.long 0x0C "TZPCPERIPHID3,TZPC Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,Configuration" rgroup.long 0xFF0++0x0F line.long 0x00 "TZPCPCELLID0,TZPC Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " TZPCPCELLID0 ,TZPCPCELLID0" line.long 0x04 "TZPCPCELLID1,TZPC Identification Register 1" hexmask.long.byte 0x04 0.--7. 1. " TZPCPCELLID1 ,TZPCPCELLID1" line.long 0x08 "TZPCPCELLID2,TZPC Identification Register 2" hexmask.long.byte 0x08 0.--7. 1. " TZPCPCELLID2 ,TZPCPCELLID2" line.long 0x0C "TZPCPCELLID3,TZPC Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " TZPCPCELLID3 ,TZPCPCELLID3" width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "SFP (Security Fuse Processor)" base ad:0x01E80000 width 13. group.long 0x20++0x03 line.long 0x00 "SFP_INGR,Instruction Register" bitfld.long 0x00 8. " ERR ,Error status" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " INST ,Instruction" rgroup.long 0x24++0x03 line.long 0x00 "SFP_SVHESR,Secret Value Hamming Error Status Register" hexmask.long.word 0x00 11.--18. 1. " OEL ,OTPMKR error location" bitfld.long 0x00 10. " OPE ,OTPMKR parity error" "No error,Error" bitfld.long 0x00 1.--6. " DEL ,DRVR error location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. " DPE ,DRVR parity error" "No error,Error" if (((per.l(ad:0x01E80000+0x28))&0x40000000)==0x00) group.long 0x28++0x03 line.long 0x00 "SFP_SFPCR,SFP Configuration Register" bitfld.long 0x00 31. " SFPWD ,SFP write disable" "No,Yes" bitfld.long 0x00 30. " SFPWDL ,SFP write disable lock" "Not locked,Locked" rbitfld.long 0x00 29. " SB ,Secure boot" "Not configured,Configured" newline hexmask.long.word 0x00 0.--15. 1. " PPW ,Program pulse width" else group.long 0x28++0x03 line.long 0x00 "SFP_SFPCR,SFP Configuration Register" rbitfld.long 0x00 31. " SFPWD ,SFP write disable" "No,Yes" bitfld.long 0x00 30. " SFPWDL ,SFP write disable lock" "Not locked,Locked" rbitfld.long 0x00 29. " SB ,Secure boot" "Not configured,Configured" newline hexmask.long.word 0x00 0.--15. 1. " PPW ,Program pulse width" endif rgroup.long 0x38++0x03 line.long 0x00 "SFP_VERSION,SFP Version Register" hexmask.long.byte 0x00 16.--19. 1. " MAJOR ,Major revision level" hexmask.long.byte 0x00 8.--11. 1. " MINOR ,Minor revision level" hexmask.long.byte 0x00 0.--3. 1. " SUB ,Sub-version" if (((per.l(ad:0x01E80000+0x200))&0x01)==0x00) group.long 0x200++0x03 line.long 0x00 "SFP_OSPR,OEM Security Policy Register" bitfld.long 0x00 31. " FR1 ,Secure boot ability disable" "No,Yes" bitfld.long 0x00 30. " FR0 ,Secure boot ability disable" "No,Yes" newline bitfld.long 0x00 15. " KREV0 ,Key revocation: first key" "Not revoked,Revoked" bitfld.long 0x00 14. " KREV1 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 13. " KREV2 ,Key revocation: third key" "Not revoked,Revoked" newline bitfld.long 0x00 12. " KREV3 ,Key revocation: first key" "Not revoked,Revoked" bitfld.long 0x00 11. " KREV4 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 10. " KREV5 ,Key revocation: third key" "Not revoked,Revoked" newline bitfld.long 0x00 9. " KREV6 ,Key revocation: first key" "Not revoked,Revoked" bitfld.long 0x00 5. " ZUCD ,Disable ZUC crypto engine" "No,Yes" bitfld.long 0x00 4. " NSEC ,Disable SEC encryption algorithms" "No,Yes" newline bitfld.long 0x00 2. " ITS ,Intent to secure" "Non-secure,Secure" bitfld.long 0x00 1. " CSFF ,Clear sensitive flip flops" "Not cleared,Cleared" bitfld.long 0x00 0. " WP ,Write protect OEM section of SFP" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "SFP_OSPR,OEM Security Policy Register" bitfld.long 0x00 31. " FR1 ,Secure boot ability disable" "No,Yes" bitfld.long 0x00 30. " FR0 ,Secure boot ability disable" "No,Yes" newline bitfld.long 0x00 15. " KREV0 ,Key revocation: first key" "Not revoked,Revoked" bitfld.long 0x00 14. " KREV1 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 13. " KREV2 ,Key revocation: third key" "Not revoked,Revoked" newline bitfld.long 0x00 12. " KREV3 ,Key revocation: first key" "Not revoked,Revoked" bitfld.long 0x00 11. " KREV4 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 10. " KREV5 ,Key revocation: third key" "Not revoked,Revoked" newline bitfld.long 0x00 9. " KREV6 ,Key revocation: first key" "Not revoked,Revoked" rbitfld.long 0x00 5. " ZUCD ,Disable ZUC crypto engine" "No,Yes" rbitfld.long 0x00 4. " NSEC ,Disable SEC encryption algorithms" "No,Yes" newline rbitfld.long 0x00 2. " ITS ,Intent to secure" "Non-secure,Secure" rbitfld.long 0x00 1. " CSFF ,Clear sensitive flip flops" "Not cleared,Cleared" rbitfld.long 0x00 0. " WP ,Write protect OEM section of SFP" "Disabled,Enabled" endif newline if (((per.l(ad:0x01E80000+0x200))&0x01)==0x00) group.long 0x204++0x03 line.long 0x00 "SFP_OSPR1,OEM Security Policy Register 1" hexmask.long.word 0x00 16.--31. 1. " MCTR ,Monotonic counter" hexmask.long.word 0x00 7.--15. 1. " SBS ,Secondary boot source" bitfld.long 0x00 0.--2. " DBLEV ,Debug level" "Wide open,Condit. open w/o notif.,Condit. open w/ notif.,Condit. open w/ notif.,Closed,Closed,Closed,Closed" else rgroup.long 0x204++0x03 line.long 0x00 "SFP_OSPR1,OEM Security Policy Register 1" hexmask.long.word 0x00 16.--31. 1. " MCTR ,Monotonic counter" hexmask.long.word 0x00 7.--15. 1. " SBS ,Secondary boot source" bitfld.long 0x00 0.--2. " DBLEV ,Debug level" "Wide open,Condit. open w/o notif.,Condit. open w/ notif.,Condit. open w/ notif.,Closed,Closed,Closed,Closed" endif newline group.long 0x208++0x03 line.long 0x00 "SFP_DCVR0,Debug Challenge Value Register 0" group.long 0x20C++0x03 line.long 0x00 "SFP_DCVR1,Debug Challenge Value Register 1" wgroup.long 0x210++0x03 line.long 0x00 "SFP_DRVR0,Debug Response Value Register 0" wgroup.long 0x214++0x03 line.long 0x00 "SFP_DRVR1,Debug Response Value Register 1" if (((per.l(ad:0x01E80000+0x218))&0x01)==0x00) group.long 0x218++0x03 line.long 0x00 "SFP_FSWPR,Freescale Section Write Protect Register" bitfld.long 0x00 9. " RDPL1 ,Redeploy 1" "Not redeployed,Redeployed" bitfld.long 0x00 8. " RDPL0 ,Redeploy 0" "Not redeployed,Redeployed" bitfld.long 0x00 6.--7. " AUX ,AUX bits connected to SFP outputs" "0,1,2,3" bitfld.long 0x00 5. " RT ,Return to testable" "Not returned,Returned" newline bitfld.long 0x00 4. " DPL ,Deploy to the field" "Not deployed,Deployed" bitfld.long 0x00 3. " CSFF ,Clear sensitive flip-flops (factory version)" "Not cleared,Cleared" bitfld.long 0x00 2. " NB ,Disable battery back-up" "No,Yes" bitfld.long 0x00 1. " NSEC ,Disable secure features" "No,Yes" newline bitfld.long 0x00 0. " WP ,Write protect Freescale section of SFP enable" "Disabled,Enabled" else group.long 0x218++0x03 line.long 0x00 "SFP_FSWPR,Freescale Section Write Protect Register" bitfld.long 0x00 9. " RDPL1 ,Redeploy 1" "Not redeployed,Redeployed" bitfld.long 0x00 8. " RDPL0 ,Redeploy 0" "Not redeployed,Redeployed" bitfld.long 0x00 6.--7. " AUX ,AUX bits connected to SFP outputs" "0,1,2,3" bitfld.long 0x00 5. " RT ,Return to testable" "Not returned,Returned" newline bitfld.long 0x00 4. " DPL ,Deploy to the field" "Not deployed,Deployed" rbitfld.long 0x00 3. " CSFF ,Clear sensitive flip-flops (FSL version)" "Not cleared,Cleared" rbitfld.long 0x00 2. " NB ,Disable battery back-up" "No,Yes" rbitfld.long 0x00 1. " NSEC ,Disable secure features" "No,Yes" newline bitfld.long 0x00 0. " WP ,Write protect Freescale section of SFP enable" "Disabled,Enabled" endif if (((per.l(ad:0x01E80000+0x218))&0x01)==0x00) group.long 0x21C++0x03 line.long 0x00 "SFP_FUIDR0,Freescale Unique ID Register 0" group.long 0x220++0x03 line.long 0x00 "SFP_FUIDR1,Freescale Unique ID Register 1" else rgroup.long 0x21C++0x03 line.long 0x00 "SFP_FUIDR0,Freescale Unique ID Register 0" rgroup.long 0x220++0x03 line.long 0x00 "SFP_FUIDR1,Freescale Unique ID Register 1" endif group.long 0x224++0x03 line.long 0x00 "SFP_ISBCCR,ISBC Configuration Register" hexmask.long.word 0x00 16.--31. 1. " ISBCV ,ISBC configuration value" group.long 0x228++0x03 line.long 0x00 "SFP_FSPFR0,Freescale Scratch Pad Fuse Register 0" group.long 0x22C++0x03 line.long 0x00 "SFP_FSPFR1,Freescale Scratch Pad Fuse Register 1" group.long 0x230++0x03 line.long 0x00 "SFP_FSPFR2,Freescale Scratch Pad Fuse Register 2" wgroup.long 0x234++0x03 line.long 0x00 "SFP_OTPMKR0,One Time Programmable Master Key 0" wgroup.long 0x238++0x03 line.long 0x00 "SFP_OTPMKR1,One Time Programmable Master Key 1" wgroup.long 0x23C++0x03 line.long 0x00 "SFP_OTPMKR2,One Time Programmable Master Key 2" wgroup.long 0x240++0x03 line.long 0x00 "SFP_OTPMKR3,One Time Programmable Master Key 3" wgroup.long 0x244++0x03 line.long 0x00 "SFP_OTPMKR4,One Time Programmable Master Key 4" wgroup.long 0x248++0x03 line.long 0x00 "SFP_OTPMKR5,One Time Programmable Master Key 5" wgroup.long 0x24C++0x03 line.long 0x00 "SFP_OTPMKR6,One Time Programmable Master Key 6" wgroup.long 0x250++0x03 line.long 0x00 "SFP_OTPMKR7,One Time Programmable Master Key 7" group.long 0x254++0x03 line.long 0x00 "SFP_SRKHR0,Super Root Key Hash 0" group.long 0x258++0x03 line.long 0x00 "SFP_SRKHR1,Super Root Key Hash 1" group.long 0x25C++0x03 line.long 0x00 "SFP_SRKHR2,Super Root Key Hash 2" group.long 0x260++0x03 line.long 0x00 "SFP_SRKHR3,Super Root Key Hash 3" group.long 0x264++0x03 line.long 0x00 "SFP_SRKHR4,Super Root Key Hash 4" group.long 0x268++0x03 line.long 0x00 "SFP_SRKHR5,Super Root Key Hash 5" group.long 0x26C++0x03 line.long 0x00 "SFP_SRKHR6,Super Root Key Hash 6" group.long 0x270++0x03 line.long 0x00 "SFP_SRKHR7,Super Root Key Hash 7" if (((per.l(ad:0x01E80000+0x200))&0x01)==0x00) group.long 0x274++0x03 line.long 0x00 "SFP_OUIDR0,OEM Unique ID/Scratch Pad Fuse Register 0" group.long 0x278++0x03 line.long 0x00 "SFP_OUIDR1,OEM Unique ID/Scratch Pad Fuse Register 1" group.long 0x27C++0x03 line.long 0x00 "SFP_OUIDR2,OEM Unique ID/Scratch Pad Fuse Register 2" else rgroup.long 0x274++0x03 line.long 0x00 "SFP_OUIDR0,OEM Unique ID/Scratch Pad Fuse Register 0" rgroup.long 0x278++0x03 line.long 0x00 "SFP_OUIDR1,OEM Unique ID/Scratch Pad Fuse Register 1" rgroup.long 0x27C++0x03 line.long 0x00 "SFP_OUIDR2,OEM Unique ID/Scratch Pad Fuse Register 2" endif group.long 0x280++0x07 line.long 0x00 "SFP_OUIDR3,OEM Unique ID/Scratch Pad Fuse Register 3" line.long 0x04 "SFP_OUIDR4,OEM Unique ID/Scratch Pad Fuse Register 4" width 0x0B tree.end else tree "SFP (Security Fuse Processor)" base ad:0x01E80000 width 13. endian.be group.long 0x20++0x03 line.long 0x00 "SFP_INGR,Instruction Register" hexmask.long.byte 0x00 24.--31. 1. " INST ,Instruction" bitfld.long 0x00 23. " ERR ,Error status" "No error,Error" rgroup.long 0x24++0x03 line.long 0x00 "SFP_SVHESR,Secret Value Hamming Error Status Register" bitfld.long 0x00 31. " DPE ,DRVR parity error" "No error,Error" newline bitfld.long 0x00 25.--30. " DEL ,DRVR error location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " OPE ,OTPMKR parity error" "No error,Error" hexmask.long.word 0x00 13.--20. 1. " OEL ,OTPMKR error location" group.long 0x28++0x03 line.long 0x00 "SFP_SFPCR,SFP Configuration Register" hexmask.long.word 0x00 16.--31. 1. " PPW ,Program pulse width" bitfld.long 0x00 0. " SFPWD ,SFP write disable" "No,Yes" rgroup.long 0x38++0x03 line.long 0x00 "SFP_VERSION,SFP Version Register" hexmask.long.byte 0x00 28.--31. 1. " SUB ,Sub-version" hexmask.long.byte 0x00 20.--23. 1. " MINOR ,Minor revision level" hexmask.long.byte 0x00 12.--15. 1. " MAJOR ,Major revision level" if (((per.l.be(ad:0x01E80000+0x200))&0x080000000)==0x00) group.long 0x200++0x03 line.long 0x00 "SFP_OSPR,OEM Security Policy Register" bitfld.long 0x00 31. " WP ,Write protect OEM section of SFP" "Disabled,Enabled" bitfld.long 0x00 30. " CSFF ,Clear sensitive flip flops" "Not cleared,Cleared" bitfld.long 0x00 29. " ITS ,Intent to secure" "Non-secure,Secure" bitfld.long 0x00 27. " NSEC ,Disable SEC encryption algorithms" "No,Yes" newline bitfld.long 0x00 26. " ZUCD ,Disable ZUC crypto engine" "No,Yes" bitfld.long 0x00 18. " KREV2 ,Key revocation: third key" "Not revoked,Revoked" bitfld.long 0x00 17. " KREV1 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 16. " KREV0 ,Key revocation: first key" "Not revoked,Revoked" else group.long 0x200++0x03 line.long 0x00 "SFP_OSPR,OEM Security Policy Register" rbitfld.long 0x00 31. " WP ,Write protect OEM section of SFP" "Disabled,Enabled" rbitfld.long 0x00 30. " CSFF ,Clear sensitive flip flops" "Not cleared,Cleared" rbitfld.long 0x00 29. " ITS ,Intent to secure" "Non-secure,Secure" rbitfld.long 0x00 27. " NSEC ,Disable SEC encryption algorithms" "No,Yes" newline rbitfld.long 0x00 26. " ZUCD ,Disable ZUC crypto engine" "No,Yes" bitfld.long 0x00 18. " KREV2 ,Key revocation: third key" "Not revoked,Revoked" bitfld.long 0x00 17. " KREV1 ,Key revocation: second key" "Not revoked,Revoked" bitfld.long 0x00 16. " KREV0 ,Key revocation: first key" "Not revoked,Revoked" endif newline if (((per.l.be(ad:0x01E80000+0x200))&0x080000000)==0x00) group.long 0x204++0x03 line.long 0x00 "SFP_OSPR1,OEM Security Policy Register 1" bitfld.long 0x00 29.--31. " DBLEV ,Debug level" "Wide open,Condit. open w/o notif.,Condit. open w/ notif.,Condit. open w/ notif.,Closed,Closed,Closed,Closed" else rgroup.long 0x204++0x03 line.long 0x00 "SFP_OSPR1,OEM Security Policy Register 1" bitfld.long 0x00 29.--31. " DBLEV ,Debug level" "Wide open,Condit. open w/o notif.,Condit. open w/ notif.,Condit. open w/ notif.,Closed,Closed,Closed,Closed" endif newline group.long 0x208++0x03 line.long 0x00 "SFP_DCVR0,Debug Challenge Value Register 0" group.long 0x20C++0x03 line.long 0x00 "SFP_DCVR1,Debug Challenge Value Register 1" wgroup.long 0x210++0x03 line.long 0x00 "SFP_DRVR0,Debug Response Value Register 0" wgroup.long 0x214++0x03 line.long 0x00 "SFP_DRVR1,Debug Response Value Register 1" if (((per.l.be(ad:0x01E80000+0x218))&0x080000000)==0x00) group.long 0x218++0x03 line.long 0x00 "SFP_FSWPR,Freescale Section Write Protect Register" bitfld.long 0x00 31. " WP ,Write protect Freescale section of SFP enable" "Disabled,Enabled" bitfld.long 0x00 30. " NSEC ,Disable secure features" "No,Yes" bitfld.long 0x00 29. " NB ,Disable battery back-up" "No,Yes" bitfld.long 0x00 28. " CSFF ,Clear sensitive flip-flops (factory version)" "Not cleared,Cleared" else group.long 0x218++0x03 line.long 0x00 "SFP_FSWPR,Freescale Section Write Protect Register" bitfld.long 0x00 31. " WP ,Write protect Freescale section of SFP enable" "Disabled,Enabled" rbitfld.long 0x00 30. " NSEC ,Disable secure features" "No,Yes" rbitfld.long 0x00 29. " NB ,Disable battery back-up" "No,Yes" rbitfld.long 0x00 28. " CSFF ,Clear sensitive flip-flops (FSL version)" "Not cleared,Cleared" endif if (((per.l.be(ad:0x01E80000+0x218))&0x080000000)==0x00) group.long 0x21C++0x03 line.long 0x00 "SFP_FUIDR0,Freescale Unique ID Register 0" group.long 0x220++0x03 line.long 0x00 "SFP_FUIDR1,Freescale Unique ID Register 1" else rgroup.long 0x21C++0x03 line.long 0x00 "SFP_FUIDR0,Freescale Unique ID Register 0" rgroup.long 0x220++0x03 line.long 0x00 "SFP_FUIDR1,Freescale Unique ID Register 1" endif group.long 0x224++0x03 line.long 0x00 "SFP_ISBCCR,ISBC Configuration Register" hexmask.long.word 0x00 0.--15. 1. " ISBCV ,ISBC configuration value" group.long 0x228++0x03 line.long 0x00 "SFP_FSPFR0,Freescale Scratch Pad Fuse Register 0" group.long 0x22C++0x03 line.long 0x00 "SFP_FSPFR1,Freescale Scratch Pad Fuse Register 1" group.long 0x230++0x03 line.long 0x00 "SFP_FSPFR2,Freescale Scratch Pad Fuse Register 2" wgroup.long 0x234++0x03 line.long 0x00 "SFP_OTPMKR0,One Time Programmable Master Key 0" wgroup.long 0x238++0x03 line.long 0x00 "SFP_OTPMKR1,One Time Programmable Master Key 1" wgroup.long 0x23C++0x03 line.long 0x00 "SFP_OTPMKR2,One Time Programmable Master Key 2" wgroup.long 0x240++0x03 line.long 0x00 "SFP_OTPMKR3,One Time Programmable Master Key 3" wgroup.long 0x244++0x03 line.long 0x00 "SFP_OTPMKR4,One Time Programmable Master Key 4" wgroup.long 0x248++0x03 line.long 0x00 "SFP_OTPMKR5,One Time Programmable Master Key 5" wgroup.long 0x24C++0x03 line.long 0x00 "SFP_OTPMKR6,One Time Programmable Master Key 6" wgroup.long 0x250++0x03 line.long 0x00 "SFP_OTPMKR7,One Time Programmable Master Key 7" group.long 0x254++0x03 line.long 0x00 "SFP_SRKHR0,Super Root Key Hash 0" group.long 0x258++0x03 line.long 0x00 "SFP_SRKHR1,Super Root Key Hash 1" group.long 0x25C++0x03 line.long 0x00 "SFP_SRKHR2,Super Root Key Hash 2" group.long 0x260++0x03 line.long 0x00 "SFP_SRKHR3,Super Root Key Hash 3" group.long 0x264++0x03 line.long 0x00 "SFP_SRKHR4,Super Root Key Hash 4" group.long 0x268++0x03 line.long 0x00 "SFP_SRKHR5,Super Root Key Hash 5" group.long 0x26C++0x03 line.long 0x00 "SFP_SRKHR6,Super Root Key Hash 6" group.long 0x270++0x03 line.long 0x00 "SFP_SRKHR7,Super Root Key Hash 7" if (((per.l.be(ad:0x01E80000+0x200))&0x080000000)==0x00) group.long 0x274++0x03 line.long 0x00 "SFP_OUIDR0,OEM Unique ID/Scratch Pad Fuse Register 0" group.long 0x278++0x03 line.long 0x00 "SFP_OUIDR1,OEM Unique ID/Scratch Pad Fuse Register 1" group.long 0x27C++0x03 line.long 0x00 "SFP_OUIDR2,OEM Unique ID/Scratch Pad Fuse Register 2" else rgroup.long 0x274++0x03 line.long 0x00 "SFP_OUIDR0,OEM Unique ID/Scratch Pad Fuse Register 0" rgroup.long 0x278++0x03 line.long 0x00 "SFP_OUIDR1,OEM Unique ID/Scratch Pad Fuse Register 1" rgroup.long 0x27C++0x03 line.long 0x00 "SFP_OUIDR2,OEM Unique ID/Scratch Pad Fuse Register 2" endif group.long 0x280++0x07 line.long 0x00 "SFP_OUIDR3,OEM Unique ID/Scratch Pad Fuse Register 3" line.long 0x04 "SFP_OUIDR4,OEM Unique ID/Scratch Pad Fuse Register 4" endian.le width 0x0B tree.end endif sif cpuis("LS10?6*")||cpuis("LS10?3*")||cpuis("LS1012*") tree "SECMON (Security Monitor)" base ad:0x01E90000 width 14. endian.be group.long 0x00++0x03 line.long 0x00 "HPLR,SM_HP Lock Register" bitfld.long 0x00 18. " HAC_L ,High assurance configuration lock. Write access" "Not locked,Locked" bitfld.long 0x00 17. " HPSICR_L ,HP security interrupt control register lock. Write access" "Not locked,Locked" bitfld.long 0x00 16. " HPSVCR_L ,HP security violation control register lock. Write access" "Not locked,Locked" newline sif !cpuis("LS1012*") bitfld.long 0x00 9. " MKS_SL ,Master key select soft lock. Write access" "Not locked,Locked" newline endif sif cpuis("LS10?6*")||cpuis("LS1012*") bitfld.long 0x00 8. " LPTDCR_SL ,LP tamper detectors configuration register soft lock" "Not locked,Locked" newline endif sif !cpuis("LS1012*") bitfld.long 0x00 6. " LPSVCR_SL ,LP security violation control register soft lock. Write access" "Not locked,Locked" bitfld.long 0x00 5. " GPR_SL ,General purpose register soft lock. Write access" "Not locked,Locked" newline endif sif !cpuis("LS10?3*") bitfld.long 0x00 4. " MC_SL ,Monotonic counter soft lock. Write access" "Not locked,Locked" newline endif sif !cpuis("LS10?6*") bitfld.long 0x00 3. " LPCALB_SL ,LP calibration soft lock. Write access" "Not locked,Locked" newline endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") bitfld.long 0x00 2. " SRTC_SL ,Secure real time counter soft lock" "Not locked,Locked" newline endif bitfld.long 0x00 1. " ZMK_RSL ,Zeroizable master key read soft lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WSL ,Zeroizable master key write soft lock" "Not locked,Locked" if (((per.l.be(ad:0x01E90000))&0x40000)==0x00) group.long 0x04++0x03 line.long 0x00 "HPCOMR,SM_HP Command Register" bitfld.long 0x00 31. " NPSWA_EN ,Non-privileged software access enable" "Disabled,Enabled" bitfld.long 0x00 19. " HAC_STOP ,High assurance counter (HAC) stop" "Not stopped,Stopped" bitfld.long 0x00 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x00 17. " HAC_LOAD ,High assurance counter load" "No effect,Load" newline bitfld.long 0x00 16. " HAC_EN ,High assurance configuration enable" "Disabled,Enabled" newline sif !cpuis("LS1012*") bitfld.long 0x00 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " PROG_ZMK ,Program zeroizable master key. This bit activates ZMK HW programming mechanism." "No effect,Activate" bitfld.long 0x00 10. " SW_LPSV ,LP SW security violation" "Disabled,Enabled" bitfld.long 0x00 9. " SW_FSV ,Software fatal security violation" "Disabled,Enabled" bitfld.long 0x00 8. " SW_SV ,Software security violation" "Disabled,Enabled" newline sif !cpuis("LS1012*") bitfld.long 0x00 5. " LP_SWR_DIS ,LP SW reset disable" "No,Yes" bitfld.long 0x00 4. " LP_SWR ,LP SW reset" "No effect,Reset" newline endif bitfld.long 0x00 2. " SSM_SFNS_DIS ,SSM soft fail to non-secure state transition disable" "No,Yes" bitfld.long 0x00 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x00 0. " SSM_ST ,SSM state transition. Transition state of the security monitor" "0,1" else group.long 0x04++0x03 line.long 0x00 "HPCOMR,SM_HP Command Register" bitfld.long 0x00 31. " NPSWA_EN ,Non-privileged software access enable" "Disabled,Enabled" bitfld.long 0x00 19. " HAC_STOP ,High assurance counter (HAC) stop" "Not stopped,Stopped" bitfld.long 0x00 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x00 17. " HAC_LOAD ,High assurance counter load" "No effect,Load" newline rbitfld.long 0x00 16. " HAC_EN ,High assurance configuration enable" "Disabled,Enabled" newline sif !cpuis("LS1012*") bitfld.long 0x00 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " PROG_ZMK ,Program zeroizable master key. This bit activates ZMK HW programming mechanism." "No effect,Activate" bitfld.long 0x00 10. " SW_LPSV ,LP SW security violation" "Disabled,Enabled" bitfld.long 0x00 9. " SW_FSV ,Software fatal security violation" "Disabled,Enabled" bitfld.long 0x00 8. " SW_SV ,Software security violation" "Disabled,Enabled" newline sif !cpuis("LS1012*") bitfld.long 0x00 5. " LP_SWR_DIS ,LP SW reset disable" "No,Yes" bitfld.long 0x00 4. " LP_SWR ,LP SW reset" "No Action,Reset" newline endif bitfld.long 0x00 2. " SSM_SFNS_DIS ,SSM soft fail to non-secure state transition disable" "No,Yes" bitfld.long 0x00 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x00 0. " SSM_ST ,SSM state transition. Transition state of the security monitor" "0,1" endif if (((per.l.be(ad:0x01E90000+0x08))&0x100)==0x100) group.long 0x08++0x03 line.long 0x00 "HPCR,SM_HP Control Register" bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "No effect,Synchronize" rbitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "+0,+1,+2,+3,+4,+5,+6,+7,+8,+9,+10,+11,+12,+13,+14,+15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,RTC bit number defining the periodic interrupt frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "HPCR,SM_HP Control Register" bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "No effect,Synchronize" bitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "+0,+1,+2,+3,+4,+5,+6,+7,+8,+9,+10,+11,+12,+13,+14,+15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,RTC bit number defining the periodic interrupt frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" endif sif cpuis("LS1012*") if (((per.l.be(ad:0x01E90000))&0x20000)==0x00) group.long 0x0C++0x03 line.long 0x00 "HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SV5_EN ,Central security unit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4 ,TrustZone-WatchDog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ETD_SV_EN ,External tamper detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SDC_SV_EN ,Secure debug controller interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SFP_SV_EN ,Security fuse processor interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RTIC_SV_EN ,RTIC interrupt enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SV5_EN ,Central security unit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4 ,TrustZone-WatchDog interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " ETD_SV_EN ,External tamper detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SDC_SV_EN ,Secure debug controller interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SFP_SV_EN ,Security fuse processor interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RTIC_SV_EN ,RTIC interrupt enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x01E90000))&0x10000)==0x00) group.long 0x10++0x03 line.long 0x00 "HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 5.--6. " SV5_CFG ,Central security unit security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV4_CFG ,TrustZone-WatchDog security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " ETD_SV_CFG ,External tamper detect security violation configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 2. " SDC_SV_CFG ,Secure debug controller security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 1. " SFP_SV_CFG ,Security fuse processor security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " RTIC_SV_CFG ,RTIC security violation configuration" "Non-fatal,Fatal" else rgroup.long 0x10++0x03 line.long 0x00 "HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 5.--6. " SV5_CFG ,Central security unit security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV4_CFG ,TrustZone-WatchDog security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " ETD_SV_CFG ,External tamper detect security violation configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 2. " SDC_SV_CFG ,Secure debug controller security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 1. " SFP_SV_CFG ,Security fuse processor security violation configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " RTIC_SV_CFG ,RTIC security violation configuration" "Non-fatal,Fatal" endif else if (((per.l.be(ad:0x01E90000))&0x20000)==0x00) group.long 0x0C++0x03 line.long 0x00 "HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SV5_EN ,Security violation 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV4_EN ,Security violation 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV3_EN ,Security violation 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SV2_EN ,Security violation 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SV1_EN ,Security violation 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV0_EN ,Security violation 0 interrupt enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " SV5_EN ,Security violation 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV4_EN ,Security violation 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV3_EN ,Security violation 3 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SV2_EN ,Security violation 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " SV1_EN ,Security violation 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV0_EN ,Security violation 0 interrupt enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x01E90000))&0x10000)==0x00) group.long 0x10++0x03 line.long 0x00 "HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 5.--6. " SV5_CFG ,Security violation 5 security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV4_CFG ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " SV3_CFG ,Security violation input 3 configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 2. " SV2_CFG ,Security violation input 2 configuration" "Non-fatal,Fatal" bitfld.long 0x00 1. " SV1_CFG ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " SV0_CFG ,Security violation input 0 configuration" "Non-fatal,Fatal" else rgroup.long 0x10++0x03 line.long 0x00 "HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 5.--6. " SV5_CFG ,Security violation 5 security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV4_CFG ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " SV3_CFG ,Security violation input 3 configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 2. " SV2_CFG ,Security violation input 2 configuration" "Non-fatal,Fatal" bitfld.long 0x00 1. " SV1_CFG ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " SV0_CFG ,Security violation input 0 configuration" "Non-fatal,Fatal" endif endif group.long 0x14++0x03 line.long 0x00 "HPSR,SM_HP Status Register" rbitfld.long 0x00 31. " ZMK_ZERO ,Zeroizable master key is equal to zero" "Not zero,Zero" rbitfld.long 0x00 27. " OTPMK_ZERO ,One time programmable master key is equal to zero" "Not zero,Zero" newline sif !cpuis("LS10?3*")&&!cpuis("LS10?6*") rbitfld.long 0x00 15. " SYS_SECURE_BOOT ,System secure boot" ",Internal ROM" rbitfld.long 0x00 12.--14. " SYS_SECURITY_CFG ,System security configuration" "Fab,Open,,Closed,,,,Field return" newline endif rbitfld.long 0x00 8.--11. " SSM_ST ,Security monitor state" "Init,Hard Fail,,Soft Fail,,,,,Init intermediate,Check,,Non-Secure,,Trusted,,Secure" eventfld.long 0x00 1. " PI ,Periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " HPTA ,HP time alarm" "Not occurred,Occurred" group.long 0x18++0x03 line.long 0x00 "HPSVSR,SM_HP Security Violation Status Register" sif !cpuis("LS10?3*")&&!cpuis("LS10?6*") rbitfld.long 0x00 31. " LP_SEC_VIO ,Security violation detected by the low power section" "Not detected,Detected" newline endif eventfld.long 0x00 27. " ZMK_ECC_FAIL ,Zeroizable master key error correcting code check failure" "Not detected,Detected" hexmask.long.word 0x00 16.--24. 1. " ZMK_SYNDROME ,Zeroizable master key syndrome value" newline sif !cpuis("LS10?3*")&&!cpuis("LS10?6*") rbitfld.long 0x00 15. " SW_LPSV ,Software security violation" "Not detected,Detected" rbitfld.long 0x00 14. " SW_FSV ,Software security violation" "Not detected,Detected" rbitfld.long 0x00 13. " SW_SV ,Software security violation" "Not detected,Detected" newline endif sif cpuis("LS10?3*")||cpuis("LS10?6*") eventfld.long 0x00 5. " SV5 ,Security violation 5 security violation was detected" "Not detected,Detected" eventfld.long 0x00 4. " SV4 ,Security violation 4 security violation was detected" "Not detected,Detected" eventfld.long 0x00 3. " SV3 ,Security violation 3 security violation was detected" "Not detected,Detected" eventfld.long 0x00 2. " SV2 ,Security violation 2 security violation was detected" "Not detected,Detected" newline eventfld.long 0x00 1. " SV1 ,Security violation 1 security violation was detected" "Not detected,Detected" eventfld.long 0x00 0. " SV0 ,Security violation 0 security violation was detected" "Not detected,Detected" else eventfld.long 0x00 5. " SV5 ,Central security unit security violation was detected" "Not detected,Detected" eventfld.long 0x00 4. " SV4 ,TrustZone-WatchDog security violation was detected" "Not detected,Detected" eventfld.long 0x00 3. " ETD_SV ,External tamper detect security violation was detected" "Not detected,Detected" eventfld.long 0x00 2. " SDC_SV ,Secure debug controller security violation was detected" "Not detected,Detected" newline eventfld.long 0x00 1. " SFP_SV ,Security fuse processor security violation was detected" "Not detected,Detected" eventfld.long 0x00 0. " RTIC_SV ,RTIC security violation was detected" "Not detected,Detected" endif if (((per.l.be(ad:0x01E90000))&0x40000)==0x00) group.long 0x1C++0x03 line.long 0x00 "HPHACIVR,SM_HP High Assurance Counter IV Register" else rgroup.long 0x1C++0x03 line.long 0x00 "HPHACIVR,SM_HP High Assurance Counter IV Register" endif rgroup.long 0x20++0x03 line.long 0x00 "HPHACR,SM_HP High Assurance Counter Register" if (((per.l.be(ad:0x01E90000+0x08))&0x01)==0x00) group.long 0x24++0x07 line.long 0x00 "HPRTCMR,SM_HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter most-significant bits" line.long 0x04 "HPRTCLR,SM_HP Real Time Counter LSB Register" else rgroup.long 0x24++0x07 line.long 0x00 "HPRTCMR,SM_HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP real time counter most-significant bits" line.long 0x04 "HPRTCLR,SM_HP Real Time Counter LSB Register" endif if (((per.l.be(ad:0x01E90000+0x08))&0x02)==0x00) group.long 0x2C++0x07 line.long 0x00 "HPTAMR,SM_HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP real time counter most-significant bits" line.long 0x04 "HPTALR,SM_HP Time Alarm LSB Register" else rgroup.long 0x2C++0x07 line.long 0x00 "HPTAMR,SM_HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP real time counter most-significant bits" line.long 0x04 "HPTALR,SM_HP Time Alarm LSB Register" endif sif !cpuis("LS1012*") group.long 0x34++0x07 line.long 0x00 "LPLR,SM_LP Lock Register" bitfld.long 0x00 9. " MKS_HL ,Master key select hard lock. Write access" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_HL ,LP tamper detectors configuration register hard lock. Write access" "Not locked,Locked" bitfld.long 0x00 6. " LPSVCR_HL ,LP security violation control register hard lock. Write access" "Not locked,Locked" bitfld.long 0x00 5. " GPR_HL ,General purpose register hard lock. Write access" "Not locked,Locked" newline bitfld.long 0x00 4. " MC_HL ,Monotonic counter hard lock. Write access" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_HL ,LP calibration hard lock" "Not locked,Locked" bitfld.long 0x00 2. " SRTC_HL ,Secure real time counter hard lock" "Not locked,Locked" bitfld.long 0x00 1. " ZMK_RHL ,Zeroizable master key read hard lock" "Not locked,Locked" newline bitfld.long 0x00 0. " ZMK_WHL ,Zeroizable master key write hard lock" "Not locked,Locked" line.long 0x04 "LPCR,SM_LP Control Register" bitfld.long 0x04 10.--14. " LPCALB_VAL ,LP calibration value" "+0,+1,+2,+3,+4,+5,+6,+7,+8,+9,+10,+11,+12,+13,+14,+15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x04 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" bitfld.long 0x04 4. " SRTC_INV_EN ,Secure real time counter invalidation enable" "Disabled,Enabled" bitfld.long 0x04 2. " MC_ENV ,Monotonic counter enabled and valid" "Disabled,Enabled" newline bitfld.long 0x04 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x04 0. " SRTC_ENV ,Secure real time counter enable and valid" "Disabled/invalid,Enabled and valid" if ((((per.l.be(ad:0x01E90000+0x34))&0x03)==0x00)&&(((per.l.be(ad:0x01E90000))&0x01)==0x00)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l.be(ad:0x01E90000+0x34))&0x03)==0x01)&&(((per.l.be(ad:0x01E90000))&0x01)==0x00)) rgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l.be(ad:0x01E90000+0x34))&0x03)==0x02)&&(((per.l.be(ad:0x01E90000))&0x01)==0x00)) wgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l.be(ad:0x01E90000+0x34))&0x03)==0x00)&&(((per.l.be(ad:0x01E90000))&0x01)==0x01)) group.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" rbitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" rbitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" rbitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l.be(ad:0x01E90000+0x34))&0x03))==0x01&&(((per.l.be(ad:0x01E90000))&0x01)==0x01)) rgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l.be(ad:0x01E90000+0x34))&0x03))==0x02&&(((per.l.be(ad:0x01E90000))&0x01)==0x01)) wgroup.long 0x3C++0x03 line.long 0x00 "LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" else hgroup.long 0x3C++0x03 hide.long 0x00 "LPMKCR,SM_LP Master Key Control Register" endif if (((per.l.be(ad:0x01E90000+0x34))&0x40)==0x00) group.long 0x40++0x03 line.long 0x00 "LPSVCR,SM_LP Security Violation Control Register" bitfld.long 0x00 5. " SV5_EN ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV4_EN ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV3_EN ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV2_EN ,Security violation 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SV1_EN ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV0_EN ,Security violation 0 enable" "Disabled,Enabled" else rgroup.long 0x40++0x03 line.long 0x00 "LPSVCR,SM_LP Security Violation Control Register" bitfld.long 0x00 5. " SV5_EN ,Security violation 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " SV4_EN ,Security violation 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SV3_EN ,Security violation 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SV2_EN ,Security violation 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SV1_EN ,Security violation 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SV0_EN ,Security violation 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x01E90000+0x34))&0x100)==0x00) group.long 0x48++0x03 line.long 0x00 "LPTDCR,SM_LP Tamper Detectors Configuration Register" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not bypassed,Bypassed" bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (POR) observability flop" "0,1" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (PFD) observability flop" "0,1" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" else rgroup.long 0x48++0x03 line.long 0x00 "LPTDCR,SM_LP Tamper Detectors Configuration Register" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not bypassed,Bypassed" bitfld.long 0x00 15. " POR_OBSERV ,Power on reset (POR) observability flop" "0,1" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector (PFD) observability flop" "0,1" bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" endif group.long 0x4C++0x03 line.long 0x00 "LPSR,SM_LP Status Register" rbitfld.long 0x00 31. " LPS ,LP section is secured. Indicates that LP section was provisioned/programmed in the secure or trusted state" "Not programmed,Programmed" rbitfld.long 0x00 30. " LPNS ,LP section is non-secured. Indicates that LP section was provisioned/programmed in the non-secure state" "Not programmed,Programmed" eventfld.long 0x00 16. " ESVD ,External security violation detected" "No violation,Violation" eventfld.long 0x00 9. " ET1D ,External tampering 1 (LP_TMP_DETECT_B) detected" "Not detected,Detected" newline eventfld.long 0x00 3. " PGD ,Power supply glitch detected" "Not detected,Detected" eventfld.long 0x00 2. " MCR ,Monotonic counter rollover. MC maximum value reached" "Not reached,Reached" eventfld.long 0x00 1. " SRTCR ,Secure real time counter rollover. SRTC maximum value reached" "Not reached,Reached" eventfld.long 0x00 0. " LPTA ,LP time alarm. A time alarm interrupt occurred" "No interrupt,Interrupt" endif if ((((per.l.be(ad:0x01E90000+0x38))&0x01)==0x00)&&(((per.l.be(ad:0x01E90000))&0x08)==0x00)&&(((per.l.be(ad:0x01E90000+0x34))&0x04)==0x00)) group.long 0x50++0x07 line.long 0x00 "LPSRTCMR,SM_LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--15. 1. " SRTC ,LP secure real time counter most-significant bits" line.long 0x04 "LPSRTCLR,SM_LP Secure Real Time Counter LSB Register" else rgroup.long 0x50++0x07 line.long 0x00 "LPSRTCMR,SM_LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--15. 1. " SRTC ,LP secure real time counter most-significant bits" line.long 0x04 "LPSRTCLR,SM_LP Secure Real Time Counter LSB Register" endif if (((per.l.be(ad:0x01E90000+0x38))&0x02)==0x00) group.long 0x58++0x03 line.long 0x00 "LPTAR,SM_LP Time Alarm Register" else rgroup.long 0x58++0x03 line.long 0x00 "LPTAR,SM_LP Time Alarm Register" endif if ((((per.l.be(ad:0x01E90000))&0x10)==0x00)&&(((per.l.be(ad:0x01E90000+0x34))&0x10)==0x00)) group.long 0x5C++0x07 line.long 0x00 "LPSMCMR,SM_LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA ,Monotonic counter era bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic counter most-significant 16 bits" line.long 0x04 "LPSMCLR,SM_LP Secure Monotonic Counter LSB Register" else rgroup.long 0x5C++0x07 line.long 0x00 "LPSMCMR,SM_LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA ,Monotonic counter era bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic counter most-significant 16 bits" line.long 0x04 "LPSMCLR,SM_LP Secure Monotonic Counter LSB Register" endif group.long 0x64++0x03 line.long 0x00 "LPPGDR,SM_LP Power Glitch Detector Register" sif !cpuis("LS1012*") if ((((per.l.be(ad:0x01E90000))&0x20)==0x00)&&(((per.l.be(ad:0x01E90000+0x34))&0x20)==0x00)) group.long 0x68++0x03 line.long 0x00 "LPGPR0_ALIAS,SM_LP General Purpose Register 0" else rgroup.long 0x68++0x03 line.long 0x00 "LPGPR0_ALIAS,SM_LP General Purpose Register 0" endif if ((per.l.be(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x6C++0x03 line.long 0x00 "LPZMKR0,SM_LP Zeroizable Master Key Register" group.long 0x70++0x03 line.long 0x00 "LPZMKR1,SM_LP Zeroizable Master Key Register" group.long 0x74++0x03 line.long 0x00 "LPZMKR2,SM_LP Zeroizable Master Key Register" group.long 0x78++0x03 line.long 0x00 "LPZMKR3,SM_LP Zeroizable Master Key Register" group.long 0x7C++0x03 line.long 0x00 "LPZMKR4,SM_LP Zeroizable Master Key Register" group.long 0x80++0x03 line.long 0x00 "LPZMKR5,SM_LP Zeroizable Master Key Register" group.long 0x84++0x03 line.long 0x00 "LPZMKR6,SM_LP Zeroizable Master Key Register" group.long 0x88++0x03 line.long 0x00 "LPZMKR7,SM_LP Zeroizable Master Key Register" elif ((per.l.be(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x6C++0x03 line.long 0x00 "LPZMKR0,SM_LP Zeroizable Master Key Register" rgroup.long 0x70++0x03 line.long 0x00 "LPZMKR1,SM_LP Zeroizable Master Key Register" rgroup.long 0x74++0x03 line.long 0x00 "LPZMKR2,SM_LP Zeroizable Master Key Register" rgroup.long 0x78++0x03 line.long 0x00 "LPZMKR3,SM_LP Zeroizable Master Key Register" rgroup.long 0x7C++0x03 line.long 0x00 "LPZMKR4,SM_LP Zeroizable Master Key Register" rgroup.long 0x80++0x03 line.long 0x00 "LPZMKR5,SM_LP Zeroizable Master Key Register" rgroup.long 0x84++0x03 line.long 0x00 "LPZMKR6,SM_LP Zeroizable Master Key Register" rgroup.long 0x88++0x03 line.long 0x00 "LPZMKR7,SM_LP Zeroizable Master Key Register" elif ((per.l.be(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x6C++0x03 line.long 0x00 "LPZMKR0,SM_LP Zeroizable Master Key Register" wgroup.long 0x70++0x03 line.long 0x00 "LPZMKR1,SM_LP Zeroizable Master Key Register" wgroup.long 0x74++0x03 line.long 0x00 "LPZMKR2,SM_LP Zeroizable Master Key Register" wgroup.long 0x78++0x03 line.long 0x00 "LPZMKR3,SM_LP Zeroizable Master Key Register" wgroup.long 0x7C++0x03 line.long 0x00 "LPZMKR4,SM_LP Zeroizable Master Key Register" wgroup.long 0x80++0x03 line.long 0x00 "LPZMKR5,SM_LP Zeroizable Master Key Register" wgroup.long 0x84++0x03 line.long 0x00 "LPZMKR6,SM_LP Zeroizable Master Key Register" wgroup.long 0x88++0x03 line.long 0x00 "LPZMKR7,SM_LP Zeroizable Master Key Register" else hgroup.long 0x6C++0x03 hide.long 0x00 "LPZMKR0,SM_LP Zeroizable Master Key Register" hgroup.long 0x70++0x03 hide.long 0x00 "LPZMKR1,SM_LP Zeroizable Master Key Register" hgroup.long 0x74++0x03 hide.long 0x00 "LPZMKR2,SM_LP Zeroizable Master Key Register" hgroup.long 0x78++0x03 hide.long 0x00 "LPZMKR3,SM_LP Zeroizable Master Key Register" hgroup.long 0x7C++0x03 hide.long 0x00 "LPZMKR4,SM_LP Zeroizable Master Key Register" hgroup.long 0x80++0x03 hide.long 0x00 "LPZMKR5,SM_LP Zeroizable Master Key Register" hgroup.long 0x84++0x03 hide.long 0x00 "LPZMKR6,SM_LP Zeroizable Master Key Register" hgroup.long 0x88++0x03 hide.long 0x00 "LPZMKR7,SM_LP Zeroizable Master Key Register" endif sif !cpuis("LS10?3*") if ((((per.l.be(ad:0x01E90000))&0x20)==0x00)&&(((per.l.be(ad:0x01E90000+0x34))&0x20)==0x00)) group.long 0x90++0x03 line.long 0x00 "LPGPR0,SM_LP General Purpose Register 0" group.long 0x94++0x03 line.long 0x00 "LPGPR1,SM_LP General Purpose Register 1" group.long 0x98++0x03 line.long 0x00 "LPGPR2,SM_LP General Purpose Register 2" group.long 0x9C++0x03 line.long 0x00 "LPGPR3,SM_LP General Purpose Register 3" else rgroup.long 0x90++0x03 line.long 0x00 "LPGPR0,SM_LP General Purpose Register 0" rgroup.long 0x94++0x03 line.long 0x00 "LPGPR1,SM_LP General Purpose Register 1" rgroup.long 0x98++0x03 line.long 0x00 "LPGPR2,SM_LP General Purpose Register 2" rgroup.long 0x9C++0x03 line.long 0x00 "LPGPR3,SM_LP General Purpose Register 3" endif endif endif rgroup.long 0xBF8++0x07 line.long 0x00 "HPVIDR1,SM_HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,Security monitor module ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,Security monitor module major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,Security monitor module minor version number" line.long 0x04 "HPVIDR2,SM_HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,IP ERA option" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,Security monitor integration option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,Security monitor ECO revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,Security monitor configuration option" endian.le width 0x0B tree.end else tree "SECMON (Security Monitor)" base ad:0x01E90000 width 21. group.long 0x00++0x03 line.long 0x00 "SECMON_HPLR,SM_HP Lock Register" bitfld.long 0x00 18. " HAC_L ,High assurance configuration write lock" "Not locked,Locked" bitfld.long 0x00 17. " HPSICR_L ,HP security interrupt control register write lock" "Not locked,Locked" bitfld.long 0x00 16. " HPSVCR_L ,HP security violation control register write lock" "Not locked,Locked" bitfld.long 0x00 9. " MKS_SL ,Master key select soft lock" "Not locked,Locked" newline bitfld.long 0x00 8. " LPTDCR_SL ,LP tamper detectors configuration register soft lock" "Not locked,Locked" bitfld.long 0x00 6. " LPSVCR_SL ,LP security violation control register soft lock" "Not locked,Locked" bitfld.long 0x00 5. " GPR_SL ,General purpose register soft lock. Write access" "Not locked,Locked" bitfld.long 0x00 4. " MC_SL ,Monotonic counter soft lock" "Not locked,Locked" newline bitfld.long 0x00 3. " LPCALB_SL ,LP calibration soft lock" "Not locked,Locked" bitfld.long 0x00 2. " SRTC_SL ,Secure real time counter soft lock" "Not locked,Locked" bitfld.long 0x00 1. " ZMK_RSL ,Zeroizable master key read soft lock" "Not locked,Locked" bitfld.long 0x00 0. " ZMK_WSL ,Zeroizable master key write soft lock" "Not locked,Locked" if (((per.l(ad:0x01E90000))&0x40000)==0x00) group.long 0x04++0x03 line.long 0x00 "SECMON_HPCOMR,SM_HP Command Register" bitfld.long 0x00 31. " NPSWA_EN ,Non-privileged software access enable" "Disabled,Enabled" bitfld.long 0x00 19. " HAC_STOP ,High assurance counter (HAC) stop" "Not stopped,Stopped" bitfld.long 0x00 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x00 17. " HAC_LOAD ,High assurance counter load" "No effect,Load" newline bitfld.long 0x00 16. " HAC_EN ,High assurance counter enable" "Disabled,Enabled" bitfld.long 0x00 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" bitfld.long 0x00 12. " PROG_ZMK ,Zeroizable master key programming" "No effect,Activate" bitfld.long 0x00 10. " SW_LPSV ,LP SW security violation" "Disabled,Enabled" newline bitfld.long 0x00 9. " SW_FSV ,Software fatal security violation" "Disabled,Enabled" bitfld.long 0x00 8. " SW_SV ,Software security violation" "Disabled,Enabled" bitfld.long 0x00 5. " LP_SWR_DIS ,LP SW reset disable" "No,Yes" bitfld.long 0x00 4. " LP_SWR ,LP SW reset" "No effect,Reset" newline bitfld.long 0x00 2. " SSM_SFNS_DIS ,SSM soft fail to non-secure state transition disable" "No,Yes" bitfld.long 0x00 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x00 0. " SSM_ST ,SSM state transition. Transition state of the security monitor" "0,1" else group.long 0x04++0x03 line.long 0x00 "SECMON_HPCOMR,SM_HP Command Register" bitfld.long 0x00 31. " NPSWA_EN ,Non-privileged software access enable" "Disabled,Enabled" bitfld.long 0x00 19. " HAC_STOP ,High assurance counter (HAC) stop" "Not stopped,Stopped" bitfld.long 0x00 18. " HAC_CLEAR ,High assurance counter clear" "No effect,Clear" bitfld.long 0x00 17. " HAC_LOAD ,High assurance counter load" "No effect,Load" newline rbitfld.long 0x00 16. " HAC_EN ,High assurance counter enable" "Disabled,Enabled" bitfld.long 0x00 13. " MKS_EN ,Master key select enable" "Disabled,Enabled" bitfld.long 0x00 12. " PROG_ZMK ,Zeroizable master key programming" "No effect,Activate" bitfld.long 0x00 10. " SW_LPSV ,LP SW security violation" "Disabled,Enabled" newline bitfld.long 0x00 9. " SW_FSV ,Software fatal security violation" "Disabled,Enabled" bitfld.long 0x00 8. " SW_SV ,Software security violation" "Disabled,Enabled" bitfld.long 0x00 5. " LP_SWR_DIS ,LP SW reset disable" "No,Yes" bitfld.long 0x00 4. " LP_SWR ,LP SW reset" "No effect,Reset" newline bitfld.long 0x00 2. " SSM_SFNS_DIS ,SSM soft fail to non-secure state transition disable" "No,Yes" bitfld.long 0x00 1. " SSM_ST_DIS ,SSM secure to trusted state transition disable" "No,Yes" bitfld.long 0x00 0. " SSM_ST ,SSM state transition. Transition state of the security monitor" "0,1" endif group.long 0x08++0x03 line.long 0x00 "SECMON_HPCR,SM_HP Control Register" bitfld.long 0x00 16. " HP_TS ,HP time synchronize" "No effect,Synchronize" bitfld.long 0x00 10.--14. " HPCALB_VAL ,HP calibration value" "+0,+1,+2,+3,+4,+5,+6,+7,+8,+9,+10,+11,+12,+13,+14,+15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x00 8. " HPCALB_EN ,HP real time counter calibration enabled" "Disabled,Enabled" bitfld.long 0x00 4.--7. " PI_FREQ ,RTC bit number defining the periodic interrupt frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " PI_EN ,HP periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " HPTA_EN ,HP time alarm enable" "Disabled,Enabled" bitfld.long 0x00 0. " RTC_EN ,HP real time counter enable" "Disabled,Enabled" if (((per.l(ad:0x01E90000))&0x20000)==0x00) group.long 0x0C++0x03 line.long 0x00 "SECMON_HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4_WDOG ,Security violation interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SVI_EN3_TMP ,Security violation interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SVI_EN2_SDC ,Security violation interrupt 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SVI_EN1_SFP ,Security violation interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SVI_EN0_RTIC ,Security violation interrupt 0 enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "SECMON_HPSICR,SM_HP Security Interrupt Control Register" bitfld.long 0x00 31. " LPSVI_EN ,LP security violation interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SVI_EN4_WDOG ,Security violation interrupt 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SVI_EN3_TMP ,Security violation interrupt 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " SVI_EN2_SDC ,Security violation interrupt 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " SVI_EN1_SFP ,Security violation interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " SVI_EN0_RTIC ,Security violation interrupt 0 enable" "Disabled,Enabled" endif if (((per.l(ad:0x01E90000))&0x10000)==0x00) group.long 0x10++0x03 line.long 0x00 "SECMON_HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV_CFG4_WDOG ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " SV_CFG3_TMP ,Security violation input 3 configuration" "Non-fatal,Fatal" bitfld.long 0x00 2. " SV_CFG2_TMP ,Security violation input 2 configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 1. " SV_CFG1_TMP ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " SV_CFG0_TMP ,Security violation input 0 configuration" "Non-fatal,Fatal" else rgroup.long 0x10++0x03 line.long 0x00 "SECMON_HPSVCR,SM_HP Security Violation Control Register" bitfld.long 0x00 30.--31. " LPSV_CFG ,LP security violation configuration" "Disabled,Non-fatal,Fatal,Fatal" bitfld.long 0x00 4. " SV_CFG4_WDOG ,Security violation input 4 configuration" "Non-fatal,Fatal" bitfld.long 0x00 3. " SV_CFG3_TMP ,Security violation input 3 configuration" "Non-fatal,Fatal" bitfld.long 0x00 2. " SV_CFG2_TMP ,Security violation input 2 configuration" "Non-fatal,Fatal" newline bitfld.long 0x00 1. " SV_CFG1_TMP ,Security violation input 1 configuration" "Non-fatal,Fatal" bitfld.long 0x00 0. " SV_CFG0_TMP ,Security violation input 0 configuration" "Non-fatal,Fatal" endif group.long 0x14++0x07 line.long 0x00 "SECMON_HPSR,SM_HP Status Register" rbitfld.long 0x00 31. " ZMK_ZERO ,Zeroizable master key is equal to zero" "Not zero,Zero" rbitfld.long 0x00 27. " OTPMK_ZERO ,One time programmable master key" "No error,Error" rbitfld.long 0x00 24. " PE ,OTPMK parity error" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " OTPMK_SYNDROME ,Indicates the error location in case of a single-bit error in the OTPMK" newline rbitfld.long 0x00 12.--15. " SYS_SECURITY_CFG ,System security configuration" "Unsecured,Not secured,Secured,?..." rbitfld.long 0x00 8.--11. " SSM_ST ,Security monitor state" "Init,Hard Fail,,Soft Fail,,,,,Init intermediate,Check,,Non-Secure,,Trusted,,Secure" rbitfld.long 0x00 4. " LPDIS ,Low power disable" "No,Yes" eventfld.long 0x00 1. " PI ,Periodic interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " HPTA ,HP time alarm" "Not occurred,Occurred" line.long 0x04 "SECMON_HPSVSR,SM_HP Security Violation Status Register" rbitfld.long 0x04 31. " LP_SEC_VIO ,Security violation detected by the low power section" "Not detected,Detected" eventfld.long 0x04 27. " ZMK_ECC_FAIL ,Zeroizable master key error correcting code check failure" "Not detected,Detected" hexmask.long.word 0x04 16.--24. 1. " ZMK_SYNDROME ,Zeroizable master key syndrome value" rbitfld.long 0x04 15. " SW_LPSV ,Software security violation" "Not detected,Detected" newline rbitfld.long 0x04 14. " SW_FSV ,Software security violation" "Not detected,Detected" rbitfld.long 0x04 13. " SW_SV ,Software security violation" "Not detected,Detected" eventfld.long 0x04 4. " TZ_WD ,TrustZone watchdog security violation detected" "Not detected,Detected" eventfld.long 0x04 3. " ETD_SV ,External Tamper Detect security violation detected" "Not detected,Detected" newline eventfld.long 0x04 2. " SDC_SV ,Secure Debug Controller security violation detected" "Not detected,Detected" eventfld.long 0x04 1. " SFP_SV ,Security Fuse Processor security violation detected" "Not detected,Detected" eventfld.long 0x04 0. " CAAM ,CAAM security violation detected" "Not detected,Detected" if (((per.l(ad:0x01E90000))&0x40000)==0x00) group.long 0x1C++0x03 line.long 0x00 "SECMON_HPHACIVR,SM_HP High Assurance Counter Initial Value Register" else rgroup.long 0x1C++0x03 line.long 0x00 "SECMON_HPHACIVR,SM_HP High Assurance Counter Initial Value Register" endif rgroup.long 0x20++0x03 line.long 0x00 "SECMON_HPHACR,SM_HP High Assurance Counter Register" if (((per.l(ad:0x01E90000+0x08))&0x01)==0x00) group.long 0x24++0x07 line.long 0x00 "SECMON_HPRTCMR,SM_HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP Real Time Counter most-significant bits" line.long 0x04 "SECMON_HPRTCLR,SM_HP Real Time Counter LSB Register" else rgroup.long 0x24++0x07 line.long 0x00 "SECMON_HPRTCMR,SM_HP Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " RTC ,HP Real Time Counter most-significant bits" line.long 0x04 "SECMON_HPRTCLR,SM_HP Real Time Counter LSB Register" endif if (((per.l(ad:0x01E90000+0x08))&0x02)==0x00) group.long 0x2C++0x07 line.long 0x00 "SECMON_HPTAMR,SNVS_HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP Real Time Counter most-significant bits" line.long 0x04 "SECMON_HPTALR,SM_HP Time Alarm LSB Register" else rgroup.long 0x2C++0x07 line.long 0x00 "SECMON_HPTAMR,SNVS_HP Time Alarm MSB Register" hexmask.long.word 0x00 0.--14. 1. " HPTA ,HP Real Time Counter most-significant bits" line.long 0x04 "SECMON_HPTALR,SM_HP Time Alarm LSB Register" endif group.long 0x34++0x07 line.long 0x00 "SECMON_LPLR,SM_LP Lock Register" bitfld.long 0x00 9. " HL ,Master key select hard lock" "Not locked,Locked" bitfld.long 0x00 8. " LPTDCR_HL ,LP tamper detectors configuration register hard lock" "Not locked,Locked" bitfld.long 0x00 6. " LPSVCR_HL ,LP security violation control register hard lock" "Not locked,Locked" bitfld.long 0x00 5. " GPR_HL ,General purpose register hard lock" "Not locked,Locked" newline bitfld.long 0x00 4. " MC_HL ,Monotonic counter hard lock" "Not locked,Locked" bitfld.long 0x00 3. " LPCALB_HL ,LP calibration hard lock" "Not locked,Locked" bitfld.long 0x00 2. " SRTC_HL ,Secure real time counter hard lock" "Not locked,Locked" bitfld.long 0x00 1. " ZMK_RHL ,Zeroizable master key read hard lock" "Not locked,Locked" newline bitfld.long 0x00 0. " ZMK_WHL ,Zeroizable master key write hard lock" "Not locked,Locked" line.long 0x04 "SECMON_LPCR,SM_LP Control Register" bitfld.long 0x04 24. " GPR_Z_DIS ,General purpose registers zeroization disable" "No,Yes" bitfld.long 0x04 10.--14. " LPCALB_VAL ,LP calibration value" "+0,+1,+2,+3,+4,+5,+6,+7,+8,+9,+10,+11,+12,+13,+14,+15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1" bitfld.long 0x04 8. " LPCALB_EN ,LP calibration enable" "Disabled,Enabled" bitfld.long 0x04 4. " SRTC_INV_EN ,Secure real time counter invalidation enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " MC_ENV ,Monotonic counter enable and valid" "Disabled/invalid,Enabled and valid" bitfld.long 0x04 1. " LPTA_EN ,LP time alarm enable" "Disabled,Enabled" bitfld.long 0x04 0. " SRTC_ENV ,Secure real time counter enable and valid" "Disabled/invalid,Enabled and valid" if ((((per.l(ad:0x01E90000+0x34))&0x03)==0x00)&&(((per.l(ad:0x01E90000))&0x01)==0x00)) group.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l(ad:0x01E90000+0x34))&0x03)==0x01)&&(((per.l(ad:0x01E90000))&0x01)==0x00)) rgroup.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l(ad:0x01E90000+0x34))&0x03)==0x02)&&(((per.l(ad:0x01E90000))&0x01)==0x00)) wgroup.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l(ad:0x01E90000+0x34))&0x03)==0x00)&&(((per.l(ad:0x01E90000))&0x01)==0x01)) group.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" rbitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" rbitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" rbitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l(ad:0x01E90000+0x34))&0x03))==0x01&&(((per.l(ad:0x01E90000))&0x01)==0x01)) rgroup.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" bitfld.long 0x00 4. " ZMK_ECC_EN ,Zeroizable master key error correcting code check enable" "Disabled,Enabled" bitfld.long 0x00 3. " ZMK_VAL ,Zeroizable master key valid" "Invalid,Valid" bitfld.long 0x00 2. " ZMK_HWP ,Zeroizable master key HW programming mode" "SW,HW" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" elif ((((per.l(ad:0x01E90000+0x34))&0x03))==0x02&&(((per.l(ad:0x01E90000))&0x01)==0x01)) wgroup.long 0x3C++0x03 line.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" hexmask.long.word 0x00 7.--15. 1. " ZMK_ECC_VALUE ,Zeroizable master key error correcting code value" newline bitfld.long 0x00 0.--1. " MASTER_KEY_SEL ,Master key select" "1-time programmable,1-time programmable,Zeroizable,Combined" else hgroup.long 0x3C++0x03 hide.long 0x00 "SECMON_LPMKCR,SM_LP Master Key Control Register" endif if (((per.l(ad:0x01E90000+0x34))&0x40)==0x00) group.long 0x40++0x03 line.long 0x00 "SECMON_LPSVCR,SM_LP Security Violation Control Register" bitfld.long 0x00 4. " TZ_WD_EN ,TrustZone watchdog reset enable" "Disabled,Enabled" bitfld.long 0x00 3. " ETD_SV_EN ,External tamper detect enable" "Disabled,Enabled" bitfld.long 0x00 2. " SDC_SV_EN ,Secure debug controller enable" "Disabled,Enabled" bitfld.long 0x00 1. " SFP_SV_EN ,Security fuse processor enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CAAM_EN ,CAAM enable" "Disabled,Enabled" else rgroup.long 0x40++0x03 line.long 0x00 "SECMON_LPSVCR,SM_LP Security Violation Control Register" bitfld.long 0x00 4. " TZ_WD_EN ,TrustZone watchdog reset enable" "Disabled,Enabled" bitfld.long 0x00 3. " ETD_SV_EN ,External tamper detect enable" "Disabled,Enabled" bitfld.long 0x00 2. " SDC_SV_EN ,Secure debug controller enable" "Disabled,Enabled" bitfld.long 0x00 1. " SFP_SV_EN ,Security fuse processor enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CAAM_EN ,CAAM enable" "Disabled,Enabled" endif group.long 0x48++0x07 line.long 0x00 "SECMON_LPTDCR,SM_LP Tamper Detectors Configuration Register" bitfld.long 0x00 28. " OSCB ,Oscillator bypass" "Not bypassed,Bypassed" bitfld.long 0x00 15. " POR_OBSERV ,Power on reset observability flop" "0,1" bitfld.long 0x00 14. " PFD_OBSERV ,System power fail detector observability flop" "0,1" bitfld.long 0x00 11. " ET1P ,External tampering 1 polarity" "Active low,Active high" newline bitfld.long 0x00 9. " ET1_EN ,External tampering 1 enable" "Disabled,Enabled" bitfld.long 0x00 2. " MCR_EN ,MC rollover enable" "Disabled,Enabled" bitfld.long 0x00 1. " SRTCR_EN ,SRTC rollover enable" "Disabled,Enabled" line.long 0x04 "SECMON_LPSR,SM_LP Status Register" rbitfld.long 0x04 31. " LPS ,LP section programmed in secure or trusted state" "Not programmed,Programmed" rbitfld.long 0x04 30. " LPNS ,LP section programmed in non-secure state" "Not programmed,Programmed" eventfld.long 0x04 16. " ESVD ,External security violation detected" "No violation,Violation" eventfld.long 0x04 9. " ET1D ,External tampering 1 detected" "Not detected,Detected" newline eventfld.long 0x04 3. " PGD ,Power supply glitch detected" "Not detected,Detected" eventfld.long 0x04 2. " MCR ,Monotonic counter rollover" "Not reached,Reached" eventfld.long 0x04 1. " SRTCR ,Secure real time counter rollover" "Not reached,Reached" eventfld.long 0x04 0. " LPTA ,LP time alarm interrupt status" "No interrupt,Interrupt" if ((((per.l(ad:0x01E90000+0x38))&0x01)==0x00)&&(((per.l(ad:0x01E90000))&0x04)==0x00)&&(((per.l(ad:0x01E90000+0x34))&0x04)==0x00)) group.long 0x50++0x07 line.long 0x00 "SECMON_LPSRTCMR,SM_LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter most-significant bits" line.long 0x04 "SECMON_LPSRTCLR,SM_LP Secure Real Time Counter LSB Register" else rgroup.long 0x50++0x07 line.long 0x00 "SECMON_LPSRTCMR,SM_LP Secure Real Time Counter MSB Register" hexmask.long.word 0x00 0.--14. 1. " SRTC ,LP secure real time counter most-significant bits" line.long 0x04 "SECMON_LPSRTCLR,SM_LP Secure Real Time Counter LSB Register" endif if (((per.l(ad:0x01E90000+0x38))&0x02)==0x00) group.long 0x58++0x03 line.long 0x00 "SECMON_LPTAR,SM_LP Time Alarm Register" else rgroup.long 0x58++0x03 line.long 0x00 "SECMON_LPTAR,SM_LP Time Alarm Register" endif if ((((per.l(ad:0x01E90000))&0x10)==0x00)&&(((per.l(ad:0x01E90000+0x34))&0x10)==0x00)) group.long 0x5C++0x03 line.long 0x00 "SECMON_LPSMCMR,SM_LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic Counter Era Bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic Counter most-significant 16 bits" else rgroup.long 0x5C++0x03 line.long 0x00 "SECMON_LPSMCMR,SM_LP Secure Monotonic Counter MSB Register" hexmask.long.word 0x00 16.--31. 1. " MC_ERA_BITS ,Monotonic Counter Era Bits" hexmask.long.word 0x00 0.--15. 1. " MON_COUNTER ,Monotonic Counter most-significant 16 bits" endif group.long 0x60++0x07 line.long 0x00 "SECMON_LPSMCLR,SM_LP Secure Monotonic Counter LSB Register" line.long 0x04 "SECMON_LPPGDR,SM_LP Power Glitch Detector Register" if ((((per.l(ad:0x01E90000))&0x20)==0x00)&&(((per.l(ad:0x01E90000+0x34))&0x20)==0x00)) group.long 0x68++0x03 line.long 0x00 "SECMON_LPGPR0_ALIAS,SM_LP General Purpose Register 0 Alias" else rgroup.long 0x68++0x03 line.long 0x00 "SECMON_LPGPR0_ALIAS,SM_LP General Purpose Register 0 Alias" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x6C++0x03 line.long 0x00 "SECMON_LPZMKR0,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x6C++0x03 line.long 0x00 "SECMON_LPZMKR0,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x6C++0x03 line.long 0x00 "SECMON_LPZMKR0,SM_LP Zeroizable Master Key Register" else hgroup.long 0x6C++0x03 hide.long 0x00 "SECMON_LPZMKR0,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x70++0x03 line.long 0x00 "SECMON_LPZMKR1,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x70++0x03 line.long 0x00 "SECMON_LPZMKR1,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x70++0x03 line.long 0x00 "SECMON_LPZMKR1,SM_LP Zeroizable Master Key Register" else hgroup.long 0x70++0x03 hide.long 0x00 "SECMON_LPZMKR1,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x74++0x03 line.long 0x00 "SECMON_LPZMKR2,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x74++0x03 line.long 0x00 "SECMON_LPZMKR2,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x74++0x03 line.long 0x00 "SECMON_LPZMKR2,SM_LP Zeroizable Master Key Register" else hgroup.long 0x74++0x03 hide.long 0x00 "SECMON_LPZMKR2,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x78++0x03 line.long 0x00 "SECMON_LPZMKR3,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x78++0x03 line.long 0x00 "SECMON_LPZMKR3,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x78++0x03 line.long 0x00 "SECMON_LPZMKR3,SM_LP Zeroizable Master Key Register" else hgroup.long 0x78++0x03 hide.long 0x00 "SECMON_LPZMKR3,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x7C++0x03 line.long 0x00 "SECMON_LPZMKR4,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x7C++0x03 line.long 0x00 "SECMON_LPZMKR4,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x7C++0x03 line.long 0x00 "SECMON_LPZMKR4,SM_LP Zeroizable Master Key Register" else hgroup.long 0x7C++0x03 hide.long 0x00 "SECMON_LPZMKR4,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x80++0x03 line.long 0x00 "SECMON_LPZMKR5,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x80++0x03 line.long 0x00 "SECMON_LPZMKR5,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x80++0x03 line.long 0x00 "SECMON_LPZMKR5,SM_LP Zeroizable Master Key Register" else hgroup.long 0x80++0x03 hide.long 0x00 "SECMON_LPZMKR5,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x84++0x03 line.long 0x00 "SECMON_LPZMKR6,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x84++0x03 line.long 0x00 "SECMON_LPZMKR6,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x84++0x03 line.long 0x00 "SECMON_LPZMKR6,SM_LP Zeroizable Master Key Register" else hgroup.long 0x84++0x03 hide.long 0x00 "SECMON_LPZMKR6,SM_LP Zeroizable Master Key Register" endif if ((per.l(ad:0x01E90000+0x34))&0x03)==0x00 group.long 0x88++0x03 line.long 0x00 "SECMON_LPZMKR7,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x01 rgroup.long 0x88++0x03 line.long 0x00 "SECMON_LPZMKR7,SM_LP Zeroizable Master Key Register" elif ((per.l(ad:0x01E90000+0x34))&0x03)==0x02 wgroup.long 0x88++0x03 line.long 0x00 "SECMON_LPZMKR7,SM_LP Zeroizable Master Key Register" else hgroup.long 0x88++0x03 hide.long 0x00 "SECMON_LPZMKR7,SM_LP Zeroizable Master Key Register" endif if ((((per.l(ad:0x01E90000))&0x20)==0x00)&&(((per.l(ad:0x01E90000+0x34))&0x20)==0x00)) group.long 0x90++0x03 line.long 0x00 "SECMON_LPGPR0,SM_LP General Purpose Register 0" group.long 0x94++0x03 line.long 0x00 "SECMON_LPGPR1,SM_LP General Purpose Register 1" group.long 0x98++0x03 line.long 0x00 "SECMON_LPGPR2,SM_LP General Purpose Register 2" group.long 0x9C++0x03 line.long 0x00 "SECMON_LPGPR3,SM_LP General Purpose Register 3" else rgroup.long 0x90++0x03 line.long 0x00 "SECMON_LPGPR0,SM_LP General Purpose Register 0" rgroup.long 0x94++0x03 line.long 0x00 "SECMON_LPGPR1,SM_LP General Purpose Register 1" rgroup.long 0x98++0x03 line.long 0x00 "SECMON_LPGPR2,SM_LP General Purpose Register 2" rgroup.long 0x9C++0x03 line.long 0x00 "SECMON_LPGPR3,SM_LP General Purpose Register 3" endif rgroup.long 0xBF8++0x07 line.long 0x00 "SECMON_HPVIDR1,SM_HP Version ID Register 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,Security monitor module ID" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_REV ,Security monitor module major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR_REV ,Security monitor module minor version number" line.long 0x04 "SECMON_HPVIDR2,SM_HP Version ID Register 2" hexmask.long.byte 0x04 24.--31. 1. " IP_ERA ,IP ERA option" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,Security monitor integration option" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,Security monitor ECO revision" hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,Security monitor configuration option" width 0x0B tree.end endif sif cpuis("LS1012*") tree "CSU (Central Security Unit)" base ad:0x01510000 width 11. if (((per.l(ad:0x01510000))&0x100)==0x100) group.long 0x00++0x03 "PCI 1" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x00++0x03 "PCI 1" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x08))&0x1000000)==0x1000000) group.long 0x08++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x08++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x0C))&0x1000100)==0x1000100) group.long 0x0C++0x03 "PCI 1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x0C))&0x1000100)==0x1000000) group.long 0x0C++0x03 "PCI 1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x0C))&0x1000100)==0x0000100) group.long 0x0C++0x03 "PCI 1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x0C++0x03 "PCI 1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x10))&0x1000000)==0x1000000) group.long 0x10++0x03 "QSPI" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x10++0x03 "QSPI" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x14))&0x1000100)==0x1000100) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x14))&0x1000100)==0x1000000) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x14))&0x1000100)==0x0000100) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x2C))&0x100)==0x100) group.long 0x2C++0x03 "PFE" line.long 0x00 "CSU_CSL11,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x2C++0x03 "PFE" line.long 0x00 "CSU_CSL11,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x40))&0x1000000)==0x1000000) group.long 0x40++0x03 "SerDes" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x40++0x03 "SerDes" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x50))&0x1000100)==0x1000100) group.long 0x50++0x03 "SPI1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x50))&0x1000100)==0x1000000) group.long 0x50++0x03 "SPI1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x50))&0x1000100)==0x0000100) group.long 0x50++0x03 "SPI1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x50++0x03 "SPI1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x54))&0x1000100)==0x1000100) group.long 0x54++0x03 "QSPI/eSDHC 1" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x54))&0x1000100)==0x1000000) group.long 0x54++0x03 "QSPI/eSDHC 1" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x54))&0x1000100)==0x0000100) group.long 0x54++0x03 "QSPI/eSDHC 1" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x54++0x03 "QSPI/eSDHC 1" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x1000100) group.long 0x5C++0x03 "I2C1/USB 2.0" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x1000000) group.long 0x5C++0x03 "I2C1/USB 2.0" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x0000100) group.long 0x5C++0x03 "I2C1/USB 2.0" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x5C++0x03 "I2C1/USB 2.0" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x60))&0x1000100)==0x1000100) group.long 0x60++0x03 "I2C2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x60))&0x1000100)==0x1000000) group.long 0x60++0x03 "I2C2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x60))&0x1000100)==0x0000100) group.long 0x60++0x03 "I2C2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x60++0x03 "I2C2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x64))&0x1000100)==0x1000100) group.long 0x64++0x03 "DUART1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x64))&0x1000100)==0x1000000) group.long 0x64++0x03 "DUART1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x64))&0x1000100)==0x0000100) group.long 0x64++0x03 "DUART1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x64++0x03 "DUART1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x68))&0x1000100)==0x1000100) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x68))&0x1000100)==0x1000000) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x68))&0x1000100)==0x0000100) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x1000100) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x1000000) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x0000100) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x70))&0x1000100)==0x1000100) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x70))&0x1000100)==0x1000000) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x70))&0x1000100)==0x0000100) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x74))&0x1000100)==0x1000100) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x74))&0x1000100)==0x1000000) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x74))&0x1000100)==0x0000100) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0x78))&0x1000100)==0x1000100) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x78))&0x1000100)==0x1000000) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x78))&0x1000100)==0x0000100) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x1000100) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x1000000) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x0000100) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x80))&0x1000100)==0x1000100) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x80))&0x1000100)==0x1000000) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x80))&0x1000100)==0x0000100) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x84))&0x1000100)==0x1000100) group.long 0x84++0x03 "SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x84))&0x1000100)==0x1000000) group.long 0x84++0x03 "SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x84))&0x1000100)==0x0000100) group.long 0x84++0x03 "SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x84++0x03 "SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x1000100) group.long 0x8C++0x03 "GPIO2/GPIO1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x1000000) group.long 0x8C++0x03 "GPIO2/GPIO1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x0000100) group.long 0x8C++0x03 "GPIO2/GPIO1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x8C++0x03 "GPIO2/GPIO1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x94))&0x1000100)==0x1000100) group.long 0x94++0x03 "Platform/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x94))&0x1000100)==0x1000000) group.long 0x94++0x03 "Platform/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x94))&0x1000100)==0x0000100) group.long 0x94++0x03 "Platform/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x94++0x03 "Platform/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x98))&0x1000100)==0x1000100) group.long 0x98++0x03 "SAI5" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x98))&0x1000100)==0x1000000) group.long 0x98++0x03 "SAI5" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x98))&0x1000100)==0x0000100) group.long 0x98++0x03 "SAI5" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x98++0x03 "SAI5" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x1000100) group.long 0xA0++0x03 "SDHC2" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x1000000) group.long 0xA0++0x03 "SDHC2" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x0000100) group.long 0xA0++0x03 "SDHC2" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0xA0++0x03 "SDHC2" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0xA4))&0x1000100)==0x1000100) group.long 0xA4++0x03 "SAI2/SAI1" line.long 0x00 "CSU_CSL41,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA4))&0x1000100)==0x1000000) group.long 0xA4++0x03 "SAI2/SAI1" line.long 0x00 "CSU_CSL41,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA4))&0x1000100)==0x0000100) group.long 0xA4++0x03 "SAI2/SAI1" line.long 0x00 "CSU_CSL41,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xA4++0x03 "SAI2/SAI1" line.long 0x00 "CSU_CSL41,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xA8))&0x1000100)==0x1000100) group.long 0xA8++0x03 "SAI4/SAI3" line.long 0x00 "CSU_CSL42,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA8))&0x1000100)==0x1000000) group.long 0xA8++0x03 "SAI4/SAI3" line.long 0x00 "CSU_CSL42,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA8))&0x1000100)==0x0000100) group.long 0xA8++0x03 "SAI4/SAI3" line.long 0x00 "CSU_CSL42,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xA8++0x03 "SAI4/SAI3" line.long 0x00 "CSU_CSL42,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x1000100) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x1000000) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x0000100) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif newline group.long 0x218++0x07 line.long 0x00 "CSU_SA0,Secure Access Register" bitfld.long 0x00 31. " L15_0 ,Secure attribute for PCI express controller 1 lock bit" "Not locked,Locked" bitfld.long 0x00 30. " SA15_0 ,Secure attribute for PCI express controller 1" "Secured,Non-secured" newline bitfld.long 0x00 19. " L9_0 ,Non-secure attribute control for debug components lock bit" "Not locked,Locked" bitfld.long 0x00 18. " SA9_0 ,Non-secure attribute control for debug components" "Secured,Non-secured" bitfld.long 0x00 17. " L8_0 ,CFGDISABLE for GIC-400 lock bit" "Not locked,Locked" bitfld.long 0x00 16. " SA8_0 ,CFGDISABLE for GIC-400" "Secured,Non-secured" newline bitfld.long 0x00 13. " L6_0 ,CP15SDISABLE for core 0 lock bit" "Not locked,Locked" bitfld.long 0x00 12. " SA6_0 ,CP15SDISABLE for core 0" "Secured,Non-secured" bitfld.long 0x00 11. " L5_0 ,Software-Override bit for DBGEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 10. " SA5_0 ,Software-Override bit for DBGEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" newline bitfld.long 0x00 9. " L4_0 ,Software-override bit for SPIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 8. " SA4_0 ,Software-override bit for SPIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" bitfld.long 0x00 7. " L3_0 ,Software-override bit for NIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 6. " SA3_0 ,Software-override bit for NIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" newline bitfld.long 0x00 5. " L2_0 ,Software-override bit for SPNIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 4. " SA2_0 ,Software-override bit for SPNIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" line.long 0x04 "CSU_SA1,Secure Access Register" bitfld.long 0x04 5. " L2_1 ,Secure boot lock for trust-zone address space controller registers lock bit" "Not locked,Locked" bitfld.long 0x04 4. " SA2_1 ,Secure boot lock for trust-zone address space controller registers" "Secured,Non-secured" bitfld.long 0x04 3. " L1_1 ,Trust zone address space controller bypass mux lock bit" "Not locked,Locked" bitfld.long 0x04 2. " SA1_1 ,Trust zone address space controller bypass mux" "Secured,Non-secured" width 0x0B tree.end elif cpuis("LS10?3*")||cpuis("LS10?6*") tree "CSU (Central Security Unit)" base ad:0x01510000 width 11. if (((per.l(ad:0x01510000+0x0))&0x1000100)==0x1000100) group.long 0x0++0x03 "PCI2 IO/PCI1 IO" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x0))&0x1000100)==0x1000000) group.long 0x0++0x03 "PCI2 IO/PCI1 IO" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x0))&0x1000100)==0x0000100) group.long 0x0++0x03 "PCI2 IO/PCI1 IO" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x0++0x03 "PCI2 IO/PCI1 IO" line.long 0x00 "CSU_CSL0,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x4))&0x1000100)==0x1000100) group.long 0x4++0x03 "IFC" line.long 0x00 "CSU_CSL1,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x4))&0x1000100)==0x1000000) group.long 0x4++0x03 "IFC" line.long 0x00 "CSU_CSL1,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x4))&0x1000100)==0x0000100) group.long 0x4++0x03 "IFC" line.long 0x00 "CSU_CSL1,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x4++0x03 "IFC" line.long 0x00 "CSU_CSL1,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x8))&0x1000100)==0x1000100) group.long 0x8++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x8))&0x1000100)==0x1000000) group.long 0x8++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x8))&0x1000100)==0x0000100) group.long 0x8++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0x8++0x03 "OCRAM1" line.long 0x00 "CSU_CSL2,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0xC))&0x1000100)==0x1000100) group.long 0xC++0x03 "PCI1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xC))&0x1000100)==0x1000000) group.long 0xC++0x03 "PCI1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xC))&0x1000100)==0x0000100) group.long 0xC++0x03 "PCI1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xC++0x03 "PCI1/OCRAM2" line.long 0x00 "CSU_CSL3,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x10))&0x1000100)==0x1000100) group.long 0x10++0x03 "QSPI/PCI2" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x10))&0x1000100)==0x1000000) group.long 0x10++0x03 "QSPI/PCI2" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x10))&0x1000100)==0x0000100) group.long 0x10++0x03 "QSPI/PCI2" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x10++0x03 "QSPI/PCI2" line.long 0x00 "CSU_CSL4,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x14))&0x1000100)==0x1000100) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x14))&0x1000100)==0x1000000) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x14))&0x1000100)==0x0000100) group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x14++0x03 "SATA/USB 3.0" line.long 0x00 "CSU_CSL5,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x18))&0x1000100)==0x1000100) group.long 0x18++0x03 "QM BM S/W Portal" line.long 0x00 "CSU_CSL6,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x18))&0x1000100)==0x1000000) group.long 0x18++0x03 "QM BM S/W Portal" line.long 0x00 "CSU_CSL6,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x18))&0x1000100)==0x0000100) group.long 0x18++0x03 "QM BM S/W Portal" line.long 0x00 "CSU_CSL6,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0x18++0x03 "QM BM S/W Portal" line.long 0x00 "CSU_CSL6,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0x20))&0x1000100)==0x1000100) group.long 0x20++0x03 "PCI 3" line.long 0x00 "CSU_CSL8,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x20))&0x1000100)==0x1000000) group.long 0x20++0x03 "PCI 3" line.long 0x00 "CSU_CSL8,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x20))&0x1000100)==0x100) group.long 0x20++0x03 "PCI 3" line.long 0x00 "CSU_CSL8,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x20++0x03 "PCI 3" line.long 0x00 "CSU_CSL8,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x28))&0x1000100)==0x1000100) group.long 0x28++0x03 "USB3/USB" line.long 0x00 "CSU_CSL10,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x28))&0x1000100)==0x1000000) group.long 0x28++0x03 "USB3/USB" line.long 0x00 "CSU_CSL10,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x28))&0x1000100)==0x0000100) group.long 0x28++0x03 "USB3/USB" line.long 0x00 "CSU_CSL10,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x28++0x03 "USB3/USB" line.long 0x00 "CSU_CSL10,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x40))&0x1000100)==0x1000100) group.long 0x40++0x03 "SerDes/qDMA" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x40))&0x1000100)==0x1000000) group.long 0x40++0x03 "SerDes/qDMA" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x40))&0x1000100)==0x0000100) group.long 0x40++0x03 "SerDes/qDMA" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x40++0x03 "SerDes/qDMA" line.long 0x00 "CSU_CSL16,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x44))&0x1000100)==0x1000100) group.long 0x44++0x03 "LPUART_2/LPUART_1" line.long 0x00 "CSU_CSL17,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x44))&0x1000100)==0x1000000) group.long 0x44++0x03 "LPUART_2/LPUART_1" line.long 0x00 "CSU_CSL17,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x44))&0x1000100)==0x0000100) group.long 0x44++0x03 "LPUART_2/LPUART_1" line.long 0x00 "CSU_CSL17,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x44++0x03 "LPUART_2/LPUART_1" line.long 0x00 "CSU_CSL17,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x48))&0x1000100)==0x1000100) group.long 0x48++0x03 "LPUART_4/LPUART_3" line.long 0x00 "CSU_CSL18,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x48))&0x1000100)==0x1000000) group.long 0x48++0x03 "LPUART_4/LPUART_3" line.long 0x00 "CSU_CSL18,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x48))&0x1000100)==0x0000100) group.long 0x48++0x03 "LPUART_4/LPUART_3" line.long 0x00 "CSU_CSL18,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x48++0x03 "LPUART_4/LPUART_3" line.long 0x00 "CSU_CSL18,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x4C))&0x1000100)==0x1000100) group.long 0x4C++0x03 "LPUART_6/LPUART_5" line.long 0x00 "CSU_CSL19,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x4C))&0x1000100)==0x1000000) group.long 0x4C++0x03 "LPUART_6/LPUART_5" line.long 0x00 "CSU_CSL19,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x4C))&0x1000100)==0x0000100) group.long 0x4C++0x03 "LPUART_6/LPUART_5" line.long 0x00 "CSU_CSL19,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x4C++0x03 "LPUART_6/LPUART_5" line.long 0x00 "CSU_CSL19,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x50))&0x1000100)==0x1000100) group.long 0x50++0x03 "DSPI_1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x50))&0x1000100)==0x1000000) group.long 0x50++0x03 "DSPI_1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x50))&0x1000100)==0x0000100) group.long 0x50++0x03 "DSPI_1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x50++0x03 "DSPI_1" line.long 0x00 "CSU_CSL20,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x54))&0x1000100)==0x1000100) group.long 0x54++0x03 "QSPI/eSDHC" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x54))&0x1000100)==0x1000000) group.long 0x54++0x03 "QSPI/eSDHC" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x54))&0x1000100)==0x0000100) group.long 0x54++0x03 "QSPI/eSDHC" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x54++0x03 "QSPI/eSDHC" line.long 0x00 "CSU_CSL21,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x58))&0x1000100)==0x1000100) group.long 0x58++0x03 "IFC" line.long 0x00 "CSU_CSL22,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x58))&0x1000100)==0x1000000) group.long 0x58++0x03 "IFC" line.long 0x00 "CSU_CSL22,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x58))&0x1000100)==0x0000100) group.long 0x58++0x03 "IFC" line.long 0x00 "CSU_CSL22,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x58++0x03 "IFC" line.long 0x00 "CSU_CSL22,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x1000100) group.long 0x5C++0x03 "I2C_1" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x1000000) group.long 0x5C++0x03 "I2C_1" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x5C))&0x1000100)==0x0000100) group.long 0x5C++0x03 "I2C_1" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0x5C++0x03 "I2C_1" line.long 0x00 "CSU_CSL23,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0x60))&0x1000100)==0x1000100) group.long 0x60++0x03 "I2C_3/I2C_2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x60))&0x1000100)==0x1000000) group.long 0x60++0x03 "I2C_3/I2C_2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x60))&0x1000100)==0x0000100) group.long 0x60++0x03 "I2C_3/I2C_2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x60++0x03 "I2C_3/I2C_2" line.long 0x00 "CSU_CSL24,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x64))&0x1000100)==0x1000100) group.long 0x64++0x03 "DUART_2/DUART_1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x64))&0x1000100)==0x1000000) group.long 0x64++0x03 "DUART_2/DUART_1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x64))&0x1000100)==0x0000100) group.long 0x64++0x03 "DUART_2/DUART_1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x64++0x03 "DUART_2/DUART_1" line.long 0x00 "CSU_CSL25,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x68))&0x1000100)==0x1000100) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x68))&0x1000100)==0x1000000) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x68))&0x1000100)==0x0000100) group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x68++0x03 "WDOG_2/WDOG_1" line.long 0x00 "CSU_CSL26,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x1000100) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x1000000) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x6C))&0x1000100)==0x0000100) group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x6C++0x03 "eDMA/System Counter" line.long 0x00 "CSU_CSL27,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x70))&0x1000100)==0x1000100) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x70))&0x1000100)==0x1000000) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x70))&0x1000100)==0x0000100) group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x70++0x03 "DMAMUX_2/DMAMUX_1" line.long 0x00 "CSU_CSL28,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x74))&0x1000100)==0x1000100) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x74))&0x1000100)==0x1000000) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline elif (((per.l(ad:0x01510000+0x74))&0x1000100)==0x0000100) group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline else group.long 0x74++0x03 "DDR" line.long 0x00 "CSU_CSL29,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline endif if (((per.l(ad:0x01510000+0x78))&0x1000100)==0x1000100) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot ROM" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x78))&0x1000100)==0x1000000) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot ROM" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x78))&0x1000100)==0x0000100) group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot ROM" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x78++0x03 "DCFG/CCU/RCPM/Boot ROM" line.long 0x00 "CSU_CSL30,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x1000100) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x1000000) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x7C))&0x1000100)==0x0000100) group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x7C++0x03 "SFP/TMU" line.long 0x00 "CSU_CSL31,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x80))&0x1000100)==0x1000100) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x80))&0x1000100)==0x1000000) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x80))&0x1000100)==0x0000100) group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x80++0x03 "Security Monitor/SCFG" line.long 0x00 "CSU_CSL32,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x84))&0x1000100)==0x1000100) group.long 0x84++0x03 "FMAN/SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x84))&0x1000100)==0x1000000) group.long 0x84++0x03 "FMAN/SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x84))&0x1000100)==0x0000100) group.long 0x84++0x03 "FMAN/SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x84++0x03 "FMAN/SEC 5.5" line.long 0x00 "CSU_CSL33,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x88))&0x1000100)==0x1000100) group.long 0x88++0x03 "BM/QM" line.long 0x00 "CSU_CSL34,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x88))&0x1000100)==0x1000000) group.long 0x88++0x03 "BM/QM" line.long 0x00 "CSU_CSL34,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x88))&0x1000100)==0x0000100) group.long 0x88++0x03 "BM/QM" line.long 0x00 "CSU_CSL34,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x88++0x03 "BM/QM" line.long 0x00 "CSU_CSL34,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x1000100) group.long 0x8C++0x03 "GPIO_2/GPIO_1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x1000000) group.long 0x8C++0x03 "GPIO_2/GPIO_1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x8C))&0x1000100)==0x0000100) group.long 0x8C++0x03 "GPIO_2/GPIO_1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x8C++0x03 "GPIO_2/GPIO_1" line.long 0x00 "CSU_CSL35,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x90))&0x1000100)==0x1000100) group.long 0x90++0x03 "GPIO_4/GPIO_3" line.long 0x00 "CSU_CSL36,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x90))&0x1000100)==0x1000000) group.long 0x90++0x03 "GPIO_4/GPIO_3" line.long 0x00 "CSU_CSL36,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x90))&0x1000100)==0x0000100) group.long 0x90++0x03 "GPIO_4/GPIO_3" line.long 0x00 "CSU_CSL36,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x90++0x03 "GPIO_4/GPIO_3" line.long 0x00 "CSU_CSL36,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x94))&0x1000100)==0x1000100) group.long 0x94++0x03 "Platform Control/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x94))&0x1000100)==0x1000000) group.long 0x94++0x03 "Platform Control/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x94))&0x1000100)==0x0000100) group.long 0x94++0x03 "Platform Control/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x94++0x03 "Platform Control/CSU" line.long 0x00 "CSU_CSL37,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x98))&0x1000100)==0x1000100) group.long 0x98++0x03 "I2C_4" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x98))&0x1000100)==0x1000000) group.long 0x98++0x03 "I2C_4" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x98))&0x1000100)==0x0000100) group.long 0x98++0x03 "I2C_4" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x98++0x03 "I2C_4" line.long 0x00 "CSU_CSL38,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0x9C))&0x1000100)==0x1000100) group.long 0x9C++0x03 "WDOG_4/WDOG_3" line.long 0x00 "CSU_CSL39,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x9C))&0x1000100)==0x1000000) group.long 0x9C++0x03 "WDOG_4/WDOG_3" line.long 0x00 "CSU_CSL39,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0x9C))&0x1000100)==0x0000100) group.long 0x9C++0x03 "WDOG_4/WDOG_3" line.long 0x00 "CSU_CSL39,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0x9C++0x03 "WDOG_4/WDOG_3" line.long 0x00 "CSU_CSL39,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x1000100) group.long 0xA0++0x03 "WDOG_5" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x1000000) group.long 0xA0++0x03 "WDOG_5" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xA0))&0x1000100)==0x0000100) group.long 0xA0++0x03 "WDOG_5" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xA0++0x03 "WDOG_5" line.long 0x00 "CSU_CSL40,Config Security Level" bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x1000100) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x1000000) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xAC))&0x1000100)==0x0000100) group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xAC++0x03 "FTM_2/FTM_1" line.long 0x00 "CSU_CSL43,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xB0))&0x1000100)==0x1000100) group.long 0xB0++0x03 "FTM_4/FTM_3" line.long 0x00 "CSU_CSL44,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB0))&0x1000100)==0x1000000) group.long 0xB0++0x03 "FTM_4/FTM_3" line.long 0x00 "CSU_CSL44,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB0))&0x1000100)==0x0000100) group.long 0xB0++0x03 "FTM_4/FTM_3" line.long 0x00 "CSU_CSL44,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xB0++0x03 "FTM_4/FTM_3" line.long 0x00 "CSU_CSL44,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xB4))&0x1000100)==0x1000100) group.long 0xB4++0x03 "FTM_6/FTM_5" line.long 0x00 "CSU_CSL45,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB4))&0x1000100)==0x1000000) group.long 0xB4++0x03 "FTM_6/FTM_5" line.long 0x00 "CSU_CSL45,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB4))&0x1000100)==0x0000100) group.long 0xB4++0x03 "FTM_6/FTM_5" line.long 0x00 "CSU_CSL45,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xB4++0x03 "FTM_6/FTM_5" line.long 0x00 "CSU_CSL45,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif if (((per.l(ad:0x01510000+0xB8))&0x1000100)==0x1000100) group.long 0xB8++0x03 "FTM_8/FTM_7" line.long 0x00 "CSU_CSL46,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB8))&0x1000100)==0x1000000) group.long 0xB8++0x03 "FTM_8/FTM_7" line.long 0x00 "CSU_CSL46,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" elif (((per.l(ad:0x01510000+0xB8))&0x1000100)==0x0000100) group.long 0xB8++0x03 "FTM_8/FTM_7" line.long 0x00 "CSU_CSL46,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline rbitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" rbitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" else group.long 0xB8++0x03 "FTM_8/FTM_7" line.long 0x00 "CSU_CSL46,Config Security Level" bitfld.long 0x00 24. " L2 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 23. " SL15 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 22. " SL14 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 21. " SL13 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 20. " SL12 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SL11 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 18. " SL10 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 17. " SL9 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 16. " SL8 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1 ,Lock bit corresponding to the slave" "Not locked,Locked" newline bitfld.long 0x00 7. " SL7 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 6. " SL6 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 5. " SL5 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 4. " SL4 ,Secured user write access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " SL3 ,Non-secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 2. " SL2 ,Non-secured user write access enable" "Disabled,Enabled" bitfld.long 0x00 1. " SL1 ,Secured supervisor write access enable" "Disabled,Enabled" bitfld.long 0x00 0. " SL0 ,Secured user write access enable" "Disabled,Enabled" endif newline group.long 0x218++0x07 line.long 0x00 "CSU_SA0,Secure Access Register" bitfld.long 0x00 27. " L13_0 ,CP15DISABLE for core3 lock bit" "Not locked,Locked" bitfld.long 0x00 26. " SA13_0 ,CP15DISABLE for core3" "Secured,Non-secured" bitfld.long 0x00 25. " L12_0 ,CP15DISABLE for core2 lock bit" "Not locked,Locked" bitfld.long 0x00 24. " SA12_0 ,CP15DISABLE for core2" "Secured,Non-secured" newline bitfld.long 0x00 19. " L9_0 ,Non-secure attribute control for debug components lock bit" "Not locked,Locked" bitfld.long 0x00 18. " SA9_0 ,Non-secure attribute control for debug components" "Secured,Non-secured" bitfld.long 0x00 17. " L8_0 ,CFGDISABLE for GIC-400 lock bit" "Not locked,Locked" bitfld.long 0x00 16. " SA8_0 ,CFGDISABLE for GIC-400" "Secured,Non-secured" newline bitfld.long 0x00 15. " L7_0 ,CP15SDISABLE for core 1 lock bit" "Not locked,Locked" bitfld.long 0x00 14. " SA7_0 ,CP15SDISABLE for core 1" "Secured,Non-secured" bitfld.long 0x00 13. " L6_0 ,CP15SDISABLE for core 0 lock bit" "Not locked,Locked" bitfld.long 0x00 12. " SA6_0 ,CP15SDISABLE for core 0" "Secured,Non-secured" newline bitfld.long 0x00 11. " L5_0 ,Software-Override bit for DBGEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 10. " SA5_0 ,Software-Override bit for DBGEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" bitfld.long 0x00 9. " L4_0 ,Software-override bit for SPIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 8. " SA4_0 ,Software-override bit for SPIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" newline bitfld.long 0x00 7. " L3_0 ,Software-override bit for NIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 6. " SA3_0 ,Software-override bit for NIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" bitfld.long 0x00 5. " L2_0 ,Software-override bit for SPNIDEN signal connectivity to A7/SMMU/debug components lock bit" "Not locked,Locked" bitfld.long 0x00 4. " SA2_0 ,Software-override bit for SPNIDEN signal connectivity to A7/SMMU/debug components" "Secured,Non-secured" line.long 0x04 "CSU_SA1,Secure Access Register" bitfld.long 0x04 5. " L2_1 ,Secure boot lock for trust-zone address space controller registers lock bit" "Not locked,Locked" bitfld.long 0x04 4. " SA2_1 ,Secure boot lock for trust-zone address space controller registers" "Secured,Non-secured" bitfld.long 0x04 3. " L1_1 ,Trust zone address space controller bypass mux lock bit" "Not locked,Locked" bitfld.long 0x04 2. " SA1_1 ,Trust zone address space controller bypass mux" "Secured,Non-secured" width 0x0B tree.end endif sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") tree "MSCM (Miscellaneous System Control Module)" base ad:0x01520000 width 19. endian.be if (((per.l.be(ad:0x01520000+0xC10))&0x80000000)==0x00) group.long 0xC10++0x03 line.long 0x00 "MSCM_ACTZS_CSLIER,ACTZS CSL Interrupt Enable Register" rbitfld.long 0x00 31. " LOCK ,Configuration state defined by MSCM_CSLIER lock" "Not locked,Locked" newline sif !cpuis("LS1012*") bitfld.long 0x00 21. " CIE21 ,CSL21 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " CIE20 ,CSL20 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIE19 ,CSL19 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " CIE18 ,CSL18 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " CIE17 ,CSL17 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " CIE16 ,CSL16 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " CIE15 ,CSL15 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " CIE13 ,CSL13 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " CIE12 ,CSL12 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CIE10 ,CSL10 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CIE9 ,CSL9 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CIE8 ,CSL8 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CIE4 ,CSL4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CIE3 ,CSL3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CIE2 ,CSL2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CIE1 ,CSL1 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CIE0 ,CSL0 interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 18. " CIE18 ,CSL18 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CIE17 ,CSL17 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " CIE12 ,CSL12 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CIE10 ,CSL10 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " CIE8 ,CSL8 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " CIE4 ,CSL4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CIE2 ,CSL2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CIE0 ,CSL0 interrupt enable" "Disabled,Enabled" endif else rgroup.long 0xC10++0x03 line.long 0x00 "MSCM_ACTZS_CSLIER,ACTZS CSL Interrupt Enable Register" bitfld.long 0x00 31. " LOCK ,Configuration state defined by MSCM_CSLIER lock" "Not locked,Locked" newline sif !cpuis("LS1012*") bitfld.long 0x00 21. " CIE21 ,CSL21 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " CIE20 ,CSL20 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIE19 ,CSL19 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " CIE18 ,CSL18 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " CIE17 ,CSL17 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " CIE16 ,CSL16 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " CIE15 ,CSL15 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " CIE13 ,CSL13 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " CIE12 ,CSL12 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CIE10 ,CSL10 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CIE9 ,CSL9 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CIE8 ,CSL8 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CIE4 ,CSL4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CIE3 ,CSL3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CIE2 ,CSL2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CIE1 ,CSL1 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CIE0 ,CSL0 interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 18. " CIE18 ,CSL18 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CIE17 ,CSL17 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " CIE12 ,CSL12 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " CIE10 ,CSL10 interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " CIE8 ,CSL8 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " CIE4 ,CSL4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CIE2 ,CSL2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CIE0 ,CSL0 interrupt enable" "Disabled,Enabled" endif endif sif !cpuis("LS1012*") group.long 0xC14++0x07 line.long 0x00 "MSCM_ACTZS_CSLIR,ACTZS CSL Interrupt Register" eventfld.long 0x00 13. " INT13 ,CSL13 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " INT12 ,CSL12 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " INT10 ,CSL10 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " INT9 ,CSL9 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 8. " INT8 ,CSL8 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " INT4 ,CSL4 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 3. " INT3 ,CSL3 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " INT2 ,CSL2 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " INT1 ,CSL1 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " INT0 ,CSL0 interrupt flag" "No interrupt,Interrupt" line.long 0x04 "MSCM_ACTZS_CSOVR,ACTZS CSL Interrupt Overrun Register" eventfld.long 0x04 13. " OVR13 ,CSL13 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 12. " OVR12 ,CSL12 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 10. " OVR10 ,CSL10 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 9. " OVR9 ,CSL9 interrupt overrun" "No overrun,Overrun" newline eventfld.long 0x04 8. " OVR8 ,CSL8 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 4. " OVR4 ,CSL4 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 3. " OVR3 ,CSL3 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 2. " OVR2 ,CSL2 interrupt overrun" "No overrun,Overrun" newline eventfld.long 0x04 1. " OVR1 ,CSL1 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 0. " OVR0 ,CSL0 interrupt overrun" "No overrun,Overrun" else group.long 0xC14++0x07 line.long 0x00 "MSCM_ACTZS_CSLIR,ACTZS CSL Interrupt Register" eventfld.long 0x00 18. " INT18 ,CSL18 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " INT17 ,CSL17 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 12. " INT12 ,CSL12 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 10. " INT10 ,CSL10 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x00 8. " INT8 ,CSL8 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " INT4 ,CSL4 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " INT2 ,CSL2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " INT0 ,CSL0 interrupt flag" "No interrupt,Interrupt" line.long 0x04 "MSCM_ACTZS_CSOVR,ACTZS CSL Interrupt Overrun Register" eventfld.long 0x04 18. " OVR18 ,CSL18 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 17. " OVR17 ,CSL17 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 12. " OVR12 ,CSL12 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 10. " OVR10 ,CSL10 interrupt overrun" "No overrun,Overrun" newline eventfld.long 0x04 8. " OVR8 ,CSL8 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 4. " OVR4 ,CSL4 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 2. " OVR2 ,CSL2 interrupt overrun" "No overrun,Overrun" eventfld.long 0x04 0. " OVR0 ,CSL0 interrupt overrun" "No overrun,Overrun" endif newline width 19. sif !cpuis("LS1012*") rgroup.long 0xD00++0x03 line.long 0x00 "MSCM_CSFAR0,ACTZS CSL0 Fail Status Address (Low) Register" rgroup.long (0xD00+0x08)++0x07 line.long 0x00 "MSCM_CSFCR0,ACTZS CSL0 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL0 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL0 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL0 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR0,ACTZS CSL0 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL0 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD10++0x03 line.long 0x00 "MSCM_CSFAR1,ACTZS CSL1 Fail Status Address (Low) Register" rgroup.long (0xD10+0x08)++0x07 line.long 0x00 "MSCM_CSFCR1,ACTZS CSL1 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL1 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL1 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL1 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR1,ACTZS CSL1 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL1 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD20++0x03 line.long 0x00 "MSCM_CSFAR2,ACTZS CSL2 Fail Status Address (Low) Register" rgroup.long (0xD20+0x08)++0x07 line.long 0x00 "MSCM_CSFCR2,ACTZS CSL2 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL2 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL2 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL2 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR2,ACTZS CSL2 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL2 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD30++0x03 line.long 0x00 "MSCM_CSFAR3,ACTZS CSL3 Fail Status Address (Low) Register" rgroup.long (0xD30+0x08)++0x07 line.long 0x00 "MSCM_CSFCR3,ACTZS CSL3 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL3 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL3 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL3 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR3,ACTZS CSL3 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL3 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD40++0x03 line.long 0x00 "MSCM_CSFAR4,ACTZS CSL4 Fail Status Address (Low) Register" rgroup.long (0xD40+0x08)++0x07 line.long 0x00 "MSCM_CSFCR4,ACTZS CSL4 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL4 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL4 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL4 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR4,ACTZS CSL4 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL4 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD80++0x03 line.long 0x00 "MSCM_CSFAR8,ACTZS CSL8 Fail Status Address (Low) Register" rgroup.long (0xD80+0x08)++0x07 line.long 0x00 "MSCM_CSFCR8,ACTZS CSL8 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL8 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL8 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL8 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR8,ACTZS CSL8 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL8 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD90++0x03 line.long 0x00 "MSCM_CSFAR9,ACTZS CSL9 Fail Status Address (Low) Register" rgroup.long (0xD90+0x08)++0x07 line.long 0x00 "MSCM_CSFCR9,ACTZS CSL9 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL9 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL9 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL9 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR9,ACTZS CSL9 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL9 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xDA0++0x03 line.long 0x00 "MSCM_CSFAR10,ACTZS CSL10 Fail Status Address (Low) Register" rgroup.long (0xDA0+0x08)++0x07 line.long 0x00 "MSCM_CSFCR10,ACTZS CSL10 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL10 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL10 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL10 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR10,ACTZS CSL10 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL10 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xDC0++0x03 line.long 0x00 "MSCM_CSFAR12,ACTZS CSL12 Fail Status Address (Low) Register" rgroup.long (0xDC0+0x08)++0x07 line.long 0x00 "MSCM_CSFCR12,ACTZS CSL12 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL12 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL12 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL12 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR12,ACTZS CSL12 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL12 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xDF0++0x03 line.long 0x00 "MSCM_CSFAR15,ACTZS CSL15 Fail Status Address (Low) Register" rgroup.long (0xDF0+0x08)++0x07 line.long 0x00 "MSCM_CSFCR15,ACTZS CSL15 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL15 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL15 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL15 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR15,ACTZS CSL15 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL15 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE00++0x03 line.long 0x00 "MSCM_CSFAR16,ACTZS CSL16 Fail Status Address (Low) Register" rgroup.long (0xE00+0x08)++0x07 line.long 0x00 "MSCM_CSFCR16,ACTZS CSL16 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL16 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL16 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL16 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR16,ACTZS CSL16 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL16 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE10++0x03 line.long 0x00 "MSCM_CSFAR17,ACTZS CSL17 Fail Status Address (Low) Register" rgroup.long (0xE10+0x08)++0x07 line.long 0x00 "MSCM_CSFCR17,ACTZS CSL17 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL17 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL17 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL17 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR17,ACTZS CSL17 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL17 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE20++0x03 line.long 0x00 "MSCM_CSFAR18,ACTZS CSL18 Fail Status Address (Low) Register" rgroup.long (0xE20+0x08)++0x07 line.long 0x00 "MSCM_CSFCR18,ACTZS CSL18 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL18 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL18 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL18 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR18,ACTZS CSL18 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL18 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE30++0x03 line.long 0x00 "MSCM_CSFAR19,ACTZS CSL19 Fail Status Address (Low) Register" rgroup.long (0xE30+0x08)++0x07 line.long 0x00 "MSCM_CSFCR19,ACTZS CSL19 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL19 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL19 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL19 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR19,ACTZS CSL19 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL19 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE40++0x03 line.long 0x00 "MSCM_CSFAR20,ACTZS CSL20 Fail Status Address (Low) Register" rgroup.long (0xE40+0x08)++0x07 line.long 0x00 "MSCM_CSFCR20,ACTZS CSL20 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL20 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL20 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL20 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR20,ACTZS CSL20 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL20 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE50++0x03 line.long 0x00 "MSCM_CSFAR21,ACTZS CSL21 Fail Status Address (Low) Register" rgroup.long (0xE50+0x08)++0x07 line.long 0x00 "MSCM_CSFCR21,ACTZS CSL21 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL21 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL21 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL21 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR21,ACTZS CSL21 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL21 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.long 0xD00++0x03 line.long 0x00 "MSCM_CSFAR0,ACTZS CSL0 Fail Status Address (Low) Register" rgroup.long (0xD00+0x08)++0x07 line.long 0x00 "MSCM_CSFCR0,ACTZS CSL0 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL0 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL0 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL0 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR0,ACTZS CSL0 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL0 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD10++0x03 line.long 0x00 "MSCM_CSFAR1,ACTZS CSL1 Fail Status Address (Low) Register" rgroup.long (0xD10+0x08)++0x07 line.long 0x00 "MSCM_CSFCR1,ACTZS CSL1 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL1 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL1 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL1 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR1,ACTZS CSL1 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL1 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD20++0x03 line.long 0x00 "MSCM_CSFAR2,ACTZS CSL2 Fail Status Address (Low) Register" rgroup.long (0xD20+0x08)++0x07 line.long 0x00 "MSCM_CSFCR2,ACTZS CSL2 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL2 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL2 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL2 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR2,ACTZS CSL2 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL2 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD80++0x03 line.long 0x00 "MSCM_CSFAR8,ACTZS CSL8 Fail Status Address (Low) Register" rgroup.long (0xD80+0x08)++0x07 line.long 0x00 "MSCM_CSFCR8,ACTZS CSL8 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL8 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL8 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL8 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR8,ACTZS CSL8 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL8 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD90++0x03 line.long 0x00 "MSCM_CSFAR9,ACTZS CSL9 Fail Status Address (Low) Register" rgroup.long (0xD90+0x08)++0x07 line.long 0x00 "MSCM_CSFCR9,ACTZS CSL9 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL9 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL9 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL9 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR9,ACTZS CSL9 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL9 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xDC0++0x03 line.long 0x00 "MSCM_CSFAR12,ACTZS CSL12 Fail Status Address (Low) Register" rgroup.long (0xDC0+0x08)++0x07 line.long 0x00 "MSCM_CSFCR12,ACTZS CSL12 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL12 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL12 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL12 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR12,ACTZS CSL12 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL12 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE10++0x03 line.long 0x00 "MSCM_CSFAR17,ACTZS CSL17 Fail Status Address (Low) Register" rgroup.long (0xE10+0x08)++0x07 line.long 0x00 "MSCM_CSFCR17,ACTZS CSL17 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL17 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL17 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL17 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR17,ACTZS CSL17 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL17 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE20++0x03 line.long 0x00 "MSCM_CSFAR18,ACTZS CSL18 Fail Status Address (Low) Register" rgroup.long (0xE20+0x08)++0x07 line.long 0x00 "MSCM_CSFCR18,ACTZS CSL18 Fail Status Control Register" bitfld.long 0x00 24. " FWT ,CSL18 fail write" "Read,Write" bitfld.long 0x00 21. " FNS ,CSL18 fail nonsecure" "Secure,Non-secure" bitfld.long 0x00 20. " FPR ,CSL18 fail privileged" "User mode,Privileged" line.long 0x04 "MSCM_CSFIR18,ACTZS CSL18 Fail Status Master ID Register" bitfld.long 0x04 0.--4. " FMID ,CSL18 fail master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endian.le width 0x0B tree.end endif sif cpuis("LS10?6*")||cpuis("LS10?3*") tree "SCFG (Supplemental Configuration Unit)" base ad:0x01570000 width 23. endian.be group.long 0x70++0x23 line.long 0x00 "USB1PRM1CR,USB1 Parameter 1 Control Register" bitfld.long 0x00 29.--31. " COMPDISTUNE ,Drives the value of USB3 COMPDISTUNE signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " OTGTUNE0 ,Drives the value of USB3 OTGTUNE0 signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. " SQRXTUNE ,Drives the value of USB3 SQRXTUNE signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. " TXFSLSTUNE ,Drives the value of USB3 TXFSLSTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " TXHSXVTUNE ,Drives the value of USB3 TXHSXVTUNE signal" ",-15 mV,+15 mV,Default" bitfld.long 0x00 15.--16. " TXPREEMPAMPTUNE ,Drives the value of USB3 TXPREEMPAMPTUNE signal" "Disabled,1X,2X,3X" newline bitfld.long 0x00 14. " TXPREEMPPULSETUNE ,Drives the value of USB3 TXPREEMPPULSETUNE signal" "1X,2X" bitfld.long 0x00 12.--13. " TXRESTUNE ,Drives the value of USB3 TXRESTUNE signal" "1.5 Ohm,Default,2 Ohm,4 Ohm" bitfld.long 0x00 10.--11. " TXRISETUNE ,Drives the value of USB3 TXRISETUNE signal" "0,1,2,3" newline bitfld.long 0x00 6.--9. " TXVREFTUNE ,Drives the value of USB3 TXVREFTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--5. " PCSTXDEEMPH3P5DB ,Drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB1PRM2CR,USB1 Parameter 2 Control Register" hexmask.long.word 0x04 22.--31. 1. " PCSRXLOSMASKVAL ,Drives the value of USB3 pcs_rx_los_mask_val signal" bitfld.long 0x04 16.--21. " PCSTXDEEMPH6DB ,Drives the value of USB3 pcs_tx_deemph_6db signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 9.--15. 1. " PCSTXSWINGFULL ,Drives the value of USB3 pcs_tx_swing_full signal" newline bitfld.long 0x04 6.--8. " LOSBIAS ,Drives the value of USB3 los_bias signal" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " TXVBOOSTLVL ,Drives the value of USB3 tx_vboost_lvl signal" "0,1,2,3,4,5,6,7" line.long 0x08 "USB1PRM3CR,USB1 Parameter 3 Control Register" bitfld.long 0x08 27.--31. " USB1ACJT ,Drives the value of USB3 acjt_level signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 25.--26. " VATESTENB ,Drives the value of USB3 PHY VATESTENB signal" "0,1,2,3" bitfld.long 0x08 24. " LPBKENB0 ,Drives the value of USB3 PHY LOOPBACKENB0 signal" "0,1" newline bitfld.long 0x08 23. " LNTX2RXLPBK ,Drives the value of all 3 USB3 PHYs lane0_tx2rx_loopbk signal" "0,1" hexmask.long.byte 0x08 16.--22. 1. " MPLL_MULT ,Drives the value of USB3 mpll_multiplier signal" group.long 0x8C++0x23 line.long 0x00 "USB2PRM1CR,USB2 Parameter 1 Control Register" bitfld.long 0x00 29.--31. " COMPDISTUNE ,Drives the value of USB3 COMPDISTUNE signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " OTGTUNE0 ,Drives the value of USB3 OTGTUNE0 signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. " SQRXTUNE ,Drives the value of USB3 SQRXTUNE signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. " TXFSLSTUNE ,Drives the value of USB3 TXFSLSTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " TXHSXVTUNE ,Drives the value of USB3 TXHSXVTUNE signal" ",-15 mV,+15 mV,Default" bitfld.long 0x00 15.--16. " TXPREEMPAMPTUNE ,Drives the value of USB3 TXPREEMPAMPTUNE signal" "Disabled,1X,2X,3X" newline bitfld.long 0x00 14. " TXPREEMPPULSETUNE ,Drives the value of USB3 TXPREEMPPULSETUNE signal" "1X,2X" bitfld.long 0x00 12.--13. " TXRESTUNE ,Drives the value of USB3 TXRESTUNE signal" "1.5 Ohm,Default,2 Ohm,4 Ohm" bitfld.long 0x00 10.--11. " TXRISETUNE ,Drives the value of USB3 TXRISETUNE signal" "0,1,2,3" newline bitfld.long 0x00 6.--9. " TXVREFTUNE ,Drives the value of USB3 TXVREFTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--5. " PCSTXDEEMPH3P5DB ,Drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB2PRM2CR,USB2 Parameter 2 Control Register" hexmask.long.word 0x04 22.--31. 1. " PCSRXLOSMASKVAL ,Drives the value of USB3 pcs_rx_los_mask_val signal" bitfld.long 0x04 16.--21. " PCSTXDEEMPH6DB ,Drives the value of USB3 pcs_tx_deemph_6db signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 9.--15. 1. " PCSTXSWINGFULL ,Drives the value of USB3 pcs_tx_swing_full signal" newline bitfld.long 0x04 6.--8. " LOSBIAS ,Drives the value of USB3 los_bias signal" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " TXVBOOSTLVL ,Drives the value of USB3 tx_vboost_lvl signal" "0,1,2,3,4,5,6,7" line.long 0x08 "USB2PRM3CR,USB2 Parameter 3 Control Register" bitfld.long 0x08 27.--31. " USB2ACJT ,Drives the value of USB3 acjt_level signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 25.--26. " VATESTENB ,Drives the value of USB3 PHY VATESTENB signal" "0,1,2,3" bitfld.long 0x08 24. " LPBKENB0 ,Drives the value of USB3 PHY LOOPBACKENB0 signal" "0,1" newline hexmask.long.byte 0x08 16.--22. 1. " MPLL_MULT ,Drives the value of USB3 mpll_multiplier signal" group.long 0xA8++0x23 line.long 0x00 "USB3PRM1CR,USB3 Parameter 1 Control Register" bitfld.long 0x00 29.--31. " COMPDISTUNE ,Drives the value of USB3 COMPDISTUNE signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " OTGTUNE0 ,Drives the value of USB3 OTGTUNE0 signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. " SQRXTUNE ,Drives the value of USB3 SQRXTUNE signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. " TXFSLSTUNE ,Drives the value of USB3 TXFSLSTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " TXHSXVTUNE ,Drives the value of USB3 TXHSXVTUNE signal" ",-15 mV,+15 mV,Default" bitfld.long 0x00 15.--16. " TXPREEMPAMPTUNE ,Drives the value of USB3 TXPREEMPAMPTUNE signal" "Disabled,1X,2X,3X" newline bitfld.long 0x00 14. " TXPREEMPPULSETUNE ,Drives the value of USB3 TXPREEMPPULSETUNE signal" "1X,2X" bitfld.long 0x00 12.--13. " TXRESTUNE ,Drives the value of USB3 TXRESTUNE signal" "1.5 Ohm,Default,2 Ohm,4 Ohm" bitfld.long 0x00 10.--11. " TXRISETUNE ,Drives the value of USB3 TXRISETUNE signal" "0,1,2,3" newline bitfld.long 0x00 6.--9. " TXVREFTUNE ,Drives the value of USB3 TXVREFTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--5. " PCSTXDEEMPH3P5DB ,Drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB3PRM2CR,USB3 Parameter 2 Control Register" hexmask.long.word 0x04 22.--31. 1. " PCSRXLOSMASKVAL ,Drives the value of USB3 pcs_rx_los_mask_val signal" bitfld.long 0x04 16.--21. " PCSTXDEEMPH6DB ,Drives the value of USB3 pcs_tx_deemph_6db signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 9.--15. 1. " PCSTXSWINGFULL ,Drives the value of USB3 pcs_tx_swing_full signal" newline bitfld.long 0x04 6.--8. " LOSBIAS ,Drives the value of USB3 los_bias signal" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " TXVBOOSTLVL ,Drives the value of USB3 tx_vboost_lvl signal" "0,1,2,3,4,5,6,7" line.long 0x08 "USB3PRM3CR,USB3 Parameter 3 Control Register" bitfld.long 0x08 27.--31. " USB3ACJT ,Drives the value of USB3 acjt_level signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 25.--26. " VATESTENB ,Drives the value of USB3 PHY VATESTENB signal" "0,1,2,3" bitfld.long 0x08 24. " LPBKENB0 ,Drives the value of USB3 PHY LOOPBACKENB0 signal" "0,1" newline hexmask.long.byte 0x08 16.--22. 1. " MPLL_MULT ,Drives the value of USB3 mpll_multiplier signal" sif !cpuis("LS1012A") group.long 0x100++0x07 line.long 0x00 "USB2_ICID,USB2 ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of USB2 controller" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "USB3_ICID,USB3 ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of USB3 controller" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" sif cpuis("LS10?3A") group.long 0x114++0x03 line.long 0x00 "DMA_ICID,QDMA ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of qDMA" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x118++0x07 line.long 0x00 "SATA_ICID,QDMA ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of SATA" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "USB1_ICID,USB1 ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of USB1 controller" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" sif cpuis("LS10?3*") group.long 0x120++0x03 line.long 0x00 "QE_ICID,QE ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of QE" bitfld.long 0x00 20. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x124++0x0B line.long 0x00 "SDHC_ICID,eSDHC ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of eSDHC" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "EDMA_ICID,eDMA ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of eDMA" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x08 "ETR_ICID,ETR ICID Register" hexmask.long.byte 0x08 24.--31. 1. " ICID ,ICID of ETR" bitfld.long 0x08 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif sif cpuis("LS1012A") group.long 0x130++0x03 line.long 0x00 "CORE0_SFT_RST,Core 0 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 0 when 1 is written on this bit" "No reset,Reset" else group.long 0x130++0x03 line.long 0x00 "CORE0_SFT_RST,Core 0 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 0 when 1 is written on this bit" "No reset,Reset" group.long 0x134++0x03 line.long 0x00 "CORE1_SFT_RST,Core 1 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 1 when 1 is written on this bit" "No reset,Reset" group.long 0x138++0x03 line.long 0x00 "CORE2_SFT_RST,Core 2 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 2 when 1 is written on this bit" "No reset,Reset" group.long 0x13C++0x03 line.long 0x00 "CORE3_SFT_RST,Core 3 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 3 when 1 is written on this bit" "No reset,Reset" endif sif cpuis("LS10?3*") group.long 0x144++0x03 line.long 0x00 "PEXPMECR,PEX PME Control Register" bitfld.long 0x00 31. " PEX1PME ,Generates PM turnoff message for power management for PEX1" "Default,RC mode only" bitfld.long 0x00 27. " PEX2PME ,Generates PM turnoff message for power management for PEX2" "Default,RC mode only" bitfld.long 0x00 23. " PEX3PME ,Generates PM turnoff message for power management for PEX3" "Default,RC mode only" endif group.long 0x154++0x03 line.long 0x00 "FTM_CHAIN_CONFIG,FTM chain configuration" sif cpuis("LS10?6A") bitfld.long 0x00 31. " CORE0 ,CORE0 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 30. " CORE1 ,CORE1 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 29. " CORE2 ,CORE2 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 28. " CORE3 ,CORE3 flextimer reset enable" "Disabled,Enabled" newline elif cpuis("LS1012A") bitfld.long 0x00 17. " FTM_CHN2 ,FTM2 chaining" "Not chained,Chained" bitfld.long 0x00 16. " FTM_CHN1 ,FTM1 chaining" "Not chained,Chained" newline endif sif !cpuis("LS1012A") bitfld.long 0x00 15. " FTM_CHN1 ,FTM1 and FTM5 chain" "Not chained,Chained" bitfld.long 0x00 14. " FTM_CHN2 ,FTM2 and FTM6 chain" "Not chained,Chained" bitfld.long 0x00 13. " FTM_CHN3 ,FTM3 and FTM7 chain" "Not chained,Chained" bitfld.long 0x00 12. " FTM_CHN4 ,FTM4 and FTM8 chain" "Not chained,Chained" endif group.long 0x158++0x07 line.long 0x00 "ALTCBAR,ALTCBAR Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " ALTCBAR ,Alt configuration base address register for PBL" line.long 0x04 "QSPI_CFG,QSPI CONFIG Register" bitfld.long 0x04 28.--31. " CLK_SEL ,Control the division of CGA1/CGA2 PLL clock to generate QuadSPI interface clocks" "/256,/64,/32,/24,/20,/16,/12,/8,?..." sif cpuis("LS1012A") group.long 0x164++0x0F line.long 0x00 "WR_QOS1,Write QOS1 Register" bitfld.long 0x00 24.--27. " PFE1_QOS ,QOS[3:0] for PFE DDR AXI master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PFE2_QOS ,QOS[3:0] for PFE HDBUD master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PFE1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WR_QOS2,Write QOS2 Register" bitfld.long 0x04 28.--31. " USB3_QOS ,QOS [3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " A53_QOS ,QOS [3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " ESDHC2_QOS ,QOS [3:0] for eSDHC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " ESDHC1_QOS ,QOS [3:0] for eSDHC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " USB2_QOS ,QOS [3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " SATA_QOS ,QOS [3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RD_QOS1,Read OS1 Register" bitfld.long 0x08 24.--27. " PFE1_QOS ,QOS[3:0] for PFE DDR AXI master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " PFE2_QOS ,QOS[3:0] for PFE HDBUD master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " PFE1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RD_QOS2,Read QOS2 Register" bitfld.long 0x0C 28.--31. " USB3_QOS ,QOS [3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " A53_QOS ,QOS [3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--15. " ESDHC2_QOS ,QOS [3:0] for eSDHC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " eSDHC1_QOS ,QOS [3:0] for eSDHC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " USB2_QOS ,QOS [3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " SATA_QOS ,QOS [3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x16C++0x07 line.long 0x00 "QOS1,QOS1 Register" bitfld.long 0x00 28.--31. " EDMA_QOS ,QOS[3:0] for eDMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " USB2_QOS ,QOS[3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " USB3_QOS ,QOS[3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " QDMA_QOS ,QOS[3:0] for qDMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " PEX2_QOS ,QOS[3:0] for PEX2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PEX1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " FM_QOS ,QOS[3:0] for FM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "QOS2,QOS2 Register" bitfld.long 0x04 28.--31. " USB1_QOS ,QOS[3:0] for USB1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " PEX3_QOS ,QOS[3:0] for PEX3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " QMAN_QOS ,QOS[3:0] for QMan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("LS10?3A") bitfld.long 0x04 16.--19. " A53_QOS ,QOS[3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("LS10?6A") bitfld.long 0x04 16.--19. " A72_QOS ,QOS[3:0] for A72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif bitfld.long 0x04 8.--11. " ESDHC_QOS ,QOS[3:0] for eSDHC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?3A") bitfld.long 0x04 4.--7. " QE_QOS ,QOS[3:0] for QE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x04 0.--3. " SATA_QOS ,QOS[3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LS10?3A") group.long 0x188++0x03 line.long 0x00 "GIC400_ADDR_ALIGN_64K,GIC-400 Address 64K Page Alignment Register" bitfld.long 0x00 31. " GIC_ADDR ,Controls the GIC-400 addressing" "64K,Non-64K" endif sif !cpuis("LS1012A") group.long 0x18C++0x03 line.long 0x00 "DEBUG_ICID,Debug ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID input to the SMMU" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x1A4++0x03 line.long 0x00 "SNPCNFGCR,Snoop Configuration Register" sif !cpuis("LS1012A") bitfld.long 0x00 31. " SECRDSNP ,Drives SEC read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 30. " SECWRSNP ,Controls snoop attribute of SEC writes" "Not snoopable,Snoopable" newline endif bitfld.long 0x00 23. " SATARDSNP ,Drives SATA read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 22. " SATAWRSNP ,Controls snoop attribute of SATA writes" "Not snoopable,Snoopable" newline sif cpuis("LS1012A") bitfld.long 0x00 21. " USBRDSNP ,Drives USB3 read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 20. " USBWRSNP ,Controls snoop attribute of USB3 writes" "Not snoopable,Snoopable" newline else bitfld.long 0x00 21. " USB1RDSNP ,Drives USB1 read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 20. " USB1WRSNP ,Controls snoop attribute of USB1 writes" "Not snoopable,Snoopable" newline endif bitfld.long 0x00 19. " DBGRDSNP ,Debug reads are snoopable" "Not snoopable,Snoopable" bitfld.long 0x00 18. " DBGWRSNP ,Drives DEBUG write snoop signal" "Not snoopable,Snoopable" sif !cpuis("LS10?6A") newline bitfld.long 0x00 17. " EDMASNP ,Drives eDMA snoop signal" "Not snoopable,Snoopable" endif sif !cpuis("LS1012A") newline bitfld.long 0x00 16. " USB2WRSNP ,Drives USB2 write snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 15. " USB2RDSNP ,Drives USB2 read snoop signal" "Not snoopable,Snoopable" newline bitfld.long 0x00 14. " USB3WRSNP ,Drives USB3 write snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 13. " USB3RDSNP ,Drives USB3 read snoop signal" "Not snoopable,Snoopable" endif sif !cpuis("LS1012A") group.long 0x1AC++0x03 line.long 0x00 "INTPCR,Interrupt Polarity Register" bitfld.long 0x00 31. " IRQ0INTP ,Controls the polarity of IRQ0" "Active high,Active low" bitfld.long 0x00 30. " IRQ1INTP ,Controls the polarity of IRQ1" "Active high,Active low" bitfld.long 0x00 29. " IRQ2INTP ,Controls the polarity of IRQ2" "Active high,Active low" newline bitfld.long 0x00 28. " IRQ3INTP ,Controls the polarity of IRQ3" "Active high,Active low" bitfld.long 0x00 27. " IRQ4INTP ,Controls the polarity of IRQ4" "Active high,Active low" bitfld.long 0x00 26. " IRQ5INTP ,Controls the polarity of IRQ5" "Active high,Active low" newline bitfld.long 0x00 25. " IRQ6INTP ,Controls the polarity of IRQ6" "Active high,Active low" bitfld.long 0x00 24. " IRQ7INTP ,Controls the polarity of IRQ7" "Active high,Active low" bitfld.long 0x00 23. " IRQ8INTP ,Controls the polarity of IRQ8" "Active high,Active low" newline bitfld.long 0x00 22. " IRQ9INTP ,Controls the polarity of IRQ9" "Active high,Active low" bitfld.long 0x00 21. " IRQ10INTP ,Controls the polarity of IRQ10" "Active high,Active low" bitfld.long 0x00 20. " IRQ11INTP ,Controls the polarity of IRQ11" "Active high,Active low" endif group.long 0x204++0x03 line.long 0x00 "CORESRENCR,CORE Soft Reset Enable Register" bitfld.long 0x00 31. " CORESREN ,Controls the enable of core soft reset functionality" "Disabled,Enabled" sif cpuis("LS1012A") group.long 0x220++0x08 line.long 0x00 "RVBAR0_0,Core 0 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR0_1,Core 0 Reset Vector Base Address Register 1" else group.long 0x220++0x08 line.long 0x00 "RVBAR0_0,Core 0 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR0_1,Core 0 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR0_1 ,Core 0 reset vector base address for bits [39:34]" group.long 0x228++0x08 line.long 0x00 "RVBAR1_0,Core 1 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR1_1,Core 1 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR1_1 ,Core 1 reset vector base address for bits [39:34]" group.long 0x230++0x08 line.long 0x00 "RVBAR2_0,Core 2 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR2_1,Core 2 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR2_1 ,Core 2 reset vector base address for bits [39:34]" group.long 0x238++0x08 line.long 0x00 "RVBAR3_0,Core 3 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR3_1,Core 3 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR3_1 ,Core 3 reset vector base address for bits [39:34]" endif group.long 0x240++0x03 line.long 0x00 "LPMCSR,Core Low Power Mode Control Status Register" sif !cpuis("LS1012A") bitfld.long 0x00 28. " SMPEN3 ,Status bit for SMPEN signal of core 3" "0,1" bitfld.long 0x00 27. " CPUQDENY3 ,Status bit for CPUQDENY signal for core 3" "0,1" bitfld.long 0x00 26. " CPUQACCEPTN3 ,Status bit for CPUQACCEPTn signal for core 3" "0,1" newline bitfld.long 0x00 25. " CPUQACTIVE3 ,Status bit for CPUQACTIVE signal for core 3" "0,1" bitfld.long 0x00 24. " CPUQREQN3 ,Control bit for CPUQREQn for core 3" "0,1" newline bitfld.long 0x00 20. " SMPEN2 ,Status bit for SMPEN signal of core 2" "0,1" bitfld.long 0x00 19. " CPUQDENY2 ,Status bit for CPUQDENY signal for core 2" "0,1" bitfld.long 0x00 18. " CPUQACCEPTN2 ,Status bit for CPUQACCEPTn signal for core 2" "0,1" newline bitfld.long 0x00 17. " CPUQACTIVE2 ,Status bit for CPUQACTIVE signal for core 2" "0,1" bitfld.long 0x00 16. " CPUQREQN2 ,Control bit for CPUQREQn for core 2" "0,1" newline bitfld.long 0x00 12. " SMPEN1 ,Status bit for SMPEN signal of core 1" "0,1" bitfld.long 0x00 11. " CPUQDENY1 ,Status bit for CPUQDENY signal for core 1" "0,1" bitfld.long 0x00 10. " CPUQACCEPTN1 ,Status bit for CPUQACCEPTn signal for core 1" "0,1" newline bitfld.long 0x00 9. " CPUQACTIVE1 ,Status bit for CPUQACTIVE signal for core 1" "0,1" bitfld.long 0x00 8. " CPUQREQN1 ,Control bit for CPUQREQn for core 1" "0,1" newline endif bitfld.long 0x00 4. " SMPEN0 ,Status bit for SMPEN signal of core 0" "0,1" bitfld.long 0x00 3. " CPUQDENY0 ,Status bit for CPUQDENY signal for core 0" "0,1" bitfld.long 0x00 2. " CPUQACCEPTN0 ,Status bit for CPUQACCEPTn signal for core 0" "0,1" newline bitfld.long 0x00 1. " CPUQACTIVE0 ,Status bit for CPUQACTIVE signal for core 0" "0,1" bitfld.long 0x00 0. " CPUQREQN0 ,Control bit for CPUQREQn for core 0" "0,1" sif !cpuis("LS1012A") group.long 0x404++0x03 line.long 0x00 "ECGTXCMCR,ECGTX Clock Mux Control Register" bitfld.long 0x00 27. " CLK_SEL ,Selects 125 MHz reference clock for RGMII" "EC1_GTX_CLK125,EC2_GTX_CLK125" endif group.long 0x408++0x03 line.long 0x00 "SDHCIOVSELCR,SDHC IO VSEL Control Register" bitfld.long 0x00 31. " TGLEN ,SDHC IO voltage switching enable" "Disabled,Enabled" bitfld.long 0x00 29.--30. " VSELVAL ,Configures voltage for SDHC" "1.8V,,3.3V,Auto" sif cpuis("LS1012A") bitfld.long 0x00 0. " SDHC_VS ,SCFG bit reflecting shadow bit controlled by software for eSDHC_PROCTL[VOLT_SEL]" "3.3V,1.8V" else bitfld.long 0x00 0. " SDHC_VS ,SCFG bit reflecting shadow bit controlled by switch for SDHC:VOLT_SEL" "3.3V,1.8V" endif sif !cpuis("LS1012A") group.long 0x40C++0x07 line.long 0x00 "RCWPMUXCR0,Extended RCW PinMux Control Register" sif cpuis("LS10?6A") bitfld.long 0x00 12.--14. " IIC3_SCL ,Configures functionality of the IIC3_SCL" "IIC3_SCL,GPIO_4[10],EVT_B[5],USB2_DRVVBUS,,FTM8_CH0,CLK11,?..." newline bitfld.long 0x00 8.--10. " IIC3_SDA ,Configures functionality of the IIC3_SDA" "IIC3_SDA,GPIO_4[11],EVT_B[6],USB2_PWRFAULT,,FTM8_CH1,CLK12_CLK8,IIC3_SDA" newline bitfld.long 0x00 4.--6. " IIC4_SCL ,Configures functionality of the IIC4_SCL" "IIC4_SCL,GPIO_4[12],EVT_B[7],USB3_DRVVBUS,,FTM3_FAULT,UC1_CDB_RXER,IIC4_SCL" newline bitfld.long 0x00 0.--2. " IIC4_SDA ,Configures functionality of the IIC4_SDA" "IIC4_SDA,GPIO_4[13],EVT_B[8],USB3_PWRFAULT,,FTM3_EXTCLK,,IIC4_SDA" elif cpuis("LS10?3A") bitfld.long 0x00 12.--14. " IIC3_SCL ,Configures functionality of the IIC3_SCL" "IIC3_SCL,GPIO_4[10],EVT_B[5],USB2_DRVVBUS,BRGO4,FTM8_CH0,CLK11,?..." newline bitfld.long 0x00 8.--10. " IIC3_SDA ,Configures functionality of the IIC3_SDA" "IIC3_SDA,GPIO_4[11],EVT_B[6],USB2_PWRFAULT,BRGO1,FTM8_CH1,CLK12_CLK8,?..." newline bitfld.long 0x00 4.--6. " IIC4_SCL ,Configures functionality of the IIC4_SCL" "IIC4_SCL,GPIO_4[12],EVT_B[7],USB3_DRVVBUS,TDMA_RQ,FTM3_FAULT,UC1_CDB_RXER,?..." newline bitfld.long 0x00 0.--2. " IIC4_SDA ,Configures functionality of the IIC4_SDA" "IIC4_SDA,GPIO_4[13],EVT_B[8],USB3_PWRFAULT,TDMB_RQ,FTM3_EXTCLK,UC3_CDB_RXER,IIC4_SDA" endif line.long 0x04 "USBDRVVBUS_SELCR,USB DRVVBUS Control Register" bitfld.long 0x04 0.--1. " USB_SEL ,Selection of USB Controller to drive USB_DRVVBUS I/O" "USB Controller 1,USB Controller 2,,USB Controller 3" endif newline group.long 0x414++0x07 line.long 0x00 "USBPWRFAULT_SELCR,USB PWRFAULT Control Register" sif cpuis("LS1012A") bitfld.long 0x00 0. " USB1_SEL ,USB1 controller connectivity" "Only 3.0,Shared" else bitfld.long 0x00 4.--5. " USB3_SEL ,USB controller 3 connectivity" "Inactive,Shared USB_PWRFAULT I/O,Dedicated USB3_PWRFAULT I/O,?..." bitfld.long 0x00 2.--3. " USB2_SEL ,USB controller 2 connectivity" "Inactive,Shared USB_PWRFAULT I/O,Dedicated USB3_PWRFAULT I/O,?..." bitfld.long 0x00 0.--1. " USB1_SEL ,USB controller 1 connectivity" "Inactive,Shared USB_PWRFAULT I/O,?..." endif sif cpuis("LS1012A") line.long 0x04 "USB_PHY_CTRL,USB PHY Control Register" bitfld.long 0x04 31. " RST ,USBPHY reset" "No reset,Reset" bitfld.long 0x04 9. " PDN_SSP ,Forces the super speed function to lowest power state" "Not forced,Forced" bitfld.long 0x04 8. " PDN_HSP ,Forces the high speed function to lowest power state" "Not forced,Forced" newline bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else line.long 0x04 "USB_REFCLK_SELCR1,USB PHY 1 Reference Clock Select Register" bitfld.long 0x04 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. " CKSEL ,Selects the reference clock for USB PHY 1 PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," endif sif !cpuis("LS1012A") group.long 0x41C++0x0B line.long 0x00 "USB_REFCLK_SELCR2,USB PHY2 Reference Clock Select Register" bitfld.long 0x00 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x00 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CKSEL ,Selects the reference clock for USB PHY 2PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," line.long 0x04 "USB_REFCLK_SELCR3,USB PHY#3 Reference Clock Select Register" bitfld.long 0x04 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. " CKSEL ,Selects the reference clock for USB PHY 2PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," line.long 0x08 "RETREQCR,Retention Request Control Register" bitfld.long 0x08 31. " RETREQ0 ,Retention request enable 0" "Disabled,Enabled" bitfld.long 0x08 30. " RETREQ1 ,Retention request enable 1" "Disabled,Enabled" newline bitfld.long 0x08 29. " RETREQ2 ,Retention request enable 2" "Disabled,Enabled" bitfld.long 0x08 28. " RETREQ3 ,Retention request enable 3" "Disabled,Enabled" endif sif cpuis("LS10?6A") group.long 0x42C++0x03 line.long 0x00 "COREPMCR,CORE PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable for core A72" "Disabled,Enabled" elif cpuis("LS10?3A") group.long 0x42C++0x03 line.long 0x00 "COREPMCR,CORE PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable for core A53" "Disabled,Enabled" elif cpuis("LS1012A") group.long 0x42C++0x03 line.long 0x00 "CLUSTERPMCR,CLUSTER PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable" "Disabled,Enabled" endif sif cpuis("LS1012A") group.long 0x430++0x03 line.long 0x00 "PMUXCR0,Pinmux Control Register" bitfld.long 0x00 31. " QSPI_MUX_OVRD ,Software override for QSPI multiplexing enable" "Disabled,Enabled" bitfld.long 0x00 30. " QSPI_DATA0_GPIO_OVRD ,Software configures alternate functionality of the QuadSPI pins for 1-bit interface" "QSPI_A_DATO/SCK/CS0,GPIO1_4/11/5" newline bitfld.long 0x00 28.--29. " QSPI_DATA1_GPIO_OVRD ,Software configures alternate functionality of the QuadSPI pins for 2-bit interface" "QSPI_A_DAT1,GPIO1_12,?..." bitfld.long 0x00 26.--27. " QSPI_IIC2_OVRD ,Software configures alternate functionality of the QuadSPI pins for additional 2-bit interface" "GPIO1_13 / 14,,QSPI_DATA2 / DATA3,?..." if (((per.l.be(ad:0x01570000+0x434))&0x08)==0x08) group.long 0x434++0x03 line.long 0x00 "RGMIIPCR,RGMII Port Control Register" bitfld.long 0x00 3. " EN_AUTO ,Link speed selection source" "SETSP/SETFD bits,Auto" bitfld.long 0x00 1.--2. " SETSP ,Set RGMII link speed" "100Mbps,10Mbps,1Gbps,?..." newline bitfld.long 0x00 0. " SETFD ,Force full duplex RGMII mode enable" ",Enabled" else group.long 0x434++0x03 line.long 0x00 "RGMIIPCR,RGMII Port Control Register" bitfld.long 0x00 3. " EN_AUTO ,Link speed selection source" "SETSP/SETFD bits,Auto" newline bitfld.long 0x00 0. " SETFD ,Force full duplex RGMII mode enable" ",Enabled" endif newline rgroup.long 0x43C++0x07 line.long 0x00 "RGMIIPSR,RGMII Port Status Register" bitfld.long 0x00 31. " RGLINK ,RGMII link status" "Not linked,Linked" bitfld.long 0x00 29.--30. " RGSP ,RGMII link speed status" "100Mbps,10Mbps,1Gbps,?..." bitfld.long 0x00 28. " RGFD ,RGMII full duplex link mode status" "Not established,Established" line.long 0x04 "PFEPCSSR1,PFE PCS Status Register 1" bitfld.long 0x04 31. " PCS ,Link synchronization event" "0,1" bitfld.long 0x04 30. " AN ,Auto negotiation status" "0,1" bitfld.long 0x04 29. " LT ,New page received by auto negotiation function" "0,1" group.long 0x444++0x03 line.long 0x00 "PFEINTENCR1,PFE Interrupt Enable Control Register 1" bitfld.long 0x00 31. " PCS_EN ,Interrupt enable bit for link synchronization event on PFE MAC1" "Disabled,Enabled" bitfld.long 0x00 30. " AN_EN ,Interrupt enable bit for auto negotiation on PFE MAC1" "Disabled,Enabled" bitfld.long 0x00 29. " LT_EN ,Interrupt enable bit for new page received on auto negotiation on PFE MAC1" "Disabled,Enabled" rgroup.long 0x448++0x03 line.long 0x00 "PFEPCSSR2,PFE PCS Status Register 2" bitfld.long 0x00 31. " PCS ,Link synchronization event" "0,1" bitfld.long 0x00 30. " AN ,Auto negotiation status" "0,1" bitfld.long 0x00 29. " LT ,New page received by auto negotiation function" "0,1" group.long 0x44C++0x0B line.long 0x00 "PFEINTENCR2,PFE Interrupt Enable Control Register 2" bitfld.long 0x00 31. " PCS_EN ,Interrupt enable bit for link synchronization event on PFE MAC2" "Disabled,Enabled" bitfld.long 0x00 30. " AN_EN ,Interrupt enable bit for auto negotiation on PFE MAC2" "Disabled,Enabled" bitfld.long 0x00 29. " LT_EN ,Interrupt enable bit for new page received on auto negotiation on PFE MAC2" "Disabled,Enabled" line.long 0x04 "PFEERRCR,PFE Error Control Register" eventfld.long 0x04 31. " WRERSPP1 ,Write error response for PFE DDR master interface" "Not captured,Captured" eventfld.long 0x04 30. " RDERSPP1 ,Read error response for PFE DDR master interface" "Not captured,Captured" newline eventfld.long 0x04 29. " WRERSPP2 ,Write error response for PFE HDBUS master interface" "Not captured,Captured" eventfld.long 0x04 28. " RDEDSPP2 ,Read error response for PFE HDBUS master interface" "Not captured,Captured" line.long 0x08 "PFEERRINTENCR,PFE Error Interrupt Enable Control Register" eventfld.long 0x08 31. " WRERSPENP1 ,Interrupt enable bit for write error response captured for PFE DDR master interface" "Disabled,Enabled" eventfld.long 0x08 30. " RDERSPENP1 ,Interrupt enable bit for read error response captured for PFE DDR master interface" "Disabled,Enabled" newline eventfld.long 0x08 29. " WRERSPENP2 ,Interrupt enable bit for write error response captured for PFE HDBUS master interface" "Disabled,Enabled" eventfld.long 0x08 28. " RDERSPENP2 ,Interrupt enable bit for read error response captured for PFE HDBUS master interface" "Disabled,Enabled" group.long 0x458++0x03 line.long 0x00 "PFEASBCR,PFEA Sideband Control Register" bitfld.long 0x00 31. " ARCACHE0 ,Control bit for ARCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 30. " AWCACHE0 ,Control bit for AWCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 29. " ARCACHE1 ,Control bit for ARCACHE[1] attribute" "Non modifable,Modifable" newline bitfld.long 0x00 28. " AWCACHE1 ,Control bit for AWCACHE[1] attribute" "Non modifable,Modifable" bitfld.long 0x00 27. " ARSNP ,Control bit for snoopable attribute of read channel" "Non snoopable,Snoopable" bitfld.long 0x00 26. " AWSNP ,Control bit for snoopable attribute of write channel" "Non snoopable,Snoopable" group.long 0x45C++0x03 line.long 0x00 "PFEBSBCR,PFEB Sideband Control Register" bitfld.long 0x00 31. " ARCACHE0 ,Control bit for ARCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 30. " AWCACHE0 ,Control bit for AWCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 29. " ARCACHE1 ,Control bit for ARCACHE[1] attribute" "Non modifable,Modifable" newline bitfld.long 0x00 28. " AWCACHE1 ,Control bit for AWCACHE[1] attribute" "Non modifable,Modifable" bitfld.long 0x00 27. " ARSNP ,Control bit for snoopable attribute of read channel" "Non snoopable,Snoopable" bitfld.long 0x00 26. " AWSNP ,Control bit for snoopable attribute of write channel" "Non snoopable,Snoopable" group.long 0x484++0x03 line.long 0x00 "MDIOSELCR,MDIO Select Control Register" bitfld.long 0x00 31. " MDIOSEL ,EMI1_MDIO source select" "SerDes,Ethernet PHY" group.long 0x500++0x03 line.long 0x00 "SPARECR1,Spare Control Register 1" group.long 0x504++0x03 line.long 0x00 "SPARECR2,Spare Control Register 2" group.long 0x508++0x03 line.long 0x00 "SPARECR3,Spare Control Register 3" group.long 0x50C++0x03 line.long 0x00 "SPARECR4,Spare Control Register 4" group.long 0x510++0x03 line.long 0x00 "SPARECR5,Spare Control Register 5" group.long 0x514++0x03 line.long 0x00 "SPARECR6,Spare Control Register 6" group.long 0x518++0x03 line.long 0x00 "SPARECR7,Spare Control Register 7" group.long 0x51C++0x03 line.long 0x00 "SPARECR8,Spare Control Register 8" group.long 0x520++0x03 line.long 0x00 "I2CDBGCR,I2C Debug Mode Control Register" bitfld.long 0x00 29. " I2C1 ,I2C1 glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 28. " I2C2 ,I2C2 glitch filter enable" "Disabled,Enabled" endif group.long 0x600++0x03 line.long 0x00 "SCRATCHRW1,Scratch Read Write Register 1" group.long 0x604++0x03 line.long 0x00 "SCRATCHRW2,Scratch Read Write Register 2" group.long 0x608++0x03 line.long 0x00 "SCRATCHRW3,Scratch Read Write Register 3" group.long 0x60C++0x03 line.long 0x00 "SCRATCHRW4,Scratch Read Write Register 4" sif cpuis("LS10?6A") group.long 0x610++0x03 line.long 0x00 "SCRATCHRW5,Scratch Read Write Register 5" group.long 0x614++0x03 line.long 0x00 "SCRATCHRW6,Scratch Read Write Register 6" group.long 0x618++0x03 line.long 0x00 "SCRATCHRW7,Scratch Read Write Register 7" group.long 0x61C++0x03 line.long 0x00 "SCRATCHRW8,Scratch Read Write Register 8" endif group.long 0x680++0x03 line.long 0x00 "COREBCR,Core Boot Control Register" sif !cpuis("LS1012A") eventfld.long 0x00 3. " CORE3 ,Write 1 to clear bit for core3" "No effect,Clear" eventfld.long 0x00 2. " CORE2 ,Write 1 to clear bit for core2" "No effect,Clear" eventfld.long 0x00 1. " CORE1 ,Write 1 to clear bit for core1" "No effect,Clear" newline endif eventfld.long 0x00 0. " CORE0 ,Write 1 to clear bit for core0" "No effect,Clear" sif cpuis("LS10?3A") if (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x0) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x1000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x2000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x3000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x1000+0x10)++0x03 hide.long 0x00 "G0MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x1000+0x14)++0x03 hide.long 0x00 "G0MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x1000+0x18)++0x03 hide.long 0x00 "G0MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x1000+0x1C)++0x03 hide.long 0x00 "G0MSIR4,Shared Message Signaled Interrupt Register 4" if (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x0) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x1000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x2000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x3000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x2000+0x10)++0x03 hide.long 0x00 "G1MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x2000+0x14)++0x03 hide.long 0x00 "G1MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x2000+0x18)++0x03 hide.long 0x00 "G1MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x2000+0x1C)++0x03 hide.long 0x00 "G1MSIR4,Shared Message Signaled Interrupt Register 4" if (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x0) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x1000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x2000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x3000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x3000+0x10)++0x03 hide.long 0x00 "G2MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x3000+0x14)++0x03 hide.long 0x00 "G2MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x3000+0x18)++0x03 hide.long 0x00 "G2MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x3000+0x1C)++0x03 hide.long 0x00 "G2MSIR4,Shared Message Signaled Interrupt Register 4" elif cpuis("LS10?6A") group.long 0x11000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x11000+0x04)++0x03 hide.long 0x00 "G0MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x11000+0x08)++0x03 hide.long 0x00 "G0MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x11000+0x0C)++0x03 hide.long 0x00 "G0MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x11000+0x10)++0x03 hide.long 0x00 "G0MSIR4,Shared Message Signaled Interrupt Register 4" in group.long 0x22000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x22000+0x04)++0x03 hide.long 0x00 "G1MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x22000+0x08)++0x03 hide.long 0x00 "G1MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x22000+0x0C)++0x03 hide.long 0x00 "G1MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x22000+0x10)++0x03 hide.long 0x00 "G1MSIR4,Shared Message Signaled Interrupt Register 4" in group.long 0x33000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x33000+0x04)++0x03 hide.long 0x00 "G2MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x33000+0x08)++0x03 hide.long 0x00 "G2MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x33000+0x0C)++0x03 hide.long 0x00 "G2MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x33000+0x10)++0x03 hide.long 0x00 "G2MSIR4,Shared Message Signaled Interrupt Register 4" in elif cpuis("LS1012A") group.long 0x2000++0x03 line.long 0x00 "PEX1MSIIR,Shared Message Signaled Interrupt Index Register" bitfld.long 0x00 27.--31. " IBS ,Interrupt bit select" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" hgroup.long 0x2004++0x03 hide.long 0x00 "PEX1MSIR,Shared Message Signaled Interrupt Register" in endif endian.le width 0x0B tree.end elif cpuis("LS1012A") tree "SCFG (Supplemental Configuration Unit)" base ad:0x01570000 width 23. endian.be group.long 0x70++0x23 line.long 0x00 "USB3PRM1CR,USB3 Parameter 1 Control Register" bitfld.long 0x00 29.--31. " COMPDISTUNE ,Drives the value of USB3 COMPDISTUNE signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. " OTGTUNE0 ,Drives the value of USB3 OTGTUNE0 signal" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. " SQRXTUNE ,Drives the value of USB3 SQRXTUNE signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--22. " TXFSLSTUNE ,Drives the value of USB3 TXFSLSTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--18. " TXHSXVTUNE ,Drives the value of USB3 TXHSXVTUNE signal" ",-15 mV,+15 mV,Default" bitfld.long 0x00 15.--16. " TXPREEMPAMPTUNE ,Drives the value of USB3 TXPREEMPAMPTUNE signal" "Disabled,1X,2X,3X" newline bitfld.long 0x00 14. " TXPREEMPPULSETUNE ,Drives the value of USB3 TXPREEMPPULSETUNE signal" "1X,2X" bitfld.long 0x00 12.--13. " TXRESTUNE ,Drives the value of USB3 TXRESTUNE signal" "1.5 Ohm,Default,2 Ohm,4 Ohm" bitfld.long 0x00 10.--11. " TXRISETUNE ,Drives the value of USB3 TXRISETUNE signal" "0,1,2,3" newline bitfld.long 0x00 6.--9. " TXVREFTUNE ,Drives the value of USB3 TXVREFTUNE signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--5. " PCSTXDEEMPH3P5DB ,Drives the value of USB3 pcs_tx_deemph_3p5db (Tx de-emphasis at 3.5 dB) signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB3PRM2CR,USB3 Parameter 2 Control Register" hexmask.long.word 0x04 22.--31. 1. " PCSRXLOSMASKVAL ,Drives the value of USB3 pcs_rx_los_mask_val signal" bitfld.long 0x04 16.--21. " PCSTXDEEMPH6DB ,Drives the value of USB3 pcs_tx_deemph_6db signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x04 9.--15. 1. " PCSTXSWINGFULL ,Drives the value of USB3 pcs_tx_swing_full signal" newline bitfld.long 0x04 6.--8. " LOSBIAS ,Drives the value of USB3 los_bias signal" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3.--5. " TXVBOOSTLVL ,Drives the value of USB3 tx_vboost_lvl signal" "0,1,2,3,4,5,6,7" line.long 0x08 "USB3PRM3CR,USB3 Parameter 3 Control Register" bitfld.long 0x08 27.--31. " USB3ACJT ,Drives the value of USB3 acjt_level signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 25.--26. " VATESTENB ,Drives the value of USB3 PHY VATESTENB signal" "0,1,2,3" bitfld.long 0x08 24. " LPBKENB0 ,Drives the value of USB3 PHY LOOPBACKENB0 signal" "0,1" newline bitfld.long 0x08 23. " LNTX2RXLPBK ,Drives the value of all 3 USB3 PHYs lane0_tx2rx_loopbk signal" "0,1" hexmask.long.byte 0x08 16.--22. 1. " MPLL_MULT ,Drives the value of USB3 mpll_multiplier signal" sif !cpuis("LS1012A") group.long 0x100++0x07 line.long 0x00 "USB2_ICID,USB2 ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of USB2 controller" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "USB3_ICID,USB3 ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of USB3 controller" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" sif cpuis("LS10?3A") group.long 0x114++0x03 line.long 0x00 "DMA_ICID,QDMA ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of qDMA" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x118++0x07 line.long 0x00 "SATA_ICID,QDMA ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of SATA" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "USB1_ICID,USB1 ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of USB1 controller" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" sif cpuis("LS10?3*") group.long 0x120++0x03 line.long 0x00 "QE_ICID,QE ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of QE" bitfld.long 0x00 20. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x124++0x0B line.long 0x00 "SDHC_ICID,eSDHC ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID of eSDHC" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x04 "EDMA_ICID,eDMA ICID Register" hexmask.long.byte 0x04 24.--31. 1. " ICID ,ICID of eDMA" bitfld.long 0x04 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" line.long 0x08 "ETR_ICID,ETR ICID Register" hexmask.long.byte 0x08 24.--31. 1. " ICID ,ICID of ETR" bitfld.long 0x08 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif sif cpuis("LS1012A") group.long 0x130++0x03 line.long 0x00 "CORE0_SFT_RST,Core 0 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 0 when 1 is written on this bit" "No reset,Reset" else group.long 0x130++0x03 line.long 0x00 "CORE0_SFT_RST,Core 0 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 0 when 1 is written on this bit" "No reset,Reset" group.long 0x134++0x03 line.long 0x00 "CORE1_SFT_RST,Core 1 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 1 when 1 is written on this bit" "No reset,Reset" group.long 0x138++0x03 line.long 0x00 "CORE2_SFT_RST,Core 2 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 2 when 1 is written on this bit" "No reset,Reset" group.long 0x13C++0x03 line.long 0x00 "CORE3_SFT_RST,Core 3 Soft Reset Register" bitfld.long 0x00 31. " SOFT_RESET ,Reset process is initiated for core 3 when 1 is written on this bit" "No reset,Reset" endif sif cpuis("LS10?3*") group.long 0x144++0x03 line.long 0x00 "PEXPMECR,PEX PME Control Register" bitfld.long 0x00 31. " PEX1PME ,Generates PM turnoff message for power management for PEX1" "Default,RC mode only" bitfld.long 0x00 27. " PEX2PME ,Generates PM turnoff message for power management for PEX2" "Default,RC mode only" bitfld.long 0x00 23. " PEX3PME ,Generates PM turnoff message for power management for PEX3" "Default,RC mode only" endif group.long 0x154++0x03 line.long 0x00 "FTM_CHAIN_CONFIG,FTM chain configuration" sif cpuis("LS10?6A") bitfld.long 0x00 31. " CORE0 ,CORE0 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 30. " CORE1 ,CORE1 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 29. " CORE2 ,CORE2 flextimer reset enable" "Disabled,Enabled" bitfld.long 0x00 28. " CORE3 ,CORE3 flextimer reset enable" "Disabled,Enabled" newline elif cpuis("LS1012A") bitfld.long 0x00 17. " FTM_CHN2 ,FTM2 chaining" "Not chained,Chained" bitfld.long 0x00 16. " FTM_CHN1 ,FTM1 chaining" "Not chained,Chained" newline endif sif !cpuis("LS1012A") bitfld.long 0x00 15. " FTM_CHN1 ,FTM1 and FTM5 chain" "Not chained,Chained" bitfld.long 0x00 14. " FTM_CHN2 ,FTM2 and FTM6 chain" "Not chained,Chained" bitfld.long 0x00 13. " FTM_CHN3 ,FTM3 and FTM7 chain" "Not chained,Chained" bitfld.long 0x00 12. " FTM_CHN4 ,FTM4 and FTM8 chain" "Not chained,Chained" endif group.long 0x158++0x07 line.long 0x00 "ALTCBAR,ALTCBAR Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " ALTCBAR ,Alt configuration base address register for PBL" line.long 0x04 "QSPI_CFG,QSPI CONFIG Register" bitfld.long 0x04 28.--31. " CLK_SEL ,Control the division of CGA1/CGA2 PLL clock to generate QuadSPI interface clocks" "/256,/64,/32,/24,/20,/16,/12,/8,?..." sif cpuis("LS1012A") group.long 0x164++0x0F line.long 0x00 "WR_QOS1,Write QOS1 Register" bitfld.long 0x00 24.--27. " PFE1_QOS ,QOS[3:0] for PFE DDR AXI master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PFE2_QOS ,QOS[3:0] for PFE HDBUD master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PFE1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "WR_QOS2,Write QOS2 Register" bitfld.long 0x04 28.--31. " USB3_QOS ,QOS [3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " A53_QOS ,QOS [3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " ESDHC2_QOS ,QOS [3:0] for eSDHC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 8.--11. " ESDHC1_QOS ,QOS [3:0] for eSDHC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " USB2_QOS ,QOS [3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " SATA_QOS ,QOS [3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RD_QOS1,Read OS1 Register" bitfld.long 0x08 24.--27. " PFE1_QOS ,QOS[3:0] for PFE DDR AXI master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " PFE2_QOS ,QOS[3:0] for PFE HDBUD master interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " PFE1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RD_QOS2,Read QOS2 Register" bitfld.long 0x0C 28.--31. " USB3_QOS ,QOS [3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " A53_QOS ,QOS [3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--15. " ESDHC2_QOS ,QOS [3:0] for eSDHC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " eSDHC1_QOS ,QOS [3:0] for eSDHC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " USB2_QOS ,QOS [3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " SATA_QOS ,QOS [3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x16C++0x07 line.long 0x00 "QOS1,QOS1 Register" bitfld.long 0x00 28.--31. " EDMA_QOS ,QOS[3:0] for eDMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " USB2_QOS ,QOS[3:0] for USB2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " USB3_QOS ,QOS[3:0] for USB3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " QDMA_QOS ,QOS[3:0] for qDMA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " PEX2_QOS ,QOS[3:0] for PEX2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PEX1_QOS ,QOS[3:0] for PEX1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SEC_QOS ,QOS[3:0] for SEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " FM_QOS ,QOS[3:0] for FM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "QOS2,QOS2 Register" bitfld.long 0x04 28.--31. " USB1_QOS ,QOS[3:0] for USB1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " PEX3_QOS ,QOS[3:0] for PEX3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " QMAN_QOS ,QOS[3:0] for QMan" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("LS10?3A") bitfld.long 0x04 16.--19. " A53_QOS ,QOS[3:0] for A53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif cpuis("LS10?6A") bitfld.long 0x04 16.--19. " A72_QOS ,QOS[3:0] for A72" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif bitfld.long 0x04 8.--11. " ESDHC_QOS ,QOS[3:0] for eSDHC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("LS10?3A") bitfld.long 0x04 4.--7. " QE_QOS ,QOS[3:0] for QE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x04 0.--3. " SATA_QOS ,QOS[3:0] for SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif cpuis("LS10?3A") group.long 0x188++0x03 line.long 0x00 "GIC400_ADDR_ALIGN_64K,GIC-400 Address 64K Page Alignment Register" bitfld.long 0x00 31. " GIC_ADDR ,Controls the GIC-400 addressing" "64K,Non-64K" endif sif !cpuis("LS1012A") group.long 0x18C++0x03 line.long 0x00 "DEBUG_ICID,Debug ICID Register" hexmask.long.byte 0x00 24.--31. 1. " ICID ,ICID input to the SMMU" bitfld.long 0x00 23. " LOCK_BIT ,Lock bit" "Not locked,Locked" endif group.long 0x1A4++0x03 line.long 0x00 "SNPCNFGCR,Snoop Configuration Register" sif !cpuis("LS1012A") bitfld.long 0x00 31. " SECRDSNP ,Drives SEC read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 30. " SECWRSNP ,Controls snoop attribute of SEC writes" "Not snoopable,Snoopable" newline endif bitfld.long 0x00 23. " SATARDSNP ,Drives SATA read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 22. " SATAWRSNP ,Controls snoop attribute of SATA writes" "Not snoopable,Snoopable" newline sif cpuis("LS1012A") bitfld.long 0x00 21. " USBRDSNP ,Drives USB3 read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 20. " USBWRSNP ,Controls snoop attribute of USB3 writes" "Not snoopable,Snoopable" newline else bitfld.long 0x00 21. " USB1RDSNP ,Drives USB1 read snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 20. " USB1WRSNP ,Controls snoop attribute of USB1 writes" "Not snoopable,Snoopable" newline endif bitfld.long 0x00 19. " DBGRDSNP ,Debug reads are snoopable" "Not snoopable,Snoopable" bitfld.long 0x00 18. " DBGWRSNP ,Drives DEBUG write snoop signal" "Not snoopable,Snoopable" sif !cpuis("LS10?6A") newline bitfld.long 0x00 17. " EDMASNP ,Drives eDMA snoop signal" "Not snoopable,Snoopable" endif sif !cpuis("LS1012A") newline bitfld.long 0x00 16. " USB2WRSNP ,Drives USB2 write snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 15. " USB2RDSNP ,Drives USB2 read snoop signal" "Not snoopable,Snoopable" newline bitfld.long 0x00 14. " USB3WRSNP ,Drives USB3 write snoop signal" "Not snoopable,Snoopable" bitfld.long 0x00 13. " USB3RDSNP ,Drives USB3 read snoop signal" "Not snoopable,Snoopable" endif sif !cpuis("LS1012A") group.long 0x1AC++0x03 line.long 0x00 "INTPCR,Interrupt Polarity Register" bitfld.long 0x00 31. " IRQ0INTP ,Controls the polarity of IRQ0" "Active high,Active low" bitfld.long 0x00 30. " IRQ1INTP ,Controls the polarity of IRQ1" "Active high,Active low" bitfld.long 0x00 29. " IRQ2INTP ,Controls the polarity of IRQ2" "Active high,Active low" newline bitfld.long 0x00 28. " IRQ3INTP ,Controls the polarity of IRQ3" "Active high,Active low" bitfld.long 0x00 27. " IRQ4INTP ,Controls the polarity of IRQ4" "Active high,Active low" bitfld.long 0x00 26. " IRQ5INTP ,Controls the polarity of IRQ5" "Active high,Active low" newline bitfld.long 0x00 25. " IRQ6INTP ,Controls the polarity of IRQ6" "Active high,Active low" bitfld.long 0x00 24. " IRQ7INTP ,Controls the polarity of IRQ7" "Active high,Active low" bitfld.long 0x00 23. " IRQ8INTP ,Controls the polarity of IRQ8" "Active high,Active low" newline bitfld.long 0x00 22. " IRQ9INTP ,Controls the polarity of IRQ9" "Active high,Active low" bitfld.long 0x00 21. " IRQ10INTP ,Controls the polarity of IRQ10" "Active high,Active low" bitfld.long 0x00 20. " IRQ11INTP ,Controls the polarity of IRQ11" "Active high,Active low" endif group.long 0x204++0x03 line.long 0x00 "CORESRENCR,CORE Soft Reset Enable Register" bitfld.long 0x00 31. " CORESREN ,Controls the enable of core soft reset functionality" "Disabled,Enabled" sif cpuis("LS1012A") group.long 0x220++0x08 line.long 0x00 "RVBAR0_0,Core 0 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR0_1,Core 0 Reset Vector Base Address Register 1" else group.long 0x220++0x08 line.long 0x00 "RVBAR0_0,Core 0 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR0_1,Core 0 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR0_1 ,Core 0 reset vector base address for bits [39:34]" group.long 0x228++0x08 line.long 0x00 "RVBAR1_0,Core 1 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR1_1,Core 1 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR1_1 ,Core 1 reset vector base address for bits [39:34]" group.long 0x230++0x08 line.long 0x00 "RVBAR2_0,Core 2 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR2_1,Core 2 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR2_1 ,Core 2 reset vector base address for bits [39:34]" group.long 0x238++0x08 line.long 0x00 "RVBAR3_0,Core 3 Reset Vector Base Address Register 0" line.long 0x04 "RVBAR3_1,Core 3 Reset Vector Base Address Register 1" hexmask.long.byte 0x04 26.--31. 0x4 " RVBAR3_1 ,Core 3 reset vector base address for bits [39:34]" endif group.long 0x240++0x03 line.long 0x00 "LPMCSR,Core Low Power Mode Control Status Register" sif !cpuis("LS1012A") bitfld.long 0x00 28. " SMPEN3 ,Status bit for SMPEN signal of core 3" "0,1" bitfld.long 0x00 27. " CPUQDENY3 ,Status bit for CPUQDENY signal for core 3" "0,1" bitfld.long 0x00 26. " CPUQACCEPTN3 ,Status bit for CPUQACCEPTn signal for core 3" "0,1" newline bitfld.long 0x00 25. " CPUQACTIVE3 ,Status bit for CPUQACTIVE signal for core 3" "0,1" bitfld.long 0x00 24. " CPUQREQN3 ,Control bit for CPUQREQn for core 3" "0,1" newline bitfld.long 0x00 20. " SMPEN2 ,Status bit for SMPEN signal of core 2" "0,1" bitfld.long 0x00 19. " CPUQDENY2 ,Status bit for CPUQDENY signal for core 2" "0,1" bitfld.long 0x00 18. " CPUQACCEPTN2 ,Status bit for CPUQACCEPTn signal for core 2" "0,1" newline bitfld.long 0x00 17. " CPUQACTIVE2 ,Status bit for CPUQACTIVE signal for core 2" "0,1" bitfld.long 0x00 16. " CPUQREQN2 ,Control bit for CPUQREQn for core 2" "0,1" newline bitfld.long 0x00 12. " SMPEN1 ,Status bit for SMPEN signal of core 1" "0,1" bitfld.long 0x00 11. " CPUQDENY1 ,Status bit for CPUQDENY signal for core 1" "0,1" bitfld.long 0x00 10. " CPUQACCEPTN1 ,Status bit for CPUQACCEPTn signal for core 1" "0,1" newline bitfld.long 0x00 9. " CPUQACTIVE1 ,Status bit for CPUQACTIVE signal for core 1" "0,1" bitfld.long 0x00 8. " CPUQREQN1 ,Control bit for CPUQREQn for core 1" "0,1" newline endif bitfld.long 0x00 4. " SMPEN0 ,Status bit for SMPEN signal of core 0" "0,1" bitfld.long 0x00 3. " CPUQDENY0 ,Status bit for CPUQDENY signal for core 0" "0,1" bitfld.long 0x00 2. " CPUQACCEPTN0 ,Status bit for CPUQACCEPTn signal for core 0" "0,1" newline bitfld.long 0x00 1. " CPUQACTIVE0 ,Status bit for CPUQACTIVE signal for core 0" "0,1" bitfld.long 0x00 0. " CPUQREQN0 ,Control bit for CPUQREQn for core 0" "0,1" sif !cpuis("LS1012A") group.long 0x404++0x03 line.long 0x00 "ECGTXCMCR,ECGTX Clock Mux Control Register" bitfld.long 0x00 27. " CLK_SEL ,Selects 125 MHz reference clock for RGMII" "EC1_GTX_CLK125,EC2_GTX_CLK125" endif group.long 0x408++0x03 line.long 0x00 "SDHCIOVSELCR,SDHC IO VSEL Control Register" bitfld.long 0x00 31. " TGLEN ,SDHC IO voltage switching enable" "Disabled,Enabled" bitfld.long 0x00 29.--30. " VSELVAL ,Configures voltage for SDHC" "1.8V,,3.3V,Auto" sif cpuis("LS1012A") bitfld.long 0x00 0. " SDHC_VS ,SCFG bit reflecting shadow bit controlled by software for eSDHC_PROCTL[VOLT_SEL]" "3.3V,1.8V" else bitfld.long 0x00 0. " SDHC_VS ,SCFG bit reflecting shadow bit controlled by switch for SDHC:VOLT_SEL" "3.3V,1.8V" endif sif !cpuis("LS1012A") group.long 0x40C++0x07 line.long 0x00 "RCWPMUXCR0,Extended RCW PinMux Control Register" sif cpuis("LS10?6A") bitfld.long 0x00 12.--14. " IIC3_SCL ,Configures functionality of the IIC3_SCL" "IIC3_SCL,GPIO_4[10],EVT_B[5],USB2_DRVVBUS,,FTM8_CH0,CLK11,?..." newline bitfld.long 0x00 8.--10. " IIC3_SDA ,Configures functionality of the IIC3_SDA" "IIC3_SDA,GPIO_4[11],EVT_B[6],USB2_PWRFAULT,,FTM8_CH1,CLK12_CLK8,IIC3_SDA" newline bitfld.long 0x00 4.--6. " IIC4_SCL ,Configures functionality of the IIC4_SCL" "IIC4_SCL,GPIO_4[12],EVT_B[7],USB3_DRVVBUS,,FTM3_FAULT,UC1_CDB_RXER,IIC4_SCL" newline bitfld.long 0x00 0.--2. " IIC4_SDA ,Configures functionality of the IIC4_SDA" "IIC4_SDA,GPIO_4[13],EVT_B[8],USB3_PWRFAULT,,FTM3_EXTCLK,,IIC4_SDA" elif cpuis("LS10?3A") bitfld.long 0x00 12.--14. " IIC3_SCL ,Configures functionality of the IIC3_SCL" "IIC3_SCL,GPIO_4[10],EVT_B[5],USB2_DRVVBUS,BRGO4,FTM8_CH0,CLK11,?..." newline bitfld.long 0x00 8.--10. " IIC3_SDA ,Configures functionality of the IIC3_SDA" "IIC3_SDA,GPIO_4[11],EVT_B[6],USB2_PWRFAULT,BRGO1,FTM8_CH1,CLK12_CLK8,?..." newline bitfld.long 0x00 4.--6. " IIC4_SCL ,Configures functionality of the IIC4_SCL" "IIC4_SCL,GPIO_4[12],EVT_B[7],USB3_DRVVBUS,TDMA_RQ,FTM3_FAULT,UC1_CDB_RXER,?..." newline bitfld.long 0x00 0.--2. " IIC4_SDA ,Configures functionality of the IIC4_SDA" "IIC4_SDA,GPIO_4[13],EVT_B[8],USB3_PWRFAULT,TDMB_RQ,FTM3_EXTCLK,UC3_CDB_RXER,IIC4_SDA" endif line.long 0x04 "USBDRVVBUS_SELCR,USB DRVVBUS Control Register" bitfld.long 0x04 0.--1. " USB_SEL ,Selection of USB Controller to drive USB_DRVVBUS I/O" "USB Controller 1,USB Controller 2,,USB Controller 3" endif newline group.long 0x414++0x07 line.long 0x00 "USBPWRFAULT_SELCR,USB PWRFAULT Control Register" sif cpuis("LS1012A") bitfld.long 0x00 0. " USB1_SEL ,USB1 controller connectivity" "Only 3.0,Shared" else bitfld.long 0x00 4.--5. " USB3_SEL ,USB controller 3 connectivity" "Inactive,Shared USB_PWRFAULT I/O,Dedicated USB3_PWRFAULT I/O,?..." bitfld.long 0x00 2.--3. " USB2_SEL ,USB controller 2 connectivity" "Inactive,Shared USB_PWRFAULT I/O,Dedicated USB3_PWRFAULT I/O,?..." bitfld.long 0x00 0.--1. " USB1_SEL ,USB controller 1 connectivity" "Inactive,Shared USB_PWRFAULT I/O,?..." endif sif cpuis("LS1012A") line.long 0x04 "USB_PHY_CTRL,USB PHY Control Register" bitfld.long 0x04 31. " RST ,USBPHY reset" "No reset,Reset" bitfld.long 0x04 9. " PDN_SSP ,Forces the super speed function to lowest power state" "Not forced,Forced" bitfld.long 0x04 8. " PDN_HSP ,Forces the high speed function to lowest power state" "Not forced,Forced" newline bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else line.long 0x04 "USB_REFCLK_SELCR1,USB PHY 1 Reference Clock Select Register" bitfld.long 0x04 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. " CKSEL ,Selects the reference clock for USB PHY 1 PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," endif sif !cpuis("LS1012A") group.long 0x41C++0x0B line.long 0x00 "USB_REFCLK_SELCR2,USB PHY2 Reference Clock Select Register" bitfld.long 0x00 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x00 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--1. " CKSEL ,Selects the reference clock for USB PHY 2PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," line.long 0x04 "USB_REFCLK_SELCR3,USB PHY#3 Reference Clock Select Register" bitfld.long 0x04 31. " RST ,Active high reset" "No reset,Reset" bitfld.long 0x04 2.--7. " FSEL ,Controls USB PHY PLL reference clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--1. " CKSEL ,Selects the reference clock for USB PHY 2PLL" "SYSCLK,,DIFF_SYSCLK/DIFF_SYSCLK_B," line.long 0x08 "RETREQCR,Retention Request Control Register" bitfld.long 0x08 31. " RETREQ0 ,Retention request enable 0" "Disabled,Enabled" bitfld.long 0x08 30. " RETREQ1 ,Retention request enable 1" "Disabled,Enabled" newline bitfld.long 0x08 29. " RETREQ2 ,Retention request enable 2" "Disabled,Enabled" bitfld.long 0x08 28. " RETREQ3 ,Retention request enable 3" "Disabled,Enabled" endif sif cpuis("LS10?6A") group.long 0x42C++0x03 line.long 0x00 "COREPMCR,CORE PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable for core A72" "Disabled,Enabled" elif cpuis("LS10?3A") group.long 0x42C++0x03 line.long 0x00 "COREPMCR,CORE PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable for core A53" "Disabled,Enabled" elif cpuis("LS1012A") group.long 0x42C++0x03 line.long 0x00 "CLUSTERPMCR,CLUSTER PM Control Register" bitfld.long 0x00 0. " WFIL2EN ,WFIL2 Enable" "Disabled,Enabled" endif sif cpuis("LS1012A") group.long 0x430++0x03 line.long 0x00 "PMUXCR0,Pinmux Control Register" bitfld.long 0x00 31. " QSPI_MUX_OVRD ,Software override for QSPI multiplexing enable" "Disabled,Enabled" bitfld.long 0x00 30. " QSPI_DATA0_GPIO_OVRD ,Software configures alternate functionality of the QuadSPI pins for 1-bit interface" "QSPI_A_DATO/SCK/CS0,GPIO1_4/11/5" newline bitfld.long 0x00 28.--29. " QSPI_DATA1_GPIO_OVRD ,Software configures alternate functionality of the QuadSPI pins for 2-bit interface" "QSPI_A_DAT1,GPIO1_12,?..." bitfld.long 0x00 26.--27. " QSPI_IIC2_OVRD ,Software configures alternate functionality of the QuadSPI pins for additional 2-bit interface" "GPIO1_13 / 14,,QSPI_DATA2 / DATA3,?..." if (((per.l.be(ad:0x01570000+0x434))&0x08)==0x08) group.long 0x434++0x03 line.long 0x00 "RGMIIPCR,RGMII Port Control Register" bitfld.long 0x00 3. " EN_AUTO ,Link speed selection source" "SETSP/SETFD bits,Auto" bitfld.long 0x00 1.--2. " SETSP ,Set RGMII link speed" "100Mbps,10Mbps,1Gbps,?..." newline bitfld.long 0x00 0. " SETFD ,Force full duplex RGMII mode enable" ",Enabled" else group.long 0x434++0x03 line.long 0x00 "RGMIIPCR,RGMII Port Control Register" bitfld.long 0x00 3. " EN_AUTO ,Link speed selection source" "SETSP/SETFD bits,Auto" newline bitfld.long 0x00 0. " SETFD ,Force full duplex RGMII mode enable" ",Enabled" endif newline rgroup.long 0x43C++0x07 line.long 0x00 "RGMIIPSR,RGMII Port Status Register" bitfld.long 0x00 31. " RGLINK ,RGMII link status" "Not linked,Linked" bitfld.long 0x00 29.--30. " RGSP ,RGMII link speed status" "100Mbps,10Mbps,1Gbps,?..." bitfld.long 0x00 28. " RGFD ,RGMII full duplex link mode status" "Not established,Established" line.long 0x04 "PFEPCSSR1,PFE PCS Status Register 1" bitfld.long 0x04 31. " PCS ,Link synchronization event" "0,1" bitfld.long 0x04 30. " AN ,Auto negotiation status" "0,1" bitfld.long 0x04 29. " LT ,New page received by auto negotiation function" "0,1" group.long 0x444++0x03 line.long 0x00 "PFEINTENCR1,PFE Interrupt Enable Control Register 1" bitfld.long 0x00 31. " PCS_EN ,Interrupt enable bit for link synchronization event on PFE MAC1" "Disabled,Enabled" bitfld.long 0x00 30. " AN_EN ,Interrupt enable bit for auto negotiation on PFE MAC1" "Disabled,Enabled" bitfld.long 0x00 29. " LT_EN ,Interrupt enable bit for new page received on auto negotiation on PFE MAC1" "Disabled,Enabled" rgroup.long 0x448++0x03 line.long 0x00 "PFEPCSSR2,PFE PCS Status Register 2" bitfld.long 0x00 31. " PCS ,Link synchronization event" "0,1" bitfld.long 0x00 30. " AN ,Auto negotiation status" "0,1" bitfld.long 0x00 29. " LT ,New page received by auto negotiation function" "0,1" group.long 0x44C++0x0B line.long 0x00 "PFEINTENCR2,PFE Interrupt Enable Control Register 2" bitfld.long 0x00 31. " PCS_EN ,Interrupt enable bit for link synchronization event on PFE MAC2" "Disabled,Enabled" bitfld.long 0x00 30. " AN_EN ,Interrupt enable bit for auto negotiation on PFE MAC2" "Disabled,Enabled" bitfld.long 0x00 29. " LT_EN ,Interrupt enable bit for new page received on auto negotiation on PFE MAC2" "Disabled,Enabled" line.long 0x04 "PFEERRCR,PFE Error Control Register" eventfld.long 0x04 31. " WRERSPP1 ,Write error response for PFE DDR master interface" "Not captured,Captured" eventfld.long 0x04 30. " RDERSPP1 ,Read error response for PFE DDR master interface" "Not captured,Captured" newline eventfld.long 0x04 29. " WRERSPP2 ,Write error response for PFE HDBUS master interface" "Not captured,Captured" eventfld.long 0x04 28. " RDEDSPP2 ,Read error response for PFE HDBUS master interface" "Not captured,Captured" line.long 0x08 "PFEERRINTENCR,PFE Error Interrupt Enable Control Register" eventfld.long 0x08 31. " WRERSPENP1 ,Interrupt enable bit for write error response captured for PFE DDR master interface" "Disabled,Enabled" eventfld.long 0x08 30. " RDERSPENP1 ,Interrupt enable bit for read error response captured for PFE DDR master interface" "Disabled,Enabled" newline eventfld.long 0x08 29. " WRERSPENP2 ,Interrupt enable bit for write error response captured for PFE HDBUS master interface" "Disabled,Enabled" eventfld.long 0x08 28. " RDERSPENP2 ,Interrupt enable bit for read error response captured for PFE HDBUS master interface" "Disabled,Enabled" group.long 0x458++0x03 line.long 0x00 "PFEASBCR,PFEA Sideband Control Register" bitfld.long 0x00 31. " ARCACHE0 ,Control bit for ARCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 30. " AWCACHE0 ,Control bit for AWCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 29. " ARCACHE1 ,Control bit for ARCACHE[1] attribute" "Non modifable,Modifable" newline bitfld.long 0x00 28. " AWCACHE1 ,Control bit for AWCACHE[1] attribute" "Non modifable,Modifable" bitfld.long 0x00 27. " ARSNP ,Control bit for snoopable attribute of read channel" "Non snoopable,Snoopable" bitfld.long 0x00 26. " AWSNP ,Control bit for snoopable attribute of write channel" "Non snoopable,Snoopable" group.long 0x45C++0x03 line.long 0x00 "PFEBSBCR,PFEB Sideband Control Register" bitfld.long 0x00 31. " ARCACHE0 ,Control bit for ARCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 30. " AWCACHE0 ,Control bit for AWCACHE[0] attribute" "Non bufferable,Bufferable" bitfld.long 0x00 29. " ARCACHE1 ,Control bit for ARCACHE[1] attribute" "Non modifable,Modifable" newline bitfld.long 0x00 28. " AWCACHE1 ,Control bit for AWCACHE[1] attribute" "Non modifable,Modifable" bitfld.long 0x00 27. " ARSNP ,Control bit for snoopable attribute of read channel" "Non snoopable,Snoopable" bitfld.long 0x00 26. " AWSNP ,Control bit for snoopable attribute of write channel" "Non snoopable,Snoopable" group.long 0x484++0x03 line.long 0x00 "MDIOSELCR,MDIO Select Control Register" bitfld.long 0x00 31. " MDIOSEL ,EMI1_MDIO source select" "SerDes,Ethernet PHY" group.long 0x500++0x03 line.long 0x00 "SPARECR1,Spare Control Register 1" group.long 0x504++0x03 line.long 0x00 "SPARECR2,Spare Control Register 2" group.long 0x508++0x03 line.long 0x00 "SPARECR3,Spare Control Register 3" group.long 0x50C++0x03 line.long 0x00 "SPARECR4,Spare Control Register 4" group.long 0x510++0x03 line.long 0x00 "SPARECR5,Spare Control Register 5" group.long 0x514++0x03 line.long 0x00 "SPARECR6,Spare Control Register 6" group.long 0x518++0x03 line.long 0x00 "SPARECR7,Spare Control Register 7" group.long 0x51C++0x03 line.long 0x00 "SPARECR8,Spare Control Register 8" group.long 0x520++0x03 line.long 0x00 "I2CDBGCR,I2C Debug Mode Control Register" bitfld.long 0x00 29. " I2C1 ,I2C1 glitch filter enable" "Disabled,Enabled" bitfld.long 0x00 28. " I2C2 ,I2C2 glitch filter enable" "Disabled,Enabled" endif group.long 0x600++0x03 line.long 0x00 "SCRATCHRW1,Scratch Read Write Register 1" group.long 0x604++0x03 line.long 0x00 "SCRATCHRW2,Scratch Read Write Register 2" group.long 0x608++0x03 line.long 0x00 "SCRATCHRW3,Scratch Read Write Register 3" group.long 0x60C++0x03 line.long 0x00 "SCRATCHRW4,Scratch Read Write Register 4" sif cpuis("LS10?6A") group.long 0x610++0x03 line.long 0x00 "SCRATCHRW5,Scratch Read Write Register 5" group.long 0x614++0x03 line.long 0x00 "SCRATCHRW6,Scratch Read Write Register 6" group.long 0x618++0x03 line.long 0x00 "SCRATCHRW7,Scratch Read Write Register 7" group.long 0x61C++0x03 line.long 0x00 "SCRATCHRW8,Scratch Read Write Register 8" endif group.long 0x680++0x03 line.long 0x00 "COREBCR,Core Boot Control Register" sif !cpuis("LS1012A") eventfld.long 0x00 3. " CORE3 ,Write 1 to clear bit for core3" "No effect,Clear" eventfld.long 0x00 2. " CORE2 ,Write 1 to clear bit for core2" "No effect,Clear" eventfld.long 0x00 1. " CORE1 ,Write 1 to clear bit for core1" "No effect,Clear" newline endif eventfld.long 0x00 0. " CORE0 ,Write 1 to clear bit for core0" "No effect,Clear" sif cpuis("LS10?3A") if (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x0) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x1000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x2000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x1000))&0x3000000)==0x3000000) group.long 0x1000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x1000+0x10)++0x03 hide.long 0x00 "G0MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x1000+0x14)++0x03 hide.long 0x00 "G0MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x1000+0x18)++0x03 hide.long 0x00 "G0MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x1000+0x1C)++0x03 hide.long 0x00 "G0MSIR4,Shared Message Signaled Interrupt Register 4" if (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x0) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x1000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x2000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x2000))&0x3000000)==0x3000000) group.long 0x2000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x2000+0x10)++0x03 hide.long 0x00 "G1MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x2000+0x14)++0x03 hide.long 0x00 "G1MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x2000+0x18)++0x03 hide.long 0x00 "G1MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x2000+0x1C)++0x03 hide.long 0x00 "G1MSIR4,Shared Message Signaled Interrupt Register 4" if (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x0) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x1000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x2000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" elif (((per.l.be(ad:0x01570000+0x3000))&0x3000000)==0x3000000) group.long 0x3000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--28. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" endif hgroup.long (0x3000+0x10)++0x03 hide.long 0x00 "G2MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x3000+0x14)++0x03 hide.long 0x00 "G2MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x3000+0x18)++0x03 hide.long 0x00 "G2MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x3000+0x1C)++0x03 hide.long 0x00 "G2MSIR4,Shared Message Signaled Interrupt Register 4" elif cpuis("LS10?6A") group.long 0x11000++0x03 line.long 0x00 "G0MSIIR,Shared Message Signaled Interrupt Index Register 0" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x11000+0x04)++0x03 hide.long 0x00 "G0MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x11000+0x08)++0x03 hide.long 0x00 "G0MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x11000+0x0C)++0x03 hide.long 0x00 "G0MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x11000+0x10)++0x03 hide.long 0x00 "G0MSIR4,Shared Message Signaled Interrupt Register 4" in group.long 0x22000++0x03 line.long 0x00 "G1MSIIR,Shared Message Signaled Interrupt Index Register 1" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x22000+0x04)++0x03 hide.long 0x00 "G1MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x22000+0x08)++0x03 hide.long 0x00 "G1MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x22000+0x0C)++0x03 hide.long 0x00 "G1MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x22000+0x10)++0x03 hide.long 0x00 "G1MSIR4,Shared Message Signaled Interrupt Register 4" in group.long 0x33000++0x03 line.long 0x00 "G2MSIIR,Shared Message Signaled Interrupt Index Register 2" bitfld.long 0x00 26.--30. " IBS ,Interrupt bit selects the bit to set in the MSIR" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" bitfld.long 0x00 24.--25. " SRS ,Shared interrupt register select" "MSIR1,MSIR2,MSIR3,MSIR4" hgroup.long (0x33000+0x04)++0x03 hide.long 0x00 "G2MSIR1,Shared Message Signaled Interrupt Register 1" in hgroup.long (0x33000+0x08)++0x03 hide.long 0x00 "G2MSIR2,Shared Message Signaled Interrupt Register 2" in hgroup.long (0x33000+0x0C)++0x03 hide.long 0x00 "G2MSIR3,Shared Message Signaled Interrupt Register 3" in hgroup.long (0x33000+0x10)++0x03 hide.long 0x00 "G2MSIR4,Shared Message Signaled Interrupt Register 4" in elif cpuis("LS1012A") group.long 0x2000++0x03 line.long 0x00 "PEX1MSIIR,Shared Message Signaled Interrupt Index Register" bitfld.long 0x00 27.--31. " IBS ,Interrupt bit select" "SH0,SH1,SH2,SH3,SH4,SH5,SH6,SH7,SH8,SH9,SH10,SH11,SH12,SH13,SH14,SH15,SH16,SH17,SH18,SH19,SH20,SH21,SH22,SH23,SH24,SH25,SH26,SH27,SH28,SH29,SH30,SH31" hgroup.long 0x2004++0x03 hide.long 0x00 "PEX1MSIR,Shared Message Signaled Interrupt Register" in endif endian.le width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "DCFG (Device Configuration and Pin Control)" base ad:0x01E00000 width 10. rgroup.long 0x00++0x07 line.long 0x00 "PORSR1,POR Status 1 Register" hexmask.long.word 0x00 23.--31. 1. " RCW_SRC ,Reset configuration word source" bitfld.long 0x00 21. " RSP_DIS ,Reset pause" "No reset,Reset" newline bitfld.long 0x00 18. " IFC_TE ,IFC external transceive enable polarity selection" "Active high,Active low" bitfld.long 0x00 7. " SOC ,SoC use" "Not set,Set" line.long 0x04 "PORSR2,POR Status 2 Register" bitfld.long 0x04 30.--31. " SVR_VER ,System version register version" "0,1,2,3" bitfld.long 0x04 20. " RCLK_CFG ,Power-on-reset reference clock configuration" "Differential clock,SYSCLK" rgroup.long 0x20++0x0F line.long 0x00 "GPPORCR1,General-Purpose POR Configuration Register 1" hexmask.long.byte 0x00 0.--7. 0x01 " POR_CFG_VEC ,Sampled from local bus address/data signals" line.long 0x04 "GPPORCR2,General-Purpose POR Configuration Register 2" line.long 0x08 "GPPORCR3,General-Purpose POR Configuration Register 3" line.long 0x0C "GPPORCR4,General-Purpose POR Configuration Register 4" rgroup.long 0x60++0x03 line.long 0x00 "FUSESR,Fuse Status Register" bitfld.long 0x00 25.--29. " DA_V ,Minimum voltage required to reach the frequency specified" "1.025 V,,0.9875 V,,0.9750 V,,,,0.9 V,,,,,,,,1.0000 V,1.0125 V,1.0250 V,?..." bitfld.long 0x00 20.--24. " DA_ALT_V ,Secondary voltage field for VDD" "1.025 V,,0.9875 V,,0.9750 V,,,,0.9 V,,,,,,,,1.0000 V,1.0125 V,1.0250 V,?..." group.long 0x70++0x17 line.long 0x00 "DEVDISR1,Device Disable 1 Register" bitfld.long 0x00 22. " SEC ,SEC disable" "No,Yes" bitfld.long 0x00 16. " SATA1_SAS1_FC1 ,SATA1/SAS1/FC1 disable" "No,Yes" newline bitfld.long 0x00 13. " USB2 ,USB2 disable" "No,Yes" bitfld.long 0x00 12. " USB1 ,USB1 disable" "No,Yes" newline bitfld.long 0x00 8. " QDMA ,QDMA disable" "No,Yes" bitfld.long 0x00 3. " HDLC ,HDLC/uQE disable" "No,Yes" newline bitfld.long 0x00 2. " ESDHC ,ESDHC disable" "No,Yes" line.long 0x04 "DEVDISR2,Device Disable 2 Register" bitfld.long 0x04 9. " MAC_10 ,MAC_10 disable" "No,Yes" newline bitfld.long 0x04 8. " MAC_9 ,MAC_9 disable" "No,Yes" bitfld.long 0x04 7. " MAC_8 ,MAC_8 disable" "No,Yes" bitfld.long 0x04 6. " MAC_7 ,MAC_7 disable" "No,Yes" newline bitfld.long 0x04 5. " MAC_6 ,MAC_6 disable" "No,Yes" bitfld.long 0x04 4. " MAC_5 ,MAC_5 disable" "No,Yes" bitfld.long 0x04 3. " MAC_4 ,MAC_4 disable" "No,Yes" newline bitfld.long 0x04 2. " MAC_3 ,MAC_3 disable" "No,Yes" bitfld.long 0x04 1. " MAC_2 ,MAC_2 disable" "No,Yes" bitfld.long 0x04 0. " MAC_1 ,MAC_1 disable" "No,Yes" line.long 0x08 "DEVDISR3,Device Disable 3 Register" bitfld.long 0x08 16. " AIOP ,AIOP disable" "No,Yes" newline bitfld.long 0x08 13. " MC ,MC disable" "No,Yes" bitfld.long 0x08 12. " QBMAN ,QBMAN disable" "No,Yes" newline bitfld.long 0x08 2. " PCIE3 ,PCIE3 disable" "No,Yes" bitfld.long 0x08 1. " PCIE2 ,PCIE2 disable" "No,Yes" newline bitfld.long 0x08 0. " PCIE1 ,PCIE1 disable" "No,Yes" line.long 0x0C "DEVDISR4,Device Disable 4 Register" bitfld.long 0x0C 9. " I2C4 ,I2C4 disable" "No,Yes" bitfld.long 0x0C 8. " I2C3 ,I2C3 disable" "No,Yes" bitfld.long 0x0C 5. " SPI ,SPI disable" "No,Yes" newline bitfld.long 0x0C 4. " QSPI ,QSPI disable" "No,Yes" bitfld.long 0x0C 3. " DUART2 ,DUART2 disable" "No,Yes" bitfld.long 0x0C 2. " DUART1 ,DUART1 disable" "No,Yes" newline bitfld.long 0x0C 1. " I2C2 ,I2C2 disable" "No,Yes" bitfld.long 0x0C 0. " I2C1 ,I2C1 disable" "No,Yes" line.long 0x10 "DEVDISR5,Device Disable 5 Register" bitfld.long 0x10 20. " PEBM ,PEBM disable" "No,Yes" bitfld.long 0x10 14. " FLEXTIMERS1_4 ,FlexTimers1_4 disable" "No,Yes" bitfld.long 0x10 13. " TMU ,TMU disable" "No,Yes" newline bitfld.long 0x10 12. " OCRAM ,OCRAM disable" "No,Yes" bitfld.long 0x10 10. " DBG ,DBG disable" "No,Yes" bitfld.long 0x10 9. " GPIO ,GPIO disable" "No,Yes" newline bitfld.long 0x10 8. " IFC ,IFC disable" "No,Yes" bitfld.long 0x10 0. " DDR1 ,DDR1 disable" "No,Yes" line.long 0x14 "DEVDISR6,Device Disable 6 Register" bitfld.long 0x14 0. " WRIOP ,WRIOP disable" "No,Yes" hgroup.long 0x88++0x03 hide.long 0x00 "DEVDISR7,Device Disable 7 Register" group.long 0x94++0x03 line.long 0x00 "COREDISR,Core Disable Register" bitfld.long 0x00 7. " CD7 ,Core 7 disable" "No,Yes" bitfld.long 0x00 6. " CD6 ,Core 6 disable" "No,Yes" newline bitfld.long 0x00 5. " CD5 ,Core 5 disable" "No,Yes" bitfld.long 0x00 4. " CD4 ,Core 4 disable" "No,Yes" newline bitfld.long 0x00 3. " CD3 ,Core 3 disable" "No,Yes" bitfld.long 0x00 2. " CD2 ,Core 2 disable" "No,Yes" newline bitfld.long 0x00 1. " CD1 ,Core 1 disable" "No,Yes" bitfld.long 0x00 0. " CD0 ,Core 0 disable" "No,Yes" hgroup.long 0xA0++0x03 hide.long 0x00 "PVR,Processor Version Register" rgroup.long 0xA4++0x03 line.long 0x00 "SVR,System Version Register" hexmask.long.byte 0x00 28.--31. 1. " MFR_ID ,Manufacturer ID" hexmask.long.byte 0x00 24.--27. 1. " FAMILY ,Family" newline hexmask.long.byte 0x00 16.--21. 1. " SOC_DEV_ID ,SoC device ID" hexmask.long.byte 0x00 8.--13. 1. " VAR_PER ,Various personalities" newline hexmask.long.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.long.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" newline width 15. rgroup.long 0x100++0x07 line.long 0x00 "RCWSR1,Reset Configuration Word Status Register 1" bitfld.long 0x00 26.--31. " CGA_PLL1_RAT ,Cluster group A PLL 1 multiplier/ratio" ",,,,,5:1,6:1,7:1,8:1,9:1,10:1,11:1,12:1,13:1,14:1,15:1,16:1,17:1,18:1,19:1,20:1,21:1,22:1,23:1,24:1,25:1,26:1,27:1,28:1,29:1,30:1,31:1,32:1,?..." newline bitfld.long 0x00 24.--25. " CGA_PLL1_CFG ,Cluster group A PLL 1 configuration" "All valid cluster group A PLL frequencies,?..." newline bitfld.long 0x00 10.--15. " MEM_PLL_RAT ,Memory controller complex PLL multiplier/ratio" ",,,,,,,,,,10:1,11:1,12:1,13:1,14:1,15:1,16:1,17:1,18:1,19:1,20:1,?..." newline bitfld.long 0x00 8.--9. " MEM_PLL_CFG ,Memory controller complex PLL configuration" "All valid DDR PLL frequencies,?..." newline bitfld.long 0x00 2.--6. " SYS_PLL_RAT ,System PLL multiplier/ratio" ",,,,4:1,,6:1,,8:1,,10:1,,12:1,,14:1,,16:1,,18:1,?..." newline bitfld.long 0x00 0.--1. " SYS_PLL_CFG ,System PLL configuration" "For all valid Platform PLL frequencies,?..." line.long 0x04 "RCWSR2,Reset Configuration Word Status Register 2" bitfld.long 0x04 2.--7. " CGA_PLL2_RAT ,Cluster group A PLL 2 multiplier/ratio" ",,,,,5:1,6:1,7:1,8:1,9:1,10:1,11:1,12:1,13:1,14:1,15:1,16:1,17:1,18:1,19:1,20:1,21:1,22:1,23:1,24:1,25:1,26:1,27:1,28:1,29:1,30:1,31:1,32:1,?..." newline bitfld.long 0x04 0.--1. " CGA_PLL2_CFG ,Cluster group A PLL 2 configuration" "All valid cluster group A PLL frequencies,?..." hgroup.long 0x108++0x03 hide.long 0x00 "RCWSR3,Reset Configuration Word Status Register 3" hgroup.long 0x10C++0x03 hide.long 0x00 "RCWSR4,Reset Configuration Word Status Register 4" rgroup.long 0x110++0x17 line.long 0x00 "RCWSR5,Reset Configuration Word Status Register 5" bitfld.long 0x00 20.--23. " C2_PLL_SEL ,Cluster 2 PLL select" "CGA_PLL1 /1,CGA_PLL1 /2,CGA_PLL1 /4,,CGA_PLL2 /1,CGA_PLL2 /2,CGA_PLL2 /4,,CGA_PLL3 / 1,CGA_PLL3 / 2,CGA_PLL3 / 4,?..." newline bitfld.long 0x00 16.--19. " C1_PLL_SEL ,Cluster 1 PLL select" "CGA_PLL1 /1,CGA_PLL1 /2,CGA_PLL1 /4,,CGA_PLL2 /1,CGA_PLL2 /2,CGA_PLL2 /4,,CGA_PLL3 / 1,CGA_PLL3 / 2,CGA_PLL3 / 4,?..." newline bitfld.long 0x00 5. " CGA_PLL2_SPD ,Cluster group A PLL 2 speed select" "High speed,Low speed" newline bitfld.long 0x00 4. " CGA_PLL1_SPD ,Cluster group A PLL 1 speed select" "High speed,Low speed" newline bitfld.long 0x00 1. " MEM_PLL_SPD ,Memory controller complex PLL speed select" "High speed,Low speed" newline bitfld.long 0x00 0. " SYS_PLL_SPD ,System PLL speed select" "High speed,Low speed" line.long 0x04 "RCWSR6,Reset Configuration Word Status Register 6" bitfld.long 0x04 19.--21. " HWA_CGA_M2_CLK_SEL ,Hardware accelerator block cluster group A mux 2 clock select" "Sync mode operation with respect to clock domain X,Async mode Cluster Group A PLL 2 /1 is clock,Async mode - Cluster Group A PLL 2 /2 is clock,Async mode - Cluster Group A PLL 2 /3 is clock,Async mode - Cluster Group A PLL 2 /4 is clock,Async mode - clock domain Y is clock,Async mode - Cluster Group A PLL 1 /2 is clock,Async mode - Cluster Group A PLL 1 /3 is clock" newline bitfld.long 0x04 16.--18. " HWA_CGA_M1_CLK_SEL ,Hardware accelerator block cluster group A mux 1 clock select" "Sync mode operation with respect to clock domain X,Async mode Cluster Group A PLL 2 /1 is clock,Async mode - Cluster Group A PLL 2 /2 is clock,Async mode - Cluster Group A PLL 2 /3 is clock,Async mode - Cluster Group A PLL 2 /4 is clock,Async mode - clock domain Y is clock,Async mode - Cluster Group A PLL 1 /2 is clock,Async mode - Cluster Group A PLL 1 /3 is clock" line.long 0x08 "RCWSR7,Reset Configuration Word Status Register 7" bitfld.long 0x08 23. " DDR_RATE ,DDR data rate" "0,1" newline bitfld.long 0x08 21.--22. " DRAM_LAT ,DDR latency" "Default,For typical unknown or higher latency DRAMs,,Only for lowest latency DRAMs" newline bitfld.long 0x08 19.--20. " DDR_REFCLK_SEL ,DDR reference clock selection" "DDRCLK,,System Clock,?..." line.long 0x0C "RCWSR8,Reset Configuration Word Status Register 8" bitfld.long 0x0C 5.--6. " REQD_CUST_CONFIG_230_229 ,Required customer configuration" "0,1,2,3" line.long 0x10 "RCWSR9,Reset Configuration Word Status Register 9" hexmask.long.word 0x10 20.--31. 1. " PBI_LENGTH ,Pre-Boot initialization length" newline hexmask.long.word 0x10 11.--19. 1. " FLASH_MODE ,Flash mode" newline bitfld.long 0x10 10. " SB_EN ,Secure boot enable" "Disabled,Enabled" newline bitfld.long 0x10 9. " BOOT_HO ,Boot holdoff" "All cores except core 0 in hold off,All cores in hold off" newline bitfld.long 0x10 4.--8. " BOOT_LOC ,Boot location" "PCIe1,PCIe2,PCIe3,PCIe4,,,,,,,,,,,,,,,,,Memory Complex,OCRAM,,,IFC,,Serial NOR,?..." line.long 0x14 "RCWSR10,Reset Configuration Word Status Register 10" bitfld.long 0x14 23. " GPIO_LED_EN ,GPIO LED enable" "Disabled,Enabled" newline hexmask.long.byte 0x14 16.--22. 1. " GPIO_LED_NUM ,GPIO LED number" newline hexmask.long.word 0x14 4.--13. 1. " SYSCLK_FREQ ,System clock frequency" newline bitfld.long 0x14 0. " SDBGEN ,Secure debug enable" "Disabled,Enabled" hgroup.long 0x128++0x03 hide.long 0x00 "RCWSR11,Reset Configuration Word Status Register 11" rgroup.long 0x12C++0x13 line.long 0x00 "RCWSR12,Reset Configuration Word Status Register 12" bitfld.long 0x00 24.--26. " IRQ_EXT ,IRQ3-11 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 21.--23. " IRQ2_EXT ,IRQ2 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " IRQ1_EXT ,IRQ1 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. " SDHC_EXT ,SDHC pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " SPI_EXT ,SPI pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " IIC4_EXT ,IIC4 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--8. " IIC3_EXT ,IIC3 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " IIC2_EXT ,IIC2 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " UART_EXT ,UART pin configuration" "0,UART1_SOUT/UART1_SIN,UART1_RTS_B/UART1_CTS_B,UART2_SOUT/UART2_SIN,UART2_RTS_B/UART2_CTS_B,?..." line.long 0x04 "RCWSR13,Reset Configuration Word Status Register 13" bitfld.long 0x04 24. " ASLEEP ,ASLEEP pin configuration" "0,1" newline bitfld.long 0x04 23. " RTC ,RTC pin configuration" "0,1" newline bitfld.long 0x04 22. " EVT_9 ,EVT_9 pin configuration" "0,1" newline bitfld.long 0x04 21. " IRQ03_BASE ,IRQ3 pin configuration" "0,1" newline bitfld.long 0x04 20. " IRQ04_BASE ,IRQ4 pin configuration" "0,1" newline bitfld.long 0x04 19. " IRQ05_BASE ,IRQ5 pin configuration" "0,1" newline bitfld.long 0x04 18. " IRQ06_BASE ,IRQ6 pin configuration" "0,1" newline bitfld.long 0x04 17. " IRQ07_BASE ,IRQ7 pin configuration" "0,1" newline bitfld.long 0x04 16. " IRQ08_BASE ,IRQ8 pin configuration" "0,1" newline bitfld.long 0x04 15. " IRQ09_BASE ,IRQ9 pin configuration" "0,1" newline bitfld.long 0x04 14. " IRQ10_BASE ,IRQ10 pin configuration" "0,1" newline bitfld.long 0x04 13. " IRQ11_BASE ,IRQ11 pin configuration" "0,1" newline bitfld.long 0x04 12. " SDHC_BASE ,SDHC pin configuration" "0,1" newline bitfld.long 0x04 10.--11. " SPI_PCS_BASE ,SPI_PCS pin configuration" "0,1,2,3" newline bitfld.long 0x04 8.--9. " SPI_BASE_BASE ,SPI pin configuration" "0,1,2,3" newline bitfld.long 0x04 6.--7. " IIC4_BASE ,IIC4 pin configuration" "0,1,2,3" newline bitfld.long 0x04 4.--5. " IIC3_BASE ,IIC3 pin configuration" "0,1,2,3" newline bitfld.long 0x04 2.--3. " IIC2_BASE ,IIC2 pin configuration" "0,1,2,3" newline bitfld.long 0x04 0.--1. " UART_BASE ,UART pin configuration" "0,UART1_RTS_B/UART1_CTS_B,UART2_SOUT/UART2_SIN,UART2_RTS_B/UART2_CTS_B" line.long 0x08 "RCWSR14,Reset Configuration Word Status Register 14" bitfld.long 0x08 24.--26. " IFC_GRP_I_EXT ,IFC_GRP_I_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 21.--23. " IFC_GRP_H_EXT ,IFC_GRP_H_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 18.--20. " IFC_GRP_G_EXT ,IFC_GRP_G_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 15.--17. " IFC_GRP_F_EXT ,IFC_GRP_F_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. " IFC_GRP_E_EXT ,IFC_GRP_E_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 9.--11. " IFC_GRP_D_EXT ,IFC_GRP_D_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 6.--8. " IFC_GRP_C_EXT ,IFC_GRP_C_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 3.--5. " IFC_GRP_B_EXT ,IFC_GRP_B_EXT pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--2. " IFC_GRP_A_EXT ,IFC_GRP_A_EXT pin configuration" "0,1,2,3,4,5,6,7" line.long 0x0C "RCWSR15,Reset Configuration Word Status Register 15" bitfld.long 0x0C 13. " QSPI_OCT_EN ,QSPI pin configuration" "0,1" newline bitfld.long 0x0C 12. " IFC_A_8_6 ,IFC_A_8_6 pin configuration" "0,1" newline bitfld.long 0x0C 10.--11. " IFC_GRP_FGHI_BASE ,IFC_GRP_FGHI_BASE pin configuration" "0,1,2,3" newline bitfld.long 0x0C 8.--9. " IFC_GRP_E_BASE ,IFC_GRP_E_BASE pin configuration" "0,1,2,3" newline bitfld.long 0x0C 6.--7. " IFC_GRP_D_BASE ,IFC_GRP_D_BASE pin configuration" "0,1,2,3" newline bitfld.long 0x0C 4. " IFC_GRP_C_BASE ,IFC_GRP_C_BASE pin configuration" "0,1" newline bitfld.long 0x0C 2.--3. " IFC_GRP_B_BASE ,IFC_GRP_B_BASE pin configuration" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " IFC_GRP_A_BASE ,IFC_GRP_A_BASE pin configuration" "0,1,2,3" line.long 0x10 "RCWSR16,Reset Configuration Word Status Register 16" bitfld.long 0x10 7. " HOST_AGT_PEX3 ,Host/Agent PEX3" "Host,Agent" newline bitfld.long 0x10 6. " HOST_AGT_PEX2 ,Host/Agent PEX2" "Host,Agent" newline bitfld.long 0x10 5. " HOST_AGT_PEX1 ,Host/Agent PEX1" "Host,Agent" hgroup.long 0x140++0x03 hide.long 0x00 "RCWSR17,Reset Configuration Word Status Register 17" hgroup.long 0x144++0x03 hide.long 0x00 "RCWSR18,Reset Configuration Word Status Register 18" hgroup.long 0x148++0x03 hide.long 0x00 "RCWSR19,Reset Configuration Word Status Register 19" hgroup.long 0x14C++0x03 hide.long 0x00 "RCWSR20,Reset Configuration Word Status Register 20" hgroup.long 0x150++0x03 hide.long 0x00 "RCWSR21,Reset Configuration Word Status Register 21" hgroup.long 0x154++0x03 hide.long 0x00 "RCWSR22,Reset Configuration Word Status Register 22" hgroup.long 0x158++0x03 hide.long 0x00 "RCWSR23,Reset Configuration Word Status Register 23" hgroup.long 0x15C++0x03 hide.long 0x00 "RCWSR24,Reset Configuration Word Status Register 24" rgroup.long 0x160++0x03 line.long 0x00 "RCWSR25,Reset Configuration Word Status Register 25" hgroup.long 0x164++0x03 hide.long 0x00 "RCWSR26,Reset Configuration Word Status Register 26" rgroup.long 0x168++0x0F line.long 0x00 "RCWSR27,Reset Configuration Word Status Register 27" bitfld.long 0x00 28.--29. " USB2_REFCLK_SEL ,B2 reference clock select" "0,1,2,3" newline bitfld.long 0x00 26.--27. " USB1_REFCLK_SEL ,USB1 reference clock select" "0,1,2,3" newline bitfld.long 0x00 24.--25. " USB ,USB pin configuration" "0,1,2,3" newline bitfld.long 0x00 7. " EM2 ,EM2 pin configuration" "0,1" newline bitfld.long 0x00 6. " EM1 ,EM1 pin configuration" "0,1" newline bitfld.long 0x00 3.--5. " EC2 ,EC2 pin configuration" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " EC1 ,EC1 pin configuration" "0,1,2,3,4,5,6,7" line.long 0x04 "RCWSR28,Reset Configuration Word Status Register 28" bitfld.long 0x04 6.--11. " USB2_CLK_FSEL ,USB2 PHY reference clock frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 0.--5. " USB1_CLK_FSEL ,USB1 PHY reference clock frequency select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "RCWSR29,Reset Configuration Word Status Register 29" bitfld.long 0x08 28.--31. " SRDS_PRTCL_S1_LN3 ,SerDes protocol select - SerDes 1 Lane3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 24.--27. " SRDS_PRTCL_S1_LN2 ,SerDes protocol select - SerDes 1 Lane2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 20.--23. " SRDS_PRTCL_S1_LN1 ,SerDes protocol select - SerDes 1 Lane1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. " SRDS_PRTCL_S1_LN0 ,SerDes protocol select - SerDes 1 Lane0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 3. " SRDS_PLL_PD_PLL4 ,SerDes PLL 4 power down" "Powered up,Powered down" newline bitfld.long 0x08 2. " SRDS_PLL_PD_PLL3 ,SerDes PLL 3 power down" "Powered up,Powered down" newline bitfld.long 0x08 1. " SRDS_PLL_PD_PLL2 ,SerDes PLL 2 power down" "Powered up,Powered down" newline bitfld.long 0x08 0. " SRDS_PLL_PD_PLL1 ,SerDes PLL 1 power down" "Powered up,Powered down" line.long 0x0C "RCWSR30,Reset Configuration Word Status Register 30" bitfld.long 0x0C 26.--27. " SRDS_S2_REFCLK_SRC_SEL ,SERDES2 PLL1/2 reference clock source select" "0,1,2,3" newline bitfld.long 0x0C 24.--25. " SRDS_S1_REFCLK_SRC_SEL ,SERDES1 PLL1/2 reference clock source select" "0,1,2,3" newline bitfld.long 0x0C 22.--23. " SRDS_DIV_PEX_S2 ,SerDes frequency divider - SerDes 2" "0,1,2,3" newline bitfld.long 0x0C 20.--21. " SRDS_DIV_PEX_S1 ,SerDes frequency divider - SerDes 1" "0,1,2,3" newline bitfld.long 0x0C 18.--19. " SRDS_PLL_REF_CLK_SEL_S2 ,SerDes PLL reference clock select - SerDes 2" "0,1,2,3" newline bitfld.long 0x0C 16.--17. " SRDS_PLL_REF_CLK_SEL_S1 ,SerDes PLL reference clock select - SerDes 1" "0,1,2,3" newline bitfld.long 0x0C 12.--15. " SRDS_PRTCL_S2_LN3 ,SRDS_PRTCL_S2_LN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 8.--11. " SRDS_PRTCL_S2_LN2 ,SRDS_PRTCL_S2_LN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 4.--7. " SRDS_PRTCL_S2_LN1 ,SRDS_PRTCL_S2_LN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " SRDS_PRTCL_S2_LN0 ,SRDS_PRTCL_S2_LN0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x178++0x03 hide.long 0x00 "RCWSR31,Reset Configuration Word Status Register 31" hgroup.long 0x17C++0x03 hide.long 0x00 "RCWSR32,Reset Configuration Word Status Register 32" newline group.long 0x200++0x03 line.long 0x00 "SCRATCHRW1-32,Scratch Read / Write Register" button "VAL" "d ad ($1+0x04)--($1+0x27C) /long" group.long 0x300++0x03 line.long 0x00 "SCRATCHW1R1-4,Scratch Read Register" button "VAL" "d ad ($1+0x04)--($1+0x30C) /long" newline width 15. group.long 0x400++0x07 line.long 0x00 "BOOTLOCPTRL,Boot Location Pointer Low-Order Address Register" line.long 0x04 "BOOTLOCPTRH,Boot Location Pointer High-Order Address Register" group.long 0x520++0x07 line.long 0x00 "USB1_AMQR,USB1_AMQR" bitfld.long 0x00 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x00 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x00 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x00 0.--6. 1. " ICID ,Isolation Context" line.long 0x04 "USB2_AMQR,USB2_AMQR" bitfld.long 0x04 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x04 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x04 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x04 0.--6. 1. " ICID ,Isolation Context" group.long 0x530++0x03 line.long 0x00 "SDMM1_AMQR,SD/MMC Access Management Qualifier Register" bitfld.long 0x00 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x00 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x00 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x00 0.--6. 1. " ICID ,Isolation Context" group.long 0x550++0x03 line.long 0x00 "SATA1_AMQR,SATA 1 Access Management Qualifier Register" bitfld.long 0x00 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x00 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x00 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x00 0.--6. 1. " ICID ,Isolation Context" group.long 0x570++0x0B line.long 0x00 "MISC1_AMQR,MISC 1 Access Management Qualifier Register" bitfld.long 0x00 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x00 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x00 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x00 0.--6. 1. " ICID ,Isolation Context" line.long 0x04 "MISC1_AMQR,MISC 1 Access Management Qualifier Register" bitfld.long 0x04 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x04 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x04 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x04 0.--6. 1. " ICID ,Isolation Context" line.long 0x08 "MISC3_AMQR,MISC 3 Access Management Qualifier Register" bitfld.long 0x08 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x08 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x08 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x08 0.--6. 1. " ICID ,Isolation Context" group.long 0x590++0x07 line.long 0x00 "SPARE1_AMQR,SPARE 1 Access Management Qualifier Register" bitfld.long 0x00 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x00 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x00 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x00 0.--6. 1. " ICID ,Isolation Context" line.long 0x04 "SPARE2_AMQR,SPARE 2 Access Management Qualifier Register" bitfld.long 0x04 18. " PL ,PL (Privileged Level) bit" "Incorrect,Correct" bitfld.long 0x04 17. " BMT ,BMT (Bypass Memory Translation) bit" "Not bypassed,Bypassed" bitfld.long 0x04 16. " VA ,VA (Virtual Address) bit" "Physical,Virtual" newline hexmask.long.byte 0x04 0.--6. 1. " ICID ,Isolation Context" newline hgroup.long 0x600++0x03 hide.long 0x00 "DMACR1,DMA Control Register" hgroup.long 0x604++0x03 hide.long 0x00 "DMACR1,DMA Control Register" group.long 0x620++0x1B line.long 0x00 "GENCR1,General Control Register" bitfld.long 0x00 31. " SYSBARDISABLE ,A57 input configuration signal" "0,1" bitfld.long 0x00 29. " BROADCASTCACHEMAINT ,BROADCASTCACHEMAINT" "0,1" hexmask.long.byte 0x00 0.--28. 1. " GEN ,Gen" line.long 0x04 "GENCR2,General Control Register" line.long 0x08 "GENCR3,General Control Register" line.long 0x0C "GENCR4,General Control Register" line.long 0x10 "GENCR5,General Control Register" line.long 0x14 "GENCR6,General Control Register" line.long 0x18 "GENCR7,General Control Register" hgroup.long 0x640++0x03 hide.long 0x00 "CGENSR1,Core General Status" hgroup.long 0x660++0x03 hide.long 0x00 "CGENCR1,Core General Control" hgroup.long 0x700++0x03 hide.long 0x00 "SRIOPSTECR,SRIO Prescaler Timer Enable Control Register" rgroup.long 0x740++0x03 line.long 0x00 "TP_ITYP0,Topology Initiator Type Register 0" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x744++0x03 line.long 0x00 "TP_ITYP1,Topology Initiator Type Register 1" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x748++0x03 line.long 0x00 "TP_ITYP2,Topology Initiator Type Register 2" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x74C++0x03 line.long 0x00 "TP_ITYP3,Topology Initiator Type Register 3" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x750++0x03 line.long 0x00 "TP_ITYP4,Topology Initiator Type Register 4" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x754++0x03 line.long 0x00 "TP_ITYP5,Topology Initiator Type Register 5" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Identifies the type of initiator for this index" rgroup.long 0x844++0x03 line.long 0x00 "TP_CLUSTER1L,Core Cluster 1 Topology Register" bitfld.long 0x00 30.--31. " EOC ,End of clusters" "Not last,Last,Last,Last" bitfld.long 0x00 24.--29. " IT_IDX_PC4 ,Initiator type index for this cluster's fourth initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. " IT_IDX_PC3 ,Initiator type index for this cluster third initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " IT_IDX_PC2 ,Initiator type index for this cluster second initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " IT_IDX_PC1 ,Initiator type index for this cluster first initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x84C++0x03 line.long 0x00 "TP_CLUSTER2L,Core Cluster 2 Topology Register" bitfld.long 0x00 30.--31. " EOC ,End of clusters" "Not last,Last,Last,Last" bitfld.long 0x00 24.--29. " IT_IDX_PC4 ,Initiator type index for this cluster's fourth initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. " IT_IDX_PC3 ,Initiator type index for this cluster third initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " IT_IDX_PC2 ,Initiator type index for this cluster second initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " IT_IDX_PC1 ,Initiator type index for this cluster first initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x900++0x03 line.long 0x00 "QSPICR1,QSPI Control Register 1" bitfld.long 0x00 0.--5. " QSPI_CLK_DIV ,QSPI clock divisor" ",,/8,/12,/16,/20,/24,/28,/32,,,,,,,,,,,,/80,?..." group.long 0x904++0x03 line.long 0x00 "QSPICR1,QSPI Control Register 2" bitfld.long 0x00 0.--5. " QSPI_CLK_DIV ,QSPI clock divisor" ",,/8,/12,/16,/20,/24,/28,/32,,,,,,,,,,,,/80,?..." group.long 0x908++0x03 line.long 0x00 "QSPICR1,QSPI Control Register 3" bitfld.long 0x00 0.--5. " QSPI_CLK_DIV ,QSPI clock divisor" ",,/8,/12,/16,/20,/24,/28,/32,,,,,,,,,,,,/80,?..." group.long 0x90C++0x03 line.long 0x00 "QSPICR1,QSPI Control Register 4" bitfld.long 0x00 0.--5. " QSPI_CLK_DIV ,QSPI clock divisor" ",,/8,/12,/16,/20,/24,/28,/32,,,,,,,,,,,,/80,?..." group.long 0x920++0x03 line.long 0x00 "IOQOSCR1,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x924++0x03 line.long 0x00 "IOQOSCR2,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x928++0x03 line.long 0x00 "IOQOSCR3,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x92C++0x03 line.long 0x00 "IOQOSCR4,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x930++0x03 line.long 0x00 "IOQOSCR5,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x934++0x03 line.long 0x00 "IOQOSCR6,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x938++0x03 line.long 0x00 "IOQOSCR7,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x93C++0x03 line.long 0x00 "IOQOSCR8,I/O Quality of Services Register" bitfld.long 0x00 16.--19. " QOS3 ,Quality of service 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " QOS2 ,Quality of service 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " QOS1 ,Quality of service 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x940++0x03 hide.long 0x00 "UCCR,UART Connectivity Control Register" group.long 0x960++0x03 line.long 0x00 "FTMCR,FlexTimer Control Register" bitfld.long 0x00 6. " CASC08_07 ,Cascade flex timer 8 to flex timer 7" "Not cascaded,Cascaded" bitfld.long 0x00 5. " CASC07_06 ,Cascade flex timer 7 to flex timer 6" "Not cascaded,Cascaded" newline bitfld.long 0x00 4. " CASC06_05 ,Cascade flex timer 6 to flex timer 5" "Not cascaded,Cascaded" bitfld.long 0x00 3. " CASC05_04 ,Cascade flex timer 5 to flex timer 4" "Not cascaded,Cascaded" newline bitfld.long 0x00 2. " CASC04_03 ,Cascade flex timer 4 to flex timer 3" "Not cascaded,Cascaded" bitfld.long 0x00 1. " CASC03_02 ,Cascade flex timer 3 to flex timer 2" "Not cascaded,Cascaded" newline bitfld.long 0x00 0. " CASC02_01 ,Cascade flex timer 2 to flex timer 1" "Not cascaded,Cascaded" rgroup.long 0x990++0x03 line.long 0x00 "COREDISABLESR,Core Disable Status Register" bitfld.long 0x00 7. " CD7 ,Core 7 disable" "No,Yes" bitfld.long 0x00 6. " CD6 ,Core 6 disable" "No,Yes" newline bitfld.long 0x00 5. " CD5 ,Core 5 disable" "No,Yes" bitfld.long 0x00 4. " CD4 ,Core 4 disable" "No,Yes" newline bitfld.long 0x00 3. " CD3 ,Core 3 disable" "No,Yes" bitfld.long 0x00 2. " CD2 ,Core 2 disable" "No,Yes" newline bitfld.long 0x00 1. " CD1 ,Core 1 disable" "No,Yes" bitfld.long 0x00 0. " CD0 ,Core 0 disable" "No,Yes" group.long 0xA00++0x03 line.long 0x00 "SDBGCR,Secure Debug Configuration Register" bitfld.long 0x00 0. " SDBG_NS ,Secure debug - TZ not secure" "Secure,Not secure" rgroup.long 0xBF8++0x07 line.long 0x00 "IPBRR1,IP Block Revision 1 Register" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" newline hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "IPBRR2,IP Block Revision 2 Register" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,IP block integration options" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,IP block configuration options" newline base ad:0x01FF8000 width 23. group.long 0x00++0x33 "Pin Control Analog Register Descriptions" line.long 0x00 "SLEWRATE_ANA_CNTRL1,Slewrate Analog Control 1" bitfld.long 0x00 30.--31. " SLEWRATE_SDHC_DAT3 ,Slewrate control for sdhc_dat3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 28.--29. " SLEWRATE_SDHC_DAT2 ,Slewrate control for sdhc_dat2" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 26.--27. " SLEWRATE_SDHC_DAT1 ,Slewrate control for sdhc_dat1" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 24.--25. " SLEWRATE_SDHC_DAT0 ,Slewrate control for sdhc_dat0" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 22.--23. " SLEWRATE_IIC2_SDA ,Slewrate control for iic2_sda" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 20.--21. " SLEWRATE_IIC2_SCL ,Slewrate control for iic2_scl" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 18.--19. " SLEWRATE_IIC1_SDA ,Slewrate control for iic1_sda" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 16.--17. " SLEWRATE_IIC1_SCL ,Slewrate control for iic1_scl" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 14.--15. " SLEWRATE_UART2_CTS_B ,Slewrate control for uart2_cts_b" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 12.--13. " SLEWRATE_UART1_CTS_B ,Slewrate control for uart1_cts_b" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 10.--11. " SLEWRATE_UART2_RTS_B ,Slewrate control for uart2_rts_b" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 8.--9. " SLEWRATE_UART1_RTS_B ,Slewrate control for uart1_rts_b" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 6.--7. " SLEWRATE_UART2_SIN ,Slewrate control for uart2_sin" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 4.--5. " SLEWRATE_UART1_SIN ,Slewrate control for uart1_sin" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x00 2.--3. " SLEWRATE_UART2_SOUT ,Slewrate control for uart2_sout" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x00 0.--1. " SLEWRATE_UART1_SOUT ,Slewrate control for uart1_sout" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" line.long 0x04 "SLEWRATE_ANA_CNTRL2,Slewrate Analog Control 2" bitfld.long 0x04 30.--31. " SLEWRATE_IRQ11 ,Slewrate control for irq11" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x04 28.--29. " SLEWRATE_IRQ10 ,Slewrate control for irq10" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x04 26.--27. " SLEWRATE_IRQ9 ,Slewrate control for irq9" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x04 24.--25. " SLEWRATE_IRQ8 ,Slewrate control for irq8" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x04 22.--23. " SLEWRATE_IRQ7 ,Slewrate control for irq7" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x04 20.--21. " SLEWRATE_IRQ6 ,Slewrate control for irq6" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x04 18.--19. " SLEWRATE_IRQ5 ,Slewrate control for irq5" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x04 16.--17. " SLEWRATE_IRQ4 ,Slewrate control for irq4" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x04 14.--15. " SLEWRATE_IRQ3 ,Slewrate control for irq3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x04 2.--3. " SLEWRATE_SDHC_CLK ,Slewrate control for sdhc_clk" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x04 0.--1. " SLEWRATE_SDHC_CMD ,Slewrate control for sdhc_cmd" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" line.long 0x08 "SLEWRATE_ANA_CNTRL3,Slewrate Analog Control 3" bitfld.long 0x08 14.--15. " SLEWRATE_USB_PWRFAULT ,Slewrate control for usb_pwrfault" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x08 12.--13. " SLEWRATE_USB_DRVVBUS ,Slewrate control for usb_drvvbus" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x08 10.--11. " SLEWRATE_IIC4_SDA ,Slewrate control for iic4_sda" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x08 8.--9. " SLEWRATE_IIC4_SCL ,Slewrate control for iic4_scl" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x08 6.--7. " SLEWRATE_IIC3_SDA ,Slewrate control for iic3_sda" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x08 4.--5. " SLEWRATE_IIC3_SCL ,Slewrate control for iic3_scl" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x08 2.--3. " SLEWRATE_EMI_MDIO ,Slewrate control for emi_mdio" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x08 0.--1. " SLEWRATE_EMI_MDC ,Slewrate control for emi_mdc" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" line.long 0x0C "SLEWRATE_ANA_CNTRL4,Slewrate Analog Control 4" bitfld.long 0x0C 24.--25. " SLEWRATE_EC1_RX_DV ,Slewrate control for ec1_rx_dv" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 22.--23. " SLEWRATE_EC1_RX_CLK ,Slewrate control for ec1_rx_clk" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 20.--21. " SLEWRATE_EC1_RXD3 ,Slewrate control for ec1_rxd3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 18.--19. " SLEWRATE_EC1_RXD2 ,Slewrate control for ec1_rxd2" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 16.--17. " SLEWRATE_EC1_RXD1 ,Slewrate control for ec1_rxd1" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 14.--15. " SLEWRATE_EC1_RXD0 ,Slewrate control for ec1_rxd0" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 12.--13. " SLEWRATE_EC1_GTX_CLK125 ,Slewrate control for ec1_gtx_clk125" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 10.--11. " SLEWRATE_EC1_GTX_CLK ,Slewrate control for ec1_gtx_clk" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 8.--9. " SLEWRATE_EC1_TX_EN ,Slewrate control for ec1_tx_en" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 6.--7. " SLEWRATE_EC1_TXD3 ,Slewrate control for ec1_txd3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 4.--5. " SLEWRATE_EC1_TXD2 ,Slewrate control for ec1_txd2" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x0C 2.--3. " SLEWRATE_EC1_TXD1 ,Slewrate control for ec1_txd1" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x0C 0.--1. " SLEWRATE_EC1_TXD0 ,Slewrate control for ec1_txd0" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" line.long 0x10 "SLEWRATE_ANA_CNTRL5,Slewrate Analog Control 5" bitfld.long 0x10 24.--25. " SLEWRATE_EC1_RX_DV ,Slewrate control for ec1_rx_dv" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 22.--23. " SLEWRATE_EC2_RX_CLK ,Slewrate control for ec2_rx_clk" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 20.--21. " SLEWRATE_EC2_RXD3 ,Slewrate control for ec2_rxd3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 18.--19. " SLEWRATE_EC2_RXD2 ,Slewrate control for ec2_rxd2" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 16.--17. " SLEWRATE_EC2_RXD1 ,Slewrate control for ec2_rxd1" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 14.--15. " SLEWRATE_EC2_RXD0 ,Slewrate control for ec2_rxd0" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 12.--13. " SLEWRATE_EC2_GTX_CLK125 ,Slewrate control for ec2_gtx_clk125" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 10.--11. " SLEWRATE_EC2_GTX_CLK ,Slewrate control for ec2_gtx_clk" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 8.--9. " SLEWRATE_EC2_TX_EN ,Slewrate control for ec2_tx_en" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 6.--7. " SLEWRATE_EC2_TXD3 ,Slewrate control for ec2_txd3" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 4.--5. " SLEWRATE_EC2_TXD2 ,Slewrate control for ec2_txd2" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" bitfld.long 0x10 2.--3. " SLEWRATE_EC2_TXD1 ,Slewrate control for ec2_txd1" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" newline bitfld.long 0x10 0.--1. " SLEWRATE_EC2_TXD0 ,Slewrate control for ec2_txd0" "Slow slew rate,Medium slew rate,Fast slew rate,Max slew rate" line.long 0x14 "HYST_ANA_CNTRL1,Hyst Analog Control Register 1" bitfld.long 0x14 31. " HYST_IRQ11 ,Hysteresis control for irq11" "CMOS input,Schmitt trigger input" bitfld.long 0x14 30. " HYST_IRQ10 ,Hysteresis control for irq10" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 29. " HYST_IRQ9 ,Hysteresis control for irq9" "CMOS input,Schmitt trigger input" bitfld.long 0x14 28. " HYST_IRQ8 ,Hysteresis control for irq8" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 27. " HYST_IRQ7 ,Hysteresis control for irq7" "CMOS input,Schmitt trigger input" bitfld.long 0x14 26. " HYST_IRQ6 ,Hysteresis control for irq6" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 25. " HYST_IRQ5 ,Hysteresis control for irq5" "CMOS input,Schmitt trigger input" bitfld.long 0x14 24. " HYST_IRQ4 ,Hysteresis control for irq4" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 23. " HYST_IRQ3 ,Hysteresis control for irq3" "CMOS input,Schmitt trigger input" bitfld.long 0x14 17. " HYST_SDHC_CLK ,Hysteresis control for sdhc_clk" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 16. " HYST_SDHC_DAT3 ,Hysteresis control for sdhc_dat3" "CMOS input,Schmitt trigger input" bitfld.long 0x14 15. " HYST_SDHC_DAT2 ,Hysteresis control for sdhc_dat2" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 14. " HYST_SDHC_DAT1 ,Hysteresis control for sdhc_dat1" "CMOS input,Schmitt trigger input" bitfld.long 0x14 13. " HYST_SDHC_DAT0 ,Hysteresis control for sdhc_dat0" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 12. " HYST_SDHC_CMD ,Hysteresis control for sdhc_cmd" "CMOS input,Schmitt trigger input" bitfld.long 0x14 11. " HYST_IIC2_SDA ,Hysteresis control for iic2_sda" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 10. " HYST_IIC2_SCL ,Hysteresis control for iic2_scl" "CMOS input,Schmitt trigger input" bitfld.long 0x14 9. " HYST_IIC1_SDA ,Hysteresis control for iic1_sda" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 8. " HYST_IIC1_SCL ,Hysteresis control for iic1_scl" "CMOS input,Schmitt trigger input" bitfld.long 0x14 7. " HYST_UART2_CTS_B ,Hysteresis control for uart2_cts_b" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 6. " HYST_UART1_CTS_B ,Hysteresis control for uart1_cts_b" "CMOS input,Schmitt trigger input" bitfld.long 0x14 5. " HYST_UART2_RTS_B ,Hysteresis control for uart2_rts_b" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 4. " HYST_UART1_RTS_B ,Hysteresis control for uart1_rts_b" "CMOS input,Schmitt trigger input" bitfld.long 0x14 3. " HYST_UART2_SIN ,Hysteresis control for uart2_sin" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 2. " HYST_UART1_SIN ,Hysteresis control for uart1_sin" "CMOS input,Schmitt trigger input" bitfld.long 0x14 1. " HYST_UART2_SOUT ,Hysteresis control for uart2_sout" "CMOS input,Schmitt trigger input" newline bitfld.long 0x14 0. " HYST_UART1_SOUT ,Hysteresis control for uart1_sout" "CMOS input,Schmitt trigger input" line.long 0x18 "HYST_ANA_CNTRL2,Hyst Analog Control Register 2" bitfld.long 0x18 7. " HYST_USB_PWRFAULT ,Hysteresis control for usb_pwrfault" "CMOS input,Schmitt trigger input" bitfld.long 0x18 6. " HYST_USB_DRVVBUS ,Hysteresis control for usb_drvvbus" "CMOS input,Schmitt trigger input" newline bitfld.long 0x18 5. " HYST_IIC4_SDA ,Hysteresis control for iic4_sda" "CMOS input,Schmitt trigger input" bitfld.long 0x18 4. " HYST_IIC4_SCL ,Hysteresis control for iic4_scl" "CMOS input,Schmitt trigger input" newline bitfld.long 0x18 3. " HYST_IIC3_SDA ,Hysteresis control for iic3_sda" "CMOS input,Schmitt trigger input" bitfld.long 0x18 2. " HYST_IIC3_SCL ,Hysteresis control for iic34_scl" "CMOS input,Schmitt trigger input" newline bitfld.long 0x18 1. " HYST_EMI_MDIO ,Hysteresis control for emi_mdio" "CMOS input,Schmitt trigger input" bitfld.long 0x18 0. " HYST_EMI_MDC ,Hysteresis control for emi_mdc" "CMOS input,Schmitt trigger input" line.long 0x1C "HYST_ANA_CNTRL3,Hyst Analog Control Register 3" bitfld.long 0x1C 25. " HYST_EC2_RX_DV ,Hysteresis control for ec2_rx_dv" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 24. " HYST_EC2_RX_CLK ,Hysteresis control for ec2_rx_clk" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 23. " HYST_EC2_RXD3 ,Hysteresis control for ec2_rxd3" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 22. " HYST_EC2_RXD2 ,Hysteresis control for ec2_rxd2" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 21. " HYST_EC2_RXD1 ,Hysteresis control for ec2_rxd1" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 20. " HYST_EC2_RXD0 ,Hysteresis control for ec2_rxd0" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 19. " HYST_EC2_GTX_CLK125 ,Hysteresis control for ec2_gtx_clk125" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 18. " HYST_EC2_GTX_CLK ,Hysteresis control for ec2_gtx_clk" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 17. " HYST_EC2_TX_EN ,Hysteresis control for ec2_tx_en" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 16. " HYST_EC2_TXD3 ,Hysteresis control for ec2_txd3" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 15. " HYST_EC2_TXD2 ,Hysteresis control for ec2_txd2" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 14. " HYST_EC2_TXD1 ,Hysteresis control for ec2_txd1" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 13. " HYST_EC2_TXD0 ,Hysteresis control for ec2_txd0" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 12. " HYST_EC1_RX_DV ,Hysteresis control for ec1_rx_dv" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 11. " HYST_EC1_RX_CLK ,Hysteresis control for ec1_rx_clk" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 10. " HYST_EC1_RXD3 ,Hysteresis control for ec1_rxd3" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 9. " HYST_EC1_RXD2 ,Hysteresis control for ec1_rxd2" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 8. " HYST_EC1_RXD1 ,Hysteresis control for ec1_rxd1" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 7. " HYST_EC1_RXD0 ,Hysteresis control for ec1_rxd0" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 6. " HYST_EC1_GTX_CLK125 ,Hysteresis control for ec1_gtx_clk125" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 5. " HYST_EC1_GTX_CLK ,Hysteresis control for ec1_gtx_clk" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 4. " HYST_EC1_TX_EN ,Hysteresis control for ec1_tx_en" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 3. " HYST_EC1_TXD3 ,Hysteresis control for ec1_txd3" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 2. " HYST_EC1_TXD2 ,Hysteresis control for ec1_txd2" "CMOS input,Schmitt trigger input" newline bitfld.long 0x1C 1. " HYST_EC1_TXD1 ,Hysteresis control for ec1_txd1" "CMOS input,Schmitt trigger input" bitfld.long 0x1C 0. " HYST_EC1_TXD0 ,Hysteresis control for ec1_txd0" "CMOS input,Schmitt trigger input" line.long 0x20 "DRV_STRGTH_ANA_CNTRL1,Drive Strength Analog Control Register 1" bitfld.long 0x20 15.--17. " DSE_GRP_F ,Drive strength enable group F" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" bitfld.long 0x20 12.--14. " DSE_GRP_E ,Drive strength enable group E" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" bitfld.long 0x20 9.--11. " DSE_GRP_D ,Drive strength enable group D" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" newline bitfld.long 0x20 6.--8. " DSE_GRP_C ,Drive strength enable group C" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" bitfld.long 0x20 3.--5. " DSE_GRP_B ,Drive strength enable group B" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" bitfld.long 0x20 0.--2. " DSE_GRP_A ,Drive strength enable group A" "Disabled,240 Ohm,120 Ohm,80 Ohm,60 Ohm,48 Ohm,40 Ohm,34 Ohm (max drive strength)" line.long 0x24 "LVTTL_ANA_CNTRL1,LVTTL Analog Control Register 1" bitfld.long 0x24 31. " LVTTL_IRQ11 ,LVTTL control for irq11" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 30. " LVTTL_IRQ10 ,LVTTL control for irq10" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 29. " LVTTL_IRQ9 ,LVTTL control for irq9" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 28. " LVTTL_IRQ8 ,LVTTL control for irq8" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 27. " LVTTL_IRQ7 ,LVTTL control for irq7" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 26. " LVTTL_IRQ6 ,LVTTL control for irq6" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 25. " LVTTL_IRQ5 ,LVTTL control for irq5" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 24. " LVTTL_IRQ4 ,LVTTL control for irq4" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 23. " LVTTL_IRQ3 ,LVTTL control for irq3" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 22. " LVTTL_IRQ2 ,LVTTL control for irq2" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 17. " LVTTL_SDHC_CLK ,LVTTL control for sdhc_clk" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 16. " LVTTL_SDHC_DAT3 ,LVTTL control for sdhc_dat3" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 15. " LVTTL_SDHC_DAT2 ,LVTTL control for sdhc_dat2" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 14. " LVTTL_SDHC_DAT1 ,LVTTL control for sdhc_dat1" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 13. " LVTTL_SDHC_DAT0 ,LVTTL control for sdhc_dat0" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 12. " LVTTL_SDHC_CMD ,LVTTL control for sdhc_cmd" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 11. " LVTTL_IIC2_SDA ,LVTTL control for iic2_sda" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 10. " LVTTL_IIC2_SCL ,LVTTL control for iic2_scl" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 9. " LVTTL_IIC1_SDA ,LVTTL control for iic1_sda" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 8. " LVTTL_IIC1_SCL ,LVTTL control for iic1_scl" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 7. " LVTTL_UART2_CTS_B ,LVTTL control for uart2_cts_b" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 6. " LVTTL_UART1_CTS_B ,LVTTL control for uart1_cts_b" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 5. " LVTTL_UART2_RTS_B ,LVTTL control for uart2_rts_b" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 4. " LVTTL_UART1_RTS_B ,LVTTL control for uart1_rts_b" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 3. " LVTTL_UART2_SIN ,LVTTL control for uart2_sin" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 2. " LVTTL_UART1_SIN ,LVTTL control for uart1_sin" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x24 1. " LVTTL_UART2_SOUT ,LVTTL control for uart2_sout" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x24 0. " LVTTL_UART1_SOUT ,LVTTL control for uart1_sout" "LVCMOS input levels,LVTTL input levels" line.long 0x28 "LVTTL_ANA_CNTRL2,LVTTL Analog Control Register 2" bitfld.long 0x28 7. " LVTTL_USB_PWRFAULT ,LVTTL control for usb_pwrfault" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x28 6. " LVTTL_USB_DRVVBUS ,LVTTL control for usb_drvvbus" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x28 5. " LVTTL_IIC4_SDA ,LVTTL control for iic4_sda" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x28 4. " LVTTL_IIC4_SCL ,LVTTL control for iic4_scl" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x28 3. " LVTTL_IIC3_SDA ,LVTTL control for iic3_sda" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x28 2. " LVTTL_IIC3_SCL ,LVTTL control for iic3_scl" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x28 1. " LVTTL_EMI_MDIO ,LVTTL control for emi_mdio" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x28 0. " LVTTL_EMI_MDC ,LVTTL control for emi_mdc" "LVCMOS input levels,LVTTL input levels" line.long 0x2C "LVTTL_ANA_CNTRL3,LVTTL Analog Control Register 3" bitfld.long 0x2C 25. " LVTTL_EC2_RX_DV ,LVTTL control for ec2_rx_dv" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 24. " LVTTL_EC2_RX_CLK ,LVTTL control for ec2_rx_clk" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 23. " LVTTL_EC2_RXD3 ,LVTTL control for ec2_rxd3" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 22. " LVTTL_EC2_RXD2 ,LVTTL control for ec2_rxd2" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 21. " LVTTL_EC2_RXD1 ,LVTTL control for ec2_rxd1" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 20. " LVTTL_EC2_RXD0 ,LVTTL control for ec2_rxd0" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 19. " LVTTL_EC2_GTX_CLK125 ,LVTTL control for ec2_gtx_clk125" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 18. " LVTTL_EC2_GTX_CLK ,LVTTL control for ec2_gtx_clk" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 17. " LVTTL_EC2_TX_EN ,LVTTL control for ec2_tx_en" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 16. " LVTTL_EC2_TXD3 ,LVTTL control for ec2_txd3" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 15. " LVTTL_EC2_TXD2 ,LVTTL control for ec2_txd2" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 14. " LVTTL_EC2_TXD1 ,LVTTL control for ec2_txd1" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 13. " LVTTL_EC2_TXD0 ,LVTTL control for ec2_txd0" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 12. " LVTTL_EC1_RX_DV ,LVTTL control for ec1_rx_dv" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 11. " LVTTL_EC1_RX_CLK ,LVTTL control for ec1_rx_clk" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 10. " LVTTL_EC1_RXD3 ,LVTTL control for ec1_rxd3" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 9. " LVTTL_EC1_RXD2 ,LVTTL control for ec1_rxd2" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 8. " LVTTL_EC1_RXD1 ,LVTTL control for ec1_rxd1" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 7. " LVTTL_EC1_RXD0 ,LVTTL control for ec1_rxd0" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 6. " LVTTL_EC1_GTX_CLK125 ,LVTTL control for ec1_gtx_clk125" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 5. " LVTTL_EC1_GTX_CLK ,LVTTL control for ec1_gtx_clk" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 4. " LVTTL_EC1_TX_EN ,LVTTL control for ec1_tx_en" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 3. " LVTTL_EC1_TXD3 ,LVTTL control for ec1_txd3" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 2. " LVTTL_EC1_TXD2 ,LVTTL control for ec1_txd2" "LVCMOS input levels,LVTTL input levels" newline bitfld.long 0x2C 1. " LVTTL_EC1_TXD1 ,LVTTL control for ec1_txd1" "LVCMOS input levels,LVTTL input levels" bitfld.long 0x2C 0. " LVTTL_EC1_TXD0 ,LVTTL control for ec1_txd0" "LVCMOS input levels,LVTTL input levels" line.long 0x30 "VSEL_CNTRL1,VSEL Control Register 1" bitfld.long 0x30 7.--8. " TVDD_VSEL ,TVDD voltage select" ",2.5V,2.5V,1.2V / 1.8V" bitfld.long 0x30 5.--6. " LVDD_VSEL ,LVDD voltage select" ",2.5V,2.5V,1.8V" newline bitfld.long 0x30 3.--4. " EVDD_VSEL ,EVDD voltage select" "3.3V,,,1.8V" bitfld.long 0x30 1.--2. " DVDD_VSEL ,DVDD voltage select" "3.3V,,,1.8V" newline bitfld.long 0x30 0. " AUTO_VOLT_CTRL ,Auto-detect voltage control" "Auto mode,Manual mode" width 33. group.long 0x60++0x03 "Pin Control Registers" line.long 0x00 "DCFG_PIN_CTRL_PIN_CTRL_DDRCLKDR,DDR clock disable register" bitfld.long 0x00 21. " D1_MCK0_DIS ,DDR controller 1 clock 0 disable" "No,Yes" bitfld.long 0x00 20. " D1_MCK1_DIS ,DDR controller 1 clock 1 disable" "No,Yes" newline bitfld.long 0x00 19. " D1_MCK2_DIS ,DDR controller 1 clock 2 disable" "No,Yes" bitfld.long 0x00 18. " D1_MCK3_DIS ,DDR controller 1 clock 3 disable" "No,Yes" group.long 0x68++0x03 line.long 0x00 "DCFG_PIN_CTRL_PIN_CTRL_IFCCLKDR,IFC Clock Disable Register" bitfld.long 0x00 2. " IFC_CLK0_DIS ,IFC clock 0 disable" "No,Yes" bitfld.long 0x00 1. " IFC_CLK1_DIS ,IFC clock 1 disable" "No,Yes" width 0x0B tree.end else tree "DCFG (Device Configuration and Pin Control)" base ad:0x01EE0000 width 14. endian.be rgroup.long 0x00++0x03 line.long 0x00 "PORSR1,POR Status Register 1" sif cpuis("LS1012A") bitfld.long 0x00 29. " RCW_SRC ,Reset configuration word source" "Hard-coded,QSPI" else hexmask.long.word 0x00 23.--31. 1. " RCW_SRC ,Reset configuration word source" bitfld.long 0x00 18. " IFC_TE ,IFC external transceive enable polarity selection" "Active high,Active low" newline bitfld.long 0x00 15. " ENG0 ,Engineering use bit 0" "0,1" bitfld.long 0x00 14. " ENG1 ,Engineering use bit 1" "0,1" bitfld.long 0x00 13. " ENG2 ,Engineering use bit 2" "0,1" endif rgroup.long 0x04++0x03 line.long 0x00 "PORSR2,POR Status Register 2" sif cpuis("LS10?6A") bitfld.long 0x00 29. " DRAM_TYPE ,DRAM type selector" "DDR4 1.2V,?..." elif cpuis("LS10?3A") bitfld.long 0x00 29. " DRAM_TYPE ,DRAM type selector" "DDR4 1.2V,DDR3L 1.35V" elif cpuis("LS1012A") bitfld.long 0x00 28. " ENG ,Engineering use bit" "0,1" bitfld.long 0x00 25. " ENG2 ,Engineering Use bit 2" "0,1" endif sif !cpuis("LS1012A") rgroup.long 0x20++0x03 line.long 0x00 "GPPORCR1,General-Purpose POR Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " POR_CFG_VEC ,General-purpose POR configuration vector sampled from integrated flash controller address/data signals" endif sif cpuis("LS10?6A") rgroup.long 0x28++0x03 line.long 0x00 "FUSESR,Fuse Status Register" bitfld.long 0x00 7. " DA_V ,VDD voltage" "1V,0.9V" elif cpuis("LS1012A") rgroup.long 0x28++0x03 line.long 0x00 "FUSESR,Fuse Status Register" bitfld.long 0x00 25.--29. " DA_V ,VDD voltage" "Unused,0.9875 V,0.9750 V,0.9625 V,0.9500 V,0.9375 V,0.9250 V,0.9125 V,0.9000 V,0.8875 V,0.8750 V,0.8625 V,0.8500 V,0.8375 V,0.8250 V,0.8125 V,1.0000 V,1.0125 V,1.0250 V,1.0375 V,1.0500 V,1.0625 V,1.0750 V,1.0875 V,1.1000 V,,,,,,,DA_ALT_V" bitfld.long 0x00 20.--24. " DA_ALT_V ,VDD alternate voltage" "Unused,0.9875 V,0.9750 V,0.9625 V,0.9500 V,0.9375 V,0.9250 V,0.9125 V,0.9000 V,0.8875 V,0.8750 V,0.8625 V,0.8500 V,0.8375 V,0.8250 V,0.8125 V,1.0000 V,1.0125 V,1.0250 V,1.0375 V,1.0500 V,1.0625 V,1.0750 V,1.0875 V,1.1000 V,?..." endif group.long 0x70++0x03 line.long 0x00 "DEVDISR1,Device Disable Register 1" sif cpuis("LS1012A") bitfld.long 0x00 31. " PBL ,Pre-boot loader disable" "No,Yes" bitfld.long 0x00 29. " ESDHC1 ,eSDHC controller 1 disable" "No,Yes" bitfld.long 0x00 28. " ESDHC2 ,eSDHC controller 2 disable" "No,Yes" newline bitfld.long 0x00 22. " EDMA ,eDMA controlle disable" "No,Yes" bitfld.long 0x00 19. " PFE ,PFE controller disable" "No,Yes" bitfld.long 0x00 18. " USB2 ,USB controller 2 disable" "No,Yes" newline bitfld.long 0x00 15. " SATA ,SATA disable" "No,Yes" bitfld.long 0x00 14. " USB3 ,USB controller 3 disable" "No,Yes" bitfld.long 0x00 9. " SEC ,SEC module disable" "No,Yes" else bitfld.long 0x00 31. " PBL ,Pre-boot loader disable" "No,Yes" bitfld.long 0x00 29. " ESDHC ,eSDHC controller disable" "No,Yes" bitfld.long 0x00 23. " DMA1 ,DMA controller 1 (eDMA) disable" "No,Yes" newline bitfld.long 0x00 22. " DMA2 ,DMA controller 2 (qDMA) disable" "No,Yes" bitfld.long 0x00 17. " USB3 ,USB controller 3 disable" "No,Yes" newline bitfld.long 0x00 16. " USB2 ,USB controller 2 disable" "No,Yes" bitfld.long 0x00 15. " SATA ,SATA disable" "No,Yes" sif cpuis("LS10?3A") bitfld.long 0x00 14. " USB1 ,USB controller 1 disable" "No,Yes" endif newline bitfld.long 0x00 9. " SEC ,SEC module disable" "No,Yes" sif cpuis("LS10?3A") bitfld.long 0x00 0. " QE ,QUICC engine disable" "No,Yes" endif endif sif cpuis("LS1012A") hgroup.long 0x74++0x03 hide.long 0x00 "DEVDISR2,Device Disable Register 2" hgroup.long 0x78++0x03 hide.long 0x00 "DEVDISR3,Device Disable Register 3" else group.long 0x74++0x07 line.long 0x00 "DEVDISR2,Device Disable Register 2" bitfld.long 0x00 31. " FMAN1_MAC1 ,Frame manager 1 MAC1 disable" "No,Yes" bitfld.long 0x00 30. " FMAN1_MAC2 ,Frame manager 1 MAC2 disable" "No,Yes" bitfld.long 0x00 29. " FMAN1_MAC3 ,Frame manager 1 MAC3 disable" "No,Yes" newline bitfld.long 0x00 28. " FMAN1_MAC4 ,Frame manager 1 MAC4 disable" "No,Yes" bitfld.long 0x00 27. " FMAN1_MAC5 ,Frame manager 1 MAC5 disable" "No,Yes" bitfld.long 0x00 26. " FMAN1_MAC6 ,Frame manager 1 MAC6 disable" "No,Yes" newline bitfld.long 0x00 23. " FMAN1_MAC9 ,Frame manager 1 MAC9 disable" "No,Yes" sif cpuis("LS10?6A") bitfld.long 0x00 22. " FMAN1_MAC10 ,Frame manager 1 MAC10 disable" "No,Yes" endif bitfld.long 0x00 7. " FMAN1 ,Frame manager 1 disable" "No,Yes" line.long 0x04 "DEVDISR3,Device Disable Register 3" bitfld.long 0x04 19. " QMAN ,Queue manager disable" "No,Yes" bitfld.long 0x04 18. " BMAN ,Buffer manager disable" "No,Yes" endif group.long 0x7C++0x07 line.long 0x00 "DEVDISR4,Device Disable Register 4" bitfld.long 0x00 29. " DUART1 ,DUART1 module disable" "No,Yes" sif !cpuis("LS1012A") bitfld.long 0x00 28. " DUART2 ,DUART2 module disable" "No,Yes" endif newline bitfld.long 0x00 27. " QSPI ,QuadSPI module disable" "No,Yes" line.long 0x04 "DEVDISR5,Device Disable Register 5" sif cpuis("LS1012A") bitfld.long 0x04 31. " MMDC_COMPLEX ,DDR controller disable" "No,Yes" bitfld.long 0x04 27. " SAI1 ,SAI1 disable" "No,Yes" bitfld.long 0x04 26. " SAI2 ,SAI2 disable" "No,Yes" else bitfld.long 0x04 31. " DDR1 ,DDR controller disable" "No,Yes" bitfld.long 0x04 28. " LPUART4 ,LPUART4 disable" "No,Yes" endif newline bitfld.long 0x04 25. " OCRAM1 ,OCRAM1 disable" "No,Yes" bitfld.long 0x04 24. " OCRAM2 ,OCRAM2 disable" "No,Yes" sif !cpuis("LS1012A") bitfld.long 0x04 23. " IFC ,Integrated flash controller disable" "No,Yes" endif newline bitfld.long 0x04 22. " GPIO ,All GPIO disable" "No,Yes" bitfld.long 0x04 21. " DBG ,Debug module disable" "No,Yes" newline sif cpuis("LS1012A") bitfld.long 0x04 20. " SAI3 ,SAI3 disable" "No,Yes" bitfld.long 0x04 19. " SAI4 ,SAI4 disable" "No,Yes" bitfld.long 0x04 18. " SAI5 ,SAI5 disable" "No,Yes" else bitfld.long 0x04 17. " LPUART1 ,LPUART1 disable" "No,Yes" bitfld.long 0x04 16. " LPUART2 ,LPUART2 disable" "No,Yes" bitfld.long 0x04 15. " LPUART3 ,LPUART3 disable" "No,Yes" newline bitfld.long 0x04 13. " LPUART5 ,LPUART5 disable" "No,Yes" bitfld.long 0x04 12. " LPUART6 ,LPUART6 disable" "No,Yes" endif newline bitfld.long 0x04 11. " WDOG1 ,WDOG1 disable" "No,Yes" bitfld.long 0x04 10. " FLEXTIMER ,FlexTimer disable" "No,Yes" bitfld.long 0x04 9. " WDOG2 ,WDOG2 disable" "No,Yes" bitfld.long 0x04 8. " SPI1 ,SPI1 disable" "No,Yes" newline sif !cpuis("LS1012A") bitfld.long 0x04 7. " WDOG3 ,WDOG3 disable" "No,Yes" bitfld.long 0x04 6. " WDOG4 ,WDOG4 disable" "No,Yes" bitfld.long 0x04 5. " WDOG5 ,WDOG5 disable" "No,Yes" newline bitfld.long 0x04 4. " IIC4 ,IIC4 disable" "No,Yes" bitfld.long 0x04 3. " IIC3 ,IIC3 disable" "No,Yes" newline endif bitfld.long 0x04 2. " IIC2 ,IIC2 disable" "No,Yes" bitfld.long 0x04 1. " IIC1 ,IIC1 disable" "No,Yes" sif cpuis("LS1012A") bitfld.long 0x04 0. " CCI_400 ,Cache coherent interconnect disable" "No,Yes" else bitfld.long 0x04 0. " ICMMU ,Interconnects and MMU disable" "No,Yes" endif sif !cpuis("LS1012A") group.long 0x94++0x03 line.long 0x00 "COREDISR,Core Disable Register" bitfld.long 0x00 3. " CD3 ,Core 3 disable" "No,Yes" bitfld.long 0x00 2. " CD2 ,Core 2 disable" "No,Yes" bitfld.long 0x00 1. " CD1 ,Core 1 disable" "No,Yes" endif rgroup.long 0xA4++0x03 line.long 0x00 "SVR,System Version Register" hexmask.long.byte 0x00 28.--31. 1. " MFR_ID ,Manufacturer ID" hexmask.long.word 0x00 16.--27. 1. " SOC_DEV_ID ,Chip device ID" hexmask.long.byte 0x00 8.--15. 1. " VAR_PER ,Various personalities" newline hexmask.long.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.long.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.long 0xB0++0x07 line.long 0x00 "RSTCR,Reset Control Register" bitfld.long 0x00 1. " RESET_REQ ,Hardware reset request" "Not requested,Requested" line.long 0x04 "RSTRQPBLSR,Reset Request Preboot Loader Status Register" eventfld.long 0x04 23. " ERR_CODE[0] ,7-bit PBL error code bit 0" "0,1" eventfld.long 0x04 22. " [1] ,7-bit PBL error code bit 1" "0,1" eventfld.long 0x04 21. " [2] ,7-bit PBL error code bit 2" "0,1" eventfld.long 0x04 20. " [3] ,7-bit PBL error code bit 3" "0,1" newline eventfld.long 0x04 19. " [4] ,7-bit PBL error code bit 4" "0,1" eventfld.long 0x04 18. " [5] ,7-bit PBL error code bit 5" "0,1" eventfld.long 0x04 17. " [6] ,7-bit PBL error code bit 6" "0,1" group.long 0xC0++0x03 line.long 0x00 "RSTRQMR1,Reset Request Mask Register" sif !cpuis("LS1012A") bitfld.long 0x00 31. " CORE_WDOG3_RST_MSK ,Core watchdog reset request mask" "Not masked,Masked" bitfld.long 0x00 30. " CORE_WDOG4_RST_MSK ,Core watchdog reset request mask" "Not masked,Masked" bitfld.long 0x00 29. " CORE_WDOG5_RST_MSK ,Core watchdog reset request mask" "Not masked,Masked" bitfld.long 0x00 22. " IFC_MSK ,Integrated Flash Controller reset request event mask" "Not masked,Masked" newline endif bitfld.long 0x00 19. " ALTCBAR_MSK ,ALTCBAR violation by PBL reset request mask" "Not masked,Masked" bitfld.long 0x00 18. " PBL_MSK ,PBL error reset request event mask" "Not masked,Masked" bitfld.long 0x00 17. " SFP_MSK ,Security fuse processor error during POR fuse process reset mask" "Not masked,Masked" bitfld.long 0x00 16. " SEC_MSK ,Security Controller reset request event mask" "Not masked,Masked" newline bitfld.long 0x00 15. " SDC_MSK ,Security debug controller error reset request mask" "Not masked,Masked" bitfld.long 0x00 14. " MBEE_MSK ,Multi-bit ECC error reset request mask" "Not masked,Masked" bitfld.long 0x00 12. " RPTOE_MSK ,RCPM Time Out reset request event mask" "Not masked,Masked" bitfld.long 0x00 11. " SRDS_RST_MSK ,SerDes reset request event mask" "Not masked,Masked" newline sif !cpuis("LS1012A") bitfld.long 0x00 10. " CCP_ERR_MSK ,REP Error Alarm from CCP(REP) event mask" "Not masked,Masked" newline endif bitfld.long 0x00 9. " CORE_WDOG_RST_MSK ,Core watchdog reset request mask" "Not masked,Masked" rgroup.long 0xC8++0x03 line.long 0x00 "RSTRQSR1,Reset Request Status Register" sif !cpuis("LS1012A") bitfld.long 0x00 31. " CORE_WDOG3_RST_RR ,Core watchdog event reset request" "Not requested,Requested" bitfld.long 0x00 30. " CORE_WDOG4_RST_RR ,Core watchdog event reset request" "Not requested,Requested" bitfld.long 0x00 29. " CORE_WDOG5_RST_RR ,Core watchdog event reset request" "Not requested,Requested" bitfld.long 0x00 22. " IFC_RR ,Integrated flash controller reset request event" "Not occurred,Occurred" newline endif bitfld.long 0x00 19. " ALTCBAR_RR ,ALTCBAR violation by PBL reset request mask" "Not occurred,Occurred" bitfld.long 0x00 18. " PBL_RR ,PBL error reset request event" "Not occurred,Occurred" bitfld.long 0x00 17. " SFP_RR ,Security fuse processor error during POR fuse process reset request" "Not occurred,Occurred" bitfld.long 0x00 16. " SEC_RR ,Security monitor error during POR fuse process reset request" "Not occurred,Occurred" newline bitfld.long 0x00 15. " SDC_RR ,Security debug controller reset request" "Not occurred,Occurred" bitfld.long 0x00 14. " MBEE_RR ,Multi-bit ECC reset request" "Not occurred,Occurred" bitfld.long 0x00 12. " RPTOE_RR ,RCPM time out reset request event" "Not occurred,Occurred" bitfld.long 0x00 11. " SRDS_RST_RR ,SerDes reset event" "Not occurred,Occurred" newline sif !cpuis("LS1012A") bitfld.long 0x00 10. " CCP_ERR_RR ,REP error alarm from CCP(REP) event reset request" "Not occurred,Occurred" newline endif bitfld.long 0x00 9. " CORE_WDOG_RST_RR ,Core watchdog event reset request" "Not occurred,Occurred" group.long 0xE4++0x03 line.long 0x00 "BRR,Boot Release Register" sif !cpuis("LS1012A") bitfld.long 0x00 3. " CR3 ,Core 3 Boot holdoff release" "Not released,Released" bitfld.long 0x00 2. " CR2 ,Core 2 Boot holdoff release" "Not released,Released" bitfld.long 0x00 1. " CR1 ,Core 1 Boot holdoff release" "Not released,Released" newline endif bitfld.long 0x00 0. " CR0 ,Core 0 Boot Holdoff release" "Not released,Released" tree "RCWSR 1-16 (Reset Control Word Status 0-15 Registers)" rgroup.long 0x100++0x4F line.long 0x00 "RCWSR1,Reset Control Word Status Register 1" bitfld.long 0x00 30.--31. " SYS_PLL_CFG ,System PLL configuration" "All platforms,?..." newline sif cpuis("LS1012A") bitfld.long 0x00 25.--29. " SYS_PLL_RAT ,System PLL multiplier/ratio in format clock:SYSCLK ratio" ",,,,4:1,?..." newline else bitfld.long 0x00 25.--29. " SYS_PLL_RAT ,System PLL multiplier/ratio in format clock:SYSCLK ratio" ",,,3:1,4:1,5:1,6:1,7:1,8:1,9:1,10:1,11:1,12:1,13:1,14:1,15:1,16:1,?..." newline bitfld.long 0x00 22.--23. " MEM_PLL_CFG ,Memory controller complex PLL configuration" "All frequencies,?..." newline bitfld.long 0x00 16.--21. " MEM_PLL_RAT ,Memory controller complex PLL multiplier/ratio in format DDR PLL:SYSCLK ratio" ",,,,,,,,8:1,9:1,10:1,11:1,12:1,13:1,14:1,15:1,16:1,17:1,18:1,19:1,20:1,21:1,22:1,23:1,24:1,?..." newline endif bitfld.long 0x00 6.--7. " CGA_PLL1_CFG ,Cluster group A PLL 1 configuration" "freq. >= 1GHz,?..." newline sif cpuis("LS1012A") bitfld.long 0x00 0.--5. " CGA_PLL1_RAT ,Cluster group A PLL 1 multiplier/ratio" ",,,,,,6:1 Async,7:1 Async,8:1 Async,?..." else bitfld.long 0x00 0.--5. " CGA_PLL1_RAT ,Cluster group A PLL 1 multiplier/ratio" ",,,,,5:1 Async,6:1 Async,7:1 Async,8:1 Async,9:1 Async,10:1 Async,11:1 Async,12:1 Async,13:1 Async,14:1 Async,15:1 Async,16:1 Async,17:1 Async,18:1 Async,19:1 Async,20:1 Async,21:1 Async,22:1 Async,23:1 Async,24:1 Async,25:1 Async,26:1 Async,27:1 Async,28:1 Async,29:1 Async,30:1 Async,31:1 Async,32:1 Async,33:1 Async,34:1 Async,35:1 Async,36:1 Async,37:1 Async,38:1 Async,39:1 Async,40:1 Async,?..." endif sif cpuis("LS1012A") hide.long 0x04 "RCWSR2,Reset Control Word Status Register 2" hide.long 0x08 "RCWSR3,Reset Control Word Status Register 3" else line.long 0x04 "RCWSR2,Reset Control Word Status Register 2" bitfld.long 0x04 30.--31. " CGA_PLL2_CFG ,Cluster group A PLL 2 configuration" "freq. >= 1GHz,?..." newline bitfld.long 0x04 24.--29. " CGA_PLL2_RAT ,Cluster group A PLL 2 multiplier/ratio" ",,,,,5:1 Async,6:1 Async,7:1 Async,8:1 Async,9:1 Async,10:1 Async,11:1 Async,12:1 Async,13:1 Async,14:1 Async,15:1 Async,16:1 Async,17:1 Async,18:1 Async,19:1 Async,20:1 Async,21:1 Async,22:1 Async,23:1 Async,24:1 Async,25:1 Async,26:1 Async,27:1 Async,28:1 Async,29:1 Async,30:1 Async,31:1 Async,32:1 Async,33:1 Async,34:1 Async,35:1 Async,36:1 Async,37:1 Async,38:1 Async,39:1 Async,40:1 Async,?..." line.long 0x08 "RCWSR3,Reset Control Word Status Register 3" endif line.long 0x0C "RCWSR4,Reset Control Word Status Register 4" sif cpuis("LS1012A") bitfld.long 0x0C 28.--31. " C1_PLL_SEL ,Cluster 1 PLL select" "CGA_PLL1/1,,CGA_PLL1/2,?..." newline else bitfld.long 0x0C 28.--31. " C1_PLL_SEL ,Cluster 1 PLL select" "CGA_PLL1/1,CGA_PLL1/2,,,CGA_PLL2/1,CGA_PLL2/2,?..." newline endif line.long 0x10 "RCWSR5,Reset Control Word Status Register 5" hexmask.long.word 0x10 16.--31. 1. " SRDS_PRTCL_S1 ,SerDes 1 protocol select" newline sif cpuis("LS10?6A") hexmask.long.word 0x10 0.--15. 1. " SRDS_PRTCL_S2 ,SerDes 2 protocol select" newline endif line.long 0x14 "RCWSR6,Reset Control Word Status Register 6" bitfld.long 0x14 31. " SRDS_PLL1_REF_CLK_SEL_S1 ,SerDes 1 PLL1 reference clock select" "100 MHz / 125 MHz,125 MHz / 156.25 MHz" newline bitfld.long 0x14 30. " SRDS_PLL2_REF_CLK_SEL_S1 ,SerDes 1 PLL2 reference clock select" "100 MHz / 125 MHz,125 MHz / 156.25 MHz" newline sif cpuis("LS1012A") bitfld.long 0x14 23. " SRDS_PLL1_PD_S1 ,SerDes 1 PLL1 power down" "Not powered down,Powered done" newline bitfld.long 0x14 22. " SRDS_PLL1_PD_S1 ,SerDes 1 PLL2 power down" "Not powered down,Powered done" newline bitfld.long 0x14 2. " SERDES_INT_REFCLK ,SerDesl reference clock selection" "External,Internal" newline else newline sif cpuis("LS10?6A") bitfld.long 0x14 29. " SRDS_PLL1_REF_CLK_SEL_S2 ,SerDes 2 PLL1 reference clock select" "100 MHz / 125 MHz,125 MHz / 156.25 MHz" newline bitfld.long 0x14 28. " SRDS_PLL2_REF_CLK_SEL_S2 ,SerDes 2 PLL2 reference clock select" "100 MHz / 125 MHz,125 MHz / 156.25 MHz" newline elif cpuis("LS10?3A") bitfld.long 0x14 25. " HDLC1_MODE ,HDLC1/TDM pin operating mode select" "Normal,Open-drain" newline bitfld.long 0x14 24. " HDLC2_MODE ,HDLC2/TDM pin operating mode select" "Normal,Open-drain" newline endif bitfld.long 0x14 23. " SRDS_PLL1_PD_S1 ,SerDes 1 PLL1 power down" "Not powered down,Powered done" newline bitfld.long 0x14 22. " SRDS_PLL1_PD_S1 ,SerDes 1 PLL2 power down" "Not powered down,Powered done" newline sif cpuis("LS10?6A") bitfld.long 0x14 21. " SRDS_PLL1_PD_S1 ,SerDes 2 PLL1 power down" "Not powered down,Powered done" newline bitfld.long 0x14 20. " SRDS_PLL1_PD_S1 ,SerDes 2 PLL2 power down" "Not powered down,Powered done" newline bitfld.long 0x14 14.--15. " SRDS_DIV_PEX_S1 ,SerDes 1 frequency divider - PEX" "Max 8G,Max 5G,Max 2.5G,?..." newline bitfld.long 0x14 12.--13. " SRDS_DIV_PEX_S2 ,SerDes 2 frequency divider - PEX" "Max 8G,Max 5G,Max 2.5G,?..." newline elif cpuis("LS10?3A") bitfld.long 0x14 14.--15. " SRDS_DIV_PEX_S1 ,SerDes 1 frequency divider - PEX" "Max 5G,Max 5G,Max 2.5G,?..." newline endif bitfld.long 0x14 4.--5. " DDR_REFCLK_SEL ,DDR reference clock source selection" "DDRCLK,DIFF_SYSCLK/DIFF_SYSCLK_B,?..." newline bitfld.long 0x14 3. " SRDS_REFCLK_SEL_S1 ,SerDes1 PLL2 reference clock selection" "SD1_REF_CLK2/SD1_REF_CLK2_B,SD1_REF_CLK1/SD1_REF_CLK1_B" newline sif cpuis("LS10?6A") bitfld.long 0x14 2. " SRDS_REFCLK_SEL_S2 ,SerDes2 PLL2 reference clock selection" "SD2_REF_CLK2/SD1_REF_CLK2_B,SD1_REF_CLK1/SD1_REF_CLK1_B" newline endif bitfld.long 0x14 0.--1. " DDR_FDBK_MULT ,DDR PLL feedback path selection and multiplication enabler" ",,2,?..." newline endif line.long 0x18 "RCWSR7,Reset Control Word Status Register 7" sif cpuis("LS1012A") bitfld.long 0x18 28.--31. " PBI_SRC ,Pre-boot initialization source" ",,,,QSPI,QSPI,?..." newline else bitfld.long 0x18 28.--31. " PBI_SRC ,Pre-boot initialization source" ",,,,QSPI,QSPI,SD/MMC,,,,,,,,IFC,?..." newline endif bitfld.long 0x18 22. " BOOT_HO ,Boot holdoff core select" "All except 0,All" newline bitfld.long 0x18 21. " SB_EN ,Secure boot enable" "Disabled,Enabled" newline sif !cpuis("LS1012A") hexmask.long.word 0x18 12.--20. 1. " IFC_MODE ,IFC mode" newline endif line.long 0x1C "RCWSR8,Reset Control Word Status Register 8" sif cpuis("LS10?6A") bitfld.long 0x1C 29.--31. " HWA_CGA_M1_CLK_SEL ,Hardware accelerator block cluster group A mux 1 clock select" ",,Async PLL 1/2,Async PLL 1/3,Async PLL 1/4,Platform freq.,Async PLL 2/2,Async PLL 2/3" newline bitfld.long 0x1C 24.--25. " DRAM_LAT ,DDR latency" "6 or 7,8 or higher,,5" newline elif cpuis("LS10?3A") bitfld.long 0x1C 29.--31. " HWA_CGA_M1_CLK_SEL ,Hardware accelerator block cluster group A mux 1 clock select" ",,Async PLL 1/2,Async PLL 1/3,,,Async PLL 2/2,Async PLL 2/3" newline bitfld.long 0x1C 24.--25. " DRAM_LAT ,DDR latency" "6 or 7,8 or higher,,5" newline endif sif cpuis("LS10?3A") bitfld.long 0x1C 13. " SYS_PLL_SPD ,System PLL speed select" ",1" newline elif cpuis("LS1012A") bitfld.long 0x1C 12.--13. " SYS_PLL_SPD ,System PLL speed select" ",1,?..." newline bitfld.long 0x1C 11. " CGA_PLL1_SPD ,Cluster group A PLL 1 speed select" ",1" newline endif sif !cpuis("LS1012A") bitfld.long 0x1C 10. " CGA_PLL2_SPD ,Cluster group A PLL2 speed select" "High speed,Low speed" endif line.long 0x20 "RCWSR9,Reset Control Word Status Register 8" sif cpuis("LS1012A") bitfld.long 0x20 23. " HOST_AGT_PEX ,Host/agent PEX mode for the PCIE interface" "Host,Agent" else bitfld.long 0x20 21.--23. " HOST_AGT_PEX ,Host/agent PEX mode for all PCIE interfaces" "All host,All agent,PEX1 agent. Rest host,PEX1 and PEX3 agent. Rest host,PEX1 and PEX2 agent. Rest host,PEX2 and PEX3 agent. Rest host,PEX2 agent. Rest host,PEX3 agent. Rest host" endif line.long 0x24 "RCWSR10,Reset Control Word Status Register 9" sif cpuis("LS1012A") hexmask.long 0x24 0.--31. 1. " GP_INFO ,General purpose information" else hexmask.long.byte 0x24 24.--31. 1. " GP_INFO0 ,General purpose information 0" newline hexmask.long.tbyte 0x24 0.--20. 1. " GP_INFO1 ,General purpose information 1" endif line.long 0x28 "RCWSR11,Reset Control Word Status Register 11" line.long 0x2C "RCWSR12,Reset Control Word Status Register 12" sif cpuis("LS10?6A") bitfld.long 0x2C 27.--29. " UART_EXT ,UART pins functionality settings" "UART_BASE,(UART1_SOUT/GPIO1_15)/LPUART[1:2]_SOUT/(UART1_SIN/GPIO1_17)/LPUART[1:2]_SIN/LPUART1_RTS_B/LPUART1_CTS_B,(UART1_SOUT/GPIO1_15)/LPUART1_SOUT/(UART1_SIN/GPIO1_17)/LPUART1_SIN/LPUART2_SOUT,LPUART4_SOUT/LPUART2_SIN/LPUART4_SIN,(UART1_SOUT/GPIO1_15)/FTM4_CH0/(UART1_SIN/GPIO1_17)/FTM4_CH1/FTM4_CH2/FTM4_CH3/FTM4_CH4/FTM4_CH5,?..." newline bitfld.long 0x2C 24.--26. " IRQ_EXT ,IRQ[3:5] pins functionality settings" "IRQ_BASE,,,,,FTM3_CH7 / FTM3_CH0 / FTM3_CH1 / FTM3_CH2 / FTM3_CH3 / FTM3_CH4 / FTM3_CH5 / FTM3_CH6 / GPIO1_31,?..." newline bitfld.long 0x2C 21.--23. " SPI_EXT ,SPI pins functionality settings" "SPI_BASE,SPI_CS_B(1/2/3)/GPIO2_(1/2/3)/SDHC_CLK_SYNC_(OUT/IN)/SDHC_(VS/DAT5/DAT6/DAT7/DAT123_DIR/DAT0_DIR/CMD_DIR),SPI_(MOSI/MISO/CS_B0/CS_B[1]/CS_B[2]/CS_B[3])/GPIO2_(0/1/2/3)/SDHC_[DAT4/DAT5/DAT6/DAT7/DAT123_DIR/DAT0_DIR/CMD_DIR],?..." newline bitfld.long 0x2C 18.--20. " SDHC_EXT ,SDHC functionality settings" "SDHC_BASE,LPUART3_SOUT / LPUART3_SIN / LPUART2_RTS_B / LPUART2_CTS_B / LPUART3_RTS_B,LPUART3_CTS_B,LPUART3_SOUT / LPUART3_SIN / LPUART5_SOUT / LPUART5_SIN / LPUART6_SOUT / LPUART6_SIN,FTM4_CH6 / FTM4_CH7 / FTM4_FAULT / FTM4_EXTCLK / FTM4_QD_PHA / FTM4_QD_PHB,?..." newline bitfld.long 0x2C 15.--17. " UART_BASE ,UART pins functionality settings" "GPIO1_[15:22],,,UART1_SOUT / UART1_SIN / GPIO1_[18:22] / GPIO1_16,UART1_SOUT / UART1_SIN / UART1_RTS_B / UART1_CTS_B / GPIO1_16 / GPIO1_18 / GPIO1_20 / GPIO1_22,UART1_SOUT / UART1_SIN / GPIO1_[19:22] / UART2_SOUT / UART2_SIN,UART[1:2]_SOUT / UART[1:2]_SIN / UART[1:2]_RTS_B / UART[1:2]_CTS_B,UART[1:4]_SOUT / UART[1:4]_SIN" newline elif cpuis("LS10?3A") bitfld.long 0x2C 27.--29. " UART_EXT ,UART pins functionality settings" "UART_BASE,(UART1_SOUT/GPIO1_15)/LPUART1_SOUT/(UART1_SIN/GPIO1_17)/LPUART1_SIN/LPUART2_SOUT/LPUART1_RTS_B/LPUART2_SIN/LPUART1_CTS_B,(UART1_SOUT/GPIO1_15)/LPUART1_SOUT/(UART1_SIN/GPIO1_17)/LPUART1_SIN/LPUART2_SOUT/LPUART4_SOUT/LPUART2_SIN/LPUART4_SIN},(UART1_SOUT/GPIO1_15)/(FTM4_CH0/UART1_SIN/GPIO1_17)/FTM4_CH1/FTM4_CH2/FTM4_CH3/FTM4_CH4/FTM4_CH5,?..." newline bitfld.long 0x2C 24.--26. " IRQ_EXT ,IRQ[3:5] pins functionality settings" "IRQ_BASE,TDMB_TSYNC/(TDMA_TXD/RXD)/TDMA_RSYNC/(TDMA_TXD/RXD_EXC)/TDMA_TSYNC/(TDMB_TXD/RXD)/TDMB_RSYNC/(TDMB_TXD/RXD_EXC)/GPIO1_31,UC3_RTSB_TXEN/UC1_RXD7/CTSB_RXDV/TXD7/RTSB_TXEN/UC3_RXD7/CTSB_RXDV/TXD7/GPIO1_31,FTM3_CH[0:7]/GPIO1_31,?..." newline bitfld.long 0x2C 21.--23. " SPI_EXT ,SPI pins functionality settings" "SPI_BASE,SDHC_CLK_SYNC_OUT/SDHC_CLK_SYNC_IN/VS/(GPIO2_1/SDHC_DAT5/CMD_DIR)/(GPIO2_2/SDHC_DAT6/DAT0_DIR)/(GPIO2_3/SDHC_DAT7/DAT123_DIR),(GPIO2_0/SDHC_DAT4)/(GPIO2_1/SDHC_DAT5/CMD_DIR)/(GPIO2_2/SDHC_DAT6/DAT0_DIR)/(GPIO2_3/SDHC_DAT7/DAT123_DIR),?..." newline bitfld.long 0x2C 18.--20. " SDHC_EXT ,SDHC functionality settings" "SDHC_BASE,LPUART3_SOUT/LPUART3_SIN/LPUART[2:3]_RTS_B/LPUART[2:3]_CTS_B,LPUART3_SOUT/LPUART3_SIN/LPUART[5:6]_SOUT/LPUART[5:6]_SIN,FTM4_CH[6:7]/FTM4_FAULT/FTM4_EXTCLK/FTM4_QD_PH[A:B],?..." newline elif cpuis("LS1012A") bitfld.long 0x2C 29. " SDHC2_EXT_CLK ,SDHC2_EXT_CLK pin functionality settings" "GPIO1[29],FTM2_CH3" newline bitfld.long 0x2C 28. " SDHC2_EXT_CMD ,SDHC2_EXT_CMD pin functionality settings" "GPIO1[24],FTM1_CH1" newline bitfld.long 0x2C 27. " SDHC2_EXT_DAT3 ,SDHC2_EXT_DAT3 pin functionality settings" "GPIO1[28],FTM2_CH1" newline bitfld.long 0x2C 26. " SDHC2_EXT_DAT2 ,SDHC2_EXT_DAT2 pin functionality settings" "GPIO1[27],FTM1_CH2" newline bitfld.long 0x2C 25. " SDHC2_EXT_DAT1 ,SDHC2_EXT_DAT1 pin functionality settings" "GPIO1[26],FTM2_CH2" newline bitfld.long 0x2C 24. " SDHC2_EXT_DAT0 ,SDHC2_EXT_DAT0 pin functionality settings" "GPIO1[25],FTM1_CH3" newline bitfld.long 0x2C 22.--23. " EC1_EXT_SAI3 ,EC1 pin functionality settings" "GPIO2[3] / GPIO2[11:12],SAI3_TX_DATA / SAI3_TX_SYNC / SAI3_TX_BCLK,SAI3_RX_DATA / SAI3_RX_SYNC / SAI3_RX_BCLK,?..." newline bitfld.long 0x2C 20.--21. " EC1_EXT_SAI4 ,EC1 pin functionality settings" "GPIO2[2] / GPIO2[13:14],SAI4_TX_DATA / SAI4_TX_SYNC / SAI4_TX_BCLK,SAI4_RX_DATA / SAI4_RX_SYNC / SAI4_RX_BCLK,?..." newline bitfld.long 0x2C 19. " EC1_EXT_SAI2_TX ,EC1 pin functionality settings" "GPIO2[4] / GPIO2[6:7],SAI2_TX_DATA / SAI2_TX_SYNC / SAI2_TX_BCLK" newline bitfld.long 0x2C 18. " EC1_EXT_SAI2_RX ,EC1 pin functionality settings" "GPIO2[5] / GPIO2[9:10],SAI2_RX_DATA / SAI2_RX_SYNC / SAI2_RX_BCLK" newline bitfld.long 0x2C 16.--17. " EC1_BASE ,EC1 ping functionality settings" "EC1_EXT_*,EC1 RGMII,USB 2.0 ULPI,?..." newline bitfld.long 0x2C 14.--15. " UART1_BASE ,UART pins functionality settings" "GPIO[0:1],UART1_SOUT,UART1_SIN,?..." newline bitfld.long 0x2C 12.--13. " UART2_BASE_FLOW ,JTAG/UART2 pins functionality settings" "GPIO[7] / GPIO[9:10],UART2_RTS_B / UART2_CTS_B / GPIO1[10],SAI5_TX_DATA / SAI5_TX_SYNC / SAI5_TX_BCLK,SAI5_RX_DATA / SAI5_RX_SYNC / SAI5_RX_BCLK" newline bitfld.long 0x2C 10.--11. " SDHC1_BASE ,eSDHC pins functionality settings" "GPIO[15:20],SDHC1_CMD / SDHC1_DAT[0:3] / SDHC1_CLK,SDHC1_CMD / SDHC1_DAT0 / GPIO1[17:19] / SDHC1_CLK,?..." newline bitfld.long 0x2C 8.--9. " SDHC2_BASE_DAT3_1 ,eSDHC1 data[3:1] pins functionality settings" "SDHC2_EXT_*,SDHC2_DAT[3:1],SAI1_RX_BCLK / SAI1_TX_BCLK / SAI1_TX_SYNC,SPI_MISO / SPICS[1:2]_B" newline bitfld.long 0x2C 6.--7. " SDHC2_BASE_BASE ,eSDHC1 single bit mode pins functionality settings" "SDHC2_EXT_*,SDHC2_CMD / SDHC2_DAT0 / SDHC2_CLK,SAI1_RX_DATA / SAI1_RX_SYNC / SAI1_TX_DATA,SPI_MOSI / SPICS0_B / SPI_CLK" newline bitfld.long 0x2C 5. " UART2_BASE_DATA ,JTAG/UART2 pin functionality settings" "GPIO[6] / GPIO[8],UART2_SIN / UART2_SOUT" newline bitfld.long 0x2C 4. " EMI1_BASE ,EMI1 pins functionality settings" "GPIO2[15:16],EMI1_MDC / EMI1_MDIO" newline bitfld.long 0x2C 2.--3. " GPIO_FTM_EXTCLK_BASE ,TBSCAN_EN_B pin functionality settings" "GPIO1[30],,FTM_EXTCLK,?..." newline bitfld.long 0x2C 0. " CLK_OUT_BASE ,CLK_OUT pin functionality settings" "GPIO1[31],CLK_OUT" newline endif sif !cpuis("LS1012A") bitfld.long 0x2C 14. " ASLEEP ,ASLEEP pin functionality settings" "ASLEEP,GPIO1_13" newline bitfld.long 0x2C 13. " RTC ,RTC pin functionality settings" "RTC,GPIO1_14" newline bitfld.long 0x2C 12. " SDHC_BASE ,SDHC_CMD / SDHC_DAT[0:3] / SDHC_CLK pin functionality settings" "SDHC_CMD / SDHC_DAT[0:3] / SDHC_CLK,GPIO2[4:9]" newline bitfld.long 0x2C 11. " IRQ_OUT ,IRQ_OUT pin functionality settings" ",1" newline bitfld.long 0x2C 10. " IRQ[3]_BASE ,IRQ[3] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 9. " IRQ[4]_BASE ,IRQ[4] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 8. " IRQ[5]_BASE ,IRQ[5] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 7. " IRQ[6]_BASE ,IRQ[6] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 6. " IRQ[7]_BASE ,IRQ[7] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 5. " IRQ[8]_BASE ,IRQ[8] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 4. " IRQ[9]_BASE ,IRQ[9] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 3. " IRQ[10]_BASE ,IRQ[10] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 2. " IRQ[11]_BASE ,IRQ[11] pin functionality settings" "IRQ,GPIO" newline bitfld.long 0x2C 0.--1. " SPI_BASE ,SPI_CS_B[0:3] pins functionality settings" "SPI_CS_B[0:3] / SPI_MOSI / SPI_MISO / SPI_CLK,SDHC_DAT[4:7],GPIO2[0:3],SDHC_CMD_DIR / SDHC_DAT0_DIR / SDHC_DAT123_DIR" endif sif cpuis("LS1012A") hide.long 0x30 "RCWSR13,Reset Control Word Status Register 13" else line.long 0x30 "RCWSR13,Reset Control Word Status Register 13" bitfld.long 0x30 29.--31. " IFC_GRP_A_EXT ,IFC group A pins functionality settings" "IFC_GRP_A_BASE,QSPI_A_DATA[3],FTM5_CH[0:1] / FTM5_EXTCLK,,IFC_CS_B[4:6],?..." newline bitfld.long 0x30 20.--22. " IFC_GRP_D_EXT ,IFC group D pins functionality settings" "IFC_GRP_D_BASE,QSPI_B_DATA[0:2],FTM6_CH[0:1] / FTM6_EXTCLK,?..." newline bitfld.long 0x30 17.--19. " IFC_GRP_E1_EXT ,IFC group E1 pins functionality settings" "IFC_GRP_E1_BASE,(IFC_CS_B[1]/GPIO2_10) / (IFC_CS_B[2]/GPIO2_11) / QSPI_B_DATA[3],FTM7_CH[0:1] / FTM7_EXTCLK,?..." newline bitfld.long 0x30 14.--16. " IFC_GRP_F_EXT ,IFC group F pins functionality settings" "(IFC_A[16:24]/IFC_WP_B[1:3]),QSPI_A_CS[0:1] / QSPI_A_SCK / QSPI_B_CS[0:1] / QSPI_B_SCK / QSPI_A_DATA[0:2],?..." newline bitfld.long 0x30 10. " IFC_GRP_E1_BASE ,IFC group E1 pins functionality settings" "IFC_CS_B[1:3],GPIO2[10:12]" newline bitfld.long 0x30 8. " IFC_GRP_D_BASE ,IFC group D pins functionality settings" "IFC_PAR[0:1]/FC_PERR_B,GPIO2[13:15]" newline bitfld.long 0x30 2.--3. " IFC_GRP_A_BASE ,IFC group A pins functionality settings" "IDC_A[25:27],GPIO2[25:27],IFC_RB_B[2:3],?..." newline bitfld.long 0x30 0. " IFC_A_22_24 ,IFC_A[22:24] pins functionality settings" "IFC_A[22:24],IFC_WP_B[1:3]" endif line.long 0x34 "RCWSR14,Reset Control Word Status Register 14" sif cpuis("LS1012A") bitfld.long 0x34 28. " SDHC1_CD ,SDHC1_CD_B pin functionality settings" "GPIO1[21],SDHC1_CD_B" newline bitfld.long 0x34 27. " SDHC1_WP ,SDHC1_WP pin functionality settings" "GPIO1[22],SDHC1_WD" newline bitfld.long 0x34 26. " QSPI_DATA0_GPIO ,QSPI pins for 2-bit interface functionality settings" "QSPI_A_DATA0 / QSPI_A_SCK / QSPI_A_CS0,GPIO[11] / GPIO[4:5]" newline bitfld.long 0x34 24.--25. " QSPI_DATA1_GPIO ,QSPI pins for 2-bit interface functionality settings" "QSPI_A_DATA1,GPIO1[12],?..." newline bitfld.long 0x34 22.--23. " QSPI_IIC2 ,QSPI pins for 4-bit interface functionality settings" "GPIO[13:14],IIC2_SCL / IIC2_SDA,QSPI_A_DATA[2:3],RESET_REQ_B" newline bitfld.long 0x34 17.--18. " USB1_DRVVBUS_BASE ,USB1_DRVVBUS pin functionality settings" "GPIO2[0],USB1_DRVVBUS,?..." newline bitfld.long 0x34 15.--16. " USB1_PWRFAULT_BASE ,USB1_PWRFAULT pin functionality settings" "GPIO2[1],USB1_PWRFAULT,ASLEEP,?..." newline bitfld.long 0x34 13. " SDHC1_VSEL ,EVDD IO domain voltage configuration" "GPIO1[23],SDHC1_VSEL" newline bitfld.long 0x34 9. " EMI1_DMODE ,Ethernet Management Interface 1 MDIO pin operating modes" "Normal,Open-drain" newline bitfld.long 0x34 7.--8. " EVDD_VSEL ,EVDD IO domain voltage configuration" "1.8 V,,3.3 V,?..." newline else bitfld.long 0x34 29.--31. " EC1 ,EC1 pins functionality settings" "RGMII1,GPIO3,,,,FTM1,?..." newline bitfld.long 0x34 26.--28. " EC2 ,EC2 pins functionality settings" "RGMII2,GPIO3,IEE1588,,,FTM2,?..." newline sif cpuis("LS10?6A") bitfld.long 0x34 24.--25. " LVDD_VSEL ,LVDD IO voltage configuration" "1.8 V,2.5 V,?..." newline bitfld.long 0x34 23. " I2C_IPGCLK_SEL ,I2C ipg clock select" "Platform clk / 4,Platform clk / 2" newline endif bitfld.long 0x34 22. " EM1 ,EM1 MDC_MDIO pins functionality settings" "MDC/MDIO (EM1),GPIO_3" newline bitfld.long 0x34 21. " EM2 ,EM2 MDC_MDIO pins functionality settings" "MDC/MDIO (EM2),GPIO_4" newline bitfld.long 0x34 20. " EMI2_DMODE ,Ethernet Management Interface 2 MDC_MDIO pin operating mode select" "Normal,Open-drain" newline bitfld.long 0x34 19. " EMI2_CMODE ,Ethernet Management Interface 2 MDC pin operating mode select" "Normal,Open-drain" newline bitfld.long 0x34 18. " USB_DRVVBUS ,USB_DRVVBUS pin functionality settings" "USB_DRVVBUS,GPIO4[29]" newline bitfld.long 0x34 17. " USB_PWRFAULT ,USB_PWRFAULT signal functionality settings" "USB_PWRFAULT,GPIO4[30]" newline bitfld.long 0x34 13.--14. " TVDD_VSEL ,TVDD IO domain voltage configuration" "1.2 V or 1.8 V,2.5 V,,Auto-voltage" newline bitfld.long 0x34 11.--12. " DVDD_VSEL ,DVDD IO domain voltage configuration" "1.8 V,,3.3 V,Auto-voltage" newline sif cpuis("LS10?3A") bitfld.long 0x34 10. " QE_CLK_OVRRIDE ,QE clocks on IIC2_SCL select" "IIC2_EXT,I2C_SCL" newline endif bitfld.long 0x34 9. " EMI1_DMODE ,Ethernet Management Interface 1 MDIO pin operating mode select" "Normal,Open-drain" newline bitfld.long 0x34 7.--8. " EVDD_VSEL ,EVDD IO domain voltage configuration" "1.8 V,,3.3 V,Auto-voltage" newline endif bitfld.long 0x34 3. " EMI1_CMODE ,Ethernet Management Interface 1 MDC pin operating mode" "Normal,Open-drain" newline sif cpuis("LS10?6A") bitfld.long 0x34 0.--2. " IIC2_EXT ,IIC2 base functionality / extension select" "IIC2_SCL / IIC2_SDA,SDHC_CD_B / SDHC_WP,GPIO4[2:3],FTM3_QD_PHA / FTM3_QD_PHB,?..." elif cpuis("LS10?3A") bitfld.long 0x34 0.--2. " IIC2_EXT ,IIC2 base functionality / extension select" "IIC2_SCL / IIC2_SDA,SDHC_CD_B / SDHC_WP,GPIO4[2:3],FTM3_QD_PHA / FTM3_QD_PHB,QE_SI1_STROBE[0:1],CLK[9:10],BRGO[2:3],?..." endif line.long 0x38 "RCWSR15,Reset Control Word Status Register 15" hexmask.long.byte 0x38 0.--7. 1. " SYSCLK_FREQ[2:9] ,SYSCLK frequency bits [2:9]" sif cpuis("LS1012A") hide.long 0x3C "RCWSR16,Reset Control Word Status Register 16" else line.long 0x3C "RCWSR16,Reset Control Word Status Register 16" hexmask.long.byte 0x3C 30.--31. 1. " SYSCLK_FREQ[0:1] ,SYSCLK frequency bits [0:1]" newline bitfld.long 0x3C 0.--2. " HWA_CGA_M2_CLK_SEL ,Hardware accelerator block cluster group A mux 2 clock select" ",Async PLL_2/1,,Async PLL_2/3,?..." endif tree.end tree "SCRATCHRW 0-3 (Scratch Read / Write 0-3 Registers)" group.long 0x200++0x03 line.long 0x00 "SCRATCHRW0,Scratch Read / Write Register 0" group.long 0x204++0x03 line.long 0x00 "SCRATCHRW1,Scratch Read / Write Register 1" group.long 0x208++0x03 line.long 0x00 "SCRATCHRW2,Scratch Read / Write Register 2" group.long 0x20C++0x03 line.long 0x00 "SCRATCHRW3,Scratch Read / Write Register 3" tree.end tree "SCRATCHW1R 0-3 (Scratch Read 0-3 Registers)" group.long 0x300++0x03 line.long 0x00 "SCRATCHW1R0,Scratch Read Register 0" group.long 0x304++0x03 line.long 0x00 "SCRATCHW1R1,Scratch Read Register 1" group.long 0x308++0x03 line.long 0x00 "SCRATCHW1R2,Scratch Read Register 2" group.long 0x30C++0x03 line.long 0x00 "SCRATCHW1R3,Scratch Read Register 3" tree.end newline sif cpuis("LS1012A") group.long 0x400++0x03 line.long 0x00 "CRSTSR0,Core Reset Status Register 0" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" else tree "CRSTSR 0-3 (Core Reset Status 0-3 Registers)" group.long 0x400++0x03 line.long 0x00 "CRSTSR0,Core Reset Status Register 0" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x404++0x03 line.long 0x00 "CRSTSR1,Core Reset Status Register 1" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x408++0x03 line.long 0x00 "CRSTSR2,Core Reset Status Register 2" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" group.long 0x40C++0x03 line.long 0x00 "CRSTSR3,Core Reset Status Register 3" rbitfld.long 0x00 2. " READY ,Core ready pin" "Not ready,Ready" eventfld.long 0x00 1. " RST_HRST ,Core was reset due to an HRESET" "No reset,Reset" eventfld.long 0x00 0. " RST_PORST ,Core was reset due to a PORESET" "No reset,Reset" tree.end endif newline group.long 0x608++0x03 line.long 0x00 "DMACR1,DMA Control Register" bitfld.long 0x00 30.--31. " DMA1_0 ,DMA 1 Channel 0 may be initiated by SoC's DMA pins/EPU" ",,,EPU" newline tree "TP_ITYP 0-63,Topology Initiator Type 0-63 Registers" rgroup.long 0x740++0x03 line.long 0x00 "TP_ITYP0,Topology Initiator Type 0 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x744++0x03 line.long 0x00 "TP_ITYP1,Topology Initiator Type 1 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x748++0x03 line.long 0x00 "TP_ITYP2,Topology Initiator Type 2 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x74C++0x03 line.long 0x00 "TP_ITYP3,Topology Initiator Type 3 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x750++0x03 line.long 0x00 "TP_ITYP4,Topology Initiator Type 4 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x754++0x03 line.long 0x00 "TP_ITYP5,Topology Initiator Type 5 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x758++0x03 line.long 0x00 "TP_ITYP6,Topology Initiator Type 6 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x75C++0x03 line.long 0x00 "TP_ITYP7,Topology Initiator Type 7 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x760++0x03 line.long 0x00 "TP_ITYP8,Topology Initiator Type 8 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x764++0x03 line.long 0x00 "TP_ITYP9,Topology Initiator Type 9 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x768++0x03 line.long 0x00 "TP_ITYP10,Topology Initiator Type 10 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x76C++0x03 line.long 0x00 "TP_ITYP11,Topology Initiator Type 11 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x770++0x03 line.long 0x00 "TP_ITYP12,Topology Initiator Type 12 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x774++0x03 line.long 0x00 "TP_ITYP13,Topology Initiator Type 13 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x778++0x03 line.long 0x00 "TP_ITYP14,Topology Initiator Type 14 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x77C++0x03 line.long 0x00 "TP_ITYP15,Topology Initiator Type 15 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x780++0x03 line.long 0x00 "TP_ITYP16,Topology Initiator Type 16 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x784++0x03 line.long 0x00 "TP_ITYP17,Topology Initiator Type 17 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x788++0x03 line.long 0x00 "TP_ITYP18,Topology Initiator Type 18 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x78C++0x03 line.long 0x00 "TP_ITYP19,Topology Initiator Type 19 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x790++0x03 line.long 0x00 "TP_ITYP20,Topology Initiator Type 20 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x794++0x03 line.long 0x00 "TP_ITYP21,Topology Initiator Type 21 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x798++0x03 line.long 0x00 "TP_ITYP22,Topology Initiator Type 22 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x79C++0x03 line.long 0x00 "TP_ITYP23,Topology Initiator Type 23 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7A0++0x03 line.long 0x00 "TP_ITYP24,Topology Initiator Type 24 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7A4++0x03 line.long 0x00 "TP_ITYP25,Topology Initiator Type 25 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7A8++0x03 line.long 0x00 "TP_ITYP26,Topology Initiator Type 26 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7AC++0x03 line.long 0x00 "TP_ITYP27,Topology Initiator Type 27 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7B0++0x03 line.long 0x00 "TP_ITYP28,Topology Initiator Type 28 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7B4++0x03 line.long 0x00 "TP_ITYP29,Topology Initiator Type 29 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7B8++0x03 line.long 0x00 "TP_ITYP30,Topology Initiator Type 30 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7BC++0x03 line.long 0x00 "TP_ITYP31,Topology Initiator Type 31 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7C0++0x03 line.long 0x00 "TP_ITYP32,Topology Initiator Type 32 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7C4++0x03 line.long 0x00 "TP_ITYP33,Topology Initiator Type 33 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7C8++0x03 line.long 0x00 "TP_ITYP34,Topology Initiator Type 34 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7CC++0x03 line.long 0x00 "TP_ITYP35,Topology Initiator Type 35 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7D0++0x03 line.long 0x00 "TP_ITYP36,Topology Initiator Type 36 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7D4++0x03 line.long 0x00 "TP_ITYP37,Topology Initiator Type 37 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7D8++0x03 line.long 0x00 "TP_ITYP38,Topology Initiator Type 38 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7DC++0x03 line.long 0x00 "TP_ITYP39,Topology Initiator Type 39 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7E0++0x03 line.long 0x00 "TP_ITYP40,Topology Initiator Type 40 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7E4++0x03 line.long 0x00 "TP_ITYP41,Topology Initiator Type 41 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7E8++0x03 line.long 0x00 "TP_ITYP42,Topology Initiator Type 42 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7EC++0x03 line.long 0x00 "TP_ITYP43,Topology Initiator Type 43 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7F0++0x03 line.long 0x00 "TP_ITYP44,Topology Initiator Type 44 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7F4++0x03 line.long 0x00 "TP_ITYP45,Topology Initiator Type 45 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7F8++0x03 line.long 0x00 "TP_ITYP46,Topology Initiator Type 46 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x7FC++0x03 line.long 0x00 "TP_ITYP47,Topology Initiator Type 47 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x800++0x03 line.long 0x00 "TP_ITYP48,Topology Initiator Type 48 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x804++0x03 line.long 0x00 "TP_ITYP49,Topology Initiator Type 49 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x808++0x03 line.long 0x00 "TP_ITYP50,Topology Initiator Type 50 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x80C++0x03 line.long 0x00 "TP_ITYP51,Topology Initiator Type 51 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x810++0x03 line.long 0x00 "TP_ITYP52,Topology Initiator Type 52 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x814++0x03 line.long 0x00 "TP_ITYP53,Topology Initiator Type 53 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x818++0x03 line.long 0x00 "TP_ITYP54,Topology Initiator Type 54 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x81C++0x03 line.long 0x00 "TP_ITYP55,Topology Initiator Type 55 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x820++0x03 line.long 0x00 "TP_ITYP56,Topology Initiator Type 56 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x824++0x03 line.long 0x00 "TP_ITYP57,Topology Initiator Type 57 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x828++0x03 line.long 0x00 "TP_ITYP58,Topology Initiator Type 58 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x82C++0x03 line.long 0x00 "TP_ITYP59,Topology Initiator Type 59 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x830++0x03 line.long 0x00 "TP_ITYP60,Topology Initiator Type 60 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x834++0x03 line.long 0x00 "TP_ITYP61,Topology Initiator Type 61 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x838++0x03 line.long 0x00 "TP_ITYP62,Topology Initiator Type 62 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" rgroup.long 0x83C++0x03 line.long 0x00 "TP_ITYP63,Topology Initiator Type 63 Register" hexmask.long.byte 0x00 0.--7. 1. " INIT_TYPE ,Initiator Type" tree.end newline rgroup.long 0x844++0x03 line.long 0x00 "TP_CLUSTER1,Core Cluster 1 Topology Register" bitfld.long 0x00 30.--31. " EOC ,End of Clusters" "Not the last,The last,The last,The last" bitfld.long 0x00 24.--29. " IT_IDX_PC4 ,Initiator Type Index for this cluster's fourth initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " IT_IDX_PC3 ,Initiator Type Index for this cluster third initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " T_IDX_PC2 ,Initiator Type Index for this cluster second initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " IT_IDX_PC1 ,Initiator Type Index for this cluster first initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("LS1012A") group.long 0xE60++0x03 line.long 0x00 "DDRCLKDR,DDR Clock Disable Register" bitfld.long 0x00 31. " D1_MCK0_DIS ,DDR Controller 1 clock 0 disable" "No,Yes" bitfld.long 0x00 30. " D1_MCK1_DIS ,DDR Controller 1 clock 1 disable" "No,Yes" group.long 0xE68++0x03 line.long 0x00 "IFCCLKDR,IFC Clock Disable Register" bitfld.long 0x00 2. " IFC_CLK0_DIS ,IFC clock 0 disable" "No,Yes" bitfld.long 0x00 1. " IFC_CLK1_DIS ,IFC clock 1 disable" "No,Yes" group.long 0xE80++0x03 line.long 0x00 "SDHCPCR,eSDHC Polarity Configuration Register" bitfld.long 0x00 31. " CD_INV ,eSDHC Card Detect Invert" "Not inverted,Inverted" bitfld.long 0x00 30. " WP_INV ,eSDHC Write Protect Invert" "Not inverted,Inverted" endif endian.le width 0x0B tree.end endif sif cpuis("LS1012A")||cpuis("LS10?3A")||cpuis("LS10?6A") tree "RCPM (Run Control and Power Management)" base ad:0x1EE2000 width 18. endian.be rgroup.long 0x4C++0x03 line.long 0x00 "TWAITSR,Thread Wait Status Register" bitfld.long 0x00 31. " T31 ,Core [31] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 30. " T30 ,Core [30] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 29. " T29 ,Core [29] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 28. " T28 ,Core [28] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 27. " T27 ,Core [27] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 26. " T26 ,Core [26] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 25. " T25 ,Core [25] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 24. " T24 ,Core [24] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 23. " T23 ,Core [23] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 22. " T22 ,Core [22] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 21. " T21 ,Core [21] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 20. " T20 ,Core [20] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 19. " T19 ,Core [19] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 18. " T18 ,Core [18] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 17. " T17 ,Core [17] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 16. " T16 ,Core [16] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 15. " T15 ,Core [15] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 14. " T14 ,Core [14] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 13. " T13 ,Core [13] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 12. " T12 ,Core [12] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 11. " T11 ,Core [11] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 10. " T10 ,Core [10] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 9. " T9 ,Core [9] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 8. " T8 ,Core [8] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 7. " T7 ,Core [7] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 6. " T6 ,Core [6] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 5. " T5 ,Core [5] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 4. " T4 ,Core [4] STANDBYWFI (PW15) status" "Off,On" newline bitfld.long 0x00 3. " T3 ,Core [3] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 2. " T2 ,Core [2] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 1. " T1 ,Core [1] STANDBYWFI (PW15) status" "Off,On" bitfld.long 0x00 0. " T0 ,Core [0] STANDBYWFI (PW15) status" "Off,On" sif cpuis("LS10?6A") group.long 0x8C++0x03 line.long 0x00 "IPPDEXPCR,IP Powerdown Exception Control Register" bitfld.long 0x00 31. " MAC1_1 ,Frame Manager 1 MAC1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 30. " MAC1_2 ,Frame Manager 1 MAC2 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 29. " MAC1_3 ,Frame Manager 1 MAC3 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 28. " MAC1_4 ,Frame Manager 1 MAC4 powerdown exception" "Not powerdown,Powerdown" newline bitfld.long 0x00 27. " MAC1_5 ,Frame Manager 1 MAC5 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 26. " MAC1_6 ,Frame Manager 1 MAC6 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 23. " MAC1_9 ,Frame Manager 1 MAC9 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 22. " MAC1_10 ,Frame Manager 1 MAC10 powerdown exception" "Not powerdown,Powerdown" newline bitfld.long 0x00 21. " I2C1 ,I2C1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 20. " LPUART1 ,LPUART1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 19. " FlexTimer1 ,FlexTimer1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 18. " OCRAM1 ,OCRAM1 powerdown exception" "Not powerdown,Powerdown" newline bitfld.long 0x00 6. " GPIO1 ,GPIO1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 3. " FM1 ,FM1 powerdown exception" "Not powerdown,Powerdown" endif newline sif !cpuis("LS1012A") group.long 0xD0++0x03 line.long 0x00 "PCPH20SR_SET/CLR,Physical Core PH20 Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " PC[31] ,Physical core 31 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Physical core 30 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Physical core 29 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Physical core 28 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Physical core 27 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Physical core 26 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Physical core 25 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Physical core 24 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Physical core 23 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Physical core 22 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Physical core 21 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Physical core 20 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Physical core 19 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Physical core 18 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Physical core 17 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Physical core 16 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Physical core 15 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Physical core 14 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Physical core 13 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Physical core 12 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Physical core 11 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Physical core 10 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Physical core 9 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Physical core 8 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Physical core 7 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Physical core 6 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Physical core 5 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Physical core 4 PH20 status." "Not in PH20,PH20" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Physical core 3 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Physical core 2 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Physical core 1 PH20 status." "Not in PH20,PH20" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Physical core 0 PH20 status." "Not in PH20,PH20" group.long 0xDC++0x03 line.long 0x00 "PCPH20PSR,Physical Core PH20 Previous Status Register" bitfld.long 0x00 31. " PC_P_PH20[31] ,Physical core 31 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 30. " [30] ,Physical core 30 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 29. " [29] ,Physical core 29 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 28. " [28] ,Physical core 28 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 27. " PC_P_PH20[27] ,Physical core 27 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 26. " [26] ,Physical core 26 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 25. " [25] ,Physical core 25 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 24. " [24] ,Physical core 24 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 23. " PC_P_PH20[23] ,Physical core 23 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 22. " [22] ,Physical core 22 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 21. " [21] ,Physical core 21 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 20. " [20] ,Physical core 20 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 19. " PC_P_PH20[19] ,Physical core 19 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 18. " [18] ,Physical core 18 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 17. " [17] ,Physical core 17 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 16. " [16] ,Physical core 16 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 15. " PC_P_PH20[15] ,Physical core 15 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 14. " [14] ,Physical core 14 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 13. " [13] ,Physical core 13 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 12. " [12] ,Physical core 12 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 11. " PC_P_PH20[11] ,Physical core 11 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 10. " [10] ,Physical core 10 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 9. " [9] ,Physical core 9 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 8. " [8] ,Physical core 8 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 7. " PC_P_PH20[7] ,Physical core 7 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 6. " [6] ,Physical core 6 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 5. " [5] ,Physical core 5 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 4. " [4] ,Physical core 4 PH20 previous status." "Not in PH20,PH20" newline bitfld.long 0x00 3. " PC_P_PH20[3] ,Physical core 3 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 2. " [2] ,Physical core 2 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 1. " [1] ,Physical core 1 PH20 previous status." "Not in PH20,PH20" bitfld.long 0x00 0. " [0] ,Physical core 0 PH20 previous status." "Not in PH20,PH20" endif newline group.long 0x130++0x03 line.long 0x00 "POWMGTCSR,Power Management Control and Status Register" bitfld.long 0x00 31. " SD_PD ,SerDes Protocol Converter Powerdown Control" "Not powerdown,Powerdown" bitfld.long 0x00 20. " LPM20_REQ ,LMP2 State Request" "Not requested,Requested" bitfld.long 0x00 9. " LPM20_ST ,LPM20 status. Device is attempting to reach LPM20 state" "Not attempting,Attempting" eventfld.long 0x00 8. " P_LPM20_ST ,Previous LPM20 status. Device was attempting to reach LPM20 state" "Not attempting,Attempting" sif !cpuis("LS10?6A") group.long 0x140++0x03 line.long 0x00 "IPPDEXPCR,IP Powerdown Exception Control Register" sif cpuis("LS1012A") bitfld.long 0x00 31. " PFE_MAC1 ,Frame Manager 1 MAC1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 30. " PFE_MAC2 ,Frame Manager 1 MAC2 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 29. " PFE_PE ,Frame Manager 1 MAC3 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 28. " PFE_250M ,Frame Manager 1 MAC4 powerdown exception" "Not powerdown,Powerdown" newline else bitfld.long 0x00 31. " MAC1_1 ,Frame Manager 1 MAC1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 30. " MAC1_2 ,Frame Manager 1 MAC2 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 29. " MAC1_3 ,Frame Manager 1 MAC3 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 28. " MAC1_4 ,Frame Manager 1 MAC4 powerdown exception" "Not powerdown,Powerdown" newline bitfld.long 0x00 27. " MAC1_5 ,Frame Manager 1 MAC5 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 26. " MAC1_6 ,Frame Manager 1 MAC6 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 23. " MAC1_9 ,Frame Manager 1 MAC9 powerdown exception" "Not powerdown,Powerdown" newline endif bitfld.long 0x00 19. " I2C1 ,I2C1 powerdown exception" "Not powerdown,Powerdown" newline sif !cpuis("LS1012A") bitfld.long 0x00 18. " LPUART1 ,LPUART1 powerdown exception" "Not powerdown,Powerdown" newline endif bitfld.long 0x00 17. " FlexTimer1 ,FlexTimer1 powerdown exception" "Not powerdown,Powerdown" bitfld.long 0x00 16. " OCRAM1 ,OCRAM1 powerdown exception" "Not powerdown,Powerdown" newline bitfld.long 0x00 6. " GPIO1 ,GPIO1 powerdown exception" "Not powerdown,Powerdown" sif cpuis("LS1012A") bitfld.long 0x00 5. " PFE ,PFE powerdown exception" "Not powerdown,Powerdown" else bitfld.long 0x00 3. " FM1 ,FM1 powerdown exception" "Not powerdown,Powerdown" endif endif newline sif cpuis("LS10?6A") group.long 0x15C++0x03 line.long 0x00 "NFIQOUTR,nFIQOUT Interrupt Register" bitfld.long 0x00 31. " IMO[31] ,Interrupt mask core [31]" "0,1" bitfld.long 0x00 30. " [30] ,Interrupt mask core [30]" "0,1" bitfld.long 0x00 29. " [29] ,Interrupt mask core [29]" "0,1" bitfld.long 0x00 28. " [28] ,Interrupt mask core [28]" "0,1" newline bitfld.long 0x00 27. " [27] ,Interrupt mask core [27]" "0,1" bitfld.long 0x00 26. " [26] ,Interrupt mask core [26]" "0,1" bitfld.long 0x00 25. " [25] ,Interrupt mask core [25]" "0,1" bitfld.long 0x00 24. " [24] ,Interrupt mask core [24]" "0,1" newline bitfld.long 0x00 23. " [23] ,Interrupt mask core [23]" "0,1" bitfld.long 0x00 22. " [22] ,Interrupt mask core [22]" "0,1" bitfld.long 0x00 21. " [21] ,Interrupt mask core [21]" "0,1" bitfld.long 0x00 20. " [20] ,Interrupt mask core [20]" "0,1" newline bitfld.long 0x00 19. " [19] ,Interrupt mask core [19]" "0,1" bitfld.long 0x00 18. " [18] ,Interrupt mask core [18]" "0,1" bitfld.long 0x00 17. " [17] ,Interrupt mask core [17]" "0,1" bitfld.long 0x00 16. " [16] ,Interrupt mask core [16]" "0,1" newline bitfld.long 0x00 15. " [15] ,Interrupt mask core [15]" "0,1" bitfld.long 0x00 14. " [14] ,Interrupt mask core [14]" "0,1" bitfld.long 0x00 13. " [13] ,Interrupt mask core [13]" "0,1" bitfld.long 0x00 12. " [12] ,Interrupt mask core [12]" "0,1" newline bitfld.long 0x00 11. " [11] ,Interrupt mask core [11]" "0,1" bitfld.long 0x00 10. " [10] ,Interrupt mask core [10]" "0,1" bitfld.long 0x00 9. " [9] ,Interrupt mask core [9]" "0,1" bitfld.long 0x00 8. " [8] ,Interrupt mask core [8]" "0,1" newline bitfld.long 0x00 7. " [7] ,Interrupt mask core [7]" "0,1" bitfld.long 0x00 6. " [6] ,Interrupt mask core [6]" "0,1" bitfld.long 0x00 5. " [5] ,Interrupt mask core [5]" "0,1" bitfld.long 0x00 4. " [4] ,Interrupt mask core [4]" "0,1" newline bitfld.long 0x00 3. " [3] ,Interrupt mask core [3]" "0,1" bitfld.long 0x00 2. " [2] ,Interrupt mask core [2]" "0,1" bitfld.long 0x00 1. " [1] ,Interrupt mask core [1]" "0,1" bitfld.long 0x00 0. " [0] ,Interrupt mask core [0]" "0,1" group.long 0x16C++0x03 line.long 0x00 "NIRQOUT,nIRQOUT Interrupt Mask Register" bitfld.long 0x00 31. " IMO[31] ,Interrupt mask core [31]" "0,1" bitfld.long 0x00 30. " [30] ,Interrupt mask core [30]" "0,1" bitfld.long 0x00 29. " [29] ,Interrupt mask core [29]" "0,1" bitfld.long 0x00 28. " [28] ,Interrupt mask core [28]" "0,1" newline bitfld.long 0x00 27. " [27] ,Interrupt mask core [27]" "0,1" bitfld.long 0x00 26. " [26] ,Interrupt mask core [26]" "0,1" bitfld.long 0x00 25. " [25] ,Interrupt mask core [25]" "0,1" bitfld.long 0x00 24. " [24] ,Interrupt mask core [24]" "0,1" newline bitfld.long 0x00 23. " [23] ,Interrupt mask core [23]" "0,1" bitfld.long 0x00 22. " [22] ,Interrupt mask core [22]" "0,1" bitfld.long 0x00 21. " [21] ,Interrupt mask core [21]" "0,1" bitfld.long 0x00 20. " [20] ,Interrupt mask core [20]" "0,1" newline bitfld.long 0x00 19. " [19] ,Interrupt mask core [19]" "0,1" bitfld.long 0x00 18. " [18] ,Interrupt mask core [18]" "0,1" bitfld.long 0x00 17. " [17] ,Interrupt mask core [17]" "0,1" bitfld.long 0x00 16. " [16] ,Interrupt mask core [16]" "0,1" newline bitfld.long 0x00 15. " [15] ,Interrupt mask core [15]" "0,1" bitfld.long 0x00 14. " [14] ,Interrupt mask core [14]" "0,1" bitfld.long 0x00 13. " [13] ,Interrupt mask core [13]" "0,1" bitfld.long 0x00 12. " [12] ,Interrupt mask core [12]" "0,1" newline bitfld.long 0x00 11. " [11] ,Interrupt mask core [11]" "0,1" bitfld.long 0x00 10. " [10] ,Interrupt mask core [10]" "0,1" bitfld.long 0x00 9. " [9] ,Interrupt mask core [9]" "0,1" bitfld.long 0x00 8. " [8] ,Interrupt mask core [8]" "0,1" newline bitfld.long 0x00 7. " [7] ,Interrupt mask core [7]" "0,1" bitfld.long 0x00 6. " [6] ,Interrupt mask core [6]" "0,1" bitfld.long 0x00 5. " [5] ,Interrupt mask core [5]" "0,1" bitfld.long 0x00 4. " [4] ,Interrupt mask core [4]" "0,1" newline bitfld.long 0x00 3. " [3] ,Interrupt mask core [3]" "0,1" bitfld.long 0x00 2. " [2] ,Interrupt mask core [2]" "0,1" bitfld.long 0x00 1. " [1] ,Interrupt mask core [1]" "0,1" bitfld.long 0x00 0. " [0] ,Interrupt mask core [0]" "0,1" else group.long 0x15C++0x03 line.long 0x00 "NIRQOUT,nIRQOUT Interrupt Mask Register" bitfld.long 0x00 31. " IMO[31] ,Interrupt mask core [31]" "0,1" bitfld.long 0x00 30. " [30] ,Interrupt mask core [30]" "0,1" bitfld.long 0x00 29. " [29] ,Interrupt mask core [29]" "0,1" bitfld.long 0x00 28. " [28] ,Interrupt mask core [28]" "0,1" newline bitfld.long 0x00 27. " [27] ,Interrupt mask core [27]" "0,1" bitfld.long 0x00 26. " [26] ,Interrupt mask core [26]" "0,1" bitfld.long 0x00 25. " [25] ,Interrupt mask core [25]" "0,1" bitfld.long 0x00 24. " [24] ,Interrupt mask core [24]" "0,1" newline bitfld.long 0x00 23. " [23] ,Interrupt mask core [23]" "0,1" bitfld.long 0x00 22. " [22] ,Interrupt mask core [22]" "0,1" bitfld.long 0x00 21. " [21] ,Interrupt mask core [21]" "0,1" bitfld.long 0x00 20. " [20] ,Interrupt mask core [20]" "0,1" newline bitfld.long 0x00 19. " [19] ,Interrupt mask core [19]" "0,1" bitfld.long 0x00 18. " [18] ,Interrupt mask core [18]" "0,1" bitfld.long 0x00 17. " [17] ,Interrupt mask core [17]" "0,1" bitfld.long 0x00 16. " [16] ,Interrupt mask core [16]" "0,1" newline bitfld.long 0x00 15. " [15] ,Interrupt mask core [15]" "0,1" bitfld.long 0x00 14. " [14] ,Interrupt mask core [14]" "0,1" bitfld.long 0x00 13. " [13] ,Interrupt mask core [13]" "0,1" bitfld.long 0x00 12. " [12] ,Interrupt mask core [12]" "0,1" newline bitfld.long 0x00 11. " [11] ,Interrupt mask core [11]" "0,1" bitfld.long 0x00 10. " [10] ,Interrupt mask core [10]" "0,1" bitfld.long 0x00 9. " [9] ,Interrupt mask core [9]" "0,1" bitfld.long 0x00 8. " [8] ,Interrupt mask core [8]" "0,1" newline bitfld.long 0x00 7. " [7] ,Interrupt mask core [7]" "0,1" bitfld.long 0x00 6. " [6] ,Interrupt mask core [6]" "0,1" bitfld.long 0x00 5. " [5] ,Interrupt mask core [5]" "0,1" bitfld.long 0x00 4. " [4] ,Interrupt mask core [4]" "0,1" newline bitfld.long 0x00 3. " [3] ,Interrupt mask core [3]" "0,1" bitfld.long 0x00 2. " [2] ,Interrupt mask core [2]" "0,1" bitfld.long 0x00 1. " [1] ,Interrupt mask core [1]" "0,1" bitfld.long 0x00 0. " [0] ,Interrupt mask core [0]" "0,1" group.long 0x16C++0x03 line.long 0x00 "NFIQOUTR,nFIQOUT Interrupt Register" bitfld.long 0x00 31. " IMO[31] ,Interrupt mask core [31]" "0,1" bitfld.long 0x00 30. " [30] ,Interrupt mask core [30]" "0,1" bitfld.long 0x00 29. " [29] ,Interrupt mask core [29]" "0,1" bitfld.long 0x00 28. " [28] ,Interrupt mask core [28]" "0,1" newline bitfld.long 0x00 27. " [27] ,Interrupt mask core [27]" "0,1" bitfld.long 0x00 26. " [26] ,Interrupt mask core [26]" "0,1" bitfld.long 0x00 25. " [25] ,Interrupt mask core [25]" "0,1" bitfld.long 0x00 24. " [24] ,Interrupt mask core [24]" "0,1" newline bitfld.long 0x00 23. " [23] ,Interrupt mask core [23]" "0,1" bitfld.long 0x00 22. " [22] ,Interrupt mask core [22]" "0,1" bitfld.long 0x00 21. " [21] ,Interrupt mask core [21]" "0,1" bitfld.long 0x00 20. " [20] ,Interrupt mask core [20]" "0,1" newline bitfld.long 0x00 19. " [19] ,Interrupt mask core [19]" "0,1" bitfld.long 0x00 18. " [18] ,Interrupt mask core [18]" "0,1" bitfld.long 0x00 17. " [17] ,Interrupt mask core [17]" "0,1" bitfld.long 0x00 16. " [16] ,Interrupt mask core [16]" "0,1" newline bitfld.long 0x00 15. " [15] ,Interrupt mask core [15]" "0,1" bitfld.long 0x00 14. " [14] ,Interrupt mask core [14]" "0,1" bitfld.long 0x00 13. " [13] ,Interrupt mask core [13]" "0,1" bitfld.long 0x00 12. " [12] ,Interrupt mask core [12]" "0,1" newline bitfld.long 0x00 11. " [11] ,Interrupt mask core [11]" "0,1" bitfld.long 0x00 10. " [10] ,Interrupt mask core [10]" "0,1" bitfld.long 0x00 9. " [9] ,Interrupt mask core [9]" "0,1" bitfld.long 0x00 8. " [8] ,Interrupt mask core [8]" "0,1" newline bitfld.long 0x00 7. " [7] ,Interrupt mask core [7]" "0,1" bitfld.long 0x00 6. " [6] ,Interrupt mask core [6]" "0,1" bitfld.long 0x00 5. " [5] ,Interrupt mask core [5]" "0,1" bitfld.long 0x00 4. " [4] ,Interrupt mask core [4]" "0,1" newline bitfld.long 0x00 3. " [3] ,Interrupt mask core [3]" "0,1" bitfld.long 0x00 2. " [2] ,Interrupt mask core [2]" "0,1" bitfld.long 0x00 1. " [1] ,Interrupt mask core [1]" "0,1" bitfld.long 0x00 0. " [0] ,Interrupt mask core [0]" "0,1" endif endian.le width 0x0B tree.end endif sif cpuis("LS10?3A")||cpuis("LS10?4A")||cpuis("LS10?8A") tree.open "QE (QUICC Engine)" base ad:0x2400000 endian.be tree "Serial DMA" endian.be width 8. group.long 0x4000++0x07 line.long 0x00 "SDSR,Serial DMA Status Register" eventfld.long 0x00 25. " BER_1 ,Bus 1 error event" "Not occurred,Occurred" line.long 0x04 "SDMR,Serial DMA Mode Register" bitfld.long 0x04 31. " GLB_1_MSK ,Mask global mode on bus 1" "Masked,Enabled" bitfld.long 0x04 29. " ADR_SEL ,Address match bus select mode" "BMR reg in UEC,Address match" bitfld.long 0x04 25. " BER_1_MSK ,Mask bus 1 error events" "Masked,Enabled" bitfld.long 0x04 23. " EB1_MSK ,Mask emergency on external bus 1" "Masked,Enabled" newline bitfld.long 0x04 19. " ER1_MSK ,Mask emergency on Multi-user RAM port 1" "Masked,Enabled" bitfld.long 0x04 18. " ER2_MSK ,Mask emergency on Multi-user RAM port 2" "Masked,Enabled" bitfld.long 0x04 13.--15. " CEN ,SDMA temporary buffer size" "512 Bytes,1 Kbyte,1.5 Kbytes,2 Kbytes,2.5 Kbytes,3 Kbytes,?..." newline bitfld.long 0x04 9. " SBER_1 ,Stop at bus error event on bus 1" "Don't stop,Stop" bitfld.long 0x04 6.--7. " EB1_PR ,Set priority level on bus 1" "0 (lowest),1,2,3 (highest)" bitfld.long 0x04 3. " ER1_PR ,Set priority on level on Multi-user RAM port 1" "Low,High" bitfld.long 0x04 2. " ER21_PR ,Set priority on level on Multi-user RAM port 2" "Low,High" group.long 0x8++0x03 line.long 0x00 "SDTR1,Serial DMA Threshold Register 1" bitfld.long 0x00 24.--28. " CQTH ,Command queue threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--21. " RBTH ,Read internal data buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WBTH ,Write internal data buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC++0x03 line.long 0x00 "SDTR2,Serial DMA Threshold Register 2" bitfld.long 0x00 24.--28. " CQTH ,Command queue threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--21. " RBTH ,Read internal data buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WBTH ,Write internal data buffer threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "SDHY1,Serial DMA Hysteresis Register 1" bitfld.long 0x00 24.--28. " CQHY ,Command queue hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--21. " RBHY ,Read internal data buffer hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WBHY ,Write internal data buffer hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "SDHY2,Serial DMA Hysteresis Register 2" bitfld.long 0x00 24.--28. " CQHY ,Command queue hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--21. " RBHY ,Read internal data buffer hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " WBHY ,Write internal data buffer hysteresis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline group.long 0x18++0x03 line.long 0x00 "SDTA1,Serial DMA Transfer Address Register 1" eventfld.long 0x00 31. " TA[31] ,Transfer address accessed during current bus transaction, bit 31" "0,1" eventfld.long 0x00 30. " [30] ,Transfer address accessed during current bus transaction, bit 30" "0,1" eventfld.long 0x00 29. " [29] ,Transfer address accessed during current bus transaction, bit 29" "0,1" eventfld.long 0x00 28. " [28] ,Transfer address accessed during current bus transaction, bit 28" "0,1" eventfld.long 0x00 27. " [27] ,Transfer address accessed during current bus transaction, bit 27" "0,1" eventfld.long 0x00 26. " [26] ,Transfer address accessed during current bus transaction, bit 26" "0,1" eventfld.long 0x00 25. " [25] ,Transfer address accessed during current bus transaction, bit 25" "0,1" eventfld.long 0x00 24. " [24] ,Transfer address accessed during current bus transaction, bit 24" "0,1" newline eventfld.long 0x00 23. " [23] ,Transfer address accessed during current bus transaction, bit 23" "0,1" eventfld.long 0x00 22. " [22] ,Transfer address accessed during current bus transaction, bit 22" "0,1" eventfld.long 0x00 21. " [21] ,Transfer address accessed during current bus transaction, bit 21" "0,1" eventfld.long 0x00 20. " [20] ,Transfer address accessed during current bus transaction, bit 20" "0,1" eventfld.long 0x00 19. " [19] ,Transfer address accessed during current bus transaction, bit 19" "0,1" eventfld.long 0x00 18. " [18] ,Transfer address accessed during current bus transaction, bit 18" "0,1" eventfld.long 0x00 17. " [17] ,Transfer address accessed during current bus transaction, bit 17" "0,1" eventfld.long 0x00 16. " [16] ,Transfer address accessed during current bus transaction, bit 16" "0,1" newline eventfld.long 0x00 15. " [15] ,Transfer address accessed during current bus transaction, bit 15" "0,1" eventfld.long 0x00 14. " [14] ,Transfer address accessed during current bus transaction, bit 14" "0,1" eventfld.long 0x00 13. " [13] ,Transfer address accessed during current bus transaction, bit 13" "0,1" eventfld.long 0x00 12. " [12] ,Transfer address accessed during current bus transaction, bit 12" "0,1" eventfld.long 0x00 11. " [11] ,Transfer address accessed during current bus transaction, bit 11" "0,1" eventfld.long 0x00 10. " [10] ,Transfer address accessed during current bus transaction, bit 10" "0,1" eventfld.long 0x00 9. " [9] ,Transfer address accessed during current bus transaction, bit 9" "0,1" eventfld.long 0x00 8. " [8] ,Transfer address accessed during current bus transaction, bit 8" "0,1" newline eventfld.long 0x00 7. " [7] ,Transfer address accessed during current bus transaction, bit 7" "0,1" eventfld.long 0x00 6. " [6] ,Transfer address accessed during current bus transaction, bit 6" "0,1" eventfld.long 0x00 5. " [5] ,Transfer address accessed during current bus transaction, bit 5" "0,1" eventfld.long 0x00 4. " [4] ,Transfer address accessed during current bus transaction, bit 4" "0,1" eventfld.long 0x00 3. " [3] ,Transfer address accessed during current bus transaction, bit 3" "0,1" eventfld.long 0x00 2. " [2] ,Transfer address accessed during current bus transaction, bit 2" "0,1" eventfld.long 0x00 1. " [1] ,Transfer address accessed during current bus transaction, bit 1" "0,1" eventfld.long 0x00 0. " [0] ,Transfer address accessed during current bus transaction, bit 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "SDTA2,Serial DMA Transfer Address Register 2" eventfld.long 0x00 31. " TA[31] ,Transfer address accessed during current bus transaction, bit 31" "0,1" eventfld.long 0x00 30. " [30] ,Transfer address accessed during current bus transaction, bit 30" "0,1" eventfld.long 0x00 29. " [29] ,Transfer address accessed during current bus transaction, bit 29" "0,1" eventfld.long 0x00 28. " [28] ,Transfer address accessed during current bus transaction, bit 28" "0,1" eventfld.long 0x00 27. " [27] ,Transfer address accessed during current bus transaction, bit 27" "0,1" eventfld.long 0x00 26. " [26] ,Transfer address accessed during current bus transaction, bit 26" "0,1" eventfld.long 0x00 25. " [25] ,Transfer address accessed during current bus transaction, bit 25" "0,1" eventfld.long 0x00 24. " [24] ,Transfer address accessed during current bus transaction, bit 24" "0,1" newline eventfld.long 0x00 23. " [23] ,Transfer address accessed during current bus transaction, bit 23" "0,1" eventfld.long 0x00 22. " [22] ,Transfer address accessed during current bus transaction, bit 22" "0,1" eventfld.long 0x00 21. " [21] ,Transfer address accessed during current bus transaction, bit 21" "0,1" eventfld.long 0x00 20. " [20] ,Transfer address accessed during current bus transaction, bit 20" "0,1" eventfld.long 0x00 19. " [19] ,Transfer address accessed during current bus transaction, bit 19" "0,1" eventfld.long 0x00 18. " [18] ,Transfer address accessed during current bus transaction, bit 18" "0,1" eventfld.long 0x00 17. " [17] ,Transfer address accessed during current bus transaction, bit 17" "0,1" eventfld.long 0x00 16. " [16] ,Transfer address accessed during current bus transaction, bit 16" "0,1" newline eventfld.long 0x00 15. " [15] ,Transfer address accessed during current bus transaction, bit 15" "0,1" eventfld.long 0x00 14. " [14] ,Transfer address accessed during current bus transaction, bit 14" "0,1" eventfld.long 0x00 13. " [13] ,Transfer address accessed during current bus transaction, bit 13" "0,1" eventfld.long 0x00 12. " [12] ,Transfer address accessed during current bus transaction, bit 12" "0,1" eventfld.long 0x00 11. " [11] ,Transfer address accessed during current bus transaction, bit 11" "0,1" eventfld.long 0x00 10. " [10] ,Transfer address accessed during current bus transaction, bit 10" "0,1" eventfld.long 0x00 9. " [9] ,Transfer address accessed during current bus transaction, bit 9" "0,1" eventfld.long 0x00 8. " [8] ,Transfer address accessed during current bus transaction, bit 8" "0,1" newline eventfld.long 0x00 7. " [7] ,Transfer address accessed during current bus transaction, bit 7" "0,1" eventfld.long 0x00 6. " [6] ,Transfer address accessed during current bus transaction, bit 6" "0,1" eventfld.long 0x00 5. " [5] ,Transfer address accessed during current bus transaction, bit 5" "0,1" eventfld.long 0x00 4. " [4] ,Transfer address accessed during current bus transaction, bit 4" "0,1" eventfld.long 0x00 3. " [3] ,Transfer address accessed during current bus transaction, bit 3" "0,1" eventfld.long 0x00 2. " [2] ,Transfer address accessed during current bus transaction, bit 2" "0,1" eventfld.long 0x00 1. " [1] ,Transfer address accessed during current bus transaction, bit 1" "0,1" eventfld.long 0x00 0. " [0] ,Transfer address accessed during current bus transaction, bit 0" "0,1" line.long 0x00 "SDTM1,Serial DMA Transfer Communication Channel Number Register 1" eventfld.long 0x00 31. " MSNUM[7] ,MSNUM served during current bus transaction, bit 7" "0,1" eventfld.long 0x00 30. " [6] ,MSNUM served during current bus transaction, bit 6" "0,1" eventfld.long 0x00 29. " [5] ,MSNUM served during current bus transaction, bit 5" "0,1" eventfld.long 0x00 28. " [4] ,MSNUM served during current bus transaction, bit 4" "0,1" eventfld.long 0x00 27. " [3] ,MSNUM served during current bus transaction, bit 3" "0,1" eventfld.long 0x00 26. " [2] ,MSNUM served during current bus transaction, bit 2" "0,1" eventfld.long 0x00 25. " [1] ,MSNUM served during current bus transaction, bit 1" "0,1" eventfld.long 0x00 24. " [0] ,MSNUM served during current bus transaction, bit 0" "0,1" line.long 0x00 "SDTM2,Serial DMA Transfer Communication Channel Number Register 2" eventfld.long 0x00 31. " MSNUM[7] ,MSNUM served during current bus transaction, bit 7" "0,1" eventfld.long 0x00 30. " [6] ,MSNUM served during current bus transaction, bit 6" "0,1" eventfld.long 0x00 29. " [5] ,MSNUM served during current bus transaction, bit 5" "0,1" eventfld.long 0x00 28. " [4] ,MSNUM served during current bus transaction, bit 4" "0,1" eventfld.long 0x00 27. " [3] ,MSNUM served during current bus transaction, bit 3" "0,1" eventfld.long 0x00 26. " [2] ,MSNUM served during current bus transaction, bit 2" "0,1" eventfld.long 0x00 25. " [1] ,MSNUM served during current bus transaction, bit 1" "0,1" eventfld.long 0x00 24. " [0] ,MSNUM served during current bus transaction, bit 0" "0,1" newline group.long 0x4038++0x07 line.long 0x00 "SDAQR,Serial DMA Address Qualify Register" hexmask.long.word 0x00 16.--31. 1. " AQ ,Address qualifier" bitfld.long 0x00 0. " BS ,Bus select in case of address match" "No match,Address match" line.long 0x04 "SDAQMR,Serial DMA Address Qualify Mask Register" bitfld.long 0x04 31. " AM[15] ,Address mask bit 15" "0,1" bitfld.long 0x04 30. " [14] ,Address mask bit 14" "0,1" bitfld.long 0x04 29. " [13] ,Address mask bit 13" "0,1" bitfld.long 0x04 28. " [12] ,Address mask bit 12" "0,1" bitfld.long 0x04 27. " [11] ,Address mask bit 11" "0,1" bitfld.long 0x04 26. " [10] ,Address mask bit 10" "0,1" bitfld.long 0x04 25. " [9] ,Address mask bit 9" "0,1" bitfld.long 0x04 24. " [8] ,Address mask bit 8" "0,1" newline bitfld.long 0x04 23. " [7] ,Address mask bit 7" "0,1" bitfld.long 0x04 22. " [6] ,Address mask bit 6" "0,1" bitfld.long 0x04 21. " [5] ,Address mask bit 5" "0,1" bitfld.long 0x04 20. " [4] ,Address mask bit 4" "0,1" bitfld.long 0x04 19. " [3] ,Address mask bit 3" "0,1" bitfld.long 0x04 18. " [2] ,Address mask bit 2" "0,1" bitfld.long 0x04 17. " [1] ,Address mask bit 1" "0,1" bitfld.long 0x04 16. " [0] ,Address mask bit 0" "0,1" group.long 0x4044++0x03 line.long 0x00 "SDEBCR,Serial DMA Temporary Buffer Base in Multi-User RAM Value" hexmask.long 0x00 0.--24. 0x01 " BA ,Temporary Buffer base address in Multi-user RAM" endian.le width 0x0B tree.end tree "Interrupt Controller" endian.be width 8. group.long 0x80++0x03 line.long 0x00 "CICR,QUICC Engine System Interrupt Configuration Register" bitfld.long 0x00 24.--29. " HP ,Highest priority. Specify the 6-bit interrupt number" "Error (No interrupt),,,RTT,,,,,,,SDMA,,Timer1,Timer2,Timer3,Timer4,,,,,VT,,,,,EXT1,EXT2,EXT3,EXT4,,,,UCC1,,UCC3,?..." bitfld.long 0x00 22. " GRTB ,RISC Tasks B interrupts priority scheme" "Grouped,Spread" bitfld.long 0x00 21. " GRTA ,RISC Tasks A interrupts priority scheme" "Grouped,Spread" bitfld.long 0x00 19. " GZCC ,ZCC priority scheme" "Grouped,Spread" newline bitfld.long 0x00 18. " GWCC ,WCC priority scheme" "Grouped,Spread" bitfld.long 0x00 17. " GXCC ,XCC priority scheme" "Grouped,Spread" bitfld.long 0x00 16. " GYCC ,YCC priority scheme" "Grouped,Spread" bitfld.long 0x00 8.--9. " HPIT ,Highest priority interrupt position" "Low,,High,?..." group.long 0xA0++0x03 line.long 0x00 "CICNR,QUICC Engine System Interrupt Control Register" bitfld.long 0x00 30.--31. " ZCC1T ,ZCC1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 28.--29. " ZCC2T ,ZCC2 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 22.--23. " WCC1T ,WCC1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 20.--21. " WCC2T ,WCC2 priority position output interrupt type" "Low,,High,?..." newline bitfld.long 0x00 14.--15. " YCC1T ,YCC1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 12.--13. " YCC2T ,YCC2 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 6.--7. " XCC1T ,XCC1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 4.--5. " XCC2T ,XCC2 priority position output interrupt type" "Low,,High,?..." group.long 0xBC++0x03 line.long 0x00 "CRICR,QUICC Engine System RISC Interrupts Control Register" bitfld.long 0x00 30.--31. " RTB1T ,RTB1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 28.--29. " RTB2T ,RTB2 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 22.--23. " RTA1T ,RTA1 priority position output interrupt type" "Low,,High,?..." bitfld.long 0x00 20.--21. " RTA2T ,RTA2 priority position output interrupt type" "Low,,High,?..." group.long 0x98++0x03 line.long 0x00 "CIPWCC,QUICC Engine System Interrupt Priority Register for WCC Peripherals" bitfld.long 0x00 29.--31. " WCC1 ,WCC1 priority order. Defines which QE Timer error asserts its request in WCC1 priority position" ",,RTT,?..." bitfld.long 0x00 26.--28. " WCC2 ,WCC2 priority order. Defines which QE Timer error asserts its request in WCC2 priority position" ",,RTT,?..." bitfld.long 0x00 23.--25. " WCC3 ,WCC3 priority order. Defines which QE Timer error asserts its request in WCC3 priority position" ",,RTT,?..." bitfld.long 0x00 20.--22. " WCC4 ,WCC4 priority order. Defines which QE Timer error asserts its request in WCC4 priority position" ",,RTT,?..." newline bitfld.long 0x00 13.--15. " WCC5 ,WCC5 priority order. Defines which QE Timer error asserts its request in WCC5 priority position" ",,RTT,?..." bitfld.long 0x00 10.--12. " WCC6 ,WCC6 priority order. Defines which QE Timer error asserts its request in WCC6 priority position" ",,RTT,?..." bitfld.long 0x00 7.--9. " WCC7 ,WCC7 priority order. Defines which QE Timer error asserts its request in WCC7 priority position" ",,RTT,?..." bitfld.long 0x00 4.--6. " WCC8 ,WCC8 priority order. Defines which QE Timer error asserts its request in WCC8 priority position" ",,RTT,?..." group.long 0x90++0x07 line.long 0x00 "CIPXCC,QUICC Engine System Interrupt Priority Register for XCC Peripherals" bitfld.long 0x00 29.--31. " XCC1 ,XCC1 priority order. Defines which UCC asserts its request in XCC1 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 26.--28. " XCC2 ,XCC2 priority order. Defines which UCC asserts its request in XCC2 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 23.--25. " XCC3 ,XCC3 priority order. Defines which UCC asserts its request in XCC3 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 20.--22. " XCC4 ,XCC4 priority order. Defines which UCC asserts its request in XCC4 priority position" "UCC1,,UCC3,?..." newline bitfld.long 0x00 13.--15. " XCC5 ,XCC5 priority order. Defines which UCC asserts its request in XCC5 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 10.--12. " XCC6 ,XCC6 priority order. Defines which UCC asserts its request in XCC6 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 7.--9. " XCC7 ,XCC7 priority order. Defines which UCC asserts its request in XCC7 priority position" "UCC1,,UCC3,?..." bitfld.long 0x00 4.--6. " XCC8 ,XCC8 priority order. Defines which UCC asserts its request in XCC8 priority position" "UCC1,,UCC3,?..." group.long 0x9C++0x03 line.long 0x00 "CIPZCC,QUICC Engine System Interrupt Priority Register for ZCC Peripherals" bitfld.long 0x00 29.--31. " ZCC1 ,ZCC1 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC1 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 26.--28. " ZCC2 ,ZCC2 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC2 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 23.--25. " ZCC3 ,ZCC3 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC3 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 20.--22. " ZCC4 ,ZCC4 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC4 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." newline bitfld.long 0x00 13.--15. " ZCC5 ,ZCC5 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC5 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 10.--12. " ZCC6 ,ZCC6 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC6 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 7.--9. " ZCC7 ,ZCC7 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC7 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." bitfld.long 0x00 4.--6. " ZCC8 ,ZCC8 priority order. Defines which QE Timer and SDMA sys error asserts its request in ZCC8 priority position" ",SDMA Sys,,Timer1,Timer2,Timer3,Timer4,?..." group.long 0xB0++0x07 line.long 0x00 "CIPRTA,QUICC Engine System Interrupt Priority Register for RISC Tasks A" bitfld.long 0x00 29.--31. " RTA1 ,RTA1 priority order. Defines which RISC task A asserts its request in RTA1 priority position" ",,,Virtual task,?..." bitfld.long 0x00 26.--28. " RTA2 ,RTA2 priority order. Defines which RISC task A asserts its request in RTA2 priority position" ",,,Virtual task,?..." bitfld.long 0x00 23.--25. " RTA3 ,RTA3 priority order. Defines which RISC task A asserts its request in RTA3 priority position" ",,,Virtual task,?..." bitfld.long 0x00 20.--22. " RTA4 ,RTA4 priority order. Defines which RISC task A asserts its request in RTA4 priority position" ",,,Virtual task,?..." newline bitfld.long 0x00 13.--15. " RTA5 ,RTA5 priority order. Defines which RISC task A asserts its request in RTA5 priority position" ",,,Virtual task,?..." bitfld.long 0x00 10.--12. " RTA6 ,RTA6 priority order. Defines which RISC task A asserts its request in RTA6 priority position" ",,,Virtual task,?..." bitfld.long 0x00 7.--9. " RTA7 ,RTA7 priority order. Defines which RISC task A asserts its request in RTA7 priority position" ",,,Virtual task,?..." bitfld.long 0x00 4.--6. " RTA8 ,RTA8 priority order. Defines which RISC task A asserts its request in RTA8 priority position" ",,,Virtual task,?..." line.long 0x04 "CIPRTB,QUICC Engine System Interrupt Priority Register for RISC Tasks B" bitfld.long 0x04 29.--31. " RTB1 ,RTB1 priority order. Defines which RISC task B asserts its request in RTB1 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 26.--28. " RTB2 ,RTB2 priority order. Defines which RISC task B asserts its request in RTB2 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 23.--25. " RTB3 ,RTB3 priority order. Defines which RISC task B asserts its request in RTB3 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 20.--22. " RTB4 ,RTB4 priority order. Defines which RISC task B asserts its request in RTB4 priority position" "EXT1,EXT2,EXT3,EXT4,?..." newline bitfld.long 0x04 13.--15. " RTB5 ,RTB5 priority order. Defines which RISC task B asserts its request in RTB5 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 10.--12. " RTB6 ,RTB6 priority order. Defines which RISC task B asserts its request in RTB6 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 7.--9. " RTB7 ,RTB7 priority order. Defines which RISC task B asserts its request in RTB7 priority position" "EXT1,EXT2,EXT3,EXT4,?..." bitfld.long 0x04 4.--6. " RTB8 ,RTB8 priority order. Defines which RISC task B asserts its request in RTB8 priority position" "EXT1,EXT2,EXT3,EXT4,?..." rgroup.long 0x8C++0x03 line.long 0x00 "CIPNR,QUICC Engine System Interrupt Pending Register" bitfld.long 0x00 31. " UCC1 ,UCC1 interrupt receive status" "Not received,Received" bitfld.long 0x00 29. " UCC3 ,UCC3 interrupt receive status" "Not received,Received" bitfld.long 0x00 13. " RTT ,RTT interrupt receive status" "Not received,Received" bitfld.long 0x00 6. " SDMA ,SDMA interrupt receive status" "Not received,Received" newline bitfld.long 0x00 4. " Timer1 ,Timer1 interrupt receive status" "Not received,Received" bitfld.long 0x00 3. " Timer2 ,Timer2 interrupt receive status" "Not received,Received" bitfld.long 0x00 2. " Timer3 ,Timer3 interrupt receive status" "Not received,Received" bitfld.long 0x00 1. " Timer4 ,Timer4 interrupt receive status" "Not received,Received" group.long 0xA0++0x03 line.long 0x00 "CIMR,QUICC Engine System Interrupt Mask Register" bitfld.long 0x00 31. " UCC1 ,UCC1 interrupt enable" "Masked,Enabled" bitfld.long 0x00 29. " UCC3 ,UCC3 interrupt enable" "Masked,Enabled" bitfld.long 0x00 13. " RTT ,RTT interrupt interrupt enable" "Masked,Enabled" bitfld.long 0x00 6. " SDMA ,SDMA interrupt interrupt enable" "Masked,Enabled" newline bitfld.long 0x00 4. " Timer1 ,Timer1 interrupt interrupt enable" "Masked,Enabled" bitfld.long 0x00 3. " Timer2 ,Timer2 interrupt interrupt enable" "Masked,Enabled" bitfld.long 0x00 2. " Timer3 ,Timer3 interrupt interrupt enable" "Masked,Enabled" bitfld.long 0x00 1. " Timer4 ,Timer4 interrupt interrupt enable" "Masked,Enabled" group.long 0x88++0x03 line.long 0x00 "CRIPNR,QUICC Engine RISC Interrupt Pending Register" bitfld.long 0x00 28. " VT ,Virtual Tasks interrupt pending" "Idle,Pending" newline bitfld.long 0x00 23. " EXT1 ,EXT1 interrupt pending" "Idle,Pending" bitfld.long 0x00 22. " EXT2 ,EXT2 interrupt pending" "Idle,Pending" bitfld.long 0x00 21. " EXT3 ,EXT3 interrupt pending" "Idle,Pending" bitfld.long 0x00 20. " EXT4 ,EXT4 interrupt pending" "Idle,Pending" group.long 0xA4++0x03 line.long 0x00 "CRIMR,QUICC Engine RISC Interrupt Mask Register" bitfld.long 0x00 28. " VT ,Virtual Tasks pending interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 23. " EXT1 ,EXT1 pending interrupt mask" "Not masked,Masked" bitfld.long 0x00 22. " EXT2 ,EXT2 pending interrupt mask" "Not masked,Masked" bitfld.long 0x00 21. " EXT3 ,EXT3 pending interrupt mask" "Not masked,Masked" bitfld.long 0x00 20. " EXT4 ,EXT4 pending interrupt mask" "Not masked,Masked" rgroup.long 0x84++0x03 line.long 0x00 "CIVEC,QUICC Engine System Interrupt Vector Register" bitfld.long 0x00 26.--31. " IVC ,Interrupt Vector Code. Represents the unmasked interrupt source of the highest priority level" "Error (No interrupt),,,RTT,,,,,,,SDMA,,Timer1,Timer2,Timer3,Timer4,,,,,VT,,,,,EXT1,EXT2,EXT3,EXT4,,,,UCC1,,UCC3,?..." bitfld.long 0x00 0.--5. " IVC ,Interrupt Vector Code duplicate" "Error (No interrupt),,,RTT,,,,,,,SDMA,,Timer1,Timer2,Timer3,Timer4,,,,,VT,,,,,EXT1,EXT2,EXT3,EXT4,,,,UCC1,,UCC3,?..." endian.le width 0x0B tree.end tree "Communication Processor" endian.be width 8. group.long 0x00++0x07 "I-RAM" line.long 0x00 "IADD,I-RAM Address Register" bitfld.long 0x00 31. " AIE ,Auto Increment enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 0x01 " IADDR ,I-RAM address" line.long 0x04 "IDATA,I-RAM Data Register" if (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2000000)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2400000) group.long 0x100++0x03 "Control Registers" line.long 0x00 "CECR,QUICC Engine Block Command Register" bitfld.long 0x00 31. " RST ,Software reset command" "No reset,Reset" hexmask.long.word 0x00 17.--25. 1. " SBC ,Sub-block code" bitfld.long 0x00 16. " FLG ,Command semaphore flag" "Ready,Processing" bitfld.long 0x00 0.--5. " OPCODE ,Operation code" "Init Rx and Tx,Init Rx,Init Tx,Enter hunt mode,Stop Tx,Graceful stop Tx,Restart Tx,L2SWITCH cmd,Set group address,Intert cell,,Cell pool get,Cell pool put,IMA host cmd,,PUSHSCHED cmd,,,Assign page,Set last Rx req. threshold,Start flow control,Stop flow control,Assign page to device,,,,Graceful stop Rx,Restart Rx,?..." elif (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x0)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x400000) group.long 0x100++0x03 "Control Registers" line.long 0x00 "CECR,QUICC Engine Block Command Register" bitfld.long 0x00 31. " RST ,Software reset command" "No reset,Reset" hexmask.long.word 0x00 17.--25. 1. " SBC ,Sub-block code" bitfld.long 0x00 16. " FLG ,Command semaphore flag" "Ready,Processing" bitfld.long 0x00 0.--5. " OPCODE ,Operation code" "Init Rx and Tx,Init Rx,Init Tx,Enter hunt mode,Stop Tx,Graceful stop Tx,Restart Tx,,,Profibus,Reset BCS,,QMC stop Tx,QMC stop Rx,,PUSHSCHED cmd,,,Assign page,QMC restart Tx,QMC restart Rx,,Assign page to device,?..." elif (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x1E00000) group.long 0x100++0x03 "Control Registers" line.long 0x00 "CECR,QUICC Engine Block Command Register" bitfld.long 0x00 31. " RST ,Software reset command" "No reset,Reset" hexmask.long.word 0x00 17.--25. 1. " SBC ,Sub-block code" bitfld.long 0x00 16. " FLG ,Command semaphore flag" "Ready,Processing" bitfld.long 0x00 0.--5. " OPCODE ,Operation code" ",,,,,,,,Set timer,,,,,,,PUSHSCHED cmd,,,Assign page,,,,Assign page to device,?..." else group.long 0x100++0x03 "Control Registers" line.long 0x00 "CECR,QUICC Engine Block Command Register" bitfld.long 0x00 31. " RST ,Software reset command" "No reset,Reset" hexmask.long.word 0x00 17.--25. 1. " SBC ,Sub-block code" bitfld.long 0x00 16. " FLG ,Command semaphore flag" "Ready,Processing" endif group.long 0x108++0x03 line.long 0x00 "CECDR,QUICC Engine RAM Control Register" group.word 0x138++0x01 line.word 0x00 "CERCR,QUICC Engine RAM Control Register" bitfld.word 0x00 15. " MEE ,Multi-user RAM ECC enable" "Disabled,Enabled" bitfld.word 0x00 14. " IEE ,Instruction RAM ECC enable" "Disabled,Enabled" bitfld.word 0x00 11. " CIR ,Common instruction RAM mode" "Individual,Shared" group.long 0x128++0x03 line.long 0x00 "CESIMR,QUICC Engine Serial Interrupt Mask Register" bitfld.long 0x00 31. " UCC1 ,UCC1 interrupt request to QUICC Engine enable" "Masked,Enabled" bitfld.long 0x00 29. " UCC3 ,UCC3 interrupt request to QUICC Engine enable" "Masked,Enabled" bitfld.long 0x00 18. " PTP1 ,PTP1 interrupt request to QUICC Engine enable" "Masked,Enabled" newline bitfld.long 0x00 17. " PTP2 ,PTP2 interrupt request to QUICC Engine enable" "Masked,Enabled" bitfld.long 0x00 16. " RTC ,RTC interrupt request to QUICC Engine enable" "Masked,Enabled" group.long 0x1BC++0x07 line.long 0x00 "CEISER,QUICC Engine Interrupt From Serial Event Register" bitfld.long 0x00 31. " ISE0 ,UCC1 interrupt from serial event occurred" "Not occurred,Occurred" bitfld.long 0x00 29. " ISE2 ,UCC3 interrupt from serial event occurred" "Not occurred,Occurred" bitfld.long 0x00 18. " ISE13 ,PTP1 interrupt from serial event occurred" "Not occurred,Occurred" newline bitfld.long 0x00 17. " ISE14 ,PTP2 interrupt from serial event occurred" "Not occurred,Occurred" bitfld.long 0x00 16. " ISE15 ,RTC interrupt from serial event occurred" "Not occurred,Occurred" line.long 0x04 "CEISMR,QUICC Engine Interrupt From Serial Mask Register" bitfld.long 0x04 31. " ISE0 ,UCC1 interrupt from serial mask occurred" "Not occurred,Occurred" bitfld.long 0x04 29. " ISE2 ,UCC3 interrupt from serial mask occurred" "Not occurred,Occurred" bitfld.long 0x04 18. " ISE13 ,PTP1 interrupt from serial mask occurred" "Not occurred,Occurred" newline bitfld.long 0x04 17. " ISE14 ,PTP2 interrupt from serial mask occurred" "Not occurred,Occurred" bitfld.long 0x04 16. " ISE15 ,RTC interrupt from serial mask occurred" "Not occurred,Occurred" group.long 0x1B8++0x03 line.long 0x00 "CEURNR,QUICC Engine Microcode Revision Number" group.long 0x104++0x03 line.long 0x00 "CECCR,QUICC Engine Controller Configuration Register" bitfld.long 0x00 31. " TIME ,Internal timer enable" "Disabled,Enabled" bitfld.long 0x00 30. " TEC ,Timer external clock enable" "Disabled,Enabled" bitfld.long 0x00 24.--29. " TIMEP ,Timer period controls the RISC timer trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " ERM1 ,External request sensitive mode for EXT1 Pin" "Edge,Level" newline bitfld.long 0x00 22. " ERM2 ,External request sensitive mode for EXT2 Pin" "Edge,Level" bitfld.long 0x00 11. " EDM1 ,External request edge detect mode for EXT1 Pin" "High,Low" bitfld.long 0x00 10. " EDM2 ,External request edge detect mode for EXT2 Pin" "High,Low" bitfld.long 0x00 9. " EDM3 ,External request edge detect mode for EXT3 Pin" "High,Low" newline bitfld.long 0x00 8. " EDM4 ,External request edge detect mode for EXT4 Pin" "High,Low" bitfld.long 0x00 7. " ERM3 ,External request sensitive mode for EXT3 Pin" "Edge,Level" bitfld.long 0x00 6. " ERM4 ,External request sensitive mode for EXT4 Pin" "Edge,Level" group.long 0x11C++0x0B line.long 0x00 "CETSR,QUICC Engine Time-Stamp Control Register" bitfld.long 0x00 31. " EC1 ,CETSR1 external clock enable" "Disabled,Enabled" bitfld.long 0x00 26. " RTE1 ,CETSR1 time-stamp timer enable" "Disable,Enable" hexmask.long.word 0x00 16.--25. 1. " CETPS1 ,Time stamp timer pre-scale 1" newline bitfld.long 0x00 15. " EC2 ,CETSR2 external clock enable" "Disabled,Enabled" bitfld.long 0x00 10. " RTE2 ,CETSR2 time-stamp timer enable" "Disable,Enable" hexmask.long.word 0x00 0.--9. 1. " CETPS2 ,Time stamp timer pre-scale 2" line.long 0x04 "CETSR1,QUICC Engine Time-Stamp Register 1" line.long 0x08 "CETSR2,QUICC Engine Time-Stamp Register 2" group.long 0x160++0x07 line.long 0x00 "CEEXE1,QUICC Engine External Request Event Register" bitfld.long 0x00 31. " EXE0 ,External request event 0" "No event,Event" bitfld.long 0x00 30. " EXE1 ,External request event 1" "No event,Event" bitfld.long 0x00 29. " EXE2 ,External request event 2" "No event,Event" bitfld.long 0x00 28. " EXE3 ,External request event 3" "No event,Event" newline bitfld.long 0x00 27. " EXE4 ,External request event 4" "No event,Event" bitfld.long 0x00 26. " EXE5 ,External request event 5" "No event,Event" bitfld.long 0x00 25. " EXE6 ,External request event 6" "No event,Event" bitfld.long 0x00 24. " EXE7 ,External request event 7" "No event,Event" newline bitfld.long 0x00 23. " EXE8 ,External request event 8" "No event,Event" bitfld.long 0x00 22. " EXE9 ,External request event 9" "No event,Event" bitfld.long 0x00 21. " EXE10 ,External request event 10" "No event,Event" bitfld.long 0x00 20. " EXE11 ,External request event 11" "No event,Event" newline bitfld.long 0x00 19. " EXE12 ,External request event 12" "No event,Event" bitfld.long 0x00 18. " EXE13 ,External request event 13" "No event,Event" bitfld.long 0x00 17. " EXE14 ,External request event 14" "No event,Event" bitfld.long 0x00 16. " EXE15 ,External request event 15" "No event,Event" newline bitfld.long 0x00 15. " EXE16 ,External request event 16" "No event,Event" bitfld.long 0x00 14. " EXE17 ,External request event 17" "No event,Event" bitfld.long 0x00 13. " EXE18 ,External request event 18" "No event,Event" bitfld.long 0x00 12. " EXE19 ,External request event 19" "No event,Event" newline bitfld.long 0x00 11. " EXE20 ,External request event 20" "No event,Event" bitfld.long 0x00 10. " EXE21 ,External request event 21" "No event,Event" bitfld.long 0x00 9. " EXE22 ,External request event 22" "No event,Event" bitfld.long 0x00 8. " EXE23 ,External request event 23" "No event,Event" newline bitfld.long 0x00 7. " EXE24 ,External request event 24" "No event,Event" bitfld.long 0x00 6. " EXE25 ,External request event 25" "No event,Event" bitfld.long 0x00 5. " EXE26 ,External request event 26" "No event,Event" bitfld.long 0x00 4. " EXE27 ,External request event 27" "No event,Event" newline bitfld.long 0x00 3. " EXE28 ,External request event 28" "No event,Event" bitfld.long 0x00 2. " EXE29 ,External request event 29" "No event,Event" bitfld.long 0x00 1. " EXE30 ,External request event 30" "No event,Event" bitfld.long 0x00 0. " EXE31 ,External request event 31" "No event,Event" line.long 0x04 "CEEXM1,QUICC Engine External Request Mask Register" bitfld.long 0x04 31. " EXE0 ,External request mask 0" "Not masked,Masked" bitfld.long 0x04 30. " EXE1 ,External request mask 1" "Not masked,Masked" bitfld.long 0x04 29. " EXE2 ,External request mask 2" "Not masked,Masked" bitfld.long 0x04 28. " EXE3 ,External request mask 3" "Not masked,Masked" newline bitfld.long 0x04 27. " EXE4 ,External request mask 4" "Not masked,Masked" bitfld.long 0x04 26. " EXE5 ,External request mask 5" "Not masked,Masked" bitfld.long 0x04 25. " EXE6 ,External request mask 6" "Not masked,Masked" bitfld.long 0x04 24. " EXE7 ,External request mask 7" "Not masked,Masked" newline bitfld.long 0x04 23. " EXE8 ,External request mask 8" "Not masked,Masked" bitfld.long 0x04 22. " EXE9 ,External request mask 9" "Not masked,Masked" bitfld.long 0x04 21. " EXE10 ,External request mask 10" "Not masked,Masked" bitfld.long 0x04 20. " EXE11 ,External request mask 11" "Not masked,Masked" newline bitfld.long 0x04 19. " EXE12 ,External request mask 12" "Not masked,Masked" bitfld.long 0x04 18. " EXE13 ,External request mask 13" "Not masked,Masked" bitfld.long 0x04 17. " EXE14 ,External request mask 14" "Not masked,Masked" bitfld.long 0x04 16. " EXE15 ,External request mask 15" "Not masked,Masked" newline bitfld.long 0x04 15. " EXE16 ,External request mask 16" "Not masked,Masked" bitfld.long 0x04 14. " EXE17 ,External request mask 17" "Not masked,Masked" bitfld.long 0x04 13. " EXE18 ,External request mask 18" "Not masked,Masked" bitfld.long 0x04 12. " EXE19 ,External request mask 19" "Not masked,Masked" newline bitfld.long 0x04 11. " EXE20 ,External request mask 20" "Not masked,Masked" bitfld.long 0x04 10. " EXE21 ,External request mask 21" "Not masked,Masked" bitfld.long 0x04 9. " EXE22 ,External request mask 22" "Not masked,Masked" bitfld.long 0x04 8. " EXE23 ,External request mask 23" "Not masked,Masked" newline bitfld.long 0x04 7. " EXE24 ,External request mask 24" "Not masked,Masked" bitfld.long 0x04 6. " EXE25 ,External request mask 25" "Not masked,Masked" bitfld.long 0x04 5. " EXE26 ,External request mask 26" "Not masked,Masked" bitfld.long 0x04 4. " EXE27 ,External request mask 27" "Not masked,Masked" newline bitfld.long 0x04 3. " EXE28 ,External request mask 28" "Not masked,Masked" bitfld.long 0x04 2. " EXE29 ,External request mask 29" "Not masked,Masked" bitfld.long 0x04 1. " EXE30 ,External request mask 30" "Not masked,Masked" bitfld.long 0x04 0. " EXE31 ,External request mask 31" "Not masked,Masked" group.long 0x164++0x07 line.long 0x00 "CEEXE2,QUICC Engine External Request Event Register" bitfld.long 0x00 31. " EXE0 ,External request event 0" "No event,Event" bitfld.long 0x00 30. " EXE1 ,External request event 1" "No event,Event" bitfld.long 0x00 29. " EXE2 ,External request event 2" "No event,Event" bitfld.long 0x00 28. " EXE3 ,External request event 3" "No event,Event" newline bitfld.long 0x00 27. " EXE4 ,External request event 4" "No event,Event" bitfld.long 0x00 26. " EXE5 ,External request event 5" "No event,Event" bitfld.long 0x00 25. " EXE6 ,External request event 6" "No event,Event" bitfld.long 0x00 24. " EXE7 ,External request event 7" "No event,Event" newline bitfld.long 0x00 23. " EXE8 ,External request event 8" "No event,Event" bitfld.long 0x00 22. " EXE9 ,External request event 9" "No event,Event" bitfld.long 0x00 21. " EXE10 ,External request event 10" "No event,Event" bitfld.long 0x00 20. " EXE11 ,External request event 11" "No event,Event" newline bitfld.long 0x00 19. " EXE12 ,External request event 12" "No event,Event" bitfld.long 0x00 18. " EXE13 ,External request event 13" "No event,Event" bitfld.long 0x00 17. " EXE14 ,External request event 14" "No event,Event" bitfld.long 0x00 16. " EXE15 ,External request event 15" "No event,Event" newline bitfld.long 0x00 15. " EXE16 ,External request event 16" "No event,Event" bitfld.long 0x00 14. " EXE17 ,External request event 17" "No event,Event" bitfld.long 0x00 13. " EXE18 ,External request event 18" "No event,Event" bitfld.long 0x00 12. " EXE19 ,External request event 19" "No event,Event" newline bitfld.long 0x00 11. " EXE20 ,External request event 20" "No event,Event" bitfld.long 0x00 10. " EXE21 ,External request event 21" "No event,Event" bitfld.long 0x00 9. " EXE22 ,External request event 22" "No event,Event" bitfld.long 0x00 8. " EXE23 ,External request event 23" "No event,Event" newline bitfld.long 0x00 7. " EXE24 ,External request event 24" "No event,Event" bitfld.long 0x00 6. " EXE25 ,External request event 25" "No event,Event" bitfld.long 0x00 5. " EXE26 ,External request event 26" "No event,Event" bitfld.long 0x00 4. " EXE27 ,External request event 27" "No event,Event" newline bitfld.long 0x00 3. " EXE28 ,External request event 28" "No event,Event" bitfld.long 0x00 2. " EXE29 ,External request event 29" "No event,Event" bitfld.long 0x00 1. " EXE30 ,External request event 30" "No event,Event" bitfld.long 0x00 0. " EXE31 ,External request event 31" "No event,Event" line.long 0x04 "CEEXM2,QUICC Engine External Request Mask Register" bitfld.long 0x04 31. " EXE0 ,External request mask 0" "Not masked,Masked" bitfld.long 0x04 30. " EXE1 ,External request mask 1" "Not masked,Masked" bitfld.long 0x04 29. " EXE2 ,External request mask 2" "Not masked,Masked" bitfld.long 0x04 28. " EXE3 ,External request mask 3" "Not masked,Masked" newline bitfld.long 0x04 27. " EXE4 ,External request mask 4" "Not masked,Masked" bitfld.long 0x04 26. " EXE5 ,External request mask 5" "Not masked,Masked" bitfld.long 0x04 25. " EXE6 ,External request mask 6" "Not masked,Masked" bitfld.long 0x04 24. " EXE7 ,External request mask 7" "Not masked,Masked" newline bitfld.long 0x04 23. " EXE8 ,External request mask 8" "Not masked,Masked" bitfld.long 0x04 22. " EXE9 ,External request mask 9" "Not masked,Masked" bitfld.long 0x04 21. " EXE10 ,External request mask 10" "Not masked,Masked" bitfld.long 0x04 20. " EXE11 ,External request mask 11" "Not masked,Masked" newline bitfld.long 0x04 19. " EXE12 ,External request mask 12" "Not masked,Masked" bitfld.long 0x04 18. " EXE13 ,External request mask 13" "Not masked,Masked" bitfld.long 0x04 17. " EXE14 ,External request mask 14" "Not masked,Masked" bitfld.long 0x04 16. " EXE15 ,External request mask 15" "Not masked,Masked" newline bitfld.long 0x04 15. " EXE16 ,External request mask 16" "Not masked,Masked" bitfld.long 0x04 14. " EXE17 ,External request mask 17" "Not masked,Masked" bitfld.long 0x04 13. " EXE18 ,External request mask 18" "Not masked,Masked" bitfld.long 0x04 12. " EXE19 ,External request mask 19" "Not masked,Masked" newline bitfld.long 0x04 11. " EXE20 ,External request mask 20" "Not masked,Masked" bitfld.long 0x04 10. " EXE21 ,External request mask 21" "Not masked,Masked" bitfld.long 0x04 9. " EXE22 ,External request mask 22" "Not masked,Masked" bitfld.long 0x04 8. " EXE23 ,External request mask 23" "Not masked,Masked" newline bitfld.long 0x04 7. " EXE24 ,External request mask 24" "Not masked,Masked" bitfld.long 0x04 6. " EXE25 ,External request mask 25" "Not masked,Masked" bitfld.long 0x04 5. " EXE26 ,External request mask 26" "Not masked,Masked" bitfld.long 0x04 4. " EXE27 ,External request mask 27" "Not masked,Masked" newline bitfld.long 0x04 3. " EXE28 ,External request mask 28" "Not masked,Masked" bitfld.long 0x04 2. " EXE29 ,External request mask 29" "Not masked,Masked" bitfld.long 0x04 1. " EXE30 ,External request mask 30" "Not masked,Masked" bitfld.long 0x04 0. " EXE31 ,External request mask 31" "Not masked,Masked" group.long 0x168++0x07 line.long 0x00 "CEEXE3,QUICC Engine External Request Event Register" bitfld.long 0x00 31. " EXE0 ,External request event 0" "No event,Event" bitfld.long 0x00 30. " EXE1 ,External request event 1" "No event,Event" bitfld.long 0x00 29. " EXE2 ,External request event 2" "No event,Event" bitfld.long 0x00 28. " EXE3 ,External request event 3" "No event,Event" newline bitfld.long 0x00 27. " EXE4 ,External request event 4" "No event,Event" bitfld.long 0x00 26. " EXE5 ,External request event 5" "No event,Event" bitfld.long 0x00 25. " EXE6 ,External request event 6" "No event,Event" bitfld.long 0x00 24. " EXE7 ,External request event 7" "No event,Event" newline bitfld.long 0x00 23. " EXE8 ,External request event 8" "No event,Event" bitfld.long 0x00 22. " EXE9 ,External request event 9" "No event,Event" bitfld.long 0x00 21. " EXE10 ,External request event 10" "No event,Event" bitfld.long 0x00 20. " EXE11 ,External request event 11" "No event,Event" newline bitfld.long 0x00 19. " EXE12 ,External request event 12" "No event,Event" bitfld.long 0x00 18. " EXE13 ,External request event 13" "No event,Event" bitfld.long 0x00 17. " EXE14 ,External request event 14" "No event,Event" bitfld.long 0x00 16. " EXE15 ,External request event 15" "No event,Event" newline bitfld.long 0x00 15. " EXE16 ,External request event 16" "No event,Event" bitfld.long 0x00 14. " EXE17 ,External request event 17" "No event,Event" bitfld.long 0x00 13. " EXE18 ,External request event 18" "No event,Event" bitfld.long 0x00 12. " EXE19 ,External request event 19" "No event,Event" newline bitfld.long 0x00 11. " EXE20 ,External request event 20" "No event,Event" bitfld.long 0x00 10. " EXE21 ,External request event 21" "No event,Event" bitfld.long 0x00 9. " EXE22 ,External request event 22" "No event,Event" bitfld.long 0x00 8. " EXE23 ,External request event 23" "No event,Event" newline bitfld.long 0x00 7. " EXE24 ,External request event 24" "No event,Event" bitfld.long 0x00 6. " EXE25 ,External request event 25" "No event,Event" bitfld.long 0x00 5. " EXE26 ,External request event 26" "No event,Event" bitfld.long 0x00 4. " EXE27 ,External request event 27" "No event,Event" newline bitfld.long 0x00 3. " EXE28 ,External request event 28" "No event,Event" bitfld.long 0x00 2. " EXE29 ,External request event 29" "No event,Event" bitfld.long 0x00 1. " EXE30 ,External request event 30" "No event,Event" bitfld.long 0x00 0. " EXE31 ,External request event 31" "No event,Event" line.long 0x04 "CEEXM3,QUICC Engine External Request Mask Register" bitfld.long 0x04 31. " EXE0 ,External request mask 0" "Not masked,Masked" bitfld.long 0x04 30. " EXE1 ,External request mask 1" "Not masked,Masked" bitfld.long 0x04 29. " EXE2 ,External request mask 2" "Not masked,Masked" bitfld.long 0x04 28. " EXE3 ,External request mask 3" "Not masked,Masked" newline bitfld.long 0x04 27. " EXE4 ,External request mask 4" "Not masked,Masked" bitfld.long 0x04 26. " EXE5 ,External request mask 5" "Not masked,Masked" bitfld.long 0x04 25. " EXE6 ,External request mask 6" "Not masked,Masked" bitfld.long 0x04 24. " EXE7 ,External request mask 7" "Not masked,Masked" newline bitfld.long 0x04 23. " EXE8 ,External request mask 8" "Not masked,Masked" bitfld.long 0x04 22. " EXE9 ,External request mask 9" "Not masked,Masked" bitfld.long 0x04 21. " EXE10 ,External request mask 10" "Not masked,Masked" bitfld.long 0x04 20. " EXE11 ,External request mask 11" "Not masked,Masked" newline bitfld.long 0x04 19. " EXE12 ,External request mask 12" "Not masked,Masked" bitfld.long 0x04 18. " EXE13 ,External request mask 13" "Not masked,Masked" bitfld.long 0x04 17. " EXE14 ,External request mask 14" "Not masked,Masked" bitfld.long 0x04 16. " EXE15 ,External request mask 15" "Not masked,Masked" newline bitfld.long 0x04 15. " EXE16 ,External request mask 16" "Not masked,Masked" bitfld.long 0x04 14. " EXE17 ,External request mask 17" "Not masked,Masked" bitfld.long 0x04 13. " EXE18 ,External request mask 18" "Not masked,Masked" bitfld.long 0x04 12. " EXE19 ,External request mask 19" "Not masked,Masked" newline bitfld.long 0x04 11. " EXE20 ,External request mask 20" "Not masked,Masked" bitfld.long 0x04 10. " EXE21 ,External request mask 21" "Not masked,Masked" bitfld.long 0x04 9. " EXE22 ,External request mask 22" "Not masked,Masked" bitfld.long 0x04 8. " EXE23 ,External request mask 23" "Not masked,Masked" newline bitfld.long 0x04 7. " EXE24 ,External request mask 24" "Not masked,Masked" bitfld.long 0x04 6. " EXE25 ,External request mask 25" "Not masked,Masked" bitfld.long 0x04 5. " EXE26 ,External request mask 26" "Not masked,Masked" bitfld.long 0x04 4. " EXE27 ,External request mask 27" "Not masked,Masked" newline bitfld.long 0x04 3. " EXE28 ,External request mask 28" "Not masked,Masked" bitfld.long 0x04 2. " EXE29 ,External request mask 29" "Not masked,Masked" bitfld.long 0x04 1. " EXE30 ,External request mask 30" "Not masked,Masked" bitfld.long 0x04 0. " EXE31 ,External request mask 31" "Not masked,Masked" group.long 0x16C++0x07 line.long 0x00 "CEEXE4,QUICC Engine External Request Event Register" bitfld.long 0x00 31. " EXE0 ,External request event 0" "No event,Event" bitfld.long 0x00 30. " EXE1 ,External request event 1" "No event,Event" bitfld.long 0x00 29. " EXE2 ,External request event 2" "No event,Event" bitfld.long 0x00 28. " EXE3 ,External request event 3" "No event,Event" newline bitfld.long 0x00 27. " EXE4 ,External request event 4" "No event,Event" bitfld.long 0x00 26. " EXE5 ,External request event 5" "No event,Event" bitfld.long 0x00 25. " EXE6 ,External request event 6" "No event,Event" bitfld.long 0x00 24. " EXE7 ,External request event 7" "No event,Event" newline bitfld.long 0x00 23. " EXE8 ,External request event 8" "No event,Event" bitfld.long 0x00 22. " EXE9 ,External request event 9" "No event,Event" bitfld.long 0x00 21. " EXE10 ,External request event 10" "No event,Event" bitfld.long 0x00 20. " EXE11 ,External request event 11" "No event,Event" newline bitfld.long 0x00 19. " EXE12 ,External request event 12" "No event,Event" bitfld.long 0x00 18. " EXE13 ,External request event 13" "No event,Event" bitfld.long 0x00 17. " EXE14 ,External request event 14" "No event,Event" bitfld.long 0x00 16. " EXE15 ,External request event 15" "No event,Event" newline bitfld.long 0x00 15. " EXE16 ,External request event 16" "No event,Event" bitfld.long 0x00 14. " EXE17 ,External request event 17" "No event,Event" bitfld.long 0x00 13. " EXE18 ,External request event 18" "No event,Event" bitfld.long 0x00 12. " EXE19 ,External request event 19" "No event,Event" newline bitfld.long 0x00 11. " EXE20 ,External request event 20" "No event,Event" bitfld.long 0x00 10. " EXE21 ,External request event 21" "No event,Event" bitfld.long 0x00 9. " EXE22 ,External request event 22" "No event,Event" bitfld.long 0x00 8. " EXE23 ,External request event 23" "No event,Event" newline bitfld.long 0x00 7. " EXE24 ,External request event 24" "No event,Event" bitfld.long 0x00 6. " EXE25 ,External request event 25" "No event,Event" bitfld.long 0x00 5. " EXE26 ,External request event 26" "No event,Event" bitfld.long 0x00 4. " EXE27 ,External request event 27" "No event,Event" newline bitfld.long 0x00 3. " EXE28 ,External request event 28" "No event,Event" bitfld.long 0x00 2. " EXE29 ,External request event 29" "No event,Event" bitfld.long 0x00 1. " EXE30 ,External request event 30" "No event,Event" bitfld.long 0x00 0. " EXE31 ,External request event 31" "No event,Event" line.long 0x04 "CEEXM4,QUICC Engine External Request Mask Register" bitfld.long 0x04 31. " EXE0 ,External request mask 0" "Not masked,Masked" bitfld.long 0x04 30. " EXE1 ,External request mask 1" "Not masked,Masked" bitfld.long 0x04 29. " EXE2 ,External request mask 2" "Not masked,Masked" bitfld.long 0x04 28. " EXE3 ,External request mask 3" "Not masked,Masked" newline bitfld.long 0x04 27. " EXE4 ,External request mask 4" "Not masked,Masked" bitfld.long 0x04 26. " EXE5 ,External request mask 5" "Not masked,Masked" bitfld.long 0x04 25. " EXE6 ,External request mask 6" "Not masked,Masked" bitfld.long 0x04 24. " EXE7 ,External request mask 7" "Not masked,Masked" newline bitfld.long 0x04 23. " EXE8 ,External request mask 8" "Not masked,Masked" bitfld.long 0x04 22. " EXE9 ,External request mask 9" "Not masked,Masked" bitfld.long 0x04 21. " EXE10 ,External request mask 10" "Not masked,Masked" bitfld.long 0x04 20. " EXE11 ,External request mask 11" "Not masked,Masked" newline bitfld.long 0x04 19. " EXE12 ,External request mask 12" "Not masked,Masked" bitfld.long 0x04 18. " EXE13 ,External request mask 13" "Not masked,Masked" bitfld.long 0x04 17. " EXE14 ,External request mask 14" "Not masked,Masked" bitfld.long 0x04 16. " EXE15 ,External request mask 15" "Not masked,Masked" newline bitfld.long 0x04 15. " EXE16 ,External request mask 16" "Not masked,Masked" bitfld.long 0x04 14. " EXE17 ,External request mask 17" "Not masked,Masked" bitfld.long 0x04 13. " EXE18 ,External request mask 18" "Not masked,Masked" bitfld.long 0x04 12. " EXE19 ,External request mask 19" "Not masked,Masked" newline bitfld.long 0x04 11. " EXE20 ,External request mask 20" "Not masked,Masked" bitfld.long 0x04 10. " EXE21 ,External request mask 21" "Not masked,Masked" bitfld.long 0x04 9. " EXE22 ,External request mask 22" "Not masked,Masked" bitfld.long 0x04 8. " EXE23 ,External request mask 23" "Not masked,Masked" newline bitfld.long 0x04 7. " EXE24 ,External request mask 24" "Not masked,Masked" bitfld.long 0x04 6. " EXE25 ,External request mask 25" "Not masked,Masked" bitfld.long 0x04 5. " EXE26 ,External request mask 26" "Not masked,Masked" bitfld.long 0x04 4. " EXE27 ,External request mask 27" "Not masked,Masked" newline bitfld.long 0x04 3. " EXE28 ,External request mask 28" "Not masked,Masked" bitfld.long 0x04 2. " EXE29 ,External request mask 29" "Not masked,Masked" bitfld.long 0x04 1. " EXE30 ,External request mask 30" "Not masked,Masked" bitfld.long 0x04 0. " EXE31 ,External request mask 31" "Not masked,Masked" endian.le width 0x0B tree.end tree "Multiplexing and Timers" endian.be width 9. group.long 0x400++0x03 "CMX Registers" line.long 0x00 "CMXGCR,CMX General Clock Route Register" bitfld.long 0x00 28.--30. " TS1CLS ,Time stamp 1 clock source" "CLK11,CLK12,,,Ext. RTC CLK,?..." bitfld.long 0x00 24.--26. " TS2CLS ,Time stamp 2 clock source" "CLK11,CLK12,,,Ext. RTC CLK,?..." bitfld.long 0x00 12.--14. " MEM ,MII Ethernet management interface select" "UCC1,,UCC3,?..." if (((per.l.be(ad:0x2400000+0x410))&0x40004000)==0x0) group.long 0x410++0x03 line.long 0x00 "CMXUCR1,CMX UCC Clock Route Register" bitfld.long 0x00 30. " UC1 ,UCC1 connection mode select" "NMSI,TSA" bitfld.long 0x00 29. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 24. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" newline bitfld.long 0x00 14. " UC3 ,UCC3 connection mode select" "NMSI,TSA" bitfld.long 0x00 13. " HBM3 ,HDLC bus mode of UCC3" "Default,TSA and HDLC" bitfld.long 0x00 8. " HBM3 ,HDLC bus mode" "Default,TSA and HDLC" elif (((per.l.be(ad:0x2400000+0x410))&0x40004000)==0x4000) group.long 0x410++0x03 line.long 0x00 "CMXUCR1,CMX UCC Clock Route Register" bitfld.long 0x00 30. " UC1 ,UCC1 connection mode select" "NMSI,TSA" bitfld.long 0x00 29. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 24. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" newline bitfld.long 0x00 15. " GR3 ,CTS grant mode of UCC3" "Automatic,IDL" bitfld.long 0x00 14. " UC3 ,UCC3 connection mode select" "NMSI,TSA" bitfld.long 0x00 13. " HBM3 ,HDLC bus mode of UCC3" "Default,TSA and HDLC" newline bitfld.long 0x00 8. " HBM3 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 4.--7. " RU3CS ,Receive UCC3 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." bitfld.long 0x00 0.--3. " TU3CS ,Transmit UCC3 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." elif (((per.l.be(ad:0x2400000+0x410))&0x40004000)==0x40000000) group.long 0x410++0x03 line.long 0x00 "CMXUCR1,CMX UCC Clock Route Register" bitfld.long 0x00 31. " GR1 ,CTS grant mode of UCC1" "Automatic,IDL" bitfld.long 0x00 30. " UC1 ,UCC1 connection mode select" "NMSI,TSA" bitfld.long 0x00 29. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" newline bitfld.long 0x00 24. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 20.--23. " RU1CS ,Receive UCC1 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,,GRX_CLK,?..." bitfld.long 0x00 16.--19. " TU1CS ,Transmit UCC1 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." newline bitfld.long 0x00 14. " UC3 ,UCC3 connection mode select" "NMSI,TSA" bitfld.long 0x00 13. " HBM3 ,HDLC bus mode of UCC3" "Default,TSA and HDLC" bitfld.long 0x00 8. " HBM3 ,HDLC bus mode" "Default,TSA and HDLC" elif (((per.l.be(ad:0x2400000+0x410))&0x40004000)==0x40004000) group.long 0x410++0x03 line.long 0x00 "CMXUCR1,CMX UCC Clock Route Register" bitfld.long 0x00 31. " GR1 ,CTS grant mode of UCC1" "Automatic,IDL" bitfld.long 0x00 30. " UC1 ,UCC1 connection mode select" "NMSI,TSA" bitfld.long 0x00 29. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" newline bitfld.long 0x00 24. " HBM1 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 20.--23. " RU1CS ,Receive UCC1 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,,GRX_CLK,?..." bitfld.long 0x00 16.--19. " TU1CS ,Transmit UCC1 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." newline bitfld.long 0x00 15. " GR3 ,CTS grant mode of UCC3" "Automatic,IDL" bitfld.long 0x00 14. " UC3 ,UCC3 connection mode select" "NMSI,TSA" bitfld.long 0x00 13. " HBM3 ,HDLC bus mode of UCC3" "Default,TSA and HDLC" newline bitfld.long 0x00 8. " HBM3 ,HDLC bus mode" "Default,TSA and HDLC" bitfld.long 0x00 4.--7. " RU3CS ,Receive UCC3 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." bitfld.long 0x00 0.--3. " TU3CS ,Transmit UCC3 clock source" "Disabled,BRG1,BRG2,,,CLK9,CLK10,CLK11,CLK12,CLK15,?..." endif group.long 0x0++0x03 "BRG Configuration Registers" line.long 0x00 "BRG1,BRG Configuration Register 1" bitfld.long 0x00 17. " RST ,Reset BRG" "No reset,Reset" bitfld.long 0x00 16. " EN ,Enable BRG count" "Disabled,Enabled" bitfld.long 0x00 14.--15. " EXTC ,External clock source" "BRGCLK,CLK3,CLK3,?..." newline bitfld.long 0x00 13. " ATB ,Autobaud of the BRG operation select" "Normal,Dynamic" hexmask.long.word 0x00 1.--12. 1. " CD ,Clock divider" bitfld.long 0x00 31. " DIV16 ,Divide by 1 or 16 prescaler before reaching the clock divider select" "/1,/16" group.long 0x4++0x03 "BRG Configuration Registers" line.long 0x00 "BRG2,BRG Configuration Register 2" bitfld.long 0x00 17. " RST ,Reset BRG" "No reset,Reset" bitfld.long 0x00 16. " EN ,Enable BRG count" "Disabled,Enabled" bitfld.long 0x00 14.--15. " EXTC ,External clock source" "BRGCLK,CLK3,CLK3,?..." newline bitfld.long 0x00 13. " ATB ,Autobaud of the BRG operation select" "Normal,Dynamic" hexmask.long.word 0x00 1.--12. 1. " CD ,Clock divider" bitfld.long 0x00 31. " DIV16 ,Divide by 1 or 16 prescaler before reaching the clock divider select" "/1,/16" group.long 0x8++0x03 "BRG Configuration Registers" line.long 0x00 "BRG3,BRG Configuration Register 3" bitfld.long 0x00 17. " RST ,Reset BRG" "No reset,Reset" bitfld.long 0x00 16. " EN ,Enable BRG count" "Disabled,Enabled" bitfld.long 0x00 14.--15. " EXTC ,External clock source" "BRGCLK,CLK9,CLK15,?..." newline bitfld.long 0x00 13. " ATB ,Autobaud of the BRG operation select" "Normal,Dynamic" hexmask.long.word 0x00 1.--12. 1. " CD ,Clock divider" bitfld.long 0x00 31. " DIV16 ,Divide by 1 or 16 prescaler before reaching the clock divider select" "/1,/16" group.long 0xC++0x03 "BRG Configuration Registers" line.long 0x00 "BRG4,BRG Configuration Register 4" bitfld.long 0x00 17. " RST ,Reset BRG" "No reset,Reset" bitfld.long 0x00 16. " EN ,Enable BRG count" "Disabled,Enabled" bitfld.long 0x00 14.--15. " EXTC ,External clock source" "BRGCLK,CLK9,CLK15,?..." newline bitfld.long 0x00 13. " ATB ,Autobaud of the BRG operation select" "Normal,Dynamic" hexmask.long.word 0x00 1.--12. 1. " CD ,Clock divider" bitfld.long 0x00 31. " DIV16 ,Divide by 1 or 16 prescaler before reaching the clock divider select" "/1,/16" if (((per.b(ad:0x2400000+0x444))&0x40)==0x40) group.byte 0x440++0x00 "Timers" line.byte 0x00 "GTCFR1,Timer 1-2 Global Timers Configuration Register" rbitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" newline bitfld.byte 0x00 6. " BCM ,Backward compatible mode" "Backward,Normal" bitfld.byte 0x00 5. " STP2 ,Stop timer 2" "No action,Stopped" bitfld.byte 0x00 4. " RST2 ,Reset timer 2" "Reset,No reset" newline bitfld.byte 0x00 1. " STP1 ,Stop timer 1" "No action,Stopped" bitfld.byte 0x00 0. " RST1 ,Reset timer 1" "Reset,No reset" else if (((per.b(ad:0x2400000+0x440))&0x11)==0x0) group.byte 0x440++0x00 "Timers" line.byte 0x00 "GTCFR1,Timer 1-2 Global Timers Configuration Register" bitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BCM ,Backward compatible mode" "Backward,Normal" bitfld.byte 0x00 5. " STP2 ,Stop timer 2" "No action,Stopped" bitfld.byte 0x00 4. " RST2 ,Reset timer 2" "Reset,No reset" newline bitfld.byte 0x00 1. " STP1 ,Stop timer 1" "No action,Stopped" bitfld.byte 0x00 0. " RST1 ,Reset timer 1" "Reset,No reset" else group.byte 0x440++0x00 "Timers" line.byte 0x00 "GTCFR1,Timer 1-2 Global Timers Configuration Register" rbitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BCM ,Backward compatible mode" "Backward,Normal" bitfld.byte 0x00 5. " STP2 ,Stop timer 2" "No action,Stopped" bitfld.byte 0x00 4. " RST2 ,Reset timer 2" "Reset,No reset" newline bitfld.byte 0x00 1. " STP1 ,Stop timer 1" "No action,Stopped" bitfld.byte 0x00 0. " RST1 ,Reset timer 1" "Reset,No reset" endif endif if (((per.b(ad:0x2400000+0x444))&0x40)==0x40) group.byte 0x444++0x00 line.byte 0x00 "GTCFR2,Timer 3-4 Global Timers Configuration Register" rbitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" newline bitfld.byte 0x00 6. " SCAS ,Super cascade mode to form 64-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " STP4 ,Stop timer 4" "No action,Stopped" bitfld.byte 0x00 4. " RST4 ,Reset timer 4" "Reset,No reset" newline bitfld.byte 0x00 1. " STP3 ,Stop timer 3" "No action,Stopped" bitfld.byte 0x00 0. " RST3 ,Reset timer 3" "Reset,No reset" else if (((per.b(ad:0x2400000+0x444))&0x11)==0x0)&&(((per.b(ad:0x2400000+0x440))&0x11)==0x0) group.byte 0x444++0x00 line.byte 0x00 "GTCFR2,Timer 3-4 Global Timers Configuration Register" bitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 6. " SCAS ,Super cascade mode to form 64-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " STP4 ,Stop timer 4" "No action,Stopped" bitfld.byte 0x00 4. " RST4 ,Reset timer 4" "Reset,No reset" newline bitfld.byte 0x00 1. " STP3 ,Stop timer 3" "No action,Stopped" bitfld.byte 0x00 0. " RST3 ,Reset timer 3" "Reset,No reset" elif (((per.b(ad:0x2400000+0x444))&0x11)==0x0) group.byte 0x444++0x00 line.byte 0x00 "GTCFR2,Timer 3-4 Global Timers Configuration Register" bitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " SCAS ,Super cascade mode to form 64-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " STP4 ,Stop timer 4" "No action,Stopped" bitfld.byte 0x00 4. " RST4 ,Reset timer 4" "Reset,No reset" newline bitfld.byte 0x00 1. " STP3 ,Stop timer 3" "No action,Stopped" bitfld.byte 0x00 0. " RST3 ,Reset timer 3" "Reset,No reset" else group.byte 0x444++0x00 line.byte 0x00 "GTCFR2,Timer 3-4 Global Timers Configuration Register" rbitfld.byte 0x00 7. " PCAS ,Pair-cascade mode to form 32-bit timer enable" "Disabled,Enabled" rbitfld.byte 0x00 6. " SCAS ,Super cascade mode to form 64-bit timer enable" "Disabled,Enabled" bitfld.byte 0x00 5. " STP4 ,Stop timer 4" "No action,Stopped" bitfld.byte 0x00 4. " RST4 ,Reset timer 4" "Reset,No reset" newline bitfld.byte 0x00 1. " STP3 ,Stop timer 3" "No action,Stopped" bitfld.byte 0x00 0. " RST3 ,Reset timer 3" "Reset,No reset" endif endif group.word 0x00++0x01 line.word 0x00 "GTMDR1,Global Timers Mode Register 1" hexmask.word.byte 0x00 8.--15. 1. " SPS ,Secondary prescaler value" bitfld.word 0x00 4. " ORI ,Output reference interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " FRR ,Free run/restart mode select" "Free run,Restart" bitfld.word 0x00 1.--2. " ICLK ,Internal input clock source for the timer" "Cascaded,QE reference CLK,Slow go CLK,?..." group.word 0x00++0x01 line.word 0x00 "GTMDR2,Global Timers Mode Register 2" hexmask.word.byte 0x00 8.--15. 1. " SPS ,Secondary prescaler value" bitfld.word 0x00 4. " ORI ,Output reference interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " FRR ,Free run/restart mode select" "Free run,Restart" bitfld.word 0x00 1.--2. " ICLK ,Internal input clock source for the timer" "Cascaded,QE reference CLK,Slow go CLK,?..." group.word 0x00++0x01 line.word 0x00 "GTMDR3,Global Timers Mode Register 3" hexmask.word.byte 0x00 8.--15. 1. " SPS ,Secondary prescaler value" bitfld.word 0x00 4. " ORI ,Output reference interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " FRR ,Free run/restart mode select" "Free run,Restart" bitfld.word 0x00 1.--2. " ICLK ,Internal input clock source for the timer" "Cascaded,QE reference CLK,Slow go CLK,?..." group.word 0x00++0x01 line.word 0x00 "GTMDR4,Global Timers Mode Register 4" hexmask.word.byte 0x00 8.--15. 1. " SPS ,Secondary prescaler value" bitfld.word 0x00 4. " ORI ,Output reference interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " FRR ,Free run/restart mode select" "Free run,Restart" bitfld.word 0x00 1.--2. " ICLK ,Internal input clock source for the timer" "Cascaded,QE reference CLK,Slow go CLK,?..." group.word 0x00++0x01 line.word 0x00 "GTRFR1,Global Timers Reference Register 1" group.word 0x00++0x01 line.word 0x00 "GTRFR2,Global Timers Reference Register 2" group.word 0x00++0x01 line.word 0x00 "GTRFR3,Global Timers Reference Register 3" group.word 0x00++0x01 line.word 0x00 "GTRFR4,Global Timers Reference Register 4" rgroup.word 0x00++0x01 line.word 0x00 "GTCPR1,Global Timers Capture Register 1" rgroup.word 0x00++0x01 line.word 0x00 "GTCPR2,Global Timers Capture Register 2" rgroup.word 0x00++0x01 line.word 0x00 "GTCPR3,Global Timers Capture Register 3" rgroup.word 0x00++0x01 line.word 0x00 "GTCPR4,Global Timers Capture Register 4" group.word 0x00++0x01 line.word 0x00 "GTCNR1,Global Timers Counter Register 1" group.word 0x00++0x01 line.word 0x00 "GTCNR2,Global Timers Counter Register 2" group.word 0x00++0x01 line.word 0x00 "GTCNR3,Global Timers Counter Register 3" group.word 0x00++0x01 line.word 0x00 "GTCNR4,Global Timers Counter Register 4" group.word 0x00++0x01 line.word 0x00 "GTEVR1,Global Timers Event Register 1" bitfld.word 0x00 1. " REF ,Output reference event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " CAP ,Counter capture event" "No event,?..." group.word 0x00++0x01 line.word 0x00 "GTEVR2,Global Timers Event Register 2" bitfld.word 0x00 1. " REF ,Output reference event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " CAP ,Counter capture event" "No event,?..." group.word 0x00++0x01 line.word 0x00 "GTEVR3,Global Timers Event Register 3" bitfld.word 0x00 1. " REF ,Output reference event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " CAP ,Counter capture event" "No event,?..." group.word 0x00++0x01 line.word 0x00 "GTEVR4,Global Timers Event Register 4" bitfld.word 0x00 1. " REF ,Output reference event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " CAP ,Counter capture event" "No event,?..." group.word 0x00++0x01 line.word 0x00 "GTPSR1,Global Timers Prescale Register 1" hexmask.word.byte 0x00 0.--7. 1. " PPS ,Primary prescaler bits" group.word 0x00++0x01 line.word 0x00 "GTPSR2,Global Timers Prescale Register 2" hexmask.word.byte 0x00 0.--7. 1. " PPS ,Primary prescaler bits" group.word 0x00++0x01 line.word 0x00 "GTPSR3,Global Timers Prescale Register 3" hexmask.word.byte 0x00 0.--7. 1. " PPS ,Primary prescaler bits" group.word 0x00++0x01 line.word 0x00 "GTPSR4,Global Timers Prescale Register 4" hexmask.word.byte 0x00 0.--7. 1. " PPS ,Primary prescaler bits" endian.le width 0x0B tree.end tree "Unified Communication Controllers" if (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x0)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2000000) base ad:0x2400000+0x2000 endian.be width 8. if (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x0)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x400000) group.long 0x00++0x07 line.long 0x00 "GUMR_L,General UCC Mode Register (Low)" bitfld.long 0x00 28. " TCI ,Transmit clock invert" "Not inverted,Inverted" bitfld.long 0x00 25. " RINV ,Rx invert data" "Not inverted,Inverted" bitfld.long 0x00 24. " TINV ,Tx invert data" "Not inverted,Inverted" newline bitfld.long 0x00 18. " TEND ,Transmitter frame ending. Encode mode select" "Idle on high,Always encode" bitfld.long 0x00 16.--17. " TDCR ,Transmitter oversampling rate" "1x clock mode,8x clock mode,16x clock mode,32x clock mode" bitfld.long 0x00 14.--15. " RDCR ,Receiver oversampling rate" "1x clock mode,8x clock mode,16x clock mode,32x clock mode" newline bitfld.long 0x00 11.--13. " RENC ,Receiver decoding method" "NRZ,NRZI Mark,?..." bitfld.long 0x00 8.--10. " TENC ,Transmitter encoding method" "NRZ,NRZI Mark,?..." bitfld.long 0x00 6.--7. " DIAG ,Diagnostic mode select" "Disabled,Local loopback,Automatic echo,Both" newline bitfld.long 0x00 5. " ENR ,Receive enable" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Transmit enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" ",,,,UART,,,,BISYNC,?..." line.long 0x04 "GUMR_H,General UCC Mode Register (High)" bitfld.long 0x04 13. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x04 10. " CDP ,CD pulse enable" "Disabled,Enabled" bitfld.long 0x04 9. " CTSP ,CTS pulse enable" "Disabled,Enabled" bitfld.long 0x04 8. " CDS ,CD sampling mode select" "Asynchronous,Synchronous" newline bitfld.long 0x04 7. " CTSS ,CTS sampling mode select" "Asynchronous,Synchronous" bitfld.long 0x04 6. " TFL ,Transmit FIFO length" "Normal,1 word" bitfld.long 0x04 5. " RFW ,Receive FIFO width" "32 bit,8 bit" bitfld.long 0x04 4. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" newline bitfld.long 0x04 2.--3. " SYNL ,Sync length" "External sync,4-bit sync,8-bit sync,16-bit sync" bitfld.long 0x04 1. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x04 0. " RSYN ,Receive synchronization timing enable" "Disabled,Enabled" if (((per.l.be(ad:0x2400000+0x2000))&0xF)==0x4) group.word 0x08++0x01 line.word 0x00 "UPSMR,UART Mode Register" bitfld.word 0x00 15. " FLC ,Asynchronous flow control enable" "Disabled,Enabled" bitfld.word 0x00 14. " SL ,Stop length" "One bit,Two bits" bitfld.word 0x00 12.--13. " CL ,Character length" "5 bits,6 bits,7 bits,8 bits" bitfld.word 0x00 10.--11. " UM ,UART mode select" "Normal,Manual multidrop,,Auto multidrop" newline bitfld.word 0x00 9. " FRZ ,Freeze transmission enable" "Disabled,Enabled" bitfld.word 0x00 8. " RZS ,Receive zero stop bits enable" "Disabled,Enabled" bitfld.word 0x00 7. " SYN ,Synchronous mode enable" "Disabled,Enabled" bitfld.word 0x00 6. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.word 0x00 4. " PEN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RPM ,Receiver parity mode" "Odd,Low,Even,High" bitfld.word 0x00 0.--1. " TPM ,Transmitter parity mode" "Odd,Low,Even,High" elif (((per.l.be(ad:0x2400000+0x2000))&0xF)==0x8) group.word 0x08++0x01 line.word 0x00 "UPSMR,BISYNC Mode Register" bitfld.word 0x00 12.--15. " NOS ,Minimum number of SYN1-SYN2 pairs sent between or before message" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 10.--11. " CRC ,CRC selection" ",CRC16,,LRC" bitfld.word 0x00 9. " RBCS ,Receive BCS enable" "Disabled,Enabled" newline bitfld.word 0x00 8. " RTR ,Receiver transparent mode enable" "Disabled,Enabled" bitfld.word 0x00 7. " RVD ,Reversed data enable" "Disabled,Enabled" bitfld.word 0x00 6. " DRT ,Disabled receiver while sending" "Enabled,Disabled" newline bitfld.word 0x00 2.--3. " RPM ,Receiver parity mode" "Odd,Low,Even,High" bitfld.word 0x00 0.--1. " TPM ,Transmitter parity mode" "Odd,Force low,Even,Force high" endif group.word 0x0C++0x01 line.word 0x00 "UTODR,UCC Transmit-On-Demand Register" bitfld.word 0x00 15. " TOD ,Transmit on demand enable" "Disabled,Enabled" group.word 0x0E++0x01 line.word 0x00 "UDSR,UCC Data Synchronization Register" hexmask.word.byte 0x00 8.--15. 1. " SYN2 ,Synchronization data 2" hexmask.word.byte 0x00 0.--7. 1. " SYN1 ,Synchronization data 1" if (((per.l.be(ad:0x2400000+0x2000))&0xF)==0x4) group.word 0x10++0x01 line.word 0x00 "UCCE,UCC UART Event Register" eventfld.word 0x00 9. " AB ,Autobaud lock detection" "Not detected,Detected" eventfld.word 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" eventfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" newline eventfld.word 0x00 6. " BRKE ,Break end" "Not ended,Ended" eventfld.word 0x00 5. " BRKS ,Break start" "Not started,Started" eventfld.word 0x00 3. " CCR ,Control character received and rejected" "Not received,Received" newline eventfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" eventfld.word 0x00 1. " TX ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.word 0x00 0. " RX ,Rx buffer event occurred" "Not occurred,Occurred" group.word 0x14++0x01 line.word 0x00 "UCCM,UCC UART Mask Register" bitfld.word 0x00 9. " AB ,Autobaud lock detection" "Not detected,Detected" bitfld.word 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" bitfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" newline bitfld.word 0x00 6. " BRKE ,Break end" "Not ended,Ended" bitfld.word 0x00 5. " BRKS ,Break start" "Not started,Started" bitfld.word 0x00 3. " CCR ,Control character received and rejected" "Not received,Received" newline bitfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" bitfld.word 0x00 1. " TX ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " RX ,Rx buffer event occurred" "Not occurred,Occurred" rgroup.word 0x17++0x01 line.word 0x00 "UCCS,UCC UART Status Register" bitfld.word 0x00 8. " ID ,UART idle status" "Not idle,Idle" elif (((per.l.be(ad:0x2400000+0x2000))&0xF)==0x8) group.word 0x10++0x01 line.word 0x00 "UCCE,BISYNC Event Register" eventfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.word 0x00 4. " TXE ,Tx error" "No error,Error" eventfld.word 0x00 3. " RCH ,Receive character" "Not received,Received" newline eventfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" eventfld.word 0x00 1. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.word 0x00 0. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" group.word 0x14++0x01 line.word 0x00 "UCCM,BISYNC Mask Register" bitfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.word 0x00 4. " TXE ,Tx error" "No error,Error" bitfld.word 0x00 3. " RCH ,Receive character" "Not received,Received" newline bitfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" bitfld.word 0x00 1. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" endif elif (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2000000)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2400000) if (((per.l.be(ad:0x2400000+0x2000+0x0))&0x18000000)==0x0) group.long 0x00++0x03 line.long 0x00 "GUMR,General UCC Mode Register" bitfld.long 0x00 30.--31. " DIAG ,Diagnostic mode select" "Normal operation,Local loopback,Auto echo,Loopback and echo" bitfld.long 0x00 29. " TCI ,Transmit clock invert enable" "Disabled,Enabled" bitfld.long 0x00 28. " TRX ,Transparent receiver enable" "Disabled,Enabled" bitfld.long 0x00 27. " TTX ,Transparent transmitter enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CDP ,CD pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " CTSP ,CTS pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " CDS ,CD sampling mode" "Asynchronous,Synchronous" bitfld.long 0x00 23. " CTSS ,CTS sampling mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 21.--22. " FFTH ,FIFO full threshold" "Default,?..." bitfld.long 0x00 17. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" bitfld.long 0x00 13. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 11.--12. " RENC ,Receiver decoding method" "NRZ,NRZI,?..." newline bitfld.long 0x00 10. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " TENC ,Transmitter encoding method" "NRZ,NRZI,?..." bitfld.long 0x00 6.--7. " TCRC ,Transparent CRC type select" "16-bit CCITT CRC,,32-bit CCITT CRC,?..." newline bitfld.long 0x00 5. " ENR ,Enable receive" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Enable transmit" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" "HDLC,,,,,,,,,,ATM,,Ethernet,,POS,?..." if (((per.l.be(ad:0x2400000+0x2000))&0x2000)==0x2000)&&(((per.l.be(ad:0x2400000+0x2000+0x04))&0x200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " FSE ,Flag sharing enable" "Enabled,Disabled" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 20. " BRM ,HDLC bus RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 12.--14. " CW ,Collision window. The number of bytes from the beginning of the frame" "1,2,3,4,5,6,7,8" bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2000))&0x2000)==0x2000)&&(((per.l.be(ad:0x2400000+0x2000+0x04))&0x200000)==0x0) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " FSE ,Flag sharing enable" "Enabled,Disabled" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2000))&0x2000)==0x0)&&(((per.l.be(ad:0x2400000+0x2000+0x04))&0x200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 20. " BRM ,HDLC bus RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 12.--14. " CW ,Collision window. The number of bytes from the beginning of the frame" "1,2,3,4,5,6,7,8" bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2000))&0x2000)==0x0)&&(((per.l.be(ad:0x2400000+0x2000+0x04))&0x200000)==0x0) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." endif else group.long 0x00++0x03 line.long 0x00 "GUMR,General UCC Mode Register" bitfld.long 0x00 30.--31. " DIAG ,Diagnostic mode select" "Normal operation,Local loopback,Auto echo,Loopback and echo" bitfld.long 0x00 29. " TCI ,Transmit clock invert enable" "Disabled,Enabled" bitfld.long 0x00 28. " TRX ,Transparent receiver enable" "Disabled,Enabled" bitfld.long 0x00 27. " TTX ,Transparent transmitter enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CDP ,CD pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " CTSP ,CTS pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " CDS ,CD sampling mode" "Asynchronous,Synchronous" bitfld.long 0x00 23. " CTSS ,CTS sampling mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 21.--22. " FFTH ,FIFO full threshold" "Default,?..." bitfld.long 0x00 17. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" bitfld.long 0x00 16. " RSYN ,Receiver synchronization timing enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " SYNL ,Sync length" "External sync,Auto sync,8-bit sync,16-bit sync" newline bitfld.long 0x00 13. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 11.--12. " RENC ,Receiver decoding method" "NRZ,NRZI,?..." bitfld.long 0x00 10. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " TENC ,Transmitter encoding method" "NRZ,NRZI,?..." newline bitfld.long 0x00 6.--7. " TCRC ,Transparent CRC type select" "16-bit CCITT CRC,,32-bit CCITT CRC,?..." bitfld.long 0x00 5. " ENR ,Enable receive" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Enable transmit" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" "HDLC,?..." group.long 0x04++0x03 line.long 0x00 "UPSMR,UCC Transparent Mode Register" bitfld.long 0x00 15.--16. " NBO ,Mode of operation select" "Normal,Nibble,Octal,?..." endif group.word 0x08++0x01 line.word 0x00 "UTODR,UCC Transmit-On-Demand Register" bitfld.word 0x00 15. " TOD ,Transmit on demand enable" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "UDSR,UCC Data Synchronization Register" hexmask.word.byte 0x00 8.--15. 1. " SYN2 ,Synchronization data 2" hexmask.word.byte 0x00 0.--7. 1. " SYN1 ,Synchronization data 1" if (((per.l.be(ad:0x2400000+0x2000+0x0))&0x18000000)==0x0) group.long 0x10++0x03 line.long 0x00 "UCCE,UCC Transparent Event Register" eventfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.long 0x00 20. " TXE ,Tx error" "No error,Error" eventfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline eventfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" eventfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" group.long 0x14++0x03 line.long 0x00 "UCCM,UCC Transparent Mask Register" bitfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.long 0x00 20. " TXE ,Tx error" "No error,Error" bitfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline bitfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" bitfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "UCCE,UCC HDLC Event Register" eventfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.long 0x00 20. " TXE ,Tx error" "No error,Error" eventfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline eventfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" eventfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" newline eventfld.long 0x00 9. " FLG ,Flag status changed" "Not changed,Changed" eventfld.long 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" group.long 0x14++0x03 line.long 0x00 "UCCM,UCC HDLC Mask Register" bitfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.long 0x00 20. " TXE ,Tx error" "No error,Error" bitfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline bitfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" bitfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" newline bitfld.long 0x00 9. " FLG ,Flag status changed" "Not changed,Changed" bitfld.long 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" endif rgroup.byte 0x18++0x00 line.byte 0x00 "UCCS,UCC Status Register" bitfld.byte 0x00 2. " FG ,Flags current receive status" "Not received,Received" bitfld.byte 0x00 0. " ID ,Idle status" "Busy,Idle" group.long 0x20++0x03 line.long 0x00 "URFB,Receive Virtual FIFO Base Register" hexmask.long.tbyte 0x00 0.--23. 0x01 " ADDR ,Receive FIFO base address" group.word 0x24++0x01 line.word 0x00 "URFS,Receive Virtual FIFO Size Register" group.word 0x28++0x01 line.word 0x00 "URFET,Receive Virtual FIFO Emergency Threshold" group.word 0x2A++0x01 line.word 0x00 "URFSET,Receive Virtual FIFO Special Emergency Threshold" group.long 0x2C++0x03 line.long 0x00 "UTFB,Transmit Virtual FIFO Base Register" hexmask.long.tbyte 0x00 0.--23. 0x01 " ADDR ,Transmit FIFO base address" group.word 0x30++0x01 line.word 0x00 "UTFS,Transmit Virtual FIFO Size Register" group.word 0x34++0x01 line.word 0x00 "UTFET,Transmit Virtual FIFO Emergency Threshold" group.word 0x38++0x01 line.word 0x00 "TFET,Transmit Virtual FIFO Transmit Threshold" group.word 0x3C++0x01 line.word 0x00 "UTPT,UCC Transmit Polling Timer" rgroup.long 0x40++0x03 line.long 0x00 "URTRY,UCC Transmit Retry Counter" group.byte 0x90++0x00 line.byte 0x00 "GUEMR,General UCC Extended Mode Register" bitfld.byte 0x00 1. " URMODE ,UCC Rx protocol mode" "Slow,Fast" bitfld.byte 0x00 0. " UTMODE ,UCC Tx protocol mode" "Slow,Fast" endif endian.le width 0x0B elif (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x400000)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2400000) base ad:0x2400000+0x2200 endian.be width 8. if (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x0)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x400000) group.long 0x00++0x07 line.long 0x00 "GUMR_L,General UCC Mode Register (Low)" bitfld.long 0x00 28. " TCI ,Transmit clock invert" "Not inverted,Inverted" bitfld.long 0x00 25. " RINV ,Rx invert data" "Not inverted,Inverted" bitfld.long 0x00 24. " TINV ,Tx invert data" "Not inverted,Inverted" newline bitfld.long 0x00 18. " TEND ,Transmitter frame ending. Encode mode select" "Idle on high,Always encode" bitfld.long 0x00 16.--17. " TDCR ,Transmitter oversampling rate" "1x clock mode,8x clock mode,16x clock mode,32x clock mode" bitfld.long 0x00 14.--15. " RDCR ,Receiver oversampling rate" "1x clock mode,8x clock mode,16x clock mode,32x clock mode" newline bitfld.long 0x00 11.--13. " RENC ,Receiver decoding method" "NRZ,NRZI Mark,?..." bitfld.long 0x00 8.--10. " TENC ,Transmitter encoding method" "NRZ,NRZI Mark,?..." bitfld.long 0x00 6.--7. " DIAG ,Diagnostic mode select" "Disabled,Local loopback,Automatic echo,Both" newline bitfld.long 0x00 5. " ENR ,Receive enable" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Transmit enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" ",,,,UART,,,,BISYNC,?..." line.long 0x04 "GUMR_H,General UCC Mode Register (High)" bitfld.long 0x04 13. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x04 10. " CDP ,CD pulse enable" "Disabled,Enabled" bitfld.long 0x04 9. " CTSP ,CTS pulse enable" "Disabled,Enabled" bitfld.long 0x04 8. " CDS ,CD sampling mode select" "Asynchronous,Synchronous" newline bitfld.long 0x04 7. " CTSS ,CTS sampling mode select" "Asynchronous,Synchronous" bitfld.long 0x04 6. " TFL ,Transmit FIFO length" "Normal,1 word" bitfld.long 0x04 5. " RFW ,Receive FIFO width" "32 bit,8 bit" bitfld.long 0x04 4. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" newline bitfld.long 0x04 2.--3. " SYNL ,Sync length" "External sync,4-bit sync,8-bit sync,16-bit sync" bitfld.long 0x04 1. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x04 0. " RSYN ,Receive synchronization timing enable" "Disabled,Enabled" if (((per.l.be(ad:0x2400000+0x2200))&0xF)==0x4) group.word 0x08++0x01 line.word 0x00 "UPSMR,UART Mode Register" bitfld.word 0x00 15. " FLC ,Asynchronous flow control enable" "Disabled,Enabled" bitfld.word 0x00 14. " SL ,Stop length" "One bit,Two bits" bitfld.word 0x00 12.--13. " CL ,Character length" "5 bits,6 bits,7 bits,8 bits" bitfld.word 0x00 10.--11. " UM ,UART mode select" "Normal,Manual multidrop,,Auto multidrop" newline bitfld.word 0x00 9. " FRZ ,Freeze transmission enable" "Disabled,Enabled" bitfld.word 0x00 8. " RZS ,Receive zero stop bits enable" "Disabled,Enabled" bitfld.word 0x00 7. " SYN ,Synchronous mode enable" "Disabled,Enabled" bitfld.word 0x00 6. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.word 0x00 4. " PEN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RPM ,Receiver parity mode" "Odd,Low,Even,High" bitfld.word 0x00 0.--1. " TPM ,Transmitter parity mode" "Odd,Low,Even,High" elif (((per.l.be(ad:0x2400000+0x2200))&0xF)==0x8) group.word 0x08++0x01 line.word 0x00 "UPSMR,BISYNC Mode Register" bitfld.word 0x00 12.--15. " NOS ,Minimum number of SYN1-SYN2 pairs sent between or before message" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 10.--11. " CRC ,CRC selection" ",CRC16,,LRC" bitfld.word 0x00 9. " RBCS ,Receive BCS enable" "Disabled,Enabled" newline bitfld.word 0x00 8. " RTR ,Receiver transparent mode enable" "Disabled,Enabled" bitfld.word 0x00 7. " RVD ,Reversed data enable" "Disabled,Enabled" bitfld.word 0x00 6. " DRT ,Disabled receiver while sending" "Enabled,Disabled" newline bitfld.word 0x00 2.--3. " RPM ,Receiver parity mode" "Odd,Low,Even,High" bitfld.word 0x00 0.--1. " TPM ,Transmitter parity mode" "Odd,Force low,Even,Force high" endif group.word 0x0C++0x01 line.word 0x00 "UTODR,UCC Transmit-On-Demand Register" bitfld.word 0x00 15. " TOD ,Transmit on demand enable" "Disabled,Enabled" group.word 0x0E++0x01 line.word 0x00 "UDSR,UCC Data Synchronization Register" hexmask.word.byte 0x00 8.--15. 1. " SYN2 ,Synchronization data 2" hexmask.word.byte 0x00 0.--7. 1. " SYN1 ,Synchronization data 1" if (((per.l.be(ad:0x2400000+0x2200))&0xF)==0x4) group.word 0x10++0x01 line.word 0x00 "UCCE,UCC UART Event Register" eventfld.word 0x00 9. " AB ,Autobaud lock detection" "Not detected,Detected" eventfld.word 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" eventfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" newline eventfld.word 0x00 6. " BRKE ,Break end" "Not ended,Ended" eventfld.word 0x00 5. " BRKS ,Break start" "Not started,Started" eventfld.word 0x00 3. " CCR ,Control character received and rejected" "Not received,Received" newline eventfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" eventfld.word 0x00 1. " TX ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.word 0x00 0. " RX ,Rx buffer event occurred" "Not occurred,Occurred" group.word 0x14++0x01 line.word 0x00 "UCCM,UCC UART Mask Register" bitfld.word 0x00 9. " AB ,Autobaud lock detection" "Not detected,Detected" bitfld.word 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" bitfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" newline bitfld.word 0x00 6. " BRKE ,Break end" "Not ended,Ended" bitfld.word 0x00 5. " BRKS ,Break start" "Not started,Started" bitfld.word 0x00 3. " CCR ,Control character received and rejected" "Not received,Received" newline bitfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" bitfld.word 0x00 1. " TX ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " RX ,Rx buffer event occurred" "Not occurred,Occurred" rgroup.word 0x17++0x01 line.word 0x00 "UCCS,UCC UART Status Register" bitfld.word 0x00 8. " ID ,UART idle status" "Not idle,Idle" elif (((per.l.be(ad:0x2400000+0x2200))&0xF)==0x8) group.word 0x10++0x01 line.word 0x00 "UCCE,BISYNC Event Register" eventfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.word 0x00 4. " TXE ,Tx error" "No error,Error" eventfld.word 0x00 3. " RCH ,Receive character" "Not received,Received" newline eventfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" eventfld.word 0x00 1. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.word 0x00 0. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" group.word 0x14++0x01 line.word 0x00 "UCCM,BISYNC Mask Register" bitfld.word 0x00 7. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.word 0x00 4. " TXE ,Tx error" "No error,Error" bitfld.word 0x00 3. " RCH ,Receive character" "Not received,Received" newline bitfld.word 0x00 2. " BSY ,Busy" "Not busy,Busy" bitfld.word 0x00 1. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.word 0x00 0. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" endif elif (((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2000000)||(((per.l.be(ad:0x2400000+0x100))&0x3FE0000)==0x2400000) if (((per.l.be(ad:0x2400000+0x2200+0x0))&0x18000000)==0x0) group.long 0x00++0x03 line.long 0x00 "GUMR,General UCC Mode Register" bitfld.long 0x00 30.--31. " DIAG ,Diagnostic mode select" "Normal operation,Local loopback,Auto echo,Loopback and echo" bitfld.long 0x00 29. " TCI ,Transmit clock invert enable" "Disabled,Enabled" bitfld.long 0x00 28. " TRX ,Transparent receiver enable" "Disabled,Enabled" bitfld.long 0x00 27. " TTX ,Transparent transmitter enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CDP ,CD pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " CTSP ,CTS pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " CDS ,CD sampling mode" "Asynchronous,Synchronous" bitfld.long 0x00 23. " CTSS ,CTS sampling mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 21.--22. " FFTH ,FIFO full threshold" "Default,?..." bitfld.long 0x00 17. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" bitfld.long 0x00 13. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 11.--12. " RENC ,Receiver decoding method" "NRZ,NRZI,?..." newline bitfld.long 0x00 10. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " TENC ,Transmitter encoding method" "NRZ,NRZI,?..." bitfld.long 0x00 6.--7. " TCRC ,Transparent CRC type select" "16-bit CCITT CRC,,32-bit CCITT CRC,?..." newline bitfld.long 0x00 5. " ENR ,Enable receive" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Enable transmit" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" "HDLC,,,,,,,,,,ATM,,Ethernet,,POS,?..." if (((per.l.be(ad:0x2400000+0x2200))&0x2000)==0x2000)&&(((per.l.be(ad:0x2400000+0x2200+0x04))&0x200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " FSE ,Flag sharing enable" "Enabled,Disabled" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 20. " BRM ,HDLC bus RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 12.--14. " CW ,Collision window. The number of bytes from the beginning of the frame" "1,2,3,4,5,6,7,8" bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2200))&0x2000)==0x2000)&&(((per.l.be(ad:0x2400000+0x2200+0x04))&0x200000)==0x0) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " FSE ,Flag sharing enable" "Enabled,Disabled" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2200))&0x2000)==0x0)&&(((per.l.be(ad:0x2400000+0x2200+0x04))&0x200000)==0x200000) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 20. " BRM ,HDLC bus RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" newline bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 12.--14. " CW ,Collision window. The number of bytes from the beginning of the frame" "1,2,3,4,5,6,7,8" bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." elif (((per.l.be(ad:0x2400000+0x2200))&0x2000)==0x0)&&(((per.l.be(ad:0x2400000+0x2200+0x04))&0x200000)==0x0) group.long 0x04++0x03 line.long 0x00 "UPSMR,HDLC Mode Register" bitfld.long 0x00 28.--31. " NOF ,Number of flags between or before frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 26. " MFF ,Multiple frames in FIFO enable" "Disabled,Enabled" bitfld.long 0x00 25. " RTE ,Retransmit enable" "Disabled,Enabled" bitfld.long 0x00 22. " TS ,1A 32-bit time stamp enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " BUS ,HDLC bus mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " DRT ,Disable receiver while transmitting" "Enabled,Disabled" bitfld.long 0x00 15.--16. " NBO ,Mode of operation" "Normal,Nibble,Octal,?..." bitfld.long 0x00 6.--7. " CRC ,CRC selection" "16-bit CCITT-CRC,,32-bit CCITT,?..." endif else group.long 0x00++0x03 line.long 0x00 "GUMR,General UCC Mode Register" bitfld.long 0x00 30.--31. " DIAG ,Diagnostic mode select" "Normal operation,Local loopback,Auto echo,Loopback and echo" bitfld.long 0x00 29. " TCI ,Transmit clock invert enable" "Disabled,Enabled" bitfld.long 0x00 28. " TRX ,Transparent receiver enable" "Disabled,Enabled" bitfld.long 0x00 27. " TTX ,Transparent transmitter enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CDP ,CD pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " CTSP ,CTS pulse mode enable" "Disabled,Enabled" bitfld.long 0x00 24. " CDS ,CD sampling mode" "Asynchronous,Synchronous" bitfld.long 0x00 23. " CTSS ,CTS sampling mode" "Asynchronous,Synchronous" newline bitfld.long 0x00 21.--22. " FFTH ,FIFO full threshold" "Default,?..." bitfld.long 0x00 17. " TXSY ,Transmitter synchronized to the receiver enable" "Disabled,Enabled" bitfld.long 0x00 16. " RSYN ,Receiver synchronization timing enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. " SYNL ,Sync length" "External sync,Auto sync,8-bit sync,16-bit sync" newline bitfld.long 0x00 13. " RTSM ,RTS mode enable" "Disabled,Enabled" bitfld.long 0x00 11.--12. " RENC ,Receiver decoding method" "NRZ,NRZI,?..." bitfld.long 0x00 10. " REVD ,Reverse data enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " TENC ,Transmitter encoding method" "NRZ,NRZI,?..." newline bitfld.long 0x00 6.--7. " TCRC ,Transparent CRC type select" "16-bit CCITT CRC,,32-bit CCITT CRC,?..." bitfld.long 0x00 5. " ENR ,Enable receive" "Disabled,Enabled" bitfld.long 0x00 4. " ENT ,Enable transmit" "Disabled,Enabled" bitfld.long 0x00 0.--3. " MODE ,Channel protocol mode select" "HDLC,?..." group.long 0x04++0x03 line.long 0x00 "UPSMR,UCC Transparent Mode Register" bitfld.long 0x00 15.--16. " NBO ,Mode of operation select" "Normal,Nibble,Octal,?..." endif group.word 0x08++0x01 line.word 0x00 "UTODR,UCC Transmit-On-Demand Register" bitfld.word 0x00 15. " TOD ,Transmit on demand enable" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "UDSR,UCC Data Synchronization Register" hexmask.word.byte 0x00 8.--15. 1. " SYN2 ,Synchronization data 2" hexmask.word.byte 0x00 0.--7. 1. " SYN1 ,Synchronization data 1" if (((per.l.be(ad:0x2400000+0x2200+0x0))&0x18000000)==0x0) group.long 0x10++0x03 line.long 0x00 "UCCE,UCC Transparent Event Register" eventfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.long 0x00 20. " TXE ,Tx error" "No error,Error" eventfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline eventfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" eventfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" group.long 0x14++0x03 line.long 0x00 "UCCM,UCC Transparent Mask Register" bitfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.long 0x00 20. " TXE ,Tx error" "No error,Error" bitfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline bitfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" bitfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "UCCE,UCC HDLC Event Register" eventfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" eventfld.long 0x00 20. " TXE ,Tx error" "No error,Error" eventfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline eventfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" eventfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" eventfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" newline eventfld.long 0x00 9. " FLG ,Flag status changed" "Not changed,Changed" eventfld.long 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" group.long 0x14++0x03 line.long 0x00 "UCCM,UCC HDLC Mask Register" bitfld.long 0x00 23. " GRA , Graceful stop complete" "Not completed,Completed" bitfld.long 0x00 20. " TXE ,Tx error" "No error,Error" bitfld.long 0x00 19. " RXF ,Complete Rx frame receive" "Not received,Received" newline bitfld.long 0x00 18. " BSY ,Busy" "Not busy,Busy" bitfld.long 0x00 17. " TXB ,Tx buffer event occurred" "Not occurred,Occurred" bitfld.long 0x00 16. " RXB ,Rx buffer event occurred" "Not occurred,Occurred" newline bitfld.long 0x00 9. " FLG ,Flag status changed" "Not changed,Changed" bitfld.long 0x00 8. " IDL ,Idle sequence status changed" "Not changed,Changed" endif rgroup.byte 0x18++0x00 line.byte 0x00 "UCCS,UCC Status Register" bitfld.byte 0x00 2. " FG ,Flags current receive status" "Not received,Received" bitfld.byte 0x00 0. " ID ,Idle status" "Busy,Idle" group.long 0x20++0x03 line.long 0x00 "URFB,Receive Virtual FIFO Base Register" hexmask.long.tbyte 0x00 0.--23. 0x01 " ADDR ,Receive FIFO base address" group.word 0x24++0x01 line.word 0x00 "URFS,Receive Virtual FIFO Size Register" group.word 0x28++0x01 line.word 0x00 "URFET,Receive Virtual FIFO Emergency Threshold" group.word 0x2A++0x01 line.word 0x00 "URFSET,Receive Virtual FIFO Special Emergency Threshold" group.long 0x2C++0x03 line.long 0x00 "UTFB,Transmit Virtual FIFO Base Register" hexmask.long.tbyte 0x00 0.--23. 0x01 " ADDR ,Transmit FIFO base address" group.word 0x30++0x01 line.word 0x00 "UTFS,Transmit Virtual FIFO Size Register" group.word 0x34++0x01 line.word 0x00 "UTFET,Transmit Virtual FIFO Emergency Threshold" group.word 0x38++0x01 line.word 0x00 "TFET,Transmit Virtual FIFO Transmit Threshold" group.word 0x3C++0x01 line.word 0x00 "UTPT,UCC Transmit Polling Timer" rgroup.long 0x40++0x03 line.long 0x00 "URTRY,UCC Transmit Retry Counter" group.byte 0x90++0x00 line.byte 0x00 "GUEMR,General UCC Extended Mode Register" bitfld.byte 0x00 1. " URMODE ,UCC Rx protocol mode" "Slow,Fast" bitfld.byte 0x00 0. " UTMODE ,UCC Tx protocol mode" "Slow,Fast" endif endian.le width 0x0B else textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Time Division Multiplex Support Serial Interface" base ad:0x2AD0700 endian.be width 9. group.byte 0x08++0x00 line.byte 0x00 "SIGLMRH,SI Global Mode Register High" bitfld.byte 0x00 5. " STZB ,Program L1TXD to zero for TDMB" "Normal operation,Zero" bitfld.byte 0x00 4. " STZA ,Program L1TXD to zero for TDMA" "Normal operation,Zero" bitfld.byte 0x00 1. " ENB ,Enable TDMB" "Disabled,Enabled" bitfld.byte 0x00 0. " ENA ,Enable TDMA" "Disabled,Enabled" group.word 0x0++0x01 line.word 0x00 "SIAMR,SI A Mode Register" bitfld.word 0x00 12.--15. " SADA ,Starting address for the RAM of TDMA" "0-31 bank0,32-63 bank0,64-95 bank1,96-127 bank1,128-159 bank2,160-191 bank2,192-223 bank3,224-255 bank3,256-287 bank4,288-319 bank4,320-351 bank5,352-383 bank5,384-415 bank6,416-447 bank6,448-479 bank7,480-511 bank7" bitfld.word 0x00 10.--11. " SDMA ,SI Diagnostic Mode for TDMA" "Normal operation,Automatic echo,Internal loopback,Loopback control" bitfld.word 0x00 8.--9. " RFSDA ,Receive frame sync delay for TDMA" "No delay,1-bit,2-bit,3-bit" newline bitfld.word 0x00 6. " CRTA ,Common receive and transmit pins for TDMA" "Separate pins,Common pins" bitfld.word 0x00 5. " SLA ,Sync level for TDMA" "Active on logic '1',Active on login '0'" bitfld.word 0x00 4. " CEA ,Clock edge for TDMA" "Falling,Rising" newline bitfld.word 0x00 3. " FEA ,Frame sync edge for TDMA" "Falling,Rising" bitfld.word 0x00 2. " GMA ,Grant mode for TDMA" "No grant mode,IDL mode" bitfld.word 0x00 0.--1. " TFSDA ,Transmit frame sync delay for TDMA" "No delay,1-bit,2-bit,3-bit" group.word 0x2++0x01 line.word 0x00 "SIBMR,SI B Mode Register" bitfld.word 0x00 12.--15. " SADB ,Starting address for the RAM of TDMB" "0-31 bank0,32-63 bank0,64-95 bank1,96-127 bank1,128-159 bank2,160-191 bank2,192-223 bank3,224-255 bank3,256-287 bank4,288-319 bank4,320-351 bank5,352-383 bank5,384-415 bank6,416-447 bank6,448-479 bank7,480-511 bank7" bitfld.word 0x00 10.--11. " SDMB ,SI Diagnostic Mode for TDMB" "Normal operation,Automatic echo,Internal loopback,Loopback control" bitfld.word 0x00 8.--9. " RFSDB ,Receive frame sync delay for TDMB" "No delay,1-bit,2-bit,3-bit" newline bitfld.word 0x00 6. " CRTB ,Common receive and transmit pins for TDMB" "Separate pins,Common pins" bitfld.word 0x00 5. " SLB ,Sync level for TDMB" "Active on logic '1',Active on login '0'" bitfld.word 0x00 4. " CEB ,Clock edge for TDMB" "Falling,Rising" newline bitfld.word 0x00 3. " FEB ,Frame sync edge for TDMB" "Falling,Rising" bitfld.word 0x00 2. " GMB ,Grant mode for TDMB" "No grant mode,IDL mode" bitfld.word 0x00 0.--1. " TFSDB ,Transmit frame sync delay for TDMB" "No delay,1-bit,2-bit,3-bit" group.word 0x0E++0x01 line.word 0x00 "SIRSRH,SI RAM Shadow Address Register High" bitfld.word 0x00 12.--15. " SSADA ,Starting address for the RAM of TDMA" "0-31 bank0,32-63 bank0,64-95 bank1,96-127 bank1,128-159 bank2,160-191 bank2,192-223 bank3,224-255 bank3,256-287 bank4,288-319 bank4,320-351 bank5,352-383 bank5,384-415 bank6,416-447 bank6,448-479 bank7,480-511 bank7" bitfld.word 0x00 8.--11. " SSADB ,Starting address for the RAM of TDMB" "0-31 bank0,32-63 bank0,64-95 bank1,96-127 bank1,128-159 bank2,160-191 bank2,192-223 bank3,224-255 bank3,256-287 bank4,288-319 bank4,320-351 bank5,352-383 bank5,384-415 bank6,416-447 bank6,448-479 bank7,480-511 bank7" group.byte 0x0A++0x00 line.byte 0x00 "SICMDRH,SI Command Register High" bitfld.byte 0x00 7. " CSRRA ,Replace current router RAM with the shadow RAM for TDMA receiver" "No action,Replace" bitfld.byte 0x00 6. " CSRTA ,Replace current router RAM with the shadow RAM for TDMA transmitter" "No action,Replace" bitfld.byte 0x00 5. " CSRRB ,Replace current router RAM with the shadow RAM for TDMB receiver" "No action,Replace" bitfld.byte 0x00 4. " CSRTB ,Replace current router RAM with the shadow RAM for TDMB transmitter" "No action,Replace" group.byte 0x0C++0x00 line.byte 0x00 "SISTRH,SI Status Register High" bitfld.byte 0x00 7. " CRORA ,Current-route receiver RAM for TDMA" "Original,Shadow" bitfld.byte 0x00 6. " CROTA ,Current-route transmitter RAM for TDMA" "Original,Shadow" bitfld.byte 0x00 5. " CRORB ,Current-route receiver RAM for TDMB" "Original,Shadow" bitfld.byte 0x00 4. " CROTB ,Current-route transmitter RAM for TDMB" "Original,Shadow" group.word 0x48++0x01 line.word 0x00 "SIMLA,SI Multiframe Limits A Register" bitfld.word 0x00 10.--15. " RRC ,Regular address count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 4.--9. " SRC ,Shadow address count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 3. " ME ,Multiframe enable flag" "Disabled,Enabled" group.word 0x4C++0x01 line.word 0x00 "SIMLB,SI Multiframe Limits B Register" bitfld.word 0x00 10.--15. " RRC ,Regular address count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 4.--9. " SRC ,Shadow address count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 3. " ME ,Multiframe enable flag" "Disabled,Enabled" rgroup.byte 0x10++0x01 line.byte 0x00 "SITARC,SI Ram Counter Tx TDM A" line.byte 0x01 "SITBRC,SI Ram Counter Tx TDM A" rgroup.byte 0x30++0x01 line.byte 0x00 "SIRARC,SI RAM Counter Rx TDM A" line.byte 0x01 "SIRBRC,SI RAM Counter Rx TDM A" group.byte 0x44++0x00 line.byte 0x00 "SIENS,SI Enhanced SDM Register" bitfld.byte 0x00 7. " ETA ,Loopback or echo mode for TDMA is enabled" "Normal operation,Enabled" bitfld.byte 0x00 6. " ETB ,Loopback or echo mode for TDMB is enabled" "Normal operation,Enabled" group.byte 0x46++0x01 line.byte 0x00 "SISPD,SI Speed Register" bitfld.byte 0x00 7. " SPDA ,High-speed mode for TDMA enable" "Disabled,Enabled" bitfld.byte 0x00 6. " SPDB ,High-speed mode for TDMB enable" "Disabled,Enabled" line.byte 0x01 "SITXCEI,SI Tx Clock Edge Invert" bitfld.byte 0x01 7. " TXCEIA ,TDMA Tx clock edge invert" "Not inverted,Inverted" bitfld.byte 0x01 6. " TXCEIB ,TDMB Tx clock edge invert" "Not inverted,Inverted" endian.le width 0x0B tree.end endian.le width 0x0B tree.end endif sif cpuis("LS10?3A")||cpuis("LS10?6A") tree.open "DPAA (Data Path Acceleration Architecture)" tree "QMan (Queue Manager)" base ad:0x0500000000 width 20. endian.be tree "Software Portals" tree "Software Portal 0" group.quad 0x0++0x07 "QMan Software Portal 0, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP0_EQCR0,QMan Software Portal 0 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x40)++0x7 line.quad 0x00 "QCSP0_EQCR1,QMan Software Portal 0 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x80)++0x7 line.quad 0x00 "QCSP0_EQCR2,QMan Software Portal 0 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x0)++0x7 line.quad 0x00 "QCSP0_EQCR3,QMan Software Portal 0 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x0)++0x7 line.quad 0x00 "QCSP0_EQCR4,QMan Software Portal 0 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x0)++0x7 line.quad 0x00 "QCSP0_EQCR5,QMan Software Portal 0 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x0)++0x7 line.quad 0x00 "QCSP0_EQCR6,QMan Software Portal 0 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x0)++0x7 line.quad 0x00 "QCSP0_EQCR7,QMan Software Portal 0 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x0)++0x7 "QMan Software Portal 0, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP0_DQRR0,QMan Software Portal 0, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR1,QMan Software Portal 0, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR2,QMan Software Portal 0, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR3,QMan Software Portal 0, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR4,QMan Software Portal 0, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR5,QMan Software Portal 0, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR6,QMan Software Portal 0, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR7,QMan Software Portal 0, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR8,QMan Software Portal 0, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR9,QMan Software Portal 0, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR10,QMan Software Portal 0, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR11,QMan Software Portal 0, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR12,QMan Software Portal 0, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR13,QMan Software Portal 0, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR14,QMan Software Portal 0, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x0)++0x7 line.quad 0x00 "QCSP0_DQRR15,QMan Software Portal 0, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x0)++0x7 "QMan Software Portal 0, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP0_MR0,QMan Software Portal 0, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x0)++0x7 line.quad 0x00 "QCSP0_MR1,QMan Software Portal 0, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x0)++0x7 line.quad 0x00 "QCSP0_MR2,QMan Software Portal 0, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x0)++0x7 line.quad 0x00 "QCSP0_MR3,QMan Software Portal 0, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x0)++0x7 line.quad 0x00 "QCSP0_MR4,QMan Software Portal 0, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x0)++0x7 line.quad 0x00 "QCSP0_MR5,QMan Software Portal 0, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x0)++0x7 line.quad 0x00 "QCSP0_MR6,QMan Software Portal 0, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x0)++0x7 line.quad 0x00 "QCSP0_MR7,QMan Software Portal 0, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x0))&0x2000000)==0x2000000) rgroup.long (0x0+0x3000)++0x03 "QMan Software Portal 0, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP0_EQCR_PI_CENA,Software Portal 0 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x0+0x3000)++0x03 "QMan Software Portal 0, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP0_EQCR_PI_CENA,Software Portal 0 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x0+0x3040)++0x03 line.long 0x00 "QCSP0_EQCR_CI_CENA,Software Portal 0 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x0)++0x3 line.long 0x00 "QCSP0_DQRR_PI_CENA,Software Portal 0 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x0)++0x3 line.long 0x00 "QCSP0_DQRR_CI_CENA,Software Portal 0 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x0)++0x3 line.long 0x00 "QCSP0_MR_PI_CENA,Software Portal 0 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x0)++0x3 line.long 0x00 "QCSP0_MR_CI_CENA,Software Portal 0 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x0)++0x7 line.quad 0x00 "QCSP0_RORI_CENA,Software Portal 0 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x0)++0x7 line.quad 0x00 "QCSP0_CR,Software Portal 0, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x0)++0x7 line.quad 0x00 "QCSP0_RR0,Software Portal 0, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x0)++0x7 line.quad 0x00 "QCSP0_RR1,Software Portal 0, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x0+0x4000000)++0x07 "QMan Software Portal 0, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP0_EQCR0,QMan Software Portal 0 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x4000040)++0x07 line.quad 0x00 "QCSP0_EQCR1,QMan Software Portal 0 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x4000080)++0x07 line.quad 0x00 "QCSP0_EQCR2,QMan Software Portal 0 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x40000C0)++0x07 line.quad 0x00 "QCSP0_EQCR3,QMan Software Portal 0 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x4000100)++0x07 line.quad 0x00 "QCSP0_EQCR4,QMan Software Portal 0 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x0+0x4000140)++0x07 line.quad 0x00 "QCSP0_EQCR5,QMan Software Portal 0 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x0+0x4000180)++0x07 line.quad 0x00 "QCSP0_EQCR6,QMan Software Portal 0 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x0+0x40001C0)++0x07 line.quad 0x00 "QCSP0_EQCR7,QMan Software Portal 0 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x0+0x4001000)++0x07 "QMan Software Portal 0, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP0_DQRR0,QMan Software Portal 0, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001040)++0x07 line.quad 0x00 "QCSP0_DQRR1,QMan Software Portal 0, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001080)++0x07 line.quad 0x00 "QCSP0_DQRR2,QMan Software Portal 0, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40010C0)++0x07 line.quad 0x00 "QCSP0_DQRR3,QMan Software Portal 0, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001100)++0x07 line.quad 0x00 "QCSP0_DQRR4,QMan Software Portal 0, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001140)++0x07 line.quad 0x00 "QCSP0_DQRR5,QMan Software Portal 0, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x0+0x4001180)++0x07 line.quad 0x00 "QCSP0_DQRR6,QMan Software Portal 0, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40011C0)++0x07 line.quad 0x00 "QCSP0_DQRR7,QMan Software Portal 0, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001200)++0x07 line.quad 0x00 "QCSP0_DQRR8,QMan Software Portal 0, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001240)++0x07 line.quad 0x00 "QCSP0_DQRR9,QMan Software Portal 0, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001280)++0x07 line.quad 0x00 "QCSP0_DQRR10,QMan Software Portal 0, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40012C0)++0x07 line.quad 0x00 "QCSP0_DQRR11,QMan Software Portal 0, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001300)++0x07 line.quad 0x00 "QCSP0_DQRR12,QMan Software Portal 0, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001340)++0x07 line.quad 0x00 "QCSP0_DQRR13,QMan Software Portal 0, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4001380)++0x07 line.quad 0x00 "QCSP0_DQRR14,QMan Software Portal 0, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40013C0)++0x07 line.quad 0x00 "QCSP0_DQRR15,QMan Software Portal 0, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002000)++0x07 "QMan Software Portal 0, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP0_MR0,QMan Software Portal 0, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002040)++0x07 line.quad 0x00 "QCSP0_MR1,QMan Software Portal 0, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002080)++0x07 line.quad 0x00 "QCSP0_MR2,QMan Software Portal 0, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40020C0)++0x07 line.quad 0x00 "QCSP0_MR3,QMan Software Portal 0, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002100)++0x07 line.quad 0x00 "QCSP0_MR4,QMan Software Portal 0, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002140)++0x07 line.quad 0x00 "QCSP0_MR5,QMan Software Portal 0, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x4002180)++0x07 line.quad 0x00 "QCSP0_MR6,QMan Software Portal 0, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x0+0x40021C0)++0x07 line.quad 0x00 "QCSP0_MR7,QMan Software Portal 0, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x0))&0x2000000)==0x2000000) rgroup.long (0x0+0x4003000)++0x3 "QMan Software Portal 0, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_EQCR_PI_CINH,Software Portal 0, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x0+0x4003000)++0x3 "QMan Software Portal 0, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_EQCR_PI_CINH,Software Portal 0, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x0+0x4003040)++0x3 line.long 0x00 "QCSP0_EQCR_CI_CINH,Software Portal 0, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x0+0x4003080)++0x3 line.long 0x00 "QCSP0_EQCR_ITR,Software Portal 0, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x0+0x4003100)++0x3 "QMan Software Portal 0, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_DQRR_PI_CINH,Software Portal 0, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x0))&0x20000)==0x20000) rgroup.long (0x0+0x4003140)++0x3 line.long 0x00 "QCSP0_DQRR_CI_CINH,Software Portal 0, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x0+0x4003140)++0x3 line.long 0x00 "QCSP0_DQRR_CI_CINH,Software Portal 0, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x0+0x4003180)++0x3 line.long 0x00 "QCSP0_DQRR_ITR,Software Portal 0, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x0+0x40031C0)++0x3 line.long 0x00 "QCSP0_DQRR_DCAP,Software Portal 0, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x0+0x4003200)++0x3 line.long 0x00 "QCSP0_DQRR_SDQCR,Software Portal 0, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x0+0x4003240)++0x3 line.long 0x00 "QCSP0_DQRR_VDQCR,Software Portal 0, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x0+0x4003280)++0x3 line.long 0x00 "QCSP0_DQRR_PDQCR,Software Portal 0, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x0+0x4003300)++0x3 "QMan Software Portal 0, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_MR_PI_CINH,Software Portal 0, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x0+0x4003340)++0x3 line.long 0x00 "QCSP0_MR_CI_CINH,Software Portal 0, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x0+0x4003380)++0x3 line.long 0x00 "QCSP0_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x0+0x4003500)++0x3 "QMan Software Portal 0, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_CFG,Software Portal 0, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x0+0x4003600)++0x3 "QMan Software Portal 0, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP0_ISR,Software Portal 0, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x0+0x4003640)++0x3 line.long 0x00 "QCSP0_IER,Software Portal 0, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x0+0x4003680)++0x3 line.long 0x00 "QCSP0_ISDR,Software Portal 0, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x0+0x40036C0)++0x3 line.long 0x00 "QCSP0_IIR,Software Portal 0, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x0+0x4003740)++0x3 line.long 0x00 "QCSP0_ITPR,Software Portal 0 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x0+0x4003800)++0x07 line.quad 0x00 "QCSP0_CR,Software Portal 0, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x0+0x4003900)++0x07 line.quad 0x00 "QCSP0_RR0,Software Portal 0, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x0+0x4003940)++0x07 line.quad 0x00 "QCSP0_RR1,Software Portal 0, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 1" group.quad 0x10000++0x07 "QMan Software Portal 1, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP1_EQCR0,QMan Software Portal 1 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x40)++0x7 line.quad 0x00 "QCSP1_EQCR1,QMan Software Portal 1 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x80)++0x7 line.quad 0x00 "QCSP1_EQCR2,QMan Software Portal 1 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x10000)++0x7 line.quad 0x00 "QCSP1_EQCR3,QMan Software Portal 1 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x10000)++0x7 line.quad 0x00 "QCSP1_EQCR4,QMan Software Portal 1 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x10000)++0x7 line.quad 0x00 "QCSP1_EQCR5,QMan Software Portal 1 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x10000)++0x7 line.quad 0x00 "QCSP1_EQCR6,QMan Software Portal 1 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x10000)++0x7 line.quad 0x00 "QCSP1_EQCR7,QMan Software Portal 1 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x10000)++0x7 "QMan Software Portal 1, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP1_DQRR0,QMan Software Portal 1, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR1,QMan Software Portal 1, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR2,QMan Software Portal 1, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR3,QMan Software Portal 1, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR4,QMan Software Portal 1, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR5,QMan Software Portal 1, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR6,QMan Software Portal 1, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR7,QMan Software Portal 1, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR8,QMan Software Portal 1, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR9,QMan Software Portal 1, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR10,QMan Software Portal 1, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR11,QMan Software Portal 1, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR12,QMan Software Portal 1, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR13,QMan Software Portal 1, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR14,QMan Software Portal 1, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x10000)++0x7 line.quad 0x00 "QCSP1_DQRR15,QMan Software Portal 1, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x10000)++0x7 "QMan Software Portal 1, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP1_MR0,QMan Software Portal 1, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x10000)++0x7 line.quad 0x00 "QCSP1_MR1,QMan Software Portal 1, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x10000)++0x7 line.quad 0x00 "QCSP1_MR2,QMan Software Portal 1, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x10000)++0x7 line.quad 0x00 "QCSP1_MR3,QMan Software Portal 1, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x10000)++0x7 line.quad 0x00 "QCSP1_MR4,QMan Software Portal 1, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x10000)++0x7 line.quad 0x00 "QCSP1_MR5,QMan Software Portal 1, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x10000)++0x7 line.quad 0x00 "QCSP1_MR6,QMan Software Portal 1, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x10000)++0x7 line.quad 0x00 "QCSP1_MR7,QMan Software Portal 1, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x10000))&0x2000000)==0x2000000) rgroup.long (0x10000+0x3000)++0x03 "QMan Software Portal 1, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP1_EQCR_PI_CENA,Software Portal 1 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x10000+0x3000)++0x03 "QMan Software Portal 1, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP1_EQCR_PI_CENA,Software Portal 1 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x10000+0x3040)++0x03 line.long 0x00 "QCSP1_EQCR_CI_CENA,Software Portal 1 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x10000)++0x3 line.long 0x00 "QCSP1_DQRR_PI_CENA,Software Portal 1 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x10000)++0x3 line.long 0x00 "QCSP1_DQRR_CI_CENA,Software Portal 1 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x10000)++0x3 line.long 0x00 "QCSP1_MR_PI_CENA,Software Portal 1 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x10000)++0x3 line.long 0x00 "QCSP1_MR_CI_CENA,Software Portal 1 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x10000)++0x7 line.quad 0x00 "QCSP1_RORI_CENA,Software Portal 1 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x10000)++0x7 line.quad 0x00 "QCSP1_CR,Software Portal 1, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x10000)++0x7 line.quad 0x00 "QCSP1_RR0,Software Portal 1, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x10000)++0x7 line.quad 0x00 "QCSP1_RR1,Software Portal 1, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x10000+0x4000000)++0x07 "QMan Software Portal 1, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP1_EQCR0,QMan Software Portal 1 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x4000040)++0x07 line.quad 0x00 "QCSP1_EQCR1,QMan Software Portal 1 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x4000080)++0x07 line.quad 0x00 "QCSP1_EQCR2,QMan Software Portal 1 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x40000C0)++0x07 line.quad 0x00 "QCSP1_EQCR3,QMan Software Portal 1 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x4000100)++0x07 line.quad 0x00 "QCSP1_EQCR4,QMan Software Portal 1 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10000+0x4000140)++0x07 line.quad 0x00 "QCSP1_EQCR5,QMan Software Portal 1 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x10000+0x4000180)++0x07 line.quad 0x00 "QCSP1_EQCR6,QMan Software Portal 1 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x10000+0x40001C0)++0x07 line.quad 0x00 "QCSP1_EQCR7,QMan Software Portal 1 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x10000+0x4001000)++0x07 "QMan Software Portal 1, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP1_DQRR0,QMan Software Portal 1, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001040)++0x07 line.quad 0x00 "QCSP1_DQRR1,QMan Software Portal 1, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001080)++0x07 line.quad 0x00 "QCSP1_DQRR2,QMan Software Portal 1, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40010C0)++0x07 line.quad 0x00 "QCSP1_DQRR3,QMan Software Portal 1, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001100)++0x07 line.quad 0x00 "QCSP1_DQRR4,QMan Software Portal 1, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001140)++0x07 line.quad 0x00 "QCSP1_DQRR5,QMan Software Portal 1, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x10000+0x4001180)++0x07 line.quad 0x00 "QCSP1_DQRR6,QMan Software Portal 1, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40011C0)++0x07 line.quad 0x00 "QCSP1_DQRR7,QMan Software Portal 1, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001200)++0x07 line.quad 0x00 "QCSP1_DQRR8,QMan Software Portal 1, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001240)++0x07 line.quad 0x00 "QCSP1_DQRR9,QMan Software Portal 1, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001280)++0x07 line.quad 0x00 "QCSP1_DQRR10,QMan Software Portal 1, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40012C0)++0x07 line.quad 0x00 "QCSP1_DQRR11,QMan Software Portal 1, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001300)++0x07 line.quad 0x00 "QCSP1_DQRR12,QMan Software Portal 1, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001340)++0x07 line.quad 0x00 "QCSP1_DQRR13,QMan Software Portal 1, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4001380)++0x07 line.quad 0x00 "QCSP1_DQRR14,QMan Software Portal 1, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40013C0)++0x07 line.quad 0x00 "QCSP1_DQRR15,QMan Software Portal 1, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002000)++0x07 "QMan Software Portal 1, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP1_MR0,QMan Software Portal 1, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002040)++0x07 line.quad 0x00 "QCSP1_MR1,QMan Software Portal 1, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002080)++0x07 line.quad 0x00 "QCSP1_MR2,QMan Software Portal 1, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40020C0)++0x07 line.quad 0x00 "QCSP1_MR3,QMan Software Portal 1, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002100)++0x07 line.quad 0x00 "QCSP1_MR4,QMan Software Portal 1, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002140)++0x07 line.quad 0x00 "QCSP1_MR5,QMan Software Portal 1, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x4002180)++0x07 line.quad 0x00 "QCSP1_MR6,QMan Software Portal 1, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10000+0x40021C0)++0x07 line.quad 0x00 "QCSP1_MR7,QMan Software Portal 1, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x10000))&0x2000000)==0x2000000) rgroup.long (0x10000+0x4003000)++0x3 "QMan Software Portal 1, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_EQCR_PI_CINH,Software Portal 1, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x10000+0x4003000)++0x3 "QMan Software Portal 1, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_EQCR_PI_CINH,Software Portal 1, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x10000+0x4003040)++0x3 line.long 0x00 "QCSP1_EQCR_CI_CINH,Software Portal 1, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x10000+0x4003080)++0x3 line.long 0x00 "QCSP1_EQCR_ITR,Software Portal 1, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x10000+0x4003100)++0x3 "QMan Software Portal 1, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_DQRR_PI_CINH,Software Portal 1, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x10000))&0x20000)==0x20000) rgroup.long (0x10000+0x4003140)++0x3 line.long 0x00 "QCSP1_DQRR_CI_CINH,Software Portal 1, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x10000+0x4003140)++0x3 line.long 0x00 "QCSP1_DQRR_CI_CINH,Software Portal 1, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x10000+0x4003180)++0x3 line.long 0x00 "QCSP1_DQRR_ITR,Software Portal 1, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x10000+0x40031C0)++0x3 line.long 0x00 "QCSP1_DQRR_DCAP,Software Portal 1, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x10000+0x4003200)++0x3 line.long 0x00 "QCSP1_DQRR_SDQCR,Software Portal 1, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x10000+0x4003240)++0x3 line.long 0x00 "QCSP1_DQRR_VDQCR,Software Portal 1, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x10000+0x4003280)++0x3 line.long 0x00 "QCSP1_DQRR_PDQCR,Software Portal 1, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x10000+0x4003300)++0x3 "QMan Software Portal 1, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_MR_PI_CINH,Software Portal 1, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x10000+0x4003340)++0x3 line.long 0x00 "QCSP1_MR_CI_CINH,Software Portal 1, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x10000+0x4003380)++0x3 line.long 0x00 "QCSP1_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x10000+0x4003500)++0x3 "QMan Software Portal 1, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_CFG,Software Portal 1, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x10000+0x4003600)++0x3 "QMan Software Portal 1, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP1_ISR,Software Portal 1, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x10000+0x4003640)++0x3 line.long 0x00 "QCSP1_IER,Software Portal 1, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x10000+0x4003680)++0x3 line.long 0x00 "QCSP1_ISDR,Software Portal 1, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x10000+0x40036C0)++0x3 line.long 0x00 "QCSP1_IIR,Software Portal 1, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x10000+0x4003740)++0x3 line.long 0x00 "QCSP1_ITPR,Software Portal 1 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x10000+0x4003800)++0x07 line.quad 0x00 "QCSP1_CR,Software Portal 1, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x10000+0x4003900)++0x07 line.quad 0x00 "QCSP1_RR0,Software Portal 1, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x10000+0x4003940)++0x07 line.quad 0x00 "QCSP1_RR1,Software Portal 1, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 2" group.quad 0x20000++0x07 "QMan Software Portal 2, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP2_EQCR0,QMan Software Portal 2 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x40)++0x7 line.quad 0x00 "QCSP2_EQCR1,QMan Software Portal 2 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x80)++0x7 line.quad 0x00 "QCSP2_EQCR2,QMan Software Portal 2 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x20000)++0x7 line.quad 0x00 "QCSP2_EQCR3,QMan Software Portal 2 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x20000)++0x7 line.quad 0x00 "QCSP2_EQCR4,QMan Software Portal 2 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x20000)++0x7 line.quad 0x00 "QCSP2_EQCR5,QMan Software Portal 2 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x20000)++0x7 line.quad 0x00 "QCSP2_EQCR6,QMan Software Portal 2 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x20000)++0x7 line.quad 0x00 "QCSP2_EQCR7,QMan Software Portal 2 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x20000)++0x7 "QMan Software Portal 2, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP2_DQRR0,QMan Software Portal 2, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR1,QMan Software Portal 2, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR2,QMan Software Portal 2, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR3,QMan Software Portal 2, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR4,QMan Software Portal 2, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR5,QMan Software Portal 2, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR6,QMan Software Portal 2, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR7,QMan Software Portal 2, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR8,QMan Software Portal 2, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR9,QMan Software Portal 2, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR10,QMan Software Portal 2, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR11,QMan Software Portal 2, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR12,QMan Software Portal 2, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR13,QMan Software Portal 2, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR14,QMan Software Portal 2, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x20000)++0x7 line.quad 0x00 "QCSP2_DQRR15,QMan Software Portal 2, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x20000)++0x7 "QMan Software Portal 2, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP2_MR0,QMan Software Portal 2, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x20000)++0x7 line.quad 0x00 "QCSP2_MR1,QMan Software Portal 2, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x20000)++0x7 line.quad 0x00 "QCSP2_MR2,QMan Software Portal 2, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x20000)++0x7 line.quad 0x00 "QCSP2_MR3,QMan Software Portal 2, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x20000)++0x7 line.quad 0x00 "QCSP2_MR4,QMan Software Portal 2, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x20000)++0x7 line.quad 0x00 "QCSP2_MR5,QMan Software Portal 2, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x20000)++0x7 line.quad 0x00 "QCSP2_MR6,QMan Software Portal 2, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x20000)++0x7 line.quad 0x00 "QCSP2_MR7,QMan Software Portal 2, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x20000))&0x2000000)==0x2000000) rgroup.long (0x20000+0x3000)++0x03 "QMan Software Portal 2, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP2_EQCR_PI_CENA,Software Portal 2 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x20000+0x3000)++0x03 "QMan Software Portal 2, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP2_EQCR_PI_CENA,Software Portal 2 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x20000+0x3040)++0x03 line.long 0x00 "QCSP2_EQCR_CI_CENA,Software Portal 2 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x20000)++0x3 line.long 0x00 "QCSP2_DQRR_PI_CENA,Software Portal 2 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x20000)++0x3 line.long 0x00 "QCSP2_DQRR_CI_CENA,Software Portal 2 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x20000)++0x3 line.long 0x00 "QCSP2_MR_PI_CENA,Software Portal 2 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x20000)++0x3 line.long 0x00 "QCSP2_MR_CI_CENA,Software Portal 2 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x20000)++0x7 line.quad 0x00 "QCSP2_RORI_CENA,Software Portal 2 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x20000)++0x7 line.quad 0x00 "QCSP2_CR,Software Portal 2, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x20000)++0x7 line.quad 0x00 "QCSP2_RR0,Software Portal 2, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x20000)++0x7 line.quad 0x00 "QCSP2_RR1,Software Portal 2, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x20000+0x4000000)++0x07 "QMan Software Portal 2, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP2_EQCR0,QMan Software Portal 2 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x4000040)++0x07 line.quad 0x00 "QCSP2_EQCR1,QMan Software Portal 2 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x4000080)++0x07 line.quad 0x00 "QCSP2_EQCR2,QMan Software Portal 2 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x40000C0)++0x07 line.quad 0x00 "QCSP2_EQCR3,QMan Software Portal 2 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x4000100)++0x07 line.quad 0x00 "QCSP2_EQCR4,QMan Software Portal 2 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x20000+0x4000140)++0x07 line.quad 0x00 "QCSP2_EQCR5,QMan Software Portal 2 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x20000+0x4000180)++0x07 line.quad 0x00 "QCSP2_EQCR6,QMan Software Portal 2 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x20000+0x40001C0)++0x07 line.quad 0x00 "QCSP2_EQCR7,QMan Software Portal 2 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x20000+0x4001000)++0x07 "QMan Software Portal 2, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP2_DQRR0,QMan Software Portal 2, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001040)++0x07 line.quad 0x00 "QCSP2_DQRR1,QMan Software Portal 2, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001080)++0x07 line.quad 0x00 "QCSP2_DQRR2,QMan Software Portal 2, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40010C0)++0x07 line.quad 0x00 "QCSP2_DQRR3,QMan Software Portal 2, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001100)++0x07 line.quad 0x00 "QCSP2_DQRR4,QMan Software Portal 2, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001140)++0x07 line.quad 0x00 "QCSP2_DQRR5,QMan Software Portal 2, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x20000+0x4001180)++0x07 line.quad 0x00 "QCSP2_DQRR6,QMan Software Portal 2, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40011C0)++0x07 line.quad 0x00 "QCSP2_DQRR7,QMan Software Portal 2, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001200)++0x07 line.quad 0x00 "QCSP2_DQRR8,QMan Software Portal 2, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001240)++0x07 line.quad 0x00 "QCSP2_DQRR9,QMan Software Portal 2, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001280)++0x07 line.quad 0x00 "QCSP2_DQRR10,QMan Software Portal 2, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40012C0)++0x07 line.quad 0x00 "QCSP2_DQRR11,QMan Software Portal 2, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001300)++0x07 line.quad 0x00 "QCSP2_DQRR12,QMan Software Portal 2, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001340)++0x07 line.quad 0x00 "QCSP2_DQRR13,QMan Software Portal 2, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4001380)++0x07 line.quad 0x00 "QCSP2_DQRR14,QMan Software Portal 2, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40013C0)++0x07 line.quad 0x00 "QCSP2_DQRR15,QMan Software Portal 2, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002000)++0x07 "QMan Software Portal 2, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP2_MR0,QMan Software Portal 2, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002040)++0x07 line.quad 0x00 "QCSP2_MR1,QMan Software Portal 2, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002080)++0x07 line.quad 0x00 "QCSP2_MR2,QMan Software Portal 2, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40020C0)++0x07 line.quad 0x00 "QCSP2_MR3,QMan Software Portal 2, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002100)++0x07 line.quad 0x00 "QCSP2_MR4,QMan Software Portal 2, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002140)++0x07 line.quad 0x00 "QCSP2_MR5,QMan Software Portal 2, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x4002180)++0x07 line.quad 0x00 "QCSP2_MR6,QMan Software Portal 2, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20000+0x40021C0)++0x07 line.quad 0x00 "QCSP2_MR7,QMan Software Portal 2, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x20000))&0x2000000)==0x2000000) rgroup.long (0x20000+0x4003000)++0x3 "QMan Software Portal 2, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_EQCR_PI_CINH,Software Portal 2, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x20000+0x4003000)++0x3 "QMan Software Portal 2, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_EQCR_PI_CINH,Software Portal 2, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x20000+0x4003040)++0x3 line.long 0x00 "QCSP2_EQCR_CI_CINH,Software Portal 2, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x20000+0x4003080)++0x3 line.long 0x00 "QCSP2_EQCR_ITR,Software Portal 2, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x20000+0x4003100)++0x3 "QMan Software Portal 2, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_DQRR_PI_CINH,Software Portal 2, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x20000))&0x20000)==0x20000) rgroup.long (0x20000+0x4003140)++0x3 line.long 0x00 "QCSP2_DQRR_CI_CINH,Software Portal 2, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x20000+0x4003140)++0x3 line.long 0x00 "QCSP2_DQRR_CI_CINH,Software Portal 2, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x20000+0x4003180)++0x3 line.long 0x00 "QCSP2_DQRR_ITR,Software Portal 2, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x20000+0x40031C0)++0x3 line.long 0x00 "QCSP2_DQRR_DCAP,Software Portal 2, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x20000+0x4003200)++0x3 line.long 0x00 "QCSP2_DQRR_SDQCR,Software Portal 2, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x20000+0x4003240)++0x3 line.long 0x00 "QCSP2_DQRR_VDQCR,Software Portal 2, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x20000+0x4003280)++0x3 line.long 0x00 "QCSP2_DQRR_PDQCR,Software Portal 2, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x20000+0x4003300)++0x3 "QMan Software Portal 2, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_MR_PI_CINH,Software Portal 2, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x20000+0x4003340)++0x3 line.long 0x00 "QCSP2_MR_CI_CINH,Software Portal 2, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x20000+0x4003380)++0x3 line.long 0x00 "QCSP2_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x20000+0x4003500)++0x3 "QMan Software Portal 2, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_CFG,Software Portal 2, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x20000+0x4003600)++0x3 "QMan Software Portal 2, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP2_ISR,Software Portal 2, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x20000+0x4003640)++0x3 line.long 0x00 "QCSP2_IER,Software Portal 2, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x20000+0x4003680)++0x3 line.long 0x00 "QCSP2_ISDR,Software Portal 2, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x20000+0x40036C0)++0x3 line.long 0x00 "QCSP2_IIR,Software Portal 2, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x20000+0x4003740)++0x3 line.long 0x00 "QCSP2_ITPR,Software Portal 2 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x20000+0x4003800)++0x07 line.quad 0x00 "QCSP2_CR,Software Portal 2, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x20000+0x4003900)++0x07 line.quad 0x00 "QCSP2_RR0,Software Portal 2, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x20000+0x4003940)++0x07 line.quad 0x00 "QCSP2_RR1,Software Portal 2, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 3" group.quad 0x30000++0x07 "QMan Software Portal 3, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP3_EQCR0,QMan Software Portal 3 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x40)++0x7 line.quad 0x00 "QCSP3_EQCR1,QMan Software Portal 3 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x80)++0x7 line.quad 0x00 "QCSP3_EQCR2,QMan Software Portal 3 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x30000)++0x7 line.quad 0x00 "QCSP3_EQCR3,QMan Software Portal 3 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x30000)++0x7 line.quad 0x00 "QCSP3_EQCR4,QMan Software Portal 3 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x30000)++0x7 line.quad 0x00 "QCSP3_EQCR5,QMan Software Portal 3 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x30000)++0x7 line.quad 0x00 "QCSP3_EQCR6,QMan Software Portal 3 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x30000)++0x7 line.quad 0x00 "QCSP3_EQCR7,QMan Software Portal 3 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x30000)++0x7 "QMan Software Portal 3, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP3_DQRR0,QMan Software Portal 3, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR1,QMan Software Portal 3, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR2,QMan Software Portal 3, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR3,QMan Software Portal 3, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR4,QMan Software Portal 3, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR5,QMan Software Portal 3, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR6,QMan Software Portal 3, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR7,QMan Software Portal 3, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR8,QMan Software Portal 3, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR9,QMan Software Portal 3, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR10,QMan Software Portal 3, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR11,QMan Software Portal 3, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR12,QMan Software Portal 3, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR13,QMan Software Portal 3, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR14,QMan Software Portal 3, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x30000)++0x7 line.quad 0x00 "QCSP3_DQRR15,QMan Software Portal 3, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x30000)++0x7 "QMan Software Portal 3, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP3_MR0,QMan Software Portal 3, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x30000)++0x7 line.quad 0x00 "QCSP3_MR1,QMan Software Portal 3, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x30000)++0x7 line.quad 0x00 "QCSP3_MR2,QMan Software Portal 3, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x30000)++0x7 line.quad 0x00 "QCSP3_MR3,QMan Software Portal 3, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x30000)++0x7 line.quad 0x00 "QCSP3_MR4,QMan Software Portal 3, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x30000)++0x7 line.quad 0x00 "QCSP3_MR5,QMan Software Portal 3, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x30000)++0x7 line.quad 0x00 "QCSP3_MR6,QMan Software Portal 3, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x30000)++0x7 line.quad 0x00 "QCSP3_MR7,QMan Software Portal 3, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x30000))&0x2000000)==0x2000000) rgroup.long (0x30000+0x3000)++0x03 "QMan Software Portal 3, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP3_EQCR_PI_CENA,Software Portal 3 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x30000+0x3000)++0x03 "QMan Software Portal 3, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP3_EQCR_PI_CENA,Software Portal 3 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x30000+0x3040)++0x03 line.long 0x00 "QCSP3_EQCR_CI_CENA,Software Portal 3 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x30000)++0x3 line.long 0x00 "QCSP3_DQRR_PI_CENA,Software Portal 3 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x30000)++0x3 line.long 0x00 "QCSP3_DQRR_CI_CENA,Software Portal 3 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x30000)++0x3 line.long 0x00 "QCSP3_MR_PI_CENA,Software Portal 3 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x30000)++0x3 line.long 0x00 "QCSP3_MR_CI_CENA,Software Portal 3 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x30000)++0x7 line.quad 0x00 "QCSP3_RORI_CENA,Software Portal 3 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x30000)++0x7 line.quad 0x00 "QCSP3_CR,Software Portal 3, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x30000)++0x7 line.quad 0x00 "QCSP3_RR0,Software Portal 3, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x30000)++0x7 line.quad 0x00 "QCSP3_RR1,Software Portal 3, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x30000+0x4000000)++0x07 "QMan Software Portal 3, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP3_EQCR0,QMan Software Portal 3 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x4000040)++0x07 line.quad 0x00 "QCSP3_EQCR1,QMan Software Portal 3 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x4000080)++0x07 line.quad 0x00 "QCSP3_EQCR2,QMan Software Portal 3 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x40000C0)++0x07 line.quad 0x00 "QCSP3_EQCR3,QMan Software Portal 3 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x4000100)++0x07 line.quad 0x00 "QCSP3_EQCR4,QMan Software Portal 3 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x30000+0x4000140)++0x07 line.quad 0x00 "QCSP3_EQCR5,QMan Software Portal 3 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x30000+0x4000180)++0x07 line.quad 0x00 "QCSP3_EQCR6,QMan Software Portal 3 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x30000+0x40001C0)++0x07 line.quad 0x00 "QCSP3_EQCR7,QMan Software Portal 3 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x30000+0x4001000)++0x07 "QMan Software Portal 3, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP3_DQRR0,QMan Software Portal 3, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001040)++0x07 line.quad 0x00 "QCSP3_DQRR1,QMan Software Portal 3, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001080)++0x07 line.quad 0x00 "QCSP3_DQRR2,QMan Software Portal 3, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40010C0)++0x07 line.quad 0x00 "QCSP3_DQRR3,QMan Software Portal 3, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001100)++0x07 line.quad 0x00 "QCSP3_DQRR4,QMan Software Portal 3, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001140)++0x07 line.quad 0x00 "QCSP3_DQRR5,QMan Software Portal 3, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x30000+0x4001180)++0x07 line.quad 0x00 "QCSP3_DQRR6,QMan Software Portal 3, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40011C0)++0x07 line.quad 0x00 "QCSP3_DQRR7,QMan Software Portal 3, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001200)++0x07 line.quad 0x00 "QCSP3_DQRR8,QMan Software Portal 3, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001240)++0x07 line.quad 0x00 "QCSP3_DQRR9,QMan Software Portal 3, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001280)++0x07 line.quad 0x00 "QCSP3_DQRR10,QMan Software Portal 3, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40012C0)++0x07 line.quad 0x00 "QCSP3_DQRR11,QMan Software Portal 3, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001300)++0x07 line.quad 0x00 "QCSP3_DQRR12,QMan Software Portal 3, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001340)++0x07 line.quad 0x00 "QCSP3_DQRR13,QMan Software Portal 3, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4001380)++0x07 line.quad 0x00 "QCSP3_DQRR14,QMan Software Portal 3, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40013C0)++0x07 line.quad 0x00 "QCSP3_DQRR15,QMan Software Portal 3, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002000)++0x07 "QMan Software Portal 3, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP3_MR0,QMan Software Portal 3, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002040)++0x07 line.quad 0x00 "QCSP3_MR1,QMan Software Portal 3, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002080)++0x07 line.quad 0x00 "QCSP3_MR2,QMan Software Portal 3, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40020C0)++0x07 line.quad 0x00 "QCSP3_MR3,QMan Software Portal 3, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002100)++0x07 line.quad 0x00 "QCSP3_MR4,QMan Software Portal 3, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002140)++0x07 line.quad 0x00 "QCSP3_MR5,QMan Software Portal 3, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x4002180)++0x07 line.quad 0x00 "QCSP3_MR6,QMan Software Portal 3, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x30000+0x40021C0)++0x07 line.quad 0x00 "QCSP3_MR7,QMan Software Portal 3, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x30000))&0x2000000)==0x2000000) rgroup.long (0x30000+0x4003000)++0x3 "QMan Software Portal 3, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_EQCR_PI_CINH,Software Portal 3, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x30000+0x4003000)++0x3 "QMan Software Portal 3, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_EQCR_PI_CINH,Software Portal 3, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x30000+0x4003040)++0x3 line.long 0x00 "QCSP3_EQCR_CI_CINH,Software Portal 3, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x30000+0x4003080)++0x3 line.long 0x00 "QCSP3_EQCR_ITR,Software Portal 3, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x30000+0x4003100)++0x3 "QMan Software Portal 3, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_DQRR_PI_CINH,Software Portal 3, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x30000))&0x20000)==0x20000) rgroup.long (0x30000+0x4003140)++0x3 line.long 0x00 "QCSP3_DQRR_CI_CINH,Software Portal 3, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x30000+0x4003140)++0x3 line.long 0x00 "QCSP3_DQRR_CI_CINH,Software Portal 3, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x30000+0x4003180)++0x3 line.long 0x00 "QCSP3_DQRR_ITR,Software Portal 3, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x30000+0x40031C0)++0x3 line.long 0x00 "QCSP3_DQRR_DCAP,Software Portal 3, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x30000+0x4003200)++0x3 line.long 0x00 "QCSP3_DQRR_SDQCR,Software Portal 3, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x30000+0x4003240)++0x3 line.long 0x00 "QCSP3_DQRR_VDQCR,Software Portal 3, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x30000+0x4003280)++0x3 line.long 0x00 "QCSP3_DQRR_PDQCR,Software Portal 3, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x30000+0x4003300)++0x3 "QMan Software Portal 3, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_MR_PI_CINH,Software Portal 3, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x30000+0x4003340)++0x3 line.long 0x00 "QCSP3_MR_CI_CINH,Software Portal 3, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x30000+0x4003380)++0x3 line.long 0x00 "QCSP3_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x30000+0x4003500)++0x3 "QMan Software Portal 3, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_CFG,Software Portal 3, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x30000+0x4003600)++0x3 "QMan Software Portal 3, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP3_ISR,Software Portal 3, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x30000+0x4003640)++0x3 line.long 0x00 "QCSP3_IER,Software Portal 3, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x30000+0x4003680)++0x3 line.long 0x00 "QCSP3_ISDR,Software Portal 3, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x30000+0x40036C0)++0x3 line.long 0x00 "QCSP3_IIR,Software Portal 3, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x30000+0x4003740)++0x3 line.long 0x00 "QCSP3_ITPR,Software Portal 3 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x30000+0x4003800)++0x07 line.quad 0x00 "QCSP3_CR,Software Portal 3, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x30000+0x4003900)++0x07 line.quad 0x00 "QCSP3_RR0,Software Portal 3, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x30000+0x4003940)++0x07 line.quad 0x00 "QCSP3_RR1,Software Portal 3, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 4" group.quad 0x40000++0x07 "QMan Software Portal 4, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP4_EQCR0,QMan Software Portal 4 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x40)++0x7 line.quad 0x00 "QCSP4_EQCR1,QMan Software Portal 4 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x80)++0x7 line.quad 0x00 "QCSP4_EQCR2,QMan Software Portal 4 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x40000)++0x7 line.quad 0x00 "QCSP4_EQCR3,QMan Software Portal 4 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x40000)++0x7 line.quad 0x00 "QCSP4_EQCR4,QMan Software Portal 4 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x40000)++0x7 line.quad 0x00 "QCSP4_EQCR5,QMan Software Portal 4 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x40000)++0x7 line.quad 0x00 "QCSP4_EQCR6,QMan Software Portal 4 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x40000)++0x7 line.quad 0x00 "QCSP4_EQCR7,QMan Software Portal 4 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x40000)++0x7 "QMan Software Portal 4, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP4_DQRR0,QMan Software Portal 4, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR1,QMan Software Portal 4, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR2,QMan Software Portal 4, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR3,QMan Software Portal 4, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR4,QMan Software Portal 4, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR5,QMan Software Portal 4, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR6,QMan Software Portal 4, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR7,QMan Software Portal 4, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR8,QMan Software Portal 4, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR9,QMan Software Portal 4, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR10,QMan Software Portal 4, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR11,QMan Software Portal 4, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR12,QMan Software Portal 4, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR13,QMan Software Portal 4, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR14,QMan Software Portal 4, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x40000)++0x7 line.quad 0x00 "QCSP4_DQRR15,QMan Software Portal 4, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x40000)++0x7 "QMan Software Portal 4, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP4_MR0,QMan Software Portal 4, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x40000)++0x7 line.quad 0x00 "QCSP4_MR1,QMan Software Portal 4, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x40000)++0x7 line.quad 0x00 "QCSP4_MR2,QMan Software Portal 4, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x40000)++0x7 line.quad 0x00 "QCSP4_MR3,QMan Software Portal 4, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x40000)++0x7 line.quad 0x00 "QCSP4_MR4,QMan Software Portal 4, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x40000)++0x7 line.quad 0x00 "QCSP4_MR5,QMan Software Portal 4, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x40000)++0x7 line.quad 0x00 "QCSP4_MR6,QMan Software Portal 4, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x40000)++0x7 line.quad 0x00 "QCSP4_MR7,QMan Software Portal 4, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x40000))&0x2000000)==0x2000000) rgroup.long (0x40000+0x3000)++0x03 "QMan Software Portal 4, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP4_EQCR_PI_CENA,Software Portal 4 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x40000+0x3000)++0x03 "QMan Software Portal 4, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP4_EQCR_PI_CENA,Software Portal 4 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x40000+0x3040)++0x03 line.long 0x00 "QCSP4_EQCR_CI_CENA,Software Portal 4 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x40000)++0x3 line.long 0x00 "QCSP4_DQRR_PI_CENA,Software Portal 4 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x40000)++0x3 line.long 0x00 "QCSP4_DQRR_CI_CENA,Software Portal 4 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x40000)++0x3 line.long 0x00 "QCSP4_MR_PI_CENA,Software Portal 4 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x40000)++0x3 line.long 0x00 "QCSP4_MR_CI_CENA,Software Portal 4 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x40000)++0x7 line.quad 0x00 "QCSP4_RORI_CENA,Software Portal 4 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x40000)++0x7 line.quad 0x00 "QCSP4_CR,Software Portal 4, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x40000)++0x7 line.quad 0x00 "QCSP4_RR0,Software Portal 4, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x40000)++0x7 line.quad 0x00 "QCSP4_RR1,Software Portal 4, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x40000+0x4000000)++0x07 "QMan Software Portal 4, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP4_EQCR0,QMan Software Portal 4 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x4000040)++0x07 line.quad 0x00 "QCSP4_EQCR1,QMan Software Portal 4 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x4000080)++0x07 line.quad 0x00 "QCSP4_EQCR2,QMan Software Portal 4 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x40000C0)++0x07 line.quad 0x00 "QCSP4_EQCR3,QMan Software Portal 4 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x4000100)++0x07 line.quad 0x00 "QCSP4_EQCR4,QMan Software Portal 4 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40000+0x4000140)++0x07 line.quad 0x00 "QCSP4_EQCR5,QMan Software Portal 4 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x40000+0x4000180)++0x07 line.quad 0x00 "QCSP4_EQCR6,QMan Software Portal 4 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x40000+0x40001C0)++0x07 line.quad 0x00 "QCSP4_EQCR7,QMan Software Portal 4 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x40000+0x4001000)++0x07 "QMan Software Portal 4, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP4_DQRR0,QMan Software Portal 4, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001040)++0x07 line.quad 0x00 "QCSP4_DQRR1,QMan Software Portal 4, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001080)++0x07 line.quad 0x00 "QCSP4_DQRR2,QMan Software Portal 4, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40010C0)++0x07 line.quad 0x00 "QCSP4_DQRR3,QMan Software Portal 4, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001100)++0x07 line.quad 0x00 "QCSP4_DQRR4,QMan Software Portal 4, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001140)++0x07 line.quad 0x00 "QCSP4_DQRR5,QMan Software Portal 4, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x40000+0x4001180)++0x07 line.quad 0x00 "QCSP4_DQRR6,QMan Software Portal 4, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40011C0)++0x07 line.quad 0x00 "QCSP4_DQRR7,QMan Software Portal 4, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001200)++0x07 line.quad 0x00 "QCSP4_DQRR8,QMan Software Portal 4, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001240)++0x07 line.quad 0x00 "QCSP4_DQRR9,QMan Software Portal 4, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001280)++0x07 line.quad 0x00 "QCSP4_DQRR10,QMan Software Portal 4, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40012C0)++0x07 line.quad 0x00 "QCSP4_DQRR11,QMan Software Portal 4, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001300)++0x07 line.quad 0x00 "QCSP4_DQRR12,QMan Software Portal 4, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001340)++0x07 line.quad 0x00 "QCSP4_DQRR13,QMan Software Portal 4, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4001380)++0x07 line.quad 0x00 "QCSP4_DQRR14,QMan Software Portal 4, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40013C0)++0x07 line.quad 0x00 "QCSP4_DQRR15,QMan Software Portal 4, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002000)++0x07 "QMan Software Portal 4, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP4_MR0,QMan Software Portal 4, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002040)++0x07 line.quad 0x00 "QCSP4_MR1,QMan Software Portal 4, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002080)++0x07 line.quad 0x00 "QCSP4_MR2,QMan Software Portal 4, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40020C0)++0x07 line.quad 0x00 "QCSP4_MR3,QMan Software Portal 4, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002100)++0x07 line.quad 0x00 "QCSP4_MR4,QMan Software Portal 4, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002140)++0x07 line.quad 0x00 "QCSP4_MR5,QMan Software Portal 4, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x4002180)++0x07 line.quad 0x00 "QCSP4_MR6,QMan Software Portal 4, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x40000+0x40021C0)++0x07 line.quad 0x00 "QCSP4_MR7,QMan Software Portal 4, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x40000))&0x2000000)==0x2000000) rgroup.long (0x40000+0x4003000)++0x3 "QMan Software Portal 4, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_EQCR_PI_CINH,Software Portal 4, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x40000+0x4003000)++0x3 "QMan Software Portal 4, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_EQCR_PI_CINH,Software Portal 4, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x40000+0x4003040)++0x3 line.long 0x00 "QCSP4_EQCR_CI_CINH,Software Portal 4, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x40000+0x4003080)++0x3 line.long 0x00 "QCSP4_EQCR_ITR,Software Portal 4, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x40000+0x4003100)++0x3 "QMan Software Portal 4, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_DQRR_PI_CINH,Software Portal 4, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x40000))&0x20000)==0x20000) rgroup.long (0x40000+0x4003140)++0x3 line.long 0x00 "QCSP4_DQRR_CI_CINH,Software Portal 4, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x40000+0x4003140)++0x3 line.long 0x00 "QCSP4_DQRR_CI_CINH,Software Portal 4, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x40000+0x4003180)++0x3 line.long 0x00 "QCSP4_DQRR_ITR,Software Portal 4, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x40000+0x40031C0)++0x3 line.long 0x00 "QCSP4_DQRR_DCAP,Software Portal 4, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x40000+0x4003200)++0x3 line.long 0x00 "QCSP4_DQRR_SDQCR,Software Portal 4, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x40000+0x4003240)++0x3 line.long 0x00 "QCSP4_DQRR_VDQCR,Software Portal 4, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x40000+0x4003280)++0x3 line.long 0x00 "QCSP4_DQRR_PDQCR,Software Portal 4, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x40000+0x4003300)++0x3 "QMan Software Portal 4, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_MR_PI_CINH,Software Portal 4, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x40000+0x4003340)++0x3 line.long 0x00 "QCSP4_MR_CI_CINH,Software Portal 4, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x40000+0x4003380)++0x3 line.long 0x00 "QCSP4_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x40000+0x4003500)++0x3 "QMan Software Portal 4, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_CFG,Software Portal 4, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x40000+0x4003600)++0x3 "QMan Software Portal 4, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP4_ISR,Software Portal 4, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x40000+0x4003640)++0x3 line.long 0x00 "QCSP4_IER,Software Portal 4, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x40000+0x4003680)++0x3 line.long 0x00 "QCSP4_ISDR,Software Portal 4, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x40000+0x40036C0)++0x3 line.long 0x00 "QCSP4_IIR,Software Portal 4, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x40000+0x4003740)++0x3 line.long 0x00 "QCSP4_ITPR,Software Portal 4 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x40000+0x4003800)++0x07 line.quad 0x00 "QCSP4_CR,Software Portal 4, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x40000+0x4003900)++0x07 line.quad 0x00 "QCSP4_RR0,Software Portal 4, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x40000+0x4003940)++0x07 line.quad 0x00 "QCSP4_RR1,Software Portal 4, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 5" group.quad 0x50000++0x07 "QMan Software Portal 5, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP5_EQCR0,QMan Software Portal 5 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x40)++0x7 line.quad 0x00 "QCSP5_EQCR1,QMan Software Portal 5 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x80)++0x7 line.quad 0x00 "QCSP5_EQCR2,QMan Software Portal 5 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x50000)++0x7 line.quad 0x00 "QCSP5_EQCR3,QMan Software Portal 5 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x50000)++0x7 line.quad 0x00 "QCSP5_EQCR4,QMan Software Portal 5 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x50000)++0x7 line.quad 0x00 "QCSP5_EQCR5,QMan Software Portal 5 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x50000)++0x7 line.quad 0x00 "QCSP5_EQCR6,QMan Software Portal 5 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x50000)++0x7 line.quad 0x00 "QCSP5_EQCR7,QMan Software Portal 5 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x50000)++0x7 "QMan Software Portal 5, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP5_DQRR0,QMan Software Portal 5, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR1,QMan Software Portal 5, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR2,QMan Software Portal 5, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR3,QMan Software Portal 5, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR4,QMan Software Portal 5, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR5,QMan Software Portal 5, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR6,QMan Software Portal 5, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR7,QMan Software Portal 5, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR8,QMan Software Portal 5, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR9,QMan Software Portal 5, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR10,QMan Software Portal 5, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR11,QMan Software Portal 5, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR12,QMan Software Portal 5, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR13,QMan Software Portal 5, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR14,QMan Software Portal 5, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x50000)++0x7 line.quad 0x00 "QCSP5_DQRR15,QMan Software Portal 5, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x50000)++0x7 "QMan Software Portal 5, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP5_MR0,QMan Software Portal 5, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x50000)++0x7 line.quad 0x00 "QCSP5_MR1,QMan Software Portal 5, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x50000)++0x7 line.quad 0x00 "QCSP5_MR2,QMan Software Portal 5, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x50000)++0x7 line.quad 0x00 "QCSP5_MR3,QMan Software Portal 5, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x50000)++0x7 line.quad 0x00 "QCSP5_MR4,QMan Software Portal 5, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x50000)++0x7 line.quad 0x00 "QCSP5_MR5,QMan Software Portal 5, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x50000)++0x7 line.quad 0x00 "QCSP5_MR6,QMan Software Portal 5, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x50000)++0x7 line.quad 0x00 "QCSP5_MR7,QMan Software Portal 5, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x50000))&0x2000000)==0x2000000) rgroup.long (0x50000+0x3000)++0x03 "QMan Software Portal 5, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP5_EQCR_PI_CENA,Software Portal 5 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x50000+0x3000)++0x03 "QMan Software Portal 5, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP5_EQCR_PI_CENA,Software Portal 5 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x50000+0x3040)++0x03 line.long 0x00 "QCSP5_EQCR_CI_CENA,Software Portal 5 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x50000)++0x3 line.long 0x00 "QCSP5_DQRR_PI_CENA,Software Portal 5 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x50000)++0x3 line.long 0x00 "QCSP5_DQRR_CI_CENA,Software Portal 5 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x50000)++0x3 line.long 0x00 "QCSP5_MR_PI_CENA,Software Portal 5 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x50000)++0x3 line.long 0x00 "QCSP5_MR_CI_CENA,Software Portal 5 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x50000)++0x7 line.quad 0x00 "QCSP5_RORI_CENA,Software Portal 5 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x50000)++0x7 line.quad 0x00 "QCSP5_CR,Software Portal 5, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x50000)++0x7 line.quad 0x00 "QCSP5_RR0,Software Portal 5, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x50000)++0x7 line.quad 0x00 "QCSP5_RR1,Software Portal 5, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x50000+0x4000000)++0x07 "QMan Software Portal 5, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP5_EQCR0,QMan Software Portal 5 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x4000040)++0x07 line.quad 0x00 "QCSP5_EQCR1,QMan Software Portal 5 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x4000080)++0x07 line.quad 0x00 "QCSP5_EQCR2,QMan Software Portal 5 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x40000C0)++0x07 line.quad 0x00 "QCSP5_EQCR3,QMan Software Portal 5 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x4000100)++0x07 line.quad 0x00 "QCSP5_EQCR4,QMan Software Portal 5 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x50000+0x4000140)++0x07 line.quad 0x00 "QCSP5_EQCR5,QMan Software Portal 5 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x50000+0x4000180)++0x07 line.quad 0x00 "QCSP5_EQCR6,QMan Software Portal 5 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x50000+0x40001C0)++0x07 line.quad 0x00 "QCSP5_EQCR7,QMan Software Portal 5 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x50000+0x4001000)++0x07 "QMan Software Portal 5, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP5_DQRR0,QMan Software Portal 5, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001040)++0x07 line.quad 0x00 "QCSP5_DQRR1,QMan Software Portal 5, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001080)++0x07 line.quad 0x00 "QCSP5_DQRR2,QMan Software Portal 5, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40010C0)++0x07 line.quad 0x00 "QCSP5_DQRR3,QMan Software Portal 5, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001100)++0x07 line.quad 0x00 "QCSP5_DQRR4,QMan Software Portal 5, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001140)++0x07 line.quad 0x00 "QCSP5_DQRR5,QMan Software Portal 5, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x50000+0x4001180)++0x07 line.quad 0x00 "QCSP5_DQRR6,QMan Software Portal 5, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40011C0)++0x07 line.quad 0x00 "QCSP5_DQRR7,QMan Software Portal 5, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001200)++0x07 line.quad 0x00 "QCSP5_DQRR8,QMan Software Portal 5, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001240)++0x07 line.quad 0x00 "QCSP5_DQRR9,QMan Software Portal 5, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001280)++0x07 line.quad 0x00 "QCSP5_DQRR10,QMan Software Portal 5, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40012C0)++0x07 line.quad 0x00 "QCSP5_DQRR11,QMan Software Portal 5, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001300)++0x07 line.quad 0x00 "QCSP5_DQRR12,QMan Software Portal 5, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001340)++0x07 line.quad 0x00 "QCSP5_DQRR13,QMan Software Portal 5, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4001380)++0x07 line.quad 0x00 "QCSP5_DQRR14,QMan Software Portal 5, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40013C0)++0x07 line.quad 0x00 "QCSP5_DQRR15,QMan Software Portal 5, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002000)++0x07 "QMan Software Portal 5, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP5_MR0,QMan Software Portal 5, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002040)++0x07 line.quad 0x00 "QCSP5_MR1,QMan Software Portal 5, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002080)++0x07 line.quad 0x00 "QCSP5_MR2,QMan Software Portal 5, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40020C0)++0x07 line.quad 0x00 "QCSP5_MR3,QMan Software Portal 5, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002100)++0x07 line.quad 0x00 "QCSP5_MR4,QMan Software Portal 5, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002140)++0x07 line.quad 0x00 "QCSP5_MR5,QMan Software Portal 5, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x4002180)++0x07 line.quad 0x00 "QCSP5_MR6,QMan Software Portal 5, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x50000+0x40021C0)++0x07 line.quad 0x00 "QCSP5_MR7,QMan Software Portal 5, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x50000))&0x2000000)==0x2000000) rgroup.long (0x50000+0x4003000)++0x3 "QMan Software Portal 5, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_EQCR_PI_CINH,Software Portal 5, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x50000+0x4003000)++0x3 "QMan Software Portal 5, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_EQCR_PI_CINH,Software Portal 5, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x50000+0x4003040)++0x3 line.long 0x00 "QCSP5_EQCR_CI_CINH,Software Portal 5, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x50000+0x4003080)++0x3 line.long 0x00 "QCSP5_EQCR_ITR,Software Portal 5, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x50000+0x4003100)++0x3 "QMan Software Portal 5, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_DQRR_PI_CINH,Software Portal 5, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x50000))&0x20000)==0x20000) rgroup.long (0x50000+0x4003140)++0x3 line.long 0x00 "QCSP5_DQRR_CI_CINH,Software Portal 5, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x50000+0x4003140)++0x3 line.long 0x00 "QCSP5_DQRR_CI_CINH,Software Portal 5, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x50000+0x4003180)++0x3 line.long 0x00 "QCSP5_DQRR_ITR,Software Portal 5, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x50000+0x40031C0)++0x3 line.long 0x00 "QCSP5_DQRR_DCAP,Software Portal 5, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x50000+0x4003200)++0x3 line.long 0x00 "QCSP5_DQRR_SDQCR,Software Portal 5, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x50000+0x4003240)++0x3 line.long 0x00 "QCSP5_DQRR_VDQCR,Software Portal 5, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x50000+0x4003280)++0x3 line.long 0x00 "QCSP5_DQRR_PDQCR,Software Portal 5, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x50000+0x4003300)++0x3 "QMan Software Portal 5, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_MR_PI_CINH,Software Portal 5, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x50000+0x4003340)++0x3 line.long 0x00 "QCSP5_MR_CI_CINH,Software Portal 5, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x50000+0x4003380)++0x3 line.long 0x00 "QCSP5_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x50000+0x4003500)++0x3 "QMan Software Portal 5, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_CFG,Software Portal 5, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x50000+0x4003600)++0x3 "QMan Software Portal 5, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP5_ISR,Software Portal 5, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x50000+0x4003640)++0x3 line.long 0x00 "QCSP5_IER,Software Portal 5, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x50000+0x4003680)++0x3 line.long 0x00 "QCSP5_ISDR,Software Portal 5, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x50000+0x40036C0)++0x3 line.long 0x00 "QCSP5_IIR,Software Portal 5, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x50000+0x4003740)++0x3 line.long 0x00 "QCSP5_ITPR,Software Portal 5 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x50000+0x4003800)++0x07 line.quad 0x00 "QCSP5_CR,Software Portal 5, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x50000+0x4003900)++0x07 line.quad 0x00 "QCSP5_RR0,Software Portal 5, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x50000+0x4003940)++0x07 line.quad 0x00 "QCSP5_RR1,Software Portal 5, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 6" group.quad 0x60000++0x07 "QMan Software Portal 6, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP6_EQCR0,QMan Software Portal 6 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x40)++0x7 line.quad 0x00 "QCSP6_EQCR1,QMan Software Portal 6 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x80)++0x7 line.quad 0x00 "QCSP6_EQCR2,QMan Software Portal 6 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x60000)++0x7 line.quad 0x00 "QCSP6_EQCR3,QMan Software Portal 6 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x60000)++0x7 line.quad 0x00 "QCSP6_EQCR4,QMan Software Portal 6 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x60000)++0x7 line.quad 0x00 "QCSP6_EQCR5,QMan Software Portal 6 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x60000)++0x7 line.quad 0x00 "QCSP6_EQCR6,QMan Software Portal 6 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x60000)++0x7 line.quad 0x00 "QCSP6_EQCR7,QMan Software Portal 6 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x60000)++0x7 "QMan Software Portal 6, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP6_DQRR0,QMan Software Portal 6, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR1,QMan Software Portal 6, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR2,QMan Software Portal 6, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR3,QMan Software Portal 6, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR4,QMan Software Portal 6, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR5,QMan Software Portal 6, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR6,QMan Software Portal 6, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR7,QMan Software Portal 6, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR8,QMan Software Portal 6, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR9,QMan Software Portal 6, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR10,QMan Software Portal 6, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR11,QMan Software Portal 6, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR12,QMan Software Portal 6, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR13,QMan Software Portal 6, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR14,QMan Software Portal 6, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x60000)++0x7 line.quad 0x00 "QCSP6_DQRR15,QMan Software Portal 6, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x60000)++0x7 "QMan Software Portal 6, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP6_MR0,QMan Software Portal 6, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x60000)++0x7 line.quad 0x00 "QCSP6_MR1,QMan Software Portal 6, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x60000)++0x7 line.quad 0x00 "QCSP6_MR2,QMan Software Portal 6, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x60000)++0x7 line.quad 0x00 "QCSP6_MR3,QMan Software Portal 6, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x60000)++0x7 line.quad 0x00 "QCSP6_MR4,QMan Software Portal 6, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x60000)++0x7 line.quad 0x00 "QCSP6_MR5,QMan Software Portal 6, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x60000)++0x7 line.quad 0x00 "QCSP6_MR6,QMan Software Portal 6, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x60000)++0x7 line.quad 0x00 "QCSP6_MR7,QMan Software Portal 6, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x60000))&0x2000000)==0x2000000) rgroup.long (0x60000+0x3000)++0x03 "QMan Software Portal 6, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP6_EQCR_PI_CENA,Software Portal 6 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x60000+0x3000)++0x03 "QMan Software Portal 6, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP6_EQCR_PI_CENA,Software Portal 6 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x60000+0x3040)++0x03 line.long 0x00 "QCSP6_EQCR_CI_CENA,Software Portal 6 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x60000)++0x3 line.long 0x00 "QCSP6_DQRR_PI_CENA,Software Portal 6 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x60000)++0x3 line.long 0x00 "QCSP6_DQRR_CI_CENA,Software Portal 6 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x60000)++0x3 line.long 0x00 "QCSP6_MR_PI_CENA,Software Portal 6 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x60000)++0x3 line.long 0x00 "QCSP6_MR_CI_CENA,Software Portal 6 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x60000)++0x7 line.quad 0x00 "QCSP6_RORI_CENA,Software Portal 6 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x60000)++0x7 line.quad 0x00 "QCSP6_CR,Software Portal 6, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x60000)++0x7 line.quad 0x00 "QCSP6_RR0,Software Portal 6, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x60000)++0x7 line.quad 0x00 "QCSP6_RR1,Software Portal 6, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x60000+0x4000000)++0x07 "QMan Software Portal 6, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP6_EQCR0,QMan Software Portal 6 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x4000040)++0x07 line.quad 0x00 "QCSP6_EQCR1,QMan Software Portal 6 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x4000080)++0x07 line.quad 0x00 "QCSP6_EQCR2,QMan Software Portal 6 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x40000C0)++0x07 line.quad 0x00 "QCSP6_EQCR3,QMan Software Portal 6 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x4000100)++0x07 line.quad 0x00 "QCSP6_EQCR4,QMan Software Portal 6 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x60000+0x4000140)++0x07 line.quad 0x00 "QCSP6_EQCR5,QMan Software Portal 6 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x60000+0x4000180)++0x07 line.quad 0x00 "QCSP6_EQCR6,QMan Software Portal 6 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x60000+0x40001C0)++0x07 line.quad 0x00 "QCSP6_EQCR7,QMan Software Portal 6 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x60000+0x4001000)++0x07 "QMan Software Portal 6, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP6_DQRR0,QMan Software Portal 6, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001040)++0x07 line.quad 0x00 "QCSP6_DQRR1,QMan Software Portal 6, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001080)++0x07 line.quad 0x00 "QCSP6_DQRR2,QMan Software Portal 6, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40010C0)++0x07 line.quad 0x00 "QCSP6_DQRR3,QMan Software Portal 6, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001100)++0x07 line.quad 0x00 "QCSP6_DQRR4,QMan Software Portal 6, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001140)++0x07 line.quad 0x00 "QCSP6_DQRR5,QMan Software Portal 6, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x60000+0x4001180)++0x07 line.quad 0x00 "QCSP6_DQRR6,QMan Software Portal 6, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40011C0)++0x07 line.quad 0x00 "QCSP6_DQRR7,QMan Software Portal 6, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001200)++0x07 line.quad 0x00 "QCSP6_DQRR8,QMan Software Portal 6, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001240)++0x07 line.quad 0x00 "QCSP6_DQRR9,QMan Software Portal 6, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001280)++0x07 line.quad 0x00 "QCSP6_DQRR10,QMan Software Portal 6, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40012C0)++0x07 line.quad 0x00 "QCSP6_DQRR11,QMan Software Portal 6, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001300)++0x07 line.quad 0x00 "QCSP6_DQRR12,QMan Software Portal 6, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001340)++0x07 line.quad 0x00 "QCSP6_DQRR13,QMan Software Portal 6, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4001380)++0x07 line.quad 0x00 "QCSP6_DQRR14,QMan Software Portal 6, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40013C0)++0x07 line.quad 0x00 "QCSP6_DQRR15,QMan Software Portal 6, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002000)++0x07 "QMan Software Portal 6, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP6_MR0,QMan Software Portal 6, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002040)++0x07 line.quad 0x00 "QCSP6_MR1,QMan Software Portal 6, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002080)++0x07 line.quad 0x00 "QCSP6_MR2,QMan Software Portal 6, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40020C0)++0x07 line.quad 0x00 "QCSP6_MR3,QMan Software Portal 6, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002100)++0x07 line.quad 0x00 "QCSP6_MR4,QMan Software Portal 6, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002140)++0x07 line.quad 0x00 "QCSP6_MR5,QMan Software Portal 6, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x4002180)++0x07 line.quad 0x00 "QCSP6_MR6,QMan Software Portal 6, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x60000+0x40021C0)++0x07 line.quad 0x00 "QCSP6_MR7,QMan Software Portal 6, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x60000))&0x2000000)==0x2000000) rgroup.long (0x60000+0x4003000)++0x3 "QMan Software Portal 6, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_EQCR_PI_CINH,Software Portal 6, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x60000+0x4003000)++0x3 "QMan Software Portal 6, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_EQCR_PI_CINH,Software Portal 6, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x60000+0x4003040)++0x3 line.long 0x00 "QCSP6_EQCR_CI_CINH,Software Portal 6, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x60000+0x4003080)++0x3 line.long 0x00 "QCSP6_EQCR_ITR,Software Portal 6, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x60000+0x4003100)++0x3 "QMan Software Portal 6, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_DQRR_PI_CINH,Software Portal 6, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x60000))&0x20000)==0x20000) rgroup.long (0x60000+0x4003140)++0x3 line.long 0x00 "QCSP6_DQRR_CI_CINH,Software Portal 6, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x60000+0x4003140)++0x3 line.long 0x00 "QCSP6_DQRR_CI_CINH,Software Portal 6, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x60000+0x4003180)++0x3 line.long 0x00 "QCSP6_DQRR_ITR,Software Portal 6, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x60000+0x40031C0)++0x3 line.long 0x00 "QCSP6_DQRR_DCAP,Software Portal 6, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x60000+0x4003200)++0x3 line.long 0x00 "QCSP6_DQRR_SDQCR,Software Portal 6, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x60000+0x4003240)++0x3 line.long 0x00 "QCSP6_DQRR_VDQCR,Software Portal 6, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x60000+0x4003280)++0x3 line.long 0x00 "QCSP6_DQRR_PDQCR,Software Portal 6, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x60000+0x4003300)++0x3 "QMan Software Portal 6, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_MR_PI_CINH,Software Portal 6, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x60000+0x4003340)++0x3 line.long 0x00 "QCSP6_MR_CI_CINH,Software Portal 6, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x60000+0x4003380)++0x3 line.long 0x00 "QCSP6_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x60000+0x4003500)++0x3 "QMan Software Portal 6, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_CFG,Software Portal 6, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x60000+0x4003600)++0x3 "QMan Software Portal 6, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP6_ISR,Software Portal 6, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x60000+0x4003640)++0x3 line.long 0x00 "QCSP6_IER,Software Portal 6, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x60000+0x4003680)++0x3 line.long 0x00 "QCSP6_ISDR,Software Portal 6, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x60000+0x40036C0)++0x3 line.long 0x00 "QCSP6_IIR,Software Portal 6, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x60000+0x4003740)++0x3 line.long 0x00 "QCSP6_ITPR,Software Portal 6 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x60000+0x4003800)++0x07 line.quad 0x00 "QCSP6_CR,Software Portal 6, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x60000+0x4003900)++0x07 line.quad 0x00 "QCSP6_RR0,Software Portal 6, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x60000+0x4003940)++0x07 line.quad 0x00 "QCSP6_RR1,Software Portal 6, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 7" group.quad 0x70000++0x07 "QMan Software Portal 7, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP7_EQCR0,QMan Software Portal 7 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x40)++0x7 line.quad 0x00 "QCSP7_EQCR1,QMan Software Portal 7 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x80)++0x7 line.quad 0x00 "QCSP7_EQCR2,QMan Software Portal 7 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x70000)++0x7 line.quad 0x00 "QCSP7_EQCR3,QMan Software Portal 7 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x70000)++0x7 line.quad 0x00 "QCSP7_EQCR4,QMan Software Portal 7 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x70000)++0x7 line.quad 0x00 "QCSP7_EQCR5,QMan Software Portal 7 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x70000)++0x7 line.quad 0x00 "QCSP7_EQCR6,QMan Software Portal 7 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x70000)++0x7 line.quad 0x00 "QCSP7_EQCR7,QMan Software Portal 7 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x70000)++0x7 "QMan Software Portal 7, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP7_DQRR0,QMan Software Portal 7, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR1,QMan Software Portal 7, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR2,QMan Software Portal 7, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR3,QMan Software Portal 7, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR4,QMan Software Portal 7, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR5,QMan Software Portal 7, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR6,QMan Software Portal 7, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR7,QMan Software Portal 7, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR8,QMan Software Portal 7, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR9,QMan Software Portal 7, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR10,QMan Software Portal 7, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR11,QMan Software Portal 7, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR12,QMan Software Portal 7, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR13,QMan Software Portal 7, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR14,QMan Software Portal 7, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x70000)++0x7 line.quad 0x00 "QCSP7_DQRR15,QMan Software Portal 7, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x70000)++0x7 "QMan Software Portal 7, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP7_MR0,QMan Software Portal 7, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x70000)++0x7 line.quad 0x00 "QCSP7_MR1,QMan Software Portal 7, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x70000)++0x7 line.quad 0x00 "QCSP7_MR2,QMan Software Portal 7, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x70000)++0x7 line.quad 0x00 "QCSP7_MR3,QMan Software Portal 7, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x70000)++0x7 line.quad 0x00 "QCSP7_MR4,QMan Software Portal 7, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x70000)++0x7 line.quad 0x00 "QCSP7_MR5,QMan Software Portal 7, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x70000)++0x7 line.quad 0x00 "QCSP7_MR6,QMan Software Portal 7, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x70000)++0x7 line.quad 0x00 "QCSP7_MR7,QMan Software Portal 7, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x70000))&0x2000000)==0x2000000) rgroup.long (0x70000+0x3000)++0x03 "QMan Software Portal 7, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP7_EQCR_PI_CENA,Software Portal 7 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x70000+0x3000)++0x03 "QMan Software Portal 7, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP7_EQCR_PI_CENA,Software Portal 7 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x70000+0x3040)++0x03 line.long 0x00 "QCSP7_EQCR_CI_CENA,Software Portal 7 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x70000)++0x3 line.long 0x00 "QCSP7_DQRR_PI_CENA,Software Portal 7 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x70000)++0x3 line.long 0x00 "QCSP7_DQRR_CI_CENA,Software Portal 7 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x70000)++0x3 line.long 0x00 "QCSP7_MR_PI_CENA,Software Portal 7 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x70000)++0x3 line.long 0x00 "QCSP7_MR_CI_CENA,Software Portal 7 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x70000)++0x7 line.quad 0x00 "QCSP7_RORI_CENA,Software Portal 7 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x70000)++0x7 line.quad 0x00 "QCSP7_CR,Software Portal 7, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x70000)++0x7 line.quad 0x00 "QCSP7_RR0,Software Portal 7, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x70000)++0x7 line.quad 0x00 "QCSP7_RR1,Software Portal 7, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x70000+0x4000000)++0x07 "QMan Software Portal 7, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP7_EQCR0,QMan Software Portal 7 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x4000040)++0x07 line.quad 0x00 "QCSP7_EQCR1,QMan Software Portal 7 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x4000080)++0x07 line.quad 0x00 "QCSP7_EQCR2,QMan Software Portal 7 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x40000C0)++0x07 line.quad 0x00 "QCSP7_EQCR3,QMan Software Portal 7 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x4000100)++0x07 line.quad 0x00 "QCSP7_EQCR4,QMan Software Portal 7 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x70000+0x4000140)++0x07 line.quad 0x00 "QCSP7_EQCR5,QMan Software Portal 7 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x70000+0x4000180)++0x07 line.quad 0x00 "QCSP7_EQCR6,QMan Software Portal 7 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x70000+0x40001C0)++0x07 line.quad 0x00 "QCSP7_EQCR7,QMan Software Portal 7 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x70000+0x4001000)++0x07 "QMan Software Portal 7, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP7_DQRR0,QMan Software Portal 7, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001040)++0x07 line.quad 0x00 "QCSP7_DQRR1,QMan Software Portal 7, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001080)++0x07 line.quad 0x00 "QCSP7_DQRR2,QMan Software Portal 7, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40010C0)++0x07 line.quad 0x00 "QCSP7_DQRR3,QMan Software Portal 7, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001100)++0x07 line.quad 0x00 "QCSP7_DQRR4,QMan Software Portal 7, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001140)++0x07 line.quad 0x00 "QCSP7_DQRR5,QMan Software Portal 7, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x70000+0x4001180)++0x07 line.quad 0x00 "QCSP7_DQRR6,QMan Software Portal 7, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40011C0)++0x07 line.quad 0x00 "QCSP7_DQRR7,QMan Software Portal 7, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001200)++0x07 line.quad 0x00 "QCSP7_DQRR8,QMan Software Portal 7, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001240)++0x07 line.quad 0x00 "QCSP7_DQRR9,QMan Software Portal 7, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001280)++0x07 line.quad 0x00 "QCSP7_DQRR10,QMan Software Portal 7, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40012C0)++0x07 line.quad 0x00 "QCSP7_DQRR11,QMan Software Portal 7, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001300)++0x07 line.quad 0x00 "QCSP7_DQRR12,QMan Software Portal 7, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001340)++0x07 line.quad 0x00 "QCSP7_DQRR13,QMan Software Portal 7, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4001380)++0x07 line.quad 0x00 "QCSP7_DQRR14,QMan Software Portal 7, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40013C0)++0x07 line.quad 0x00 "QCSP7_DQRR15,QMan Software Portal 7, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002000)++0x07 "QMan Software Portal 7, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP7_MR0,QMan Software Portal 7, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002040)++0x07 line.quad 0x00 "QCSP7_MR1,QMan Software Portal 7, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002080)++0x07 line.quad 0x00 "QCSP7_MR2,QMan Software Portal 7, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40020C0)++0x07 line.quad 0x00 "QCSP7_MR3,QMan Software Portal 7, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002100)++0x07 line.quad 0x00 "QCSP7_MR4,QMan Software Portal 7, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002140)++0x07 line.quad 0x00 "QCSP7_MR5,QMan Software Portal 7, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x4002180)++0x07 line.quad 0x00 "QCSP7_MR6,QMan Software Portal 7, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x70000+0x40021C0)++0x07 line.quad 0x00 "QCSP7_MR7,QMan Software Portal 7, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x70000))&0x2000000)==0x2000000) rgroup.long (0x70000+0x4003000)++0x3 "QMan Software Portal 7, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_EQCR_PI_CINH,Software Portal 7, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x70000+0x4003000)++0x3 "QMan Software Portal 7, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_EQCR_PI_CINH,Software Portal 7, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x70000+0x4003040)++0x3 line.long 0x00 "QCSP7_EQCR_CI_CINH,Software Portal 7, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x70000+0x4003080)++0x3 line.long 0x00 "QCSP7_EQCR_ITR,Software Portal 7, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x70000+0x4003100)++0x3 "QMan Software Portal 7, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_DQRR_PI_CINH,Software Portal 7, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x70000))&0x20000)==0x20000) rgroup.long (0x70000+0x4003140)++0x3 line.long 0x00 "QCSP7_DQRR_CI_CINH,Software Portal 7, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x70000+0x4003140)++0x3 line.long 0x00 "QCSP7_DQRR_CI_CINH,Software Portal 7, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x70000+0x4003180)++0x3 line.long 0x00 "QCSP7_DQRR_ITR,Software Portal 7, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x70000+0x40031C0)++0x3 line.long 0x00 "QCSP7_DQRR_DCAP,Software Portal 7, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x70000+0x4003200)++0x3 line.long 0x00 "QCSP7_DQRR_SDQCR,Software Portal 7, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x70000+0x4003240)++0x3 line.long 0x00 "QCSP7_DQRR_VDQCR,Software Portal 7, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x70000+0x4003280)++0x3 line.long 0x00 "QCSP7_DQRR_PDQCR,Software Portal 7, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x70000+0x4003300)++0x3 "QMan Software Portal 7, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_MR_PI_CINH,Software Portal 7, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x70000+0x4003340)++0x3 line.long 0x00 "QCSP7_MR_CI_CINH,Software Portal 7, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x70000+0x4003380)++0x3 line.long 0x00 "QCSP7_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x70000+0x4003500)++0x3 "QMan Software Portal 7, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_CFG,Software Portal 7, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x70000+0x4003600)++0x3 "QMan Software Portal 7, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP7_ISR,Software Portal 7, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x70000+0x4003640)++0x3 line.long 0x00 "QCSP7_IER,Software Portal 7, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x70000+0x4003680)++0x3 line.long 0x00 "QCSP7_ISDR,Software Portal 7, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x70000+0x40036C0)++0x3 line.long 0x00 "QCSP7_IIR,Software Portal 7, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x70000+0x4003740)++0x3 line.long 0x00 "QCSP7_ITPR,Software Portal 7 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x70000+0x4003800)++0x07 line.quad 0x00 "QCSP7_CR,Software Portal 7, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x70000+0x4003900)++0x07 line.quad 0x00 "QCSP7_RR0,Software Portal 7, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x70000+0x4003940)++0x07 line.quad 0x00 "QCSP7_RR1,Software Portal 7, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 8" group.quad 0x80000++0x07 "QMan Software Portal 8, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP8_EQCR0,QMan Software Portal 8 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x40)++0x7 line.quad 0x00 "QCSP8_EQCR1,QMan Software Portal 8 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x80)++0x7 line.quad 0x00 "QCSP8_EQCR2,QMan Software Portal 8 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x80000)++0x7 line.quad 0x00 "QCSP8_EQCR3,QMan Software Portal 8 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x80000)++0x7 line.quad 0x00 "QCSP8_EQCR4,QMan Software Portal 8 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x80000)++0x7 line.quad 0x00 "QCSP8_EQCR5,QMan Software Portal 8 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x80000)++0x7 line.quad 0x00 "QCSP8_EQCR6,QMan Software Portal 8 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x80000)++0x7 line.quad 0x00 "QCSP8_EQCR7,QMan Software Portal 8 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x80000)++0x7 "QMan Software Portal 8, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP8_DQRR0,QMan Software Portal 8, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR1,QMan Software Portal 8, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR2,QMan Software Portal 8, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR3,QMan Software Portal 8, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR4,QMan Software Portal 8, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR5,QMan Software Portal 8, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR6,QMan Software Portal 8, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR7,QMan Software Portal 8, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR8,QMan Software Portal 8, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR9,QMan Software Portal 8, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR10,QMan Software Portal 8, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR11,QMan Software Portal 8, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR12,QMan Software Portal 8, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR13,QMan Software Portal 8, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR14,QMan Software Portal 8, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x80000)++0x7 line.quad 0x00 "QCSP8_DQRR15,QMan Software Portal 8, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x80000)++0x7 "QMan Software Portal 8, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP8_MR0,QMan Software Portal 8, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x80000)++0x7 line.quad 0x00 "QCSP8_MR1,QMan Software Portal 8, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x80000)++0x7 line.quad 0x00 "QCSP8_MR2,QMan Software Portal 8, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x80000)++0x7 line.quad 0x00 "QCSP8_MR3,QMan Software Portal 8, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x80000)++0x7 line.quad 0x00 "QCSP8_MR4,QMan Software Portal 8, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x80000)++0x7 line.quad 0x00 "QCSP8_MR5,QMan Software Portal 8, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x80000)++0x7 line.quad 0x00 "QCSP8_MR6,QMan Software Portal 8, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x80000)++0x7 line.quad 0x00 "QCSP8_MR7,QMan Software Portal 8, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x80000))&0x2000000)==0x2000000) rgroup.long (0x80000+0x3000)++0x03 "QMan Software Portal 8, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP8_EQCR_PI_CENA,Software Portal 8 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x80000+0x3000)++0x03 "QMan Software Portal 8, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP8_EQCR_PI_CENA,Software Portal 8 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x80000+0x3040)++0x03 line.long 0x00 "QCSP8_EQCR_CI_CENA,Software Portal 8 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x80000)++0x3 line.long 0x00 "QCSP8_DQRR_PI_CENA,Software Portal 8 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x80000)++0x3 line.long 0x00 "QCSP8_DQRR_CI_CENA,Software Portal 8 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x80000)++0x3 line.long 0x00 "QCSP8_MR_PI_CENA,Software Portal 8 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x80000)++0x3 line.long 0x00 "QCSP8_MR_CI_CENA,Software Portal 8 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x80000)++0x7 line.quad 0x00 "QCSP8_RORI_CENA,Software Portal 8 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x80000)++0x7 line.quad 0x00 "QCSP8_CR,Software Portal 8, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x80000)++0x7 line.quad 0x00 "QCSP8_RR0,Software Portal 8, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x80000)++0x7 line.quad 0x00 "QCSP8_RR1,Software Portal 8, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x80000+0x4000000)++0x07 "QMan Software Portal 8, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP8_EQCR0,QMan Software Portal 8 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x4000040)++0x07 line.quad 0x00 "QCSP8_EQCR1,QMan Software Portal 8 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x4000080)++0x07 line.quad 0x00 "QCSP8_EQCR2,QMan Software Portal 8 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x40000C0)++0x07 line.quad 0x00 "QCSP8_EQCR3,QMan Software Portal 8 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x4000100)++0x07 line.quad 0x00 "QCSP8_EQCR4,QMan Software Portal 8 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x80000+0x4000140)++0x07 line.quad 0x00 "QCSP8_EQCR5,QMan Software Portal 8 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x80000+0x4000180)++0x07 line.quad 0x00 "QCSP8_EQCR6,QMan Software Portal 8 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x80000+0x40001C0)++0x07 line.quad 0x00 "QCSP8_EQCR7,QMan Software Portal 8 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x80000+0x4001000)++0x07 "QMan Software Portal 8, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP8_DQRR0,QMan Software Portal 8, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001040)++0x07 line.quad 0x00 "QCSP8_DQRR1,QMan Software Portal 8, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001080)++0x07 line.quad 0x00 "QCSP8_DQRR2,QMan Software Portal 8, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40010C0)++0x07 line.quad 0x00 "QCSP8_DQRR3,QMan Software Portal 8, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001100)++0x07 line.quad 0x00 "QCSP8_DQRR4,QMan Software Portal 8, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001140)++0x07 line.quad 0x00 "QCSP8_DQRR5,QMan Software Portal 8, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x80000+0x4001180)++0x07 line.quad 0x00 "QCSP8_DQRR6,QMan Software Portal 8, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40011C0)++0x07 line.quad 0x00 "QCSP8_DQRR7,QMan Software Portal 8, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001200)++0x07 line.quad 0x00 "QCSP8_DQRR8,QMan Software Portal 8, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001240)++0x07 line.quad 0x00 "QCSP8_DQRR9,QMan Software Portal 8, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001280)++0x07 line.quad 0x00 "QCSP8_DQRR10,QMan Software Portal 8, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40012C0)++0x07 line.quad 0x00 "QCSP8_DQRR11,QMan Software Portal 8, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001300)++0x07 line.quad 0x00 "QCSP8_DQRR12,QMan Software Portal 8, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001340)++0x07 line.quad 0x00 "QCSP8_DQRR13,QMan Software Portal 8, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4001380)++0x07 line.quad 0x00 "QCSP8_DQRR14,QMan Software Portal 8, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40013C0)++0x07 line.quad 0x00 "QCSP8_DQRR15,QMan Software Portal 8, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002000)++0x07 "QMan Software Portal 8, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP8_MR0,QMan Software Portal 8, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002040)++0x07 line.quad 0x00 "QCSP8_MR1,QMan Software Portal 8, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002080)++0x07 line.quad 0x00 "QCSP8_MR2,QMan Software Portal 8, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40020C0)++0x07 line.quad 0x00 "QCSP8_MR3,QMan Software Portal 8, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002100)++0x07 line.quad 0x00 "QCSP8_MR4,QMan Software Portal 8, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002140)++0x07 line.quad 0x00 "QCSP8_MR5,QMan Software Portal 8, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x4002180)++0x07 line.quad 0x00 "QCSP8_MR6,QMan Software Portal 8, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x80000+0x40021C0)++0x07 line.quad 0x00 "QCSP8_MR7,QMan Software Portal 8, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x80000))&0x2000000)==0x2000000) rgroup.long (0x80000+0x4003000)++0x3 "QMan Software Portal 8, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_EQCR_PI_CINH,Software Portal 8, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x80000+0x4003000)++0x3 "QMan Software Portal 8, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_EQCR_PI_CINH,Software Portal 8, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x80000+0x4003040)++0x3 line.long 0x00 "QCSP8_EQCR_CI_CINH,Software Portal 8, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x80000+0x4003080)++0x3 line.long 0x00 "QCSP8_EQCR_ITR,Software Portal 8, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x80000+0x4003100)++0x3 "QMan Software Portal 8, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_DQRR_PI_CINH,Software Portal 8, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x80000))&0x20000)==0x20000) rgroup.long (0x80000+0x4003140)++0x3 line.long 0x00 "QCSP8_DQRR_CI_CINH,Software Portal 8, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x80000+0x4003140)++0x3 line.long 0x00 "QCSP8_DQRR_CI_CINH,Software Portal 8, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x80000+0x4003180)++0x3 line.long 0x00 "QCSP8_DQRR_ITR,Software Portal 8, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x80000+0x40031C0)++0x3 line.long 0x00 "QCSP8_DQRR_DCAP,Software Portal 8, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x80000+0x4003200)++0x3 line.long 0x00 "QCSP8_DQRR_SDQCR,Software Portal 8, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x80000+0x4003240)++0x3 line.long 0x00 "QCSP8_DQRR_VDQCR,Software Portal 8, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x80000+0x4003280)++0x3 line.long 0x00 "QCSP8_DQRR_PDQCR,Software Portal 8, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x80000+0x4003300)++0x3 "QMan Software Portal 8, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_MR_PI_CINH,Software Portal 8, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x80000+0x4003340)++0x3 line.long 0x00 "QCSP8_MR_CI_CINH,Software Portal 8, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x80000+0x4003380)++0x3 line.long 0x00 "QCSP8_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x80000+0x4003500)++0x3 "QMan Software Portal 8, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_CFG,Software Portal 8, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x80000+0x4003600)++0x3 "QMan Software Portal 8, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP8_ISR,Software Portal 8, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x80000+0x4003640)++0x3 line.long 0x00 "QCSP8_IER,Software Portal 8, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x80000+0x4003680)++0x3 line.long 0x00 "QCSP8_ISDR,Software Portal 8, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x80000+0x40036C0)++0x3 line.long 0x00 "QCSP8_IIR,Software Portal 8, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x80000+0x4003740)++0x3 line.long 0x00 "QCSP8_ITPR,Software Portal 8 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x80000+0x4003800)++0x07 line.quad 0x00 "QCSP8_CR,Software Portal 8, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x80000+0x4003900)++0x07 line.quad 0x00 "QCSP8_RR0,Software Portal 8, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x80000+0x4003940)++0x07 line.quad 0x00 "QCSP8_RR1,Software Portal 8, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree "Software Portal 9" group.quad 0x90000++0x07 "QMan Software Portal 9, Enqueue Command Ring (EQCR), Cache-Enabled Area" line.quad 0x00 "QCSP9_EQCR0,QMan Software Portal 9 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x40)++0x7 line.quad 0x00 "QCSP9_EQCR1,QMan Software Portal 9 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x80)++0x7 line.quad 0x00 "QCSP9_EQCR2,QMan Software Portal 9 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0xC0+0x90000)++0x7 line.quad 0x00 "QCSP9_EQCR3,QMan Software Portal 9 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x100+0x90000)++0x7 line.quad 0x00 "QCSP9_EQCR4,QMan Software Portal 9 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x140+0x90000)++0x7 line.quad 0x00 "QCSP9_EQCR5,QMan Software Portal 9 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x180+0x90000)++0x7 line.quad 0x00 "QCSP9_EQCR6,QMan Software Portal 9 EQCR Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1C0+0x90000)++0x7 line.quad 0x00 "QCSP9_EQCR7,QMan Software Portal 9 EQCR Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x1000+0x90000)++0x7 "QMan Software Portal 9, Dequeue Response Ring (DQRR), Cache-Enabled Area" line.quad 0x00 "QCSP9_DQRR0,QMan Software Portal 9, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1040+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR1,QMan Software Portal 9, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1080+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR2,QMan Software Portal 9, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x10C0+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR3,QMan Software Portal 9, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1100+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR4,QMan Software Portal 9, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1140+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR5,QMan Software Portal 9, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1180+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR6,QMan Software Portal 9, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x11C0+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR7,QMan Software Portal 9, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1200+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR8,QMan Software Portal 9, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1240+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR9,QMan Software Portal 9, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1280+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR10,QMan Software Portal 9, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x12C0+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR11,QMan Software Portal 9, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1300+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR12,QMan Software Portal 9, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1340+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR13,QMan Software Portal 9, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x1380+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR14,QMan Software Portal 9, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x13C0+0x90000)++0x7 line.quad 0x00 "QCSP9_DQRR15,QMan Software Portal 9, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2000+0x90000)++0x7 "QMan Software Portal 9, Message Ring (MR), Cache-Enabled Area" line.quad 0x00 "QCSP9_MR0,QMan Software Portal 9, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2040+0x90000)++0x7 line.quad 0x00 "QCSP9_MR1,QMan Software Portal 9, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2080+0x90000)++0x7 line.quad 0x00 "QCSP9_MR2,QMan Software Portal 9, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x20C0+0x90000)++0x7 line.quad 0x00 "QCSP9_MR3,QMan Software Portal 9, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2100+0x90000)++0x7 line.quad 0x00 "QCSP9_MR4,QMan Software Portal 9, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2140+0x90000)++0x7 line.quad 0x00 "QCSP9_MR5,QMan Software Portal 9, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x2180+0x90000)++0x7 line.quad 0x00 "QCSP9_MR6,QMan Software Portal 9, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x21C0+0x90000)++0x7 line.quad 0x00 "QCSP9_MR7,QMan Software Portal 9, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x90000))&0x2000000)==0x2000000) rgroup.long (0x90000+0x3000)++0x03 "QMan Software Portal 9, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP9_EQCR_PI_CENA,Software Portal 9 Enqueue Command Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x90000+0x3000)++0x03 "QMan Software Portal 9, Command and Response Ring Index Registers Cache-Enabled Area" line.long 0x00 "QCSP9_EQCR_PI_CENA,Software Portal 9 Enqueue Command Ring Producer Index Register Cache-Enabled" rbitfld.long 0x00 3. " VP ,Current valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" endif rgroup.long (0x90000+0x3040)++0x03 line.long 0x00 "QCSP9_EQCR_CI_CENA,Software Portal 9 Enqueue Command Ring Consumer Index Register Cache-Enabled" bitfld.long 0x00 15. " VP ,Current valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked" "0,1" bitfld.long 0x00 3. " VC ,Current valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x90000)++0x3 line.long 0x00 "QCSP9_DQRR_PI_CENA,Software Portal 9 Dequeue Response Ring Producer Index Register Cache-Enabled" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" group.long (0x3140+0x90000)++0x3 line.long 0x00 "QCSP9_DQRR_CI_CENA,Software Portal 9 Dequeue Response Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--3. 1. " CI ,Consumer index" rgroup.long (0x3300+0x90000)++0x3 line.long 0x00 "QCSP9_MR_PI_CENA,Software Portal 9 Message Ring Producer Index Register Cache-Enabled" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x3340+0x90000)++0x3 line.long 0x00 "QCSP9_MR_CI_CENA,Software Portal 9 Message Ring Consumer Index Register Cache-Enabled" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" rgroup.quad (0x3400+0x90000)++0x7 line.quad 0x00 "QCSP9_RORI_CENA,Software Portal 9 Read Only Ring Indices Register Cache-Enabled" hexmask.quad.byte 0x00 60.--63. 1. " EQCR_CI_CENA ,EQCR consumer index, cache-enabled" hexmask.quad.byte 0x00 56.--59. 1. " DQRR_PI_CENA ,DQRR producer index, cache-enabled" hexmask.quad.byte 0x00 52.--55. 1. " MR_PI_CENA ,MR producer index, cache-enabled" newline hexmask.quad.byte 0x00 44.--47. 1. " EQCR_PI_CENA ,EQCR producer index, cache-enabled" hexmask.quad.byte 0x00 40.--43. 1. " DQRR_CI_CENA ,DQRR consumer index, cache-enabled" hexmask.quad.byte 0x00 36.--39. 1. " MR_CI_CENA ,MR consumer index, cache-enabled" group.quad (0x3800+0x90000)++0x7 line.quad 0x00 "QCSP9_CR,Software Portal 9, Management Command Register" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x3900+0x90000)++0x7 line.quad 0x00 "QCSP9_RR0,Software Portal 9, Management Response Register 0" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x3940+0x90000)++0x7 line.quad 0x00 "QCSP9_RR1,Software Portal 9, Management Response Register 1" bitfld.quad 0x00 63. " Verb ,VERB byte" "0,1" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x90000+0x4000000)++0x07 "QMan Software Portal 9, EQCR Index Registers, Cache-Inhibited Area" line.quad 0x00 "QCSP9_EQCR0,QMan Software Portal 9 EQCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x4000040)++0x07 line.quad 0x00 "QCSP9_EQCR1,QMan Software Portal 9 EQCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x4000080)++0x07 line.quad 0x00 "QCSP9_EQCR2,QMan Software Portal 9 EQCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x40000C0)++0x07 line.quad 0x00 "QCSP9_EQCR3,QMan Software Portal 9 EQCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x4000100)++0x07 line.quad 0x00 "QCSP9_EQCR4,QMan Software Portal 9 EQCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x90000+0x4000140)++0x07 line.quad 0x00 "QCSP9_EQCR5,QMan Software Portal 9 EQCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" newline group.quad (0x90000+0x4000180)++0x07 line.quad 0x00 "QCSP9_EQCR6,QMan Software Portal 9 EQCR Entry 6" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" group.quad (0x90000+0x40001C0)++0x07 line.quad 0x00 "QCSP9_EQCR7,QMan Software Portal 9 EQCR Entry 7" hexmask.quad.long 0x00 32.--62. 1. " COMMAND_DATA ,Command data" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" rgroup.quad (0x90000+0x4001000)++0x07 "QMan Software Portal 9, Dequeue Response Ring (DQRR), Cache-Inhibited Area" line.quad 0x00 "QCSP9_DQRR0,QMan Software Portal 9, DQRR, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001040)++0x07 line.quad 0x00 "QCSP9_DQRR1,QMan Software Portal 9, DQRR, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001080)++0x07 line.quad 0x00 "QCSP9_DQRR2,QMan Software Portal 9, DQRR, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40010C0)++0x07 line.quad 0x00 "QCSP9_DQRR3,QMan Software Portal 9, DQRR, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001100)++0x07 line.quad 0x00 "QCSP9_DQRR4,QMan Software Portal 9, DQRR, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001140)++0x07 line.quad 0x00 "QCSP9_DQRR5,QMan Software Portal 9, DQRR, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" newline rgroup.quad (0x90000+0x4001180)++0x07 line.quad 0x00 "QCSP9_DQRR6,QMan Software Portal 9, DQRR, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40011C0)++0x07 line.quad 0x00 "QCSP9_DQRR7,QMan Software Portal 9, DQRR, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001200)++0x07 line.quad 0x00 "QCSP9_DQRR8,QMan Software Portal 9, DQRR, Entry 8" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001240)++0x07 line.quad 0x00 "QCSP9_DQRR9,QMan Software Portal 9, DQRR, Entry 9" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001280)++0x07 line.quad 0x00 "QCSP9_DQRR10,QMan Software Portal 9, DQRR, Entry 10" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40012C0)++0x07 line.quad 0x00 "QCSP9_DQRR11,QMan Software Portal 9, DQRR, Entry 11" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001300)++0x07 line.quad 0x00 "QCSP9_DQRR12,QMan Software Portal 9, DQRR, Entry 12" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001340)++0x07 line.quad 0x00 "QCSP9_DQRR13,QMan Software Portal 9, DQRR, Entry 13" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4001380)++0x07 line.quad 0x00 "QCSP9_DQRR14,QMan Software Portal 9, DQRR, Entry 14" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40013C0)++0x07 line.quad 0x00 "QCSP9_DQRR15,QMan Software Portal 9, DQRR, Entry 15" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002000)++0x07 "QMan Software Portal 9, Message Ring (MR), Cache-Inhibited Area" line.quad 0x00 "QCSP9_MR0,QMan Software Portal 9, Message Ring, Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002040)++0x07 line.quad 0x00 "QCSP9_MR1,QMan Software Portal 9, Message Ring, Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002080)++0x07 line.quad 0x00 "QCSP9_MR2,QMan Software Portal 9, Message Ring, Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40020C0)++0x07 line.quad 0x00 "QCSP9_MR3,QMan Software Portal 9, Message Ring, Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002100)++0x07 line.quad 0x00 "QCSP9_MR4,QMan Software Portal 9, Message Ring, Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002140)++0x07 line.quad 0x00 "QCSP9_MR5,QMan Software Portal 9, Message Ring, Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x4002180)++0x07 line.quad 0x00 "QCSP9_MR6,QMan Software Portal 9, Message Ring, Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x90000+0x40021C0)++0x07 line.quad 0x00 "QCSP9_MR7,QMan Software Portal 9, Message Ring, Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte " "0,1" hexmask.quad.long 0x00 32.--62. 1. " RESPONSE_DATA ,Response data" if (((per.l.be(ad:0x0500000000+0x4003500+0x90000))&0x2000000)==0x2000000) rgroup.long (0x90000+0x4003000)++0x3 "QMan Software Portal 9, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_EQCR_PI_CINH,Software Portal 9, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" else group.long (0x90000+0x4003000)++0x3 "QMan Software Portal 9, EQCR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_EQCR_PI_CINH,Software Portal 9, Enqueue Command Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" endif newline rgroup.long (0x90000+0x4003040)++0x3 line.long 0x00 "QCSP9_EQCR_CI_CINH,Software Portal 9, Enqueue Command Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 15. " VP ,valid bit polarity at producer index " "0,1" bitfld.long 0x00 11. " PB ,PFDR enqueues blocked " "0,1" bitfld.long 0x00 3. " VC ,valid bit polarity at consumer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x90000+0x4003080)++0x3 line.long 0x00 "QCSP9_EQCR_ITR,Software Portal 9, EQCR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " EQCR_IT ,EQCR interrupt threshold" newline rgroup.long (0x90000+0x4003100)++0x3 "QMan Software Portal 9, DQRR Index and Command Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_DQRR_PI_CINH,Software Portal 9, Dequeue Response Ring, Producer Index Register, Cache-Inhibited" hexmask.long.word 0x00 16.--31. 1. " DQRR_VV ,DQRR valid vector" hexmask.long.byte 0x00 8.--11. 1. " HFS ,Held FQ status" bitfld.long 0x00 4. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--3. 1. " PI ,Producer index" if (((per.l.be(ad:0x0500000000+0x4003500+0x90000))&0x20000)==0x20000) rgroup.long (0x90000+0x4003140)++0x3 line.long 0x00 "QCSP9_DQRR_CI_CINH,Software Portal 9, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x90000+0x4003140)++0x3 line.long 0x00 "QCSP9_DQRR_CI_CINH,Software Portal 9, Dequeue Response Ring, Consumer Index Register, Cache-Inhibited" bitfld.long 0x00 0.--3. " CI ,Consumer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long (0x90000+0x4003180)++0x3 line.long 0x00 "QCSP9_DQRR_ITR,Software Portal 9, DQRR Interrupt Threshold" hexmask.long.byte 0x00 0.--3. 1. " DQRR_IT ,DQRR interrupt threshold" wgroup.long (0x90000+0x40031C0)++0x3 line.long 0x00 "QCSP9_DQRR_DCAP,Software Portal 9, Dequeue Response Ring, Discrete Consumption Acknowledgment and Park Register" hexmask.long.word 0x00 16.--31. 1. " CI_VECTOR ,Consumer index vector" bitfld.long 0x00 8. " S ,Select" "0,1" bitfld.long 0x00 6. " PK ,Park" "0,1" hexmask.long.byte 0x00 0.--3. 1. " DCAP_CI ,Discrete consumption acknowledgment and park consumer index" group.long (0x90000+0x4003200)++0x3 line.long 0x00 "QCSP9_DQRR_SDQCR,Software Portal 9, Static Dequeue Command Register" bitfld.long 0x00 30. " SS ,Source Select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue Command Frame Count" "0,1" bitfld.long 0x00 28. " DP ,Dedicated Channel Precedence. Only valid if SS = 0" "0,1" newline bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " TOKEN ,Dequeue Command Token" hexmask.long.word 0x00 0.--15. 1. " DQ_SRC ,Dequeue Source" group.long (0x90000+0x4003240)++0x3 line.long 0x00 "QCSP9_DQRR_VDQCR,Software Portal 9, Volatile Dequeue Command Register" bitfld.long 0x00 31. " P ,Precedence" "VDQCR,SDQCR" bitfld.long 0x00 30. " E ,Exact" "0,1" hexmask.long.byte 0x00 24.--29. 1. " NUM_FRAMES ,Number of frames that are dequeued from the specified FQ" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame queue ID" group.long (0x90000+0x4003280)++0x3 line.long 0x00 "QCSP9_DQRR_PDQCR,Software Portal 9, Pull Dequeue Command Register" bitfld.long 0x00 31. " SU ,Scheduled/Unscheduled" "0,1" bitfld.long 0x00 30. " SS ,Source select" "0,1" bitfld.long 0x00 29. " FC ,Dequeue command frame count" "0,1" newline bitfld.long 0x00 28. " DP ,Dedicated channel precedence" "0,1" bitfld.long 0x00 24.--25. " DCT ,Dequeue Command Type" "0,1,2,3" hexmask.long.tbyte 0x00 0.--23. 1. " DQ_SRC_FQID ,Dequeue source Frame queue ID" rgroup.long (0x90000+0x4003300)++0x3 "QMan Software Portal 9, MR Index Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_MR_PI_CINH,Software Portal 9, Message Ring, Producer Index Register, Cache-Inhibited" bitfld.long 0x00 3. " VP ,valid bit polarity at producer index " "0,1" hexmask.long.byte 0x00 0.--2. 1. " PI ,Producer index" group.long (0x90000+0x4003340)++0x3 line.long 0x00 "QCSP9_MR_CI_CINH,Software Portal 9, Message Ring, Consumer Index Register, Cache-Inhibited" hexmask.long.byte 0x00 0.--2. 1. " CI ,Consumer index" group.long (0x90000+0x4003380)++0x3 line.long 0x00 "QCSP9_MR_ITR,Software Portal 0, MR Interrupt Threshold" hexmask.long.byte 0x00 0.--2. 1. " MR_IT ,MR interrupt threshold" group.long (0x90000+0x4003500)++0x3 "QMan Software Portal 9, Configuration Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_CFG,Software Portal 9, Configuration Register" bitfld.long 0x00 28.--30. " EST ,EQCR_CI stashing threshold" "dis.,1,2,3,4,5,6,7" bitfld.long 0x00 26. " EP ,EQCR_CI stashing priority" "low,high" bitfld.long 0x00 24.--25. " EPM ,EQCR production notification mode" "0,1,2,3" hexmask.long.byte 0x00 20.--23. 1. " DQRR_MF ,DQRR max fill" newline bitfld.long 0x00 18. " DP ,DQRR push/pull mode" "push,pull" bitfld.long 0x00 16.--17. " DCM ,DQRR consumption notification mode" "0,1,2,3" hexmask.long.byte 0x00 12.--15. 1. " SDESTH ,Stashing destination. Msbits of the SDEST from QCSP_IO_CFG" bitfld.long 0x00 10. " WN ,Writes Non-cacheable" "0,1" newline bitfld.long 0x00 8. " MM ,MR consumption notification mode" "0,1" bitfld.long 0x00 7. " RE ,Dequeue response ring (DQRR) entry stashing enable" "0,1" bitfld.long 0x00 6. " RP ,Dequeue response ring (DQRR) entry stashing priority" "low,high" hexmask.long.byte 0x00 0.--2. 1. " SDESTL ,Stashing destination. Lsbits of the SDEST from QCSP_IO_CFG" group.long (0x90000+0x4003600)++0x3 "QMan Software Portal 9, Interrupt Registers, Cache-Inhibited Area" line.long 0x00 "QCSP9_ISR,Software Portal 9, Interrupt Status Register" rbitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" eventfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" eventfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" eventfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " eventfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" eventfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x90000+0x4003640)++0x3 line.long 0x00 "QCSP9_IER,Software Portal 9, Interrupt Enable Register" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x90000+0x4003680)++0x3 line.long 0x00 "QCSP9_ISDR,Software Portal 9, Interrupt Status Disable" bitfld.long 0x00 21. " CCSCI ,Congestion state change notifications (CEETM CSCN) interrupt" "0,1" bitfld.long 0x00 20. " CSCI ,Congestion state change notifications (CSCN) interrupt" "0,1" bitfld.long 0x00 19. " EQCI ,Enqueue command dispatched interrupt" "0,1" bitfld.long 0x00 18. " EQRI ,EQCR ring interrupt" "0,1" textline " " bitfld.long 0x00 17. " DQRI ,DQRR non-empty interrupt" "0,1" bitfld.long 0x00 16. " MRI ,MR non-empty interrupt" "0,1" hexmask.long.word 0x00 0.--15. 1. " DQ_AVAIL ,dequeue available notification" group.long (0x90000+0x40036C0)++0x3 line.long 0x00 "QCSP9_IIR,Software Portal 9, Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" group.long (0x90000+0x4003740)++0x3 line.long 0x00 "QCSP9_ITPR,Software Portal 9 Interrupt Time out Period Register" hexmask.long.word 0x00 0.--11. 1. " ITP ,DQRR and MR non-empty Interrupt time out period" group.quad (0x90000+0x4003800)++0x07 line.quad 0x00 "QCSP9_CR,Software Portal 9, Management Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x90000+0x4003900)++0x07 line.quad 0x00 "QCSP9_RR0,Software Portal 9, Management Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" rgroup.quad (0x90000+0x4003940)++0x07 line.quad 0x00 "QCSP9_RR1,Software Portal 9, Management Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "0,1" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" tree.end tree.end base ad:0x01880000 width 25. tree "Software Portal Configuration Registers" group.long (0x1000)++0x03 line.long 0x00 "QCSP0_LIO_CFG,QMan Software Portal 0 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 0" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 0" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 0" endif group.long (0x1000+0x04)++0x03 line.long 0x00 "QCSP0_IO_CFG,QMan Software Portal 0 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1000+0x0C)++0x03 line.long 0x00 "QCSP0_DD_CFG,Software Portal 0 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1010)++0x03 line.long 0x00 "QCSP1_LIO_CFG,QMan Software Portal 1 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 1" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 1" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 1" endif group.long (0x1010+0x04)++0x03 line.long 0x00 "QCSP1_IO_CFG,QMan Software Portal 1 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1010+0x0C)++0x03 line.long 0x00 "QCSP1_DD_CFG,Software Portal 1 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1020)++0x03 line.long 0x00 "QCSP2_LIO_CFG,QMan Software Portal 2 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 2" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 2" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 2" endif group.long (0x1020+0x04)++0x03 line.long 0x00 "QCSP2_IO_CFG,QMan Software Portal 2 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1020+0x0C)++0x03 line.long 0x00 "QCSP2_DD_CFG,Software Portal 2 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1030)++0x03 line.long 0x00 "QCSP3_LIO_CFG,QMan Software Portal 3 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 3" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 3" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 3" endif group.long (0x1030+0x04)++0x03 line.long 0x00 "QCSP3_IO_CFG,QMan Software Portal 3 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1030+0x0C)++0x03 line.long 0x00 "QCSP3_DD_CFG,Software Portal 3 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1040)++0x03 line.long 0x00 "QCSP4_LIO_CFG,QMan Software Portal 4 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 4" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 4" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 4" endif group.long (0x1040+0x04)++0x03 line.long 0x00 "QCSP4_IO_CFG,QMan Software Portal 4 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1040+0x0C)++0x03 line.long 0x00 "QCSP4_DD_CFG,Software Portal 4 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1050)++0x03 line.long 0x00 "QCSP5_LIO_CFG,QMan Software Portal 5 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 5" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 5" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 5" endif group.long (0x1050+0x04)++0x03 line.long 0x00 "QCSP5_IO_CFG,QMan Software Portal 5 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1050+0x0C)++0x03 line.long 0x00 "QCSP5_DD_CFG,Software Portal 5 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1060)++0x03 line.long 0x00 "QCSP6_LIO_CFG,QMan Software Portal 6 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 6" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 6" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 6" endif group.long (0x1060+0x04)++0x03 line.long 0x00 "QCSP6_IO_CFG,QMan Software Portal 6 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1060+0x0C)++0x03 line.long 0x00 "QCSP6_DD_CFG,Software Portal 6 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1070)++0x03 line.long 0x00 "QCSP7_LIO_CFG,QMan Software Portal 7 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 7" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 7" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 7" endif group.long (0x1070+0x04)++0x03 line.long 0x00 "QCSP7_IO_CFG,QMan Software Portal 7 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1070+0x0C)++0x03 line.long 0x00 "QCSP7_DD_CFG,Software Portal 7 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1080)++0x03 line.long 0x00 "QCSP8_LIO_CFG,QMan Software Portal 8 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 8" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 8" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 8" endif group.long (0x1080+0x04)++0x03 line.long 0x00 "QCSP8_IO_CFG,QMan Software Portal 8 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1080+0x0C)++0x03 line.long 0x00 "QCSP8_DD_CFG,Software Portal 8 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1090)++0x03 line.long 0x00 "QCSP9_LIO_CFG,QMan Software Portal 9 LIO Configuration" hexmask.long.byte 0x00 22.--23. 1. " EICID ,Extended Isolation context ID 4 msb bits of complete ICID software portal 9" hexmask.long.byte 0x00 16.--21. 1. " ICID ,Isolation context ID 6 lsbits of complete ICID software portal 9" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " DICID ,DQRR entry isolation context identifier of complete ICID software portal 9" endif group.long (0x1090+0x04)++0x03 line.long 0x00 "QCSP9_IO_CFG,QMan Software Portal 9 IO Configuration" hexmask.long.byte 0x00 16.--23. 1. " SDEST ,Stashing destination" sif cpuis("LS10?6A") hexmask.long.byte 0x00 0.--7. 1. " FICID ,Frame data isolation context identifier" endif group.long (0x1090+0x0C)++0x03 line.long 0x00 "QCSP9_DD_CFG,Software Portal 9 Dynamic Debug Configuration" bitfld.long 0x00 22.--24. " ED_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " ED_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " ED_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " E_TP_CFG[10] ,Trace point configuration for frame DD code point = 10(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " E_TP_CFG[11] ,Trace point configuration for frame DD code point = 11(Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" tree.end tree "Dynamic Debug (DD) Configuration Registers" group.long 0x200++0x3 line.long 0x00 "QMAN_DD_CFG,QMan Dynamic Debug Configuration" bitfld.long 0x00 31. " L ,Lossy Mode" "Disabled,Enabled" bitfld.long 0x00 30. " F ,FIFO full" "Not full,Full" newline bitfld.long 0x00 4.--5. " MDD ,Order Restoration deferral Marking Dynamic Debug code point" "Disabled,Enabled,Enabled,Enabled" bitfld.long 0x00 3. " M_CFG[00] ,Marking configuration for frame DD code point = 00" "Disabled,Enabled" bitfld.long 0x00 2. " [01] ,Marking configuration for frame DD code point = 01" "Disabled,Enabled" newline bitfld.long 0x00 1. " M_CFG[10] ,Marking configuration for frame DD code point = 10" "Disabled,Enabled" bitfld.long 0x00 0. " [11] ,Marking configuration for frame DD code point = 11" "Disabled,Enabled" group.long 0x220++0x3 line.long 0x00 "DCP_DD_IHRSR,DCP DD Internal Halt Request Status" eventfld.long 0x00 31. " IHRS[0] ,Internal Halt Request Status for software portal 0" "Not asserted,Asserted" eventfld.long 0x00 30. " [1] ,Internal Halt Request Status for software portal 1" "Not asserted,Asserted" eventfld.long 0x00 29. " [2] ,Internal Halt Request Status for software portal 2" "Not asserted,Asserted" wgroup.long 0x224++0x3 line.long 0x00 "QCSP_DD_IHRFR,DCP DD Internal Halt Request Force" bitfld.long 0x00 31. " IHRF[0] ,Internal Halt Request Force for QMan CoreNet Software Portal 0" "Not assert,Assert" bitfld.long 0x00 30. " [1] ,Internal Halt Request Force for QMan CoreNet Software Portal 1" "Not assert,Assert" bitfld.long 0x00 29. " [2] ,Internal Halt Request Force for QMan CoreNet Software Portal 2" "Not assert,Assert" rgroup.long 0x228++0x3 line.long 0x00 "DCP_DD_HASR,Dynamic Debug Halt Acknowledge Status" bitfld.long 0x00 31. " HAS[0] ,Halt Acknowledge Status for direct connect portal 0" "Not halted,Halted" bitfld.long 0x00 30. " [1] ,Halt Acknowledge Status for direct connect portal 1" "Not halted,Halted" bitfld.long 0x00 29. " [2] ,Halt Acknowledge Status for direct connect portal 2" "Not halted,Halted" group.long 0x240++0x03 line.long 0x00 "QCSP_DD_IHRSR_0,Software Portal DD Internal Halt Request Status Register" eventfld.long 0x00 31. " IHRS[0] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 30. " [1] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 29. " [2] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 28. " [3] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 27. " [4] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 26. " [5] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 25. " [6] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 24. " [7] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 23. " [8] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 22. " [9] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 21. " [10] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 20. " [11] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 19. " [12] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 18. " [13] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 17. " [14] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 16. " [15] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 15. " [16] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 14. " [17] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 13. " [18] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 12. " [19] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 11. " [20] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 10. " [21] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 9. " [22] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 8. " [23] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 7. " [24] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 6. " [25] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 5. " [26] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 4. " [27] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 3. " [28] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 2. " [29] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 1. " [30] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 0. " [31] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" wgroup.long 0x244++0x03 line.long 0x00 "QCSP_DD_IHRFR_0,Software Portal DD Internal Halt Request Force Register" bitfld.long 0x00 31. " IHRF[0] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [1] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [2] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [3] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [4] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [5] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [6] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [7] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [8] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [9] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [10] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [11] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [12] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [13] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [14] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [15] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [16] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [17] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [18] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [19] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [20] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [21] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [22] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [23] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [24] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [25] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [26] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [27] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [28] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [29] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [30] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [31] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" rgroup.long 0x248++0x03 line.long 0x00 "QCSP_DD_HASR_0,Software Portal DD Halt Acknowledge Status Register" bitfld.long 0x00 31. " HAS[0] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [1] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [2] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [3] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [4] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [5] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [6] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [7] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [8] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [9] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [10] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [11] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [12] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [13] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [14] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [15] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [16] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [17] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [18] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [19] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [20] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [21] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [22] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [23] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [24] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [25] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [26] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [27] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [28] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [29] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [30] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [31] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" group.long 0x250++0x03 line.long 0x00 "QCSP_DD_IHRSR_1,Software Portal DD Internal Halt Request Status Register" eventfld.long 0x00 31. " IHRS[32] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 30. " [33] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 29. " [34] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 28. " [35] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 27. " [36] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 26. " [37] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 25. " [38] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 24. " [39] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 23. " [40] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 22. " [41] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 21. " [42] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 20. " [43] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 19. " [44] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 18. " [45] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 17. " [46] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 16. " [47] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 15. " [48] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 14. " [49] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 13. " [50] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 12. " [51] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 11. " [52] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 10. " [53] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 9. " [54] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 8. " [55] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 7. " [56] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 6. " [57] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 5. " [58] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 4. " [59] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 3. " [60] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 2. " [61] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 1. " [62] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 0. " [63] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" wgroup.long 0x254++0x03 line.long 0x00 "QCSP_DD_IHRFR_1,Software Portal DD Internal Halt Request Force Register" bitfld.long 0x00 31. " IHRF[32] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [33] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [34] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [35] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [36] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [37] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [38] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [39] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [40] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [41] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [42] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [43] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [44] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [45] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [46] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [47] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [48] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [49] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [50] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [51] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [52] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [53] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [54] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [55] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [56] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [57] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [58] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [59] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [60] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [61] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [62] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [63] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" rgroup.long 0x258++0x03 line.long 0x00 "QCSP_DD_HASR_1,Software Portal DD Halt Acknowledge Status Register" bitfld.long 0x00 31. " HAS[32] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [33] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [34] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [35] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [36] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [37] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [38] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [39] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [40] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [41] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [42] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [43] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [44] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [45] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [46] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [47] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [48] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [49] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [50] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [51] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [52] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [53] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [54] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [55] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [56] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [57] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [58] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [59] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [60] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [61] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [62] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [63] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" group.long 0x260++0x03 line.long 0x00 "QCSP_DD_IHRSR_2,Software Portal DD Internal Halt Request Status Register" eventfld.long 0x00 31. " IHRS[64] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 30. " [65] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 29. " [66] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 28. " [67] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 27. " [68] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 26. " [69] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 25. " [70] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 24. " [71] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 23. " [72] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 22. " [73] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 21. " [74] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 20. " [75] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 19. " [76] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 18. " [77] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 17. " [78] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 16. " [79] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 15. " [80] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 14. " [81] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 13. " [82] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 12. " [83] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 11. " [84] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 10. " [85] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 9. " [86] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 8. " [87] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 7. " [88] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 6. " [89] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 5. " [90] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 4. " [91] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" newline eventfld.long 0x00 3. " [92] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 2. " [93] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 1. " [94] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" eventfld.long 0x00 0. " [95] ,Internal halt request status for QMan software portals" "Not asserted,Asserted" wgroup.long 0x264++0x03 line.long 0x00 "QCSP_DD_IHRFR_2,Software Portal DD Internal Halt Request Force Register" bitfld.long 0x00 31. " IHRF[64] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [65] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [66] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [67] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [68] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [69] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [70] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [71] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [72] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [73] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [74] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [75] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [76] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [77] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [78] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [79] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [80] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [81] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [82] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [83] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [84] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [85] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [86] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [87] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [88] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [89] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [90] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [91] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [92] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [93] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [94] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [95] ,Internal halt request force for QMan software portals" "Not asserted,Asserted" rgroup.long 0x268++0x03 line.long 0x00 "QCSP_DD_HASR_2,Software Portal DD Halt Acknowledge Status Register" bitfld.long 0x00 31. " HAS[64] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 30. " [65] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 29. " [66] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 28. " [67] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 27. " [68] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 26. " [69] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 25. " [70] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 24. " [71] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 23. " [72] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 22. " [73] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 21. " [74] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 20. " [75] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 19. " [76] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 18. " [77] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 17. " [78] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 16. " [79] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 15. " [80] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 14. " [81] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 13. " [82] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 12. " [83] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 11. " [84] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 10. " [85] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 9. " [86] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 8. " [87] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 7. " [88] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 6. " [89] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 5. " [90] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 4. " [91] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" newline bitfld.long 0x00 3. " [92] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 2. " [93] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 1. " [94] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" bitfld.long 0x00 0. " [95] ,Halt acknowledge status for QMan software portals" "Not asserted,Asserted" tree.end tree "Direct Connect Portal (DCP) Configuration Registers" group.long (0x300)++0x0F line.long 0x00 "DCP0_CFG,Direct Connect Portal 0 Configuration" bitfld.long 0x00 31. " CEETM[0] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 21. " [10] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 20. " [11] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [12] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 18. " [13] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 17. " [14] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 16. " [15] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " ED ,Enqueue Rejection Notification (ERN) Destination" "Software,Hardware" hexmask.long.word 0x00 0.--9. 1. " SERND ,Software Enqueue Rejection Notification (ERN) Destination" line.long 0x04 "DCP0_DD_CFG,Direct Connect Portal 0 Dynamic Debug Configuration" bitfld.long 0x04 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01 (Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x04 3.--5. " [10] ,Trace point configuration for frame DD code point = 10" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x04 0.--2. " [11] ,Trace point configuration for frame DD code point = 11" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" line.long 0x08 "DCP0_DLM_CFG,DCP0 Dequeue Latency Monitor Configuration" bitfld.long 0x08 28.--31. " DLM_TH_A ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency A Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" bitfld.long 0x08 24.--27. " DLM_TH_B ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency B Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" bitfld.long 0x08 20.--23. " DLM_TH_C ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency C Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" newline bitfld.long 0x08 16.--19. " DLM_TH_D ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency D Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" newline bitfld.long 0x08 15. " SM[0] ,Enable monitoring for dequeue commands made via sub portal 0" "Disabled,Enabled" bitfld.long 0x08 14. " [1] ,Enable monitoring for dequeue commands made via sub portal 1" "Disabled,Enabled" bitfld.long 0x08 13. " [2] ,Enable monitoring for dequeue commands made via sub portal 2" "Disabled,Enabled" bitfld.long 0x08 12. " [3] ,Enable monitoring for dequeue commands made via sub portal 3" "Disabled,Enabled" newline bitfld.long 0x08 11. " [4] ,Enable monitoring for dequeue commands made via sub portal 4" "Disabled,Enabled" bitfld.long 0x08 10. " [5] ,Enable monitoring for dequeue commands made via sub portal 5" "Disabled,Enabled" bitfld.long 0x08 9. " [6] ,Enable monitoring for dequeue commands made via sub portal 6" "Disabled,Enabled" bitfld.long 0x08 8. " [7] ,Enable monitoring for dequeue commands made via sub portal 7" "Disabled,Enabled" newline bitfld.long 0x08 7. " [8] ,Enable monitoring for dequeue commands made via sub portal 8" "Disabled,Enabled" bitfld.long 0x08 6. " [9] ,Enable monitoring for dequeue commands made via sub portal 9" "Disabled,Enabled" bitfld.long 0x08 5. " [10] ,Enable monitoring for dequeue commands made via sub portal 10" "Disabled,Enabled" bitfld.long 0x08 4. " [11] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" newline bitfld.long 0x08 3. " [12] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 2. " [13] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 1. " [14] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 0. " [15] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" line.long 0x0C "DCP0_DLM_AVG,DCP0 Dequeue Latency Monitor Average" hexmask.long.word 0x0C 8.--19. 1. " DLM_AVG_INT ,Integer portion of the measured average latency value" hexmask.long.byte 0x0C 0.--7. 1. " DLM_AVG_FRACT ,Fractional portion of the measured average latency value" newline group.long (0x320)++0x0F line.long 0x00 "DCP2_CFG,Direct Connect Portal 2 Configuration" bitfld.long 0x00 31. " CEETM[0] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 21. " [10] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 20. " [11] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [12] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 18. " [13] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 17. " [14] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" bitfld.long 0x00 16. " [15] ,Customer edge egress traffic management (CEETM) enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " ED ,Enqueue Rejection Notification (ERN) Destination" "Software,Hardware" hexmask.long.word 0x00 0.--9. 1. " SERND ,Software Enqueue Rejection Notification (ERN) Destination" line.long 0x04 "DCP2_DD_CFG,Direct Connect Portal 2 Dynamic Debug Configuration" bitfld.long 0x04 6.--8. " E_TP_CFG[01] ,Trace point configuration for frame DD code point = 01 (Trace/Portal)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x04 3.--5. " [10] ,Trace point configuration for frame DD code point = 10" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x04 0.--2. " [11] ,Trace point configuration for frame DD code point = 11" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" line.long 0x08 "DCP2_DLM_CFG,DCP2 Dequeue Latency Monitor Configuration" bitfld.long 0x08 28.--31. " DLM_TH_A ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency A Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" bitfld.long 0x08 24.--27. " DLM_TH_B ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency B Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" bitfld.long 0x08 20.--23. " DLM_TH_C ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency C Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" newline bitfld.long 0x08 16.--19. " DLM_TH_D ,Threshold which is used for comparison in the generation of the DCP Dequeue Latency D Performance Monitor signal" "9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,16 cycles,18 cycles,20 cycles,24 cycles,32 cycles,48 cycles,64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles" newline bitfld.long 0x08 15. " SM[0] ,Enable monitoring for dequeue commands made via sub portal 0" "Disabled,Enabled" bitfld.long 0x08 14. " [1] ,Enable monitoring for dequeue commands made via sub portal 1" "Disabled,Enabled" bitfld.long 0x08 13. " [2] ,Enable monitoring for dequeue commands made via sub portal 2" "Disabled,Enabled" bitfld.long 0x08 12. " [3] ,Enable monitoring for dequeue commands made via sub portal 3" "Disabled,Enabled" newline bitfld.long 0x08 11. " [4] ,Enable monitoring for dequeue commands made via sub portal 4" "Disabled,Enabled" bitfld.long 0x08 10. " [5] ,Enable monitoring for dequeue commands made via sub portal 5" "Disabled,Enabled" bitfld.long 0x08 9. " [6] ,Enable monitoring for dequeue commands made via sub portal 6" "Disabled,Enabled" bitfld.long 0x08 8. " [7] ,Enable monitoring for dequeue commands made via sub portal 7" "Disabled,Enabled" newline bitfld.long 0x08 7. " [8] ,Enable monitoring for dequeue commands made via sub portal 8" "Disabled,Enabled" bitfld.long 0x08 6. " [9] ,Enable monitoring for dequeue commands made via sub portal 9" "Disabled,Enabled" bitfld.long 0x08 5. " [10] ,Enable monitoring for dequeue commands made via sub portal 10" "Disabled,Enabled" bitfld.long 0x08 4. " [11] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" newline bitfld.long 0x08 3. " [12] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 2. " [13] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 1. " [14] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" bitfld.long 0x08 0. " [15] ,Enable monitoring for dequeue commands made via sub portal 11" "Disabled,Enabled" line.long 0x0C "DCP2_DLM_AVG,DCP2 Dequeue Latency Monitor Average" hexmask.long.word 0x0C 8.--19. 1. " DLM_AVG_INT ,Integer portion of the measured average latency value" hexmask.long.byte 0x0C 0.--7. 1. " DLM_AVG_FRACT ,Fractional portion of the measured average latency value" newline tree.end tree "Packed Frame Descriptor Record (PFDR) Manager Query Registers" rgroup.long 0x400++0x3 line.long 0x00 "PFDR_FPC,PFDR Free Pool Count" hexmask.long.tbyte 0x00 0.--23. 1. " FPC ,Free Pool Count" rgroup.long 0x404++0x3 line.long 0x00 "PFDR_FP_HEAD,PFDR Free Pool Head Pointer" hexmask.long.tbyte 0x00 0.--23. 1. " FPHP ,Packed Frame Descriptor Record Free Pool Head Pointer" rgroup.long 0x408++0x03 line.long 0x00 "PFDR_FP_TAIL,PFDR Free Pool Tail pointer" hexmask.long.tbyte 0x00 0.--23. 1. " FPTP ,Packed Frame Descriptor Record Free Pool Tail Pointer" group.long 0x410++0x3 line.long 0x00 "PFDR_FP_LWIT,PFDR Free Pool Low Watermark Interrupt Threshold" hexmask.long.tbyte 0x00 0.--23. 1. " TH ,PFDR Low Watermark Interrupt Threshold" group.long 0x414++0x3 line.long 0x00 "PFDR_CFG,PFDR Configuration" hexmask.long.byte 0x00 0.--7. 1. " K ,PFDR Base Constant" tree.end tree "Single Frame Descriptor Record (SFDR) Manager Registers" group.long 0x500++0x3 line.long 0x00 "SFDR_CFG,SFDR Configuration Register" bitfld.long 0x00 31. " RM ,SFDR reservation mode" "High prior. WQs,Allocate bit set" hexmask.long.word 0x00 0.--9. 1. " TH ,SFDR high priority reservation Threshold" rgroup.long 0x504++0x3 line.long 0x00 "SFDR_IN_USE,SFDR In Use Register" hexmask.long.word 0x00 0.--11. 1. " NUM ,SFDR In Use Number" tree.end tree "Work Queue Semaphore and Context Manager Registers" group.long (0x600)++0x03 line.long 0x00 "WQ_CS_CFG0,Work Queue Class Scheduler Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " CS_ELEV ,WQ Class Scheduler Priority Elevation weight" bitfld.long 0x00 20.--22. " CSW2 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " CSW3 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" bitfld.long 0x00 12.--14. " CSW4 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" bitfld.long 0x00 8.--10. " CSW5 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" bitfld.long 0x00 4.--6. " CSW6 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--2. " CSW7 ,Class Scheduler Weight for WQ 0" "1,2,3,4,5,6,7,8" group.long (0x604)++0x03 line.long 0x00 "WQ_CS_CFG1,Work Queue Class Scheduler Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " CS_ELEV ,WQ Class Scheduler Priority Elevation weight" bitfld.long 0x00 20.--22. " CSW2 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " CSW3 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 12.--14. " CSW4 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 8.--10. " CSW5 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 4.--6. " CSW6 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--2. " CSW7 ,Class Scheduler Weight for WQ 1" "1,2,3,4,5,6,7,8" group.long (0x608)++0x03 line.long 0x00 "WQ_CS_CFG2,Work Queue Class Scheduler Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " CS_ELEV ,WQ Class Scheduler Priority Elevation weight" bitfld.long 0x00 20.--22. " CSW2 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " CSW3 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" bitfld.long 0x00 12.--14. " CSW4 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" bitfld.long 0x00 8.--10. " CSW5 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" bitfld.long 0x00 4.--6. " CSW6 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--2. " CSW7 ,Class Scheduler Weight for WQ 2" "1,2,3,4,5,6,7,8" group.long (0x60C)++0x03 line.long 0x00 "WQ_CS_CFG3,Work Queue Class Scheduler Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " CS_ELEV ,WQ Class Scheduler Priority Elevation weight" bitfld.long 0x00 20.--22. " CSW2 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" bitfld.long 0x00 16.--18. " CSW3 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" bitfld.long 0x00 12.--14. " CSW4 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" bitfld.long 0x00 8.--10. " CSW5 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" bitfld.long 0x00 4.--6. " CSW6 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--2. " CSW7 ,Class Scheduler Weight for WQ 3" "1,2,3,4,5,6,7,8" newline group.long 0x630++0x3 line.long 0x00 "WQ_DEF_ENQ_WQID,WQ Default Enqueue WQID" hexmask.long.word 0x00 0.--15. 1. " WQID ,Default Enqueue Work Queue ID" group.long (0x680)++0x3 line.long 0x00 "WQ_PC_DD_CFG_0,WQ Channel Dynamic Debug Configuration Register 0" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Pool channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Pool channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Pool channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline group.long (0x684)++0x3 line.long 0x00 "WQ_PC_DD_CFG_1,WQ Channel Dynamic Debug Configuration Register 1" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Pool channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Pool channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Pool channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Pool channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Pool channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Pool channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x6C0)++0x3 line.long 0x00 "WQ_DC0_DD_CFG_0,WQ Channel Dynamic Debug Configuration Register 0" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Direct Connect portal 0 - Channel 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Direct Connect portal 0 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x6C4)++0x3 line.long 0x00 "WQ_DC0_DD_CFG_1,WQ Channel Dynamic Debug Configuration Register 1" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Direct Connect portal 0 - Channel 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Direct Connect portal 0 - Channel 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x6C8)++0x3 line.long 0x00 "WQ_DC0_DD_CFG_2,WQ Channel Dynamic Debug Configuration Register 2" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Direct Connect portal 0 - Channel 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Direct Connect portal 0 - Channel 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x6CC)++0x3 line.long 0x00 "WQ_DC0_DD_CFG_3,WQ Channel Dynamic Debug Configuration Register 3" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Direct Connect portal 0 - Channel 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Direct Connect portal 0 - Channel 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Direct Connect portal 0 - Channel 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Direct Connect portal 0 - Channel 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long 0x740++0x3 line.long 0x00 "WQ_DC2_DD_CFG_0,WQ Channel Dynamic Debug Configuration Register 0" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Direct connect portal 2 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Direct connect portal 2 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Direct Connect portal 2 - Channel 0)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" tree.end tree "Congestion Manager (CM) Register" group.long 0x800++0x3 line.long 0x00 "CM_CFG,CM Configuration Register" hexmask.long.word 0x00 0.--15. 1. " PRES ,WRED block averaging timer pre-scaler" tree.end tree "Customer Edge Egress Traffic Management Configuration (CEETM_CFG) Register" group.long 0x900++0x07 line.long 0x00 "CEETM_CFG_IDX,CEETM Configuration Index Register" bitfld.long 0x00 0.--3. " DCPID ,CEETM portal ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CEETM_CFG_PRES,CEETM Configuration Shaper Pre-Scaler Register" hexmask.long.word 0x04 0.--15. 1. " PRES ,CEETM shaper pre-scaler value" rgroup.long 0x908++0x03 line.long 0x00 "CEETM_XSFDR_IN_USE,CEETM XSFDR In Use Register" hexmask.long.word 0x00 0.--12. 1. " NUM ,XSFDR in use number" tree.end tree "QMan Error Capture Registers" group.long 0xA00++0x3 line.long 0x00 "QMAN_ECSR,QMan Error Capture Status Register" eventfld.long 0x00 31. " ME ,Multiple Errors" "Not occurred,Occurred" eventfld.long 0x00 25. " MBEI ,Multi Bit ECC Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " SBEI ,Single Bit ECC Error Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 17. " IFSI ,Invalid FQ Flow Control State Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " ICVI ,Invalid Command Verb Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " IDDI ,Invalid Dequeue Direct Connect Portal Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " IDFI ,Invalid Dequeue FQ Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " IDSI ,Invalid Dequeue Source Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " IDQI ,Invalid Dequeue Queue Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " IECE ,Invalid Enqueue Configuration Error" "No interrupt,Interrupt" eventfld.long 0x00 3. " IEOI ,Invalid Enqueue Overflow Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 2. " IESI ,Invalid Enqueue State Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " IECI ,Invalid Enqueue Channel Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " IEQI ,Invalid Enqueue Queue Interrupt" "No interrupt,Interrupt" rgroup.long 0xA04++0x3 line.long 0x00 "QMAN_ECIR1,QMan Error Capture Information Register" hexmask.long.tbyte 0x00 0.--23. 1. " FQID ,Frame Queue ID" newline rgroup.long 0xA08++0x3 line.long 0x00 "QMAN_EADR,QMan ECC Error Address Register" bitfld.long 0x00 24.--28. " MEM_ID ,Memory ID" "FQD cache tag memory 0,FQD cache tag memory 1,FQD cache tag memory 2,FQD cache tag memory 3,FQD cache memory,SFDR memory,WQ context memory,Congestion Group Record memory,Internal Order Restoration List memory,Software portal ring memory,Egress traffic management class queue descriptor memory,Egress traffic management extended SFDR memory,Egress traffic management logical FQ mapping memory,Egress traffic management dequeue context memory,Egress traffic management class congestion group record memory,Egress traffic management class queue channel shaping memory,Egress traffic management class queue channel scheduling memory,Egress traffic management dequeue statistics memory,?..." newline hexmask.long.word 0x00 0.--15. 1. " EADR ,Error Address" newline rgroup.long 0xA0C++0x3 line.long 0x00 "QMAN_ECIR2,QMan Error Capture Information Register" bitfld.long 0x00 31. " T ,Portal type" "Software portal,Direct connect portal" hexmask.long.word 0x00 0.--9. 1. " PORTAL ,Portal number" rgroup.long (0xA10)++0x3 line.long 0x00 "QMAN_EDATA0,QMan ECC Error Data Register 0" rgroup.long (0xA14)++0x3 line.long 0x00 "QMAN_EDATA1,QMan ECC Error Data Register 1" rgroup.long (0xA18)++0x3 line.long 0x00 "QMAN_EDATA2,QMan ECC Error Data Register 2" rgroup.long (0xA1C)++0x3 line.long 0x00 "QMAN_EDATA3,QMan ECC Error Data Register 3" rgroup.long (0xA20)++0x3 line.long 0x00 "QMAN_EDATA4,QMan ECC Error Data Register 4" rgroup.long (0xA24)++0x3 line.long 0x00 "QMAN_EDATA5,QMan ECC Error Data Register 5" rgroup.long (0xA28)++0x3 line.long 0x00 "QMAN_EDATA6,QMan ECC Error Data Register 6" rgroup.long (0xA2C)++0x3 line.long 0x00 "QMAN_EDATA7,QMan ECC Error Data Register 7" rgroup.long (0xA30)++0x3 line.long 0x00 "QMAN_EDATA8,QMan ECC Error Data Register 8" rgroup.long (0xA34)++0x3 line.long 0x00 "QMAN_EDATA9,QMan ECC Error Data Register 9" rgroup.long (0xA38)++0x3 line.long 0x00 "QMAN_EDATA10,QMan ECC Error Data Register 10" rgroup.long (0xA3C)++0x3 line.long 0x00 "QMAN_EDATA11,QMan ECC Error Data Register 11" rgroup.long (0xA40)++0x3 line.long 0x00 "QMAN_EDATA12,QMan ECC Error Data Register 12" rgroup.long (0xA44)++0x3 line.long 0x00 "QMAN_EDATA13,QMan ECC Error Data Register 13" rgroup.long (0xA48)++0x3 line.long 0x00 "QMAN_EDATA14,QMan ECC Error Data Register 14" rgroup.long (0xA4C)++0x3 line.long 0x00 "QMAN_EDATA15,QMan ECC Error Data Register 15" group.long 0xA70++0x3 line.long 0x00 "QMAN_SBET,QMan Single Bit ECC Error Threshold Register" bitfld.long 0x00 31. " ECDD[0] ,FQD cache memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 30. " [1] ,FQD cache tag memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 29. " [2] ,SFDR memory Error Correction and Detection Disable" "No,Yes" newline bitfld.long 0x00 28. " [3] ,WQ context memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 27. " [4] ,Congestion Group Record memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 26. " [5] ,Internal Order Restoration List memory Error Correction and Detection Disable" "No,Yes" newline bitfld.long 0x00 25. " [6] ,Software portal ring memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 24. " [7] ,Egress traffic management class queue descriptor memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 23. " [8] , Egress traffic management extended SFDR memory Error Correction and Detection Disable" "No,Yes" newline bitfld.long 0x00 22. " [9] ,Egress traffic management logical FQ mapping memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 21. " [10] ,Egress traffic management dequeue context memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 20. " [11] ,Egress traffic management class congestion group record memory Error Correction and Detection Disable" "No,Yes" newline bitfld.long 0x00 19. " [12] ,Egress traffic management class queue channel shaping memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 18. " [13] ,Egress traffic management class queue channel scheduling memory Error Correction and Detection Disable" "No,Yes" bitfld.long 0x00 17. " [14] ,Egress traffic management dequeue statistics memory Error Correction and Detection Disable" "No,Yes" newline hexmask.long.byte 0x00 0.--7. 1. " SBET ,Single Bit Error Threshold" hgroup.long (0xA80)++0x3 hide.long 0x00 "QMAN_SBEC0,QMan Single Bit ECC Error Count Register 0" in hgroup.long (0xA84)++0x3 hide.long 0x00 "QMAN_SBEC1,QMan Single Bit ECC Error Count Register 1" in hgroup.long (0xA88)++0x3 hide.long 0x00 "QMAN_SBEC2,QMan Single Bit ECC Error Count Register 2" in hgroup.long (0xA8C)++0x3 hide.long 0x00 "QMAN_SBEC3,QMan Single Bit ECC Error Count Register 3" in hgroup.long (0xA90)++0x3 hide.long 0x00 "QMAN_SBEC4,QMan Single Bit ECC Error Count Register 4" in hgroup.long (0xA94)++0x3 hide.long 0x00 "QMAN_SBEC5,QMan Single Bit ECC Error Count Register 5" in hgroup.long (0xA98)++0x3 hide.long 0x00 "QMAN_SBEC6,QMan Single Bit ECC Error Count Register 6" in hgroup.long (0xA9C)++0x3 hide.long 0x00 "QMAN_SBEC7,QMan Single Bit ECC Error Count Register 7" in hgroup.long (0xAA0)++0x3 hide.long 0x00 "QMAN_SBEC8,QMan Single Bit ECC Error Count Register 8" in hgroup.long (0xAA4)++0x3 hide.long 0x00 "QMAN_SBEC9,QMan Single Bit ECC Error Count Register 9" in hgroup.long (0xAA8)++0x3 hide.long 0x00 "QMAN_SBEC10,QMan Single Bit ECC Error Count Register 10" in hgroup.long (0xAAC)++0x3 hide.long 0x00 "QMAN_SBEC11,QMan Single Bit ECC Error Count Register 11" in hgroup.long (0xAB0)++0x3 hide.long 0x00 "QMAN_SBEC12,QMan Single Bit ECC Error Count Register 12" in hgroup.long (0xAB4)++0x3 hide.long 0x00 "QMAN_SBEC13,QMan Single Bit ECC Error Count Register 13" in hgroup.long (0xAB8)++0x3 hide.long 0x00 "QMAN_SBEC14,QMan Single Bit ECC Error Count Register 14" in tree.end tree "QMan Initialization and Debug Control Registers" group.long 0xB00++0x3 line.long 0x00 "QMAN_MCR,QMan Management Command/Result Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_RSLT ,QMan Management Command/Result" group.long 0xB04++0x3 line.long 0x00 "QMAN_MCP0,QMan Management Command Parameter 0 Register" group.long 0xB08++0x3 line.long 0x00 "QMAN_MCP1,QMan Management Command Parameter 1 Register" rgroup.long (0xB20)++0x3 line.long 0x00 "QMAN_MR0,QMan Management Command Result Register 0" rgroup.long (0xB24)++0x3 line.long 0x00 "QMAN_MR1,QMan Management Command Result Register 1" rgroup.long (0xB28)++0x3 line.long 0x00 "QMAN_MR2,QMan Management Command Result Register 2" rgroup.long (0xB2C)++0x3 line.long 0x00 "QMAN_MR3,QMan Management Command Result Register 3" rgroup.long (0xB30)++0x3 line.long 0x00 "QMAN_MR4,QMan Management Command Result Register 4" rgroup.long (0xB34)++0x3 line.long 0x00 "QMAN_MR5,QMan Management Command Result Register 5" rgroup.long (0xB38)++0x3 line.long 0x00 "QMAN_MR6,QMan Management Command Result Register 6" rgroup.long (0xB3C)++0x3 line.long 0x00 "QMAN_MR7,QMan Management Command Result Register 7" rgroup.long (0xB40)++0x3 line.long 0x00 "QMAN_MR8,QMan Management Command Result Register 8" rgroup.long (0xB44)++0x3 line.long 0x00 "QMAN_MR9,QMan Management Command Result Register 9" rgroup.long (0xB48)++0x3 line.long 0x00 "QMAN_MR10,QMan Management Command Result Register 10" rgroup.long (0xB4C)++0x3 line.long 0x00 "QMAN_MR11,QMan Management Command Result Register 11" rgroup.long (0xB50)++0x3 line.long 0x00 "QMAN_MR12,QMan Management Command Result Register 12" rgroup.long (0xB54)++0x3 line.long 0x00 "QMAN_MR13,QMan Management Command Result Register 13" rgroup.long (0xB58)++0x3 line.long 0x00 "QMAN_MR14,QMan Management Command Result Register 14" rgroup.long (0xB5C)++0x3 line.long 0x00 "QMAN_MR15,QMan Management Command Result Register 15" group.long 0xBE0++0x3 line.long 0x00 "QMAN_MISC_CFG,QMan Miscellaneous Configuration Register" bitfld.long 0x00 1. " WPM ,Waterfall power management enable" "Disabled,Enabled" bitfld.long 0x00 0. " FCM ,FQD cache mode" "Hash mapped,Direct mapped" rgroup.long 0xBF4++0x3 line.long 0x00 "QMAN_IDLE_STAT,QMan Idle Status Register" bitfld.long 0x00 1. " E ,Empty" "Not empty,Empty" bitfld.long 0x00 0. " I ,Idle" "Busy,Idle" tree.end tree "QMan ID/Revision Registers" rgroup.long 0xBF8++0x3 line.long 0x00 "QMAN_IP_REV_1,QMan IP Block Revision 1 Register" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP Block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" rgroup.long 0xBFC++0x3 line.long 0x00 "QMAN_IP_REV_2,QMan IP Block Revision 2 Register" hexmask.long.byte 0x00 16.--23. 1. " IP_INT ,Integration options" hexmask.long.byte 0x00 8.--15. 1. " IP_ERR ,Errata revision level" hexmask.long.byte 0x00 0.--7. 1. " IP_CFG ,Configuration options" tree.end tree "CoreNet Initiator Interface Memory Window Configuration Registers" group.long 0xC00++0x03 line.long 0x00 "FQD_BARE,FQD Extended Base Address Register" hexmask.long.word 0x00 0.--15. 0x01 " EBA ,Extended Base Address" group.long 0xC04++0x3 line.long 0x00 "FQD_BAR,FQD Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BA ,Base Address" group.long 0xC10++0x3 line.long 0x00 "FQD_AR,FQD Attributes Register" bitfld.long 0x00 31. " EN ,Data Structure Access Enable" "Disabled,Enabled" bitfld.long 0x00 30. " P ,Data Structure Transaction Priority" "Lower,Higher" newline bitfld.long 0x00 29. " SE ,CPC Stash Enable" "Disabled,Enabled" bitfld.long 0x00 28. " SO ,CPC stash optimize" "All FQD,Only FQD" bitfld.long 0x00 0.--5. " SIZE ,Size of the window from the base address" ",,,,,,,,,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,?..." group.long 0xC20++0x03 line.long 0x00 "PFDR_BARE,PFDR Extended Base Address Register" hexmask.long.word 0x00 0.--15. 0x01 " EBA ,Extended Base Address" group.long 0xC24++0x3 line.long 0x00 "PFDR_BAR,PFDR Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " BA ,Base Address" group.long 0xC30++0x3 line.long 0x00 "PFDR_AR,PFDR Attributes Register" bitfld.long 0x00 31. " EN ,Data Structure Access Enable" "Disabled,Enabled" bitfld.long 0x00 30. " P ,Data Structure Transaction Priority" "Lower,Higher" newline bitfld.long 0x00 29. " SE ,CPC Stash Enable" "Disabled,Enabled" bitfld.long 0x00 0.--5. " SIZE ,Size of the window from the base address" ",,,,,,,,,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,?..." group.long 0xC80++0x3 line.long 0x00 "QCSP_BARE,QCSP Extended Base Address" hexmask.long.word 0x00 0.--15. 0x01 " EBA ,Extended Base Address" group.long 0xC84++0x03 line.long 0x00 "QCSP_BAR,QCSP Base Address" hexmask.long.byte 0x00 27.--31. 0x08 " BA ,Base Address" group.long 0xD00++0x3 line.long 0x00 "CI_SCHED_CFG,Initiator Initiator Scheduling Configuration" bitfld.long 0x00 8.--10. " SRQ_W ,Stash Request Queues (SRQ) scheduling Weight" "1,2,3,4,5,6,7,8" bitfld.long 0x00 4.--6. " RW_W ,QMan read/write transaction scheduling Weight" "1,2,3,4,5,6,7,8" newline bitfld.long 0x00 0.--2. " BMAN_W ,BMan Fetch/Flush sequencer scheduling Weight" "1,2,3,4,5,6,7,8" rgroup.long 0xD04++0x3 line.long 0x00 "QMAN_SRCIDR,QMan Source ID Register" hexmask.long.byte 0x00 0.--7. 1. " SRCID ,QMan's Source ID" group.long 0xD08++0x3 line.long 0x00 "QMAN_ICIDR,QManIsolation Context ID Register" bitfld.long 0x00 22. " WC ,Write Allocate stash Coherency mode" "Non-coherent,Coherent" bitfld.long 0x00 21. " RA ,Read Allocate stash steering mode" "Side-band,No side-band" bitfld.long 0x00 20. " WA ,Write Allocate stash steering mode" "Side-band,No side-band" hexmask.long.word 0x00 0.--11. 1. " QMAN_ICID ,QMan's Isolation context identifier" group.long 0xD10++0x3 line.long 0x00 "CI_RLM_CFG,Initiator Read Latency Monitor Configuration" bitfld.long 0x00 28.--31. " RLM_TH_A ,Threshold which is used for comparison in the generation of the Initiator Read Latency A Performance Monitor signal" "6 cycles,8 cycles,12 cycles,16 cycles,24 cycles,32 cycles,48 cycles,64 cycles,96 cycles,128 cycles,192 cycles,256 cycles,384 cycles,512 cycles,768 cycles,1024 cycles" bitfld.long 0x00 24.--27. " RLM_TH_B ,Threshold which is used for comparison in the generation of the Initiator Read Latency B Performance Monitor signal" "6 cycles,8 cycles,12 cycles,16 cycles,24 cycles,32 cycles,48 cycles,64 cycles,96 cycles,128 cycles,192 cycles,256 cycles,384 cycles,512 cycles,768 cycles,1024 cycles" bitfld.long 0x00 20.--23. " RLM_TH_C ,Threshold which is used for comparison in the generation of the Initiator Read Latency C Performance Monitor signal" "6 cycles,8 cycles,12 cycles,16 cycles,24 cycles,32 cycles,48 cycles,64 cycles,96 cycles,128 cycles,192 cycles,256 cycles,384 cycles,512 cycles,768 cycles,1024 cycles" newline bitfld.long 0x00 16.--19. " RLM_TH_D ,Threshold which is used for comparison in the generation of the Initiator Read Latency D Performance Monitor signal" "6 cycles,8 cycles,12 cycles,16 cycles,24 cycles,32 cycles,48 cycles,64 cycles,96 cycles,128 cycles,192 cycles,256 cycles,384 cycles,512 cycles,768 cycles,1024 cycles" group.long 0xD14++0x03 line.long 0x00 "CI_RLM_AVG,CoreNet Initiator Read Latency Monitor Average" hexmask.long.word 0x00 8.--19. 1. " RLM_AVG_INT ,Integer portion of the measured average latency value" hexmask.long.byte 0x00 0.--7. 1. " RLM_AVG_FRACT ,Fractional portion of the measured average latency value" tree.end tree "QMan Interrupt and Error Registers" group.long 0xE00++0x3 line.long 0x00 "QMAN_ERR_ISR,QMan Error Interrupt Status Register" eventfld.long 0x00 29. " CIDE ,CoreNet Initiator Data Error" "No interrupt,Interrupt" eventfld.long 0x00 28. " CTDE ,CoreNet Target Data Error" "No interrupt,Interrupt" eventfld.long 0x00 27. " CITT ,CoreNet Invalid Target Transaction" "No interrupt,Interrupt" newline eventfld.long 0x00 26. " PLWI ,PFDR Low Watermark Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " MBEI ,Multi Bit ECC Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " SBEI ,Single Bit ECC Error Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " PEBI ,PFDR Enqueues Blocked Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " IFSI ,Invalid FQ Flow Control State Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " ICVI ,Invalid Command Verb Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " IDDI ,Invalid Dequeue Direct Connect Portal Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " IDFI ,Invalid Dequeue FQ Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " IDSI ,Invalid Dequeue Source Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " IDQI ,Invalid Dequeue Queue Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " IECE ,Invalid Enqueue Configuration Error" "No interrupt,Interrupt" eventfld.long 0x00 3. " IEOI ,Invalid Enqueue Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " IESI ,Invalid Enqueue State Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " IECI ,Invalid Enqueue Channel Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " IEQI ,Invalid Enqueue Queue Interrupt" "No interrupt,Interrupt" group.long 0xE04++0x3 line.long 0x00 "QMAN_ERR_IER,QMan Error Interrupt Enable Register" bitfld.long 0x00 29. " CIDE ,CoreNet Initiator Data Error" "No effect,Enable" bitfld.long 0x00 28. " CTDE ,CoreNet Target Data Error" "No effect,Enable" bitfld.long 0x00 27. " CITT ,CoreNet Invalid Target Transaction" "No effect,Enable" bitfld.long 0x00 26. " PLWI ,PFDR Low Watermark Interrupt" "No effect,Enable" newline bitfld.long 0x00 25. " MBEI ,Multi Bit ECC Error Interrupt" "No effect,Enable" bitfld.long 0x00 24. " SBEI ,Single Bit ECC Error Interrupt" "No effect,Enable" bitfld.long 0x00 23. " PEBI ,PFDR Enqueues Blocked Interrupt" "No effect,Enable" bitfld.long 0x00 17. " IFSI ,Invalid FQ Flow Control State Interrupt" "No effect,Enable" newline bitfld.long 0x00 16. " ICVI ,Invalid Command Verb Interrupt" "No effect,Enable" newline bitfld.long 0x00 11. " IDDI ,Invalid Dequeue Direct Connect Portal Interrupt" "No effect,Enable" bitfld.long 0x00 10. " IDFI ,Invalid Dequeue FQ Interrupt" "No effect,Enable" bitfld.long 0x00 9. " IDSI ,Invalid Dequeue Source Interrupt" "No effect,Enable" bitfld.long 0x00 8. " IDQI ,Invalid Dequeue Queue Interrupt" "No effect,Enable" newline bitfld.long 0x00 4. " IEOI ,Invalid Enqueue Configuration Error" "No effect,Enable" bitfld.long 0x00 3. " IEOI ,Invalid Enqueue Overflow Interrupt" "No effect,Enable" bitfld.long 0x00 2. " IESI ,Invalid Enqueue State Interrupt" "No effect,Enable" bitfld.long 0x00 1. " IECI ,Invalid Enqueue Channel Interrupt" "No effect,Enable" bitfld.long 0x00 0. " IEQI ,Invalid Enqueue Queue Interrupt" "No effect,Enable" group.long 0xE08++0x3 line.long 0x00 "QMAN_ERR_ISDR,QMan Error Interrupt Status Disable Register" bitfld.long 0x00 29. " CIDE ,CoreNet Initiator Data Error" "No effect,Disable" bitfld.long 0x00 28. " CTDE ,CoreNet Target Data Error" "No effect,Disable" bitfld.long 0x00 27. " CITT ,CoreNet Invalid Target Transaction" "No effect,Disable" bitfld.long 0x00 26. " PLWI ,PFDR Low Watermark Interrupt" "No effect,Disable" newline bitfld.long 0x00 25. " MBEI ,Multi Bit ECC Error Interrupt" "No effect,Disable" bitfld.long 0x00 24. " SBEI ,Single Bit ECC Error Interrupt" "No effect,Disable" bitfld.long 0x00 23. " PEBI ,PFDR Enqueues Blocked Interrupt" "No effect,Disable" bitfld.long 0x00 17. " IFSI ,Invalid FQ Flow Control State Interrupt" "No effect,Enable" newline bitfld.long 0x00 16. " ICVI ,Invalid Command Verb Interrupt" "No effect,Disable" newline bitfld.long 0x00 11. " IDDI ,Invalid Dequeue Direct Connect Portal Interrupt" "No effect,Disable" bitfld.long 0x00 10. " IDFI ,Invalid Dequeue FQ Interrupt" "No effect,Disable" bitfld.long 0x00 9. " IDSI ,Invalid Dequeue Source Interrupt" "No effect,Disable" bitfld.long 0x00 8. " IDQI ,Invalid Dequeue Queue Interrupt" "No effect,Disable" newline bitfld.long 0x00 4. " IECE ,Invalid Enqueue Configuration Error" "No effect,Disable" bitfld.long 0x00 3. " IEOI ,Invalid Enqueue Overflow Interrupt" "No effect,Disable" bitfld.long 0x00 2. " IESI ,Invalid Enqueue State Interrupt" "No effect,Disable" bitfld.long 0x00 1. " IECI ,Invalid Enqueue Channel Interrupt" "No effect,Disable" bitfld.long 0x00 0. " IEQI ,Invalid Enqueue Queue Interrupt" "No effect,Disable" group.long 0xE0C++0x3 line.long 0x00 "QMAN_ERR_IIR,QMan Error Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt Inhibit" "Not inhibited,Inhibited" group.long 0xE14++0x3 line.long 0x00 "QMAN_ERR_HER,QMan Error Halt Enable Register" bitfld.long 0x00 29. " CIDE ,CoreNet Initiator Data Error Halt Enable" "Disabled,Enabled" bitfld.long 0x00 28. " CTDE ,CoreNet Target Data Erro Halt Enabler" "Disabled,Enabled" bitfld.long 0x00 27. " CITT ,CoreNet Invalid Target Transaction Halt Enable" "Disabled,Enabled" bitfld.long 0x00 26. " PLWI ,PFDR Low Watermark Interrupt Halt Enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " MBEI ,Multi Bit ECC Error Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " SBEI ,Single Bit ECC Error Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " PEBI ,PFDR Enqueues Blocked Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " IFSI ,Invalid FQ Flow Control State Interrupt" "Disabled,Enabled" newline bitfld.long 0x00 16. " ICVI ,Invalid Command Verb Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " IDDI ,Invalid Dequeue Direct Connect Portal Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " IDFI ,Invalid Dequeue FQ Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 9. " IDSI ,Invalid Dequeue Source Interrupt Halt Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " IDQI ,Invalid Dequeue Queue Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " IECE ,Invalid Enqueue Configuration Error" "Disabled,Enabled" bitfld.long 0x00 3. " IEOI ,Invalid Enqueue Overflow Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " IESI ,Invalid Enqueue State Interrupt Halt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " IECI ,Invalid Enqueue Channel Interrupt Halt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " IEQI ,Invalid Enqueue Queue Interrupt Halt Enable" "Disabled,Enabled" tree.end tree "QMAN SC WQ Channel Dynamic Debug Configuration Registers" group.long (0x1E00)++0x3 line.long 0x00 "WQ_SC_DD_CFG_0,WQ Channel Dynamic Debug Configuration Register 0" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Software portal 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Software portal 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Software portal 1)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Software portal 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Software portal 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Software portal 2)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1E04)++0x3 line.long 0x00 "WQ_SC_DD_CFG_1,WQ Channel Dynamic Debug Configuration Register 1" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Software portal 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Software portal 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Software portal 3)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Software portal 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Software portal 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Software portal 4)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1E08)++0x3 line.long 0x00 "WQ_SC_DD_CFG_2,WQ Channel Dynamic Debug Configuration Register 2" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Software portal 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Software portal 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Software portal 5)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Software portal 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Software portal 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Software portal 6)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1E0C)++0x3 line.long 0x00 "WQ_SC_DD_CFG_3,WQ Channel Dynamic Debug Configuration Register 3" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Software portal 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Software portal 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Software portal 7)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Software portal 8)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Software portal 8)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Software portal 8)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" group.long (0x1E10)++0x3 line.long 0x00 "WQ_SC_DD_CFG_4,WQ Channel Dynamic Debug Configuration Register 4" bitfld.long 0x00 22.--24. " D_TP_CFG1[01] ,Trace point configuration for frame DD code point = 01 (Software portal 9)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 19.--21. " D_TP_CFG1[10] ,Trace point configuration for frame DD code point = 10 (Software portal 9)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 16.--18. " D_TP_CFG1[11] ,Trace point configuration for frame DD code point = 11(Software portal 9)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 6.--8. " D_TP_CFG0[01] ,Trace point configuration for frame DD code point = 01 (Software portal 10)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" newline bitfld.long 0x00 3.--5. " D_TP_CFG0[10] ,Trace point configuration for frame DD code point = 10 (Software portal 10)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" bitfld.long 0x00 0.--2. " D_TP_CFG0[11] ,Trace point configuration for frame DD code point = 11 (Software portal 10)" "Disabled/Halt disabled,Enabled (terse output)/Halt disabled,Disabled/Halt disabled,Enabled (verbose output)/Halt disabled,Disabled/Halt enabled,Enabled (terse output)/Halt enabled,Disabled/Halt enabled,Enabled (verbose output)/Halt enabled" tree.end endian.le width 0x0B tree.end tree "BMan (Buffer Manager)" base ad:0x01890000 width 24. endian.be tree "Software Portals" tree "Software Portal 0" group.quad (0x00+0x0)++0x07 "BMan Software Portal 0 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP0_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x0)++0x07 line.quad 0x00 "BCSP0_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x0)++0x07 line.quad 0x00 "BCSP0_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x0)++0x7 line.quad 0x00 "BCSP0_RCR0,BMan Software Portal 0 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x0)++0x7 line.quad 0x00 "BCSP0_RCR1,BMan Software Portal 0 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x0)++0x7 line.quad 0x00 "BCSP0_RCR2,BMan Software Portal 0 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x0)++0x7 line.quad 0x00 "BCSP0_RCR3,BMan Software Portal 0 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x0)++0x7 line.quad 0x00 "BCSP0_RCR4,BMan Software Portal 0 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x0)++0x7 line.quad 0x00 "BCSP0_RCR5,BMan Software Portal 0 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x0)++0x7 line.quad 0x00 "BCSP0_RCR6,BMan Software Portal 0 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x0)++0x7 line.quad 0x00 "BCSP0_RCR7,BMan Software Portal 0 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x0)++0x3 line.long 0x00 "BCSP0_RCR_PI_CENA,Software Portal 0 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x0)++0x3 line.long 0x00 "BCSP0_RCR_CI_CENA,Software Portal 0 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x0)++0x07 "BMan Software Portal 0 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP0_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x0)++0x7 line.quad 0x00 "BCSP0_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x0)++0x7 line.quad 0x00 "BCSP0_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x0)++0x7 line.quad 0x00 "BCSP0_RCR0,BMan Software Portal 0 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x0)++0x7 line.quad 0x00 "BCSP0_RCR1,BMan Software Portal 0 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x0)++0x7 line.quad 0x00 "BCSP0_RCR2,BMan Software Portal 0 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x0)++0x7 line.quad 0x00 "BCSP0_RCR3,BMan Software Portal 0 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x0)++0x7 line.quad 0x00 "BCSP0_RCR4,BMan Software Portal 0 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x0)++0x7 line.quad 0x00 "BCSP0_RCR5,BMan Software Portal 0 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x0)++0x7 line.quad 0x00 "BCSP0_RCR6,BMan Software Portal 0 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x0)++0x7 line.quad 0x00 "BCSP0_RCR7,BMan Software Portal 0 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x0)++0x3 line.long 0x00 "BCSP0_RCR_PI_CINH,Software Portal 0 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x0)++0x3 line.long 0x00 "BCSP0_RCR_CI_CINH,Software Portal 0 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x0)++0x03 line.long 0x00 "BCSP0_RCR_ITR,Software Portal 0 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x0)++0x03 line.long 0x00 "BCSP0_CFG,BMan Software Portal 0 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x0)++0x03 line.long 0x00 "BCSP0_SCN0,Software Portal 0 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x0)++0x03 line.long 0x00 "BCSP0_SCN1,Software Portal 0 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x0)++0x03 line.long 0x00 "BCSP0_ISR,BMan Software Portal 0 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x0)++0x03 line.long 0x00 "BCSP0_IER,BMan Software Portal 0 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x0)++0x03 line.long 0x00 "BCSP0_ISDR,BMan Software Portal 0 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x0)++0x03 line.long 0x00 "BCSP0_IIR,BMan Software Portal 0 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x0)++0x03 line.long 0x00 "BCSP0_IFR,BMan Software Portal 0 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 1" group.quad (0x00+0x10000)++0x07 "BMan Software Portal 1 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP1_CR,BMan Software Portal 1 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x10000)++0x07 line.quad 0x00 "BCSP1_RR0,BMan Software Portal 1 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x10000)++0x07 line.quad 0x00 "BCSP1_RR1,BMan Software Portal 1 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR0,BMan Software Portal 1 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR1,BMan Software Portal 1 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR2,BMan Software Portal 1 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR3,BMan Software Portal 1 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR4,BMan Software Portal 1 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR5,BMan Software Portal 1 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR6,BMan Software Portal 1 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR7,BMan Software Portal 1 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x10000)++0x3 line.long 0x00 "BCSP1_RCR_PI_CENA,Software Portal 1 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x10000)++0x3 line.long 0x00 "BCSP1_RCR_CI_CENA,Software Portal 1 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x10000)++0x07 "BMan Software Portal 1 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP1_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x10000)++0x7 line.quad 0x00 "BCSP1_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x10000)++0x7 line.quad 0x00 "BCSP1_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR0,BMan Software Portal 1 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR1,BMan Software Portal 1 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR2,BMan Software Portal 1 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR3,BMan Software Portal 1 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR4,BMan Software Portal 1 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR5,BMan Software Portal 1 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR6,BMan Software Portal 1 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x10000)++0x7 line.quad 0x00 "BCSP1_RCR7,BMan Software Portal 1 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x10000)++0x3 line.long 0x00 "BCSP1_RCR_PI_CINH,Software Portal 1 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x10000)++0x3 line.long 0x00 "BCSP1_RCR_CI_CINH,Software Portal 1 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x10000)++0x03 line.long 0x00 "BCSP1_RCR_ITR,Software Portal 1 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x10000)++0x03 line.long 0x00 "BCSP1_CFG,BMan Software Portal 1 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x10000)++0x03 line.long 0x00 "BCSP1_SCN0,Software Portal 1 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x10000)++0x03 line.long 0x00 "BCSP1_SCN1,Software Portal 1 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x10000)++0x03 line.long 0x00 "BCSP1_ISR,BMan Software Portal 1 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x10000)++0x03 line.long 0x00 "BCSP1_IER,BMan Software Portal 1 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x10000)++0x03 line.long 0x00 "BCSP1_ISDR,BMan Software Portal 1 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x10000)++0x03 line.long 0x00 "BCSP1_IIR,BMan Software Portal 1 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x10000)++0x03 line.long 0x00 "BCSP1_IFR,BMan Software Portal 1 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 2" group.quad (0x00+0x20000)++0x07 "BMan Software Portal 2 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP2_CR,BMan Software Portal 2 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x20000)++0x07 line.quad 0x00 "BCSP2_RR0,BMan Software Portal 2 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x20000)++0x07 line.quad 0x00 "BCSP2_RR1,BMan Software Portal 2 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR0,BMan Software Portal 2 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR1,BMan Software Portal 2 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR2,BMan Software Portal 2 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR3,BMan Software Portal 2 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR4,BMan Software Portal 2 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR5,BMan Software Portal 2 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR6,BMan Software Portal 2 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR7,BMan Software Portal 2 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x20000)++0x3 line.long 0x00 "BCSP2_RCR_PI_CENA,Software Portal 2 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x20000)++0x3 line.long 0x00 "BCSP2_RCR_CI_CENA,Software Portal 2 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x20000)++0x07 "BMan Software Portal 2 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP2_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x20000)++0x7 line.quad 0x00 "BCSP2_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x20000)++0x7 line.quad 0x00 "BCSP2_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR0,BMan Software Portal 2 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR1,BMan Software Portal 2 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR2,BMan Software Portal 2 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR3,BMan Software Portal 2 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR4,BMan Software Portal 2 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR5,BMan Software Portal 2 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR6,BMan Software Portal 2 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x20000)++0x7 line.quad 0x00 "BCSP2_RCR7,BMan Software Portal 2 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x20000)++0x3 line.long 0x00 "BCSP2_RCR_PI_CINH,Software Portal 2 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x20000)++0x3 line.long 0x00 "BCSP2_RCR_CI_CINH,Software Portal 2 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x20000)++0x03 line.long 0x00 "BCSP2_RCR_ITR,Software Portal 2 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x20000)++0x03 line.long 0x00 "BCSP2_CFG,BMan Software Portal 2 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x20000)++0x03 line.long 0x00 "BCSP2_SCN0,Software Portal 2 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x20000)++0x03 line.long 0x00 "BCSP2_SCN1,Software Portal 2 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x20000)++0x03 line.long 0x00 "BCSP2_ISR,BMan Software Portal 2 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x20000)++0x03 line.long 0x00 "BCSP2_IER,BMan Software Portal 2 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x20000)++0x03 line.long 0x00 "BCSP2_ISDR,BMan Software Portal 2 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x20000)++0x03 line.long 0x00 "BCSP2_IIR,BMan Software Portal 2 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x20000)++0x03 line.long 0x00 "BCSP2_IFR,BMan Software Portal 2 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 3" group.quad (0x00+0x30000)++0x07 "BMan Software Portal 3 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP3_CR,BMan Software Portal 3 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x30000)++0x07 line.quad 0x00 "BCSP3_RR0,BMan Software Portal 3 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x30000)++0x07 line.quad 0x00 "BCSP3_RR1,BMan Software Portal 3 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR0,BMan Software Portal 3 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR1,BMan Software Portal 3 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR2,BMan Software Portal 3 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR3,BMan Software Portal 3 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR4,BMan Software Portal 3 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR5,BMan Software Portal 3 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR6,BMan Software Portal 3 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR7,BMan Software Portal 3 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x30000)++0x3 line.long 0x00 "BCSP3_RCR_PI_CENA,Software Portal 3 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x30000)++0x3 line.long 0x00 "BCSP3_RCR_CI_CENA,Software Portal 3 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x30000)++0x07 "BMan Software Portal 3 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP3_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x30000)++0x7 line.quad 0x00 "BCSP3_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x30000)++0x7 line.quad 0x00 "BCSP3_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR0,BMan Software Portal 3 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR1,BMan Software Portal 3 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR2,BMan Software Portal 3 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR3,BMan Software Portal 3 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR4,BMan Software Portal 3 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR5,BMan Software Portal 3 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR6,BMan Software Portal 3 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x30000)++0x7 line.quad 0x00 "BCSP3_RCR7,BMan Software Portal 3 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x30000)++0x3 line.long 0x00 "BCSP3_RCR_PI_CINH,Software Portal 3 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x30000)++0x3 line.long 0x00 "BCSP3_RCR_CI_CINH,Software Portal 3 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x30000)++0x03 line.long 0x00 "BCSP3_RCR_ITR,Software Portal 3 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x30000)++0x03 line.long 0x00 "BCSP3_CFG,BMan Software Portal 3 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x30000)++0x03 line.long 0x00 "BCSP3_SCN0,Software Portal 3 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x30000)++0x03 line.long 0x00 "BCSP3_SCN1,Software Portal 3 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x30000)++0x03 line.long 0x00 "BCSP3_ISR,BMan Software Portal 3 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x30000)++0x03 line.long 0x00 "BCSP3_IER,BMan Software Portal 3 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x30000)++0x03 line.long 0x00 "BCSP3_ISDR,BMan Software Portal 3 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x30000)++0x03 line.long 0x00 "BCSP3_IIR,BMan Software Portal 3 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x30000)++0x03 line.long 0x00 "BCSP3_IFR,BMan Software Portal 3 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 4" group.quad (0x00+0x40000)++0x07 "BMan Software Portal 4 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP4_CR,BMan Software Portal 4 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x40000)++0x07 line.quad 0x00 "BCSP4_RR0,BMan Software Portal 4 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x40000)++0x07 line.quad 0x00 "BCSP4_RR1,BMan Software Portal 4 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR0,BMan Software Portal 4 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR1,BMan Software Portal 4 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR2,BMan Software Portal 4 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR3,BMan Software Portal 4 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR4,BMan Software Portal 4 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR5,BMan Software Portal 4 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR6,BMan Software Portal 4 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR7,BMan Software Portal 4 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x40000)++0x3 line.long 0x00 "BCSP4_RCR_PI_CENA,Software Portal 4 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x40000)++0x3 line.long 0x00 "BCSP4_RCR_CI_CENA,Software Portal 4 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x40000)++0x07 "BMan Software Portal 4 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP4_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x40000)++0x7 line.quad 0x00 "BCSP4_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x40000)++0x7 line.quad 0x00 "BCSP4_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR0,BMan Software Portal 4 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR1,BMan Software Portal 4 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR2,BMan Software Portal 4 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR3,BMan Software Portal 4 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR4,BMan Software Portal 4 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR5,BMan Software Portal 4 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR6,BMan Software Portal 4 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x40000)++0x7 line.quad 0x00 "BCSP4_RCR7,BMan Software Portal 4 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x40000)++0x3 line.long 0x00 "BCSP4_RCR_PI_CINH,Software Portal 4 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x40000)++0x3 line.long 0x00 "BCSP4_RCR_CI_CINH,Software Portal 4 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x40000)++0x03 line.long 0x00 "BCSP4_RCR_ITR,Software Portal 4 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x40000)++0x03 line.long 0x00 "BCSP4_CFG,BMan Software Portal 4 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x40000)++0x03 line.long 0x00 "BCSP4_SCN0,Software Portal 4 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x40000)++0x03 line.long 0x00 "BCSP4_SCN1,Software Portal 4 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x40000)++0x03 line.long 0x00 "BCSP4_ISR,BMan Software Portal 4 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x40000)++0x03 line.long 0x00 "BCSP4_IER,BMan Software Portal 4 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x40000)++0x03 line.long 0x00 "BCSP4_ISDR,BMan Software Portal 4 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x40000)++0x03 line.long 0x00 "BCSP4_IIR,BMan Software Portal 4 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x40000)++0x03 line.long 0x00 "BCSP4_IFR,BMan Software Portal 4 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 5" group.quad (0x00+0x50000)++0x07 "BMan Software Portal 5 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP5_CR,BMan Software Portal 5 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x50000)++0x07 line.quad 0x00 "BCSP5_RR0,BMan Software Portal 5 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x50000)++0x07 line.quad 0x00 "BCSP5_RR1,BMan Software Portal 5 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR0,BMan Software Portal 5 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR1,BMan Software Portal 5 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR2,BMan Software Portal 5 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR3,BMan Software Portal 5 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR4,BMan Software Portal 5 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR5,BMan Software Portal 5 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR6,BMan Software Portal 5 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR7,BMan Software Portal 5 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x50000)++0x3 line.long 0x00 "BCSP5_RCR_PI_CENA,Software Portal 5 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x50000)++0x3 line.long 0x00 "BCSP5_RCR_CI_CENA,Software Portal 5 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x50000)++0x07 "BMan Software Portal 5 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP5_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x50000)++0x7 line.quad 0x00 "BCSP5_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x50000)++0x7 line.quad 0x00 "BCSP5_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR0,BMan Software Portal 5 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR1,BMan Software Portal 5 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR2,BMan Software Portal 5 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR3,BMan Software Portal 5 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR4,BMan Software Portal 5 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR5,BMan Software Portal 5 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR6,BMan Software Portal 5 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x50000)++0x7 line.quad 0x00 "BCSP5_RCR7,BMan Software Portal 5 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x50000)++0x3 line.long 0x00 "BCSP5_RCR_PI_CINH,Software Portal 5 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x50000)++0x3 line.long 0x00 "BCSP5_RCR_CI_CINH,Software Portal 5 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x50000)++0x03 line.long 0x00 "BCSP5_RCR_ITR,Software Portal 5 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x50000)++0x03 line.long 0x00 "BCSP5_CFG,BMan Software Portal 5 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x50000)++0x03 line.long 0x00 "BCSP5_SCN0,Software Portal 5 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x50000)++0x03 line.long 0x00 "BCSP5_SCN1,Software Portal 5 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x50000)++0x03 line.long 0x00 "BCSP5_ISR,BMan Software Portal 5 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x50000)++0x03 line.long 0x00 "BCSP5_IER,BMan Software Portal 5 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x50000)++0x03 line.long 0x00 "BCSP5_ISDR,BMan Software Portal 5 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x50000)++0x03 line.long 0x00 "BCSP5_IIR,BMan Software Portal 5 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x50000)++0x03 line.long 0x00 "BCSP5_IFR,BMan Software Portal 5 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 6" group.quad (0x00+0x60000)++0x07 "BMan Software Portal 6 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP6_CR,BMan Software Portal 6 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x60000)++0x07 line.quad 0x00 "BCSP6_RR0,BMan Software Portal 6 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x60000)++0x07 line.quad 0x00 "BCSP6_RR1,BMan Software Portal 6 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR0,BMan Software Portal 6 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR1,BMan Software Portal 6 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR2,BMan Software Portal 6 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR3,BMan Software Portal 6 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR4,BMan Software Portal 6 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR5,BMan Software Portal 6 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR6,BMan Software Portal 6 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR7,BMan Software Portal 6 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x60000)++0x3 line.long 0x00 "BCSP6_RCR_PI_CENA,Software Portal 6 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x60000)++0x3 line.long 0x00 "BCSP6_RCR_CI_CENA,Software Portal 6 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x60000)++0x07 "BMan Software Portal 6 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP6_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x60000)++0x7 line.quad 0x00 "BCSP6_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x60000)++0x7 line.quad 0x00 "BCSP6_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR0,BMan Software Portal 6 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR1,BMan Software Portal 6 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR2,BMan Software Portal 6 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR3,BMan Software Portal 6 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR4,BMan Software Portal 6 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR5,BMan Software Portal 6 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR6,BMan Software Portal 6 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x60000)++0x7 line.quad 0x00 "BCSP6_RCR7,BMan Software Portal 6 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x60000)++0x3 line.long 0x00 "BCSP6_RCR_PI_CINH,Software Portal 6 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x60000)++0x3 line.long 0x00 "BCSP6_RCR_CI_CINH,Software Portal 6 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x60000)++0x03 line.long 0x00 "BCSP6_RCR_ITR,Software Portal 6 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x60000)++0x03 line.long 0x00 "BCSP6_CFG,BMan Software Portal 6 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x60000)++0x03 line.long 0x00 "BCSP6_SCN0,Software Portal 6 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x60000)++0x03 line.long 0x00 "BCSP6_SCN1,Software Portal 6 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x60000)++0x03 line.long 0x00 "BCSP6_ISR,BMan Software Portal 6 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x60000)++0x03 line.long 0x00 "BCSP6_IER,BMan Software Portal 6 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x60000)++0x03 line.long 0x00 "BCSP6_ISDR,BMan Software Portal 6 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x60000)++0x03 line.long 0x00 "BCSP6_IIR,BMan Software Portal 6 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x60000)++0x03 line.long 0x00 "BCSP6_IFR,BMan Software Portal 6 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 7" group.quad (0x00+0x70000)++0x07 "BMan Software Portal 7 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP7_CR,BMan Software Portal 7 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x70000)++0x07 line.quad 0x00 "BCSP7_RR0,BMan Software Portal 7 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x70000)++0x07 line.quad 0x00 "BCSP7_RR1,BMan Software Portal 7 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR0,BMan Software Portal 7 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR1,BMan Software Portal 7 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR2,BMan Software Portal 7 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR3,BMan Software Portal 7 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR4,BMan Software Portal 7 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR5,BMan Software Portal 7 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR6,BMan Software Portal 7 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR7,BMan Software Portal 7 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x70000)++0x3 line.long 0x00 "BCSP7_RCR_PI_CENA,Software Portal 7 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x70000)++0x3 line.long 0x00 "BCSP7_RCR_CI_CENA,Software Portal 7 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x70000)++0x07 "BMan Software Portal 7 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP7_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x70000)++0x7 line.quad 0x00 "BCSP7_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x70000)++0x7 line.quad 0x00 "BCSP7_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR0,BMan Software Portal 7 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR1,BMan Software Portal 7 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR2,BMan Software Portal 7 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR3,BMan Software Portal 7 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR4,BMan Software Portal 7 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR5,BMan Software Portal 7 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR6,BMan Software Portal 7 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x70000)++0x7 line.quad 0x00 "BCSP7_RCR7,BMan Software Portal 7 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x70000)++0x3 line.long 0x00 "BCSP7_RCR_PI_CINH,Software Portal 7 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x70000)++0x3 line.long 0x00 "BCSP7_RCR_CI_CINH,Software Portal 7 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x70000)++0x03 line.long 0x00 "BCSP7_RCR_ITR,Software Portal 7 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x70000)++0x03 line.long 0x00 "BCSP7_CFG,BMan Software Portal 7 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x70000)++0x03 line.long 0x00 "BCSP7_SCN0,Software Portal 7 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x70000)++0x03 line.long 0x00 "BCSP7_SCN1,Software Portal 7 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x70000)++0x03 line.long 0x00 "BCSP7_ISR,BMan Software Portal 7 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x70000)++0x03 line.long 0x00 "BCSP7_IER,BMan Software Portal 7 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x70000)++0x03 line.long 0x00 "BCSP7_ISDR,BMan Software Portal 7 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x70000)++0x03 line.long 0x00 "BCSP7_IIR,BMan Software Portal 7 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x70000)++0x03 line.long 0x00 "BCSP7_IFR,BMan Software Portal 7 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 8" group.quad (0x00+0x80000)++0x07 "BMan Software Portal 8 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP8_CR,BMan Software Portal 8 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x80000)++0x07 line.quad 0x00 "BCSP8_RR0,BMan Software Portal 8 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x80000)++0x07 line.quad 0x00 "BCSP8_RR1,BMan Software Portal 8 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR0,BMan Software Portal 8 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR1,BMan Software Portal 8 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR2,BMan Software Portal 8 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR3,BMan Software Portal 8 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR4,BMan Software Portal 8 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR5,BMan Software Portal 8 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR6,BMan Software Portal 8 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR7,BMan Software Portal 8 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x80000)++0x3 line.long 0x00 "BCSP8_RCR_PI_CENA,Software Portal 8 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x80000)++0x3 line.long 0x00 "BCSP8_RCR_CI_CENA,Software Portal 8 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x80000)++0x07 "BMan Software Portal 8 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP8_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x80000)++0x7 line.quad 0x00 "BCSP8_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x80000)++0x7 line.quad 0x00 "BCSP8_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR0,BMan Software Portal 8 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR1,BMan Software Portal 8 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR2,BMan Software Portal 8 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR3,BMan Software Portal 8 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR4,BMan Software Portal 8 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR5,BMan Software Portal 8 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR6,BMan Software Portal 8 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x80000)++0x7 line.quad 0x00 "BCSP8_RCR7,BMan Software Portal 8 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x80000)++0x3 line.long 0x00 "BCSP8_RCR_PI_CINH,Software Portal 8 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x80000)++0x3 line.long 0x00 "BCSP8_RCR_CI_CINH,Software Portal 8 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x80000)++0x03 line.long 0x00 "BCSP8_RCR_ITR,Software Portal 8 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x80000)++0x03 line.long 0x00 "BCSP8_CFG,BMan Software Portal 8 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x80000)++0x03 line.long 0x00 "BCSP8_SCN0,Software Portal 8 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x80000)++0x03 line.long 0x00 "BCSP8_SCN1,Software Portal 8 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x80000)++0x03 line.long 0x00 "BCSP8_ISR,BMan Software Portal 8 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x80000)++0x03 line.long 0x00 "BCSP8_IER,BMan Software Portal 8 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x80000)++0x03 line.long 0x00 "BCSP8_ISDR,BMan Software Portal 8 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x80000)++0x03 line.long 0x00 "BCSP8_IIR,BMan Software Portal 8 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x80000)++0x03 line.long 0x00 "BCSP8_IFR,BMan Software Portal 8 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree "Software Portal 9" group.quad (0x00+0x90000)++0x07 "BMan Software Portal 9 Command/Response and Release Command Ring Registers, Cache-Enabled Area" line.quad 0x00 "BCSP9_CR,BMan Software Portal 9 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x100+0x90000)++0x07 line.quad 0x00 "BCSP9_RR0,BMan Software Portal 9 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x140+0x90000)++0x07 line.quad 0x00 "BCSP9_RR1,BMan Software Portal 9 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x1000+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR0,BMan Software Portal 9 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1040+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR1,BMan Software Portal 9 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1080+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR2,BMan Software Portal 9 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x10C0+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR3,BMan Software Portal 9 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1100+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR4,BMan Software Portal 9 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1140+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR5,BMan Software Portal 9 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x1180+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR6,BMan Software Portal 9 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x11C0+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR7,BMan Software Portal 9 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x90000)++0x3 line.long 0x00 "BCSP9_RCR_PI_CENA,Software Portal 9 Release Command Ring Producer Index Cache-Enabled Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x90000)++0x3 line.long 0x00 "BCSP9_RCR_CI_CENA,Software Portal 9 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.quad (0x4000000+0x90000)++0x07 "BMan Software Portal 9 RCR Index, Configuration and Interrupt Control Registers, Cache-Inhibited Area" line.quad 0x00 "BCSP9_CR,BMan Software Portal 0 Command Register" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" bitfld.quad 0x00 62. " CD ,Command data" "0,1" rgroup.quad (0x4000100+0x90000)++0x7 line.quad 0x00 "BCSP9_RR0,BMan Software Portal 0 Response Register 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" rgroup.quad (0x4000140+0x90000)++0x7 line.quad 0x00 "BCSP9_RR1,BMan Software Portal 0 Response Register 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Response verb" hexmask.quad 0x00 0.--62. 1. " RESPONSE_DATA ,Response data" group.quad (0x4001000+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR0,BMan Software Portal 9 RCR Entry 0" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001040+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR1,BMan Software Portal 9 RCR Entry 1" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001080+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR2,BMan Software Portal 9 RCR Entry 2" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40010C0+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR3,BMan Software Portal 9 RCR Entry 3" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001100+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR4,BMan Software Portal 9 RCR Entry 4" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001140+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR5,BMan Software Portal 9 RCR Entry 5" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x4001180+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR6,BMan Software Portal 9 RCR Entry 6" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.quad (0x40011C0+0x90000)++0x7 line.quad 0x00 "BCSP9_RCR7,BMan Software Portal 9 RCR Entry 7" bitfld.quad 0x00 63. " VERB ,Verb byte" "Valid bit,Release command verb" hexmask.quad 0x00 0.--62. 1. " COMMAND_DATA ,Command data" group.long (0x3000+0x90000)++0x3 line.long 0x00 "BCSP9_RCR_PI_CINH,Software Portal 9 Release Command Ring Producer Index Cache-Inhibited Register" rbitfld.long 0x00 3. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 0.--2. " PI ,Producer index" "0,1,2,3,4,5,6,7" rgroup.long (0x3100+0x90000)++0x3 line.long 0x00 "BCSP9_RCR_CI_CINH,Software Portal 9 Release Command Ring Consumer Index Cache-Enabled Register" bitfld.long 0x00 15. " VP ,Valid bit polarity at producer index" "0,1" bitfld.long 0x00 3. " VC ,Valid bit polarity at consumer index" "0,1" bitfld.long 0x00 0.--2. " CI ,Consumer index" "0,1,2,3,4,5,6,7" group.long (0x4003200+0x90000)++0x03 line.long 0x00 "BCSP9_RCR_ITR,Software Portal 9 RCR Interrupt Threshold Register" bitfld.long 0x00 0.--2. " RCR_IT ,RCR interrupt threshold" "0,1,2,3,4,5,6,7" group.long (0x4003300+0x90000)++0x03 line.long 0x00 "BCSP9_CFG,BMan Software Portal 9 Configuration Register" bitfld.long 0x00 4. " WN ,Writes non-cacheable" "Cache inhibited,Cache enabled" bitfld.long 0x00 0.--1. " RPM ,RCR production notification mode" "Cache inhibited,Cache enabled,Valid bit mode,Valid bit mode" group.long (0x4003400+0x90000)++0x03 line.long 0x00 "BCSP9_SCN0,Software Portal 9 Depletion State Change Notification Interrupt Enable Register Pools 0 to 31" group.long (0x4003440+0x90000)++0x03 line.long 0x00 "BCSP9_SCN1,Software Portal 9 Depletion State Change Notification Interrupt Enable Register Pools 32 to 63" group.long (0x4003E00+0x90000)++0x03 line.long 0x00 "BCSP9_ISR,BMan Software Portal 9 Interrupt Status Register" eventfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" eventfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" eventfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E40+0x90000)++0x03 line.long 0x00 "BCSP9_IER,BMan Software Portal 9 Interrupt Enable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003E80+0x90000)++0x03 line.long 0x00 "BCSP9_ISDR,BMan Software Portal 9 Interrupt Status Disable Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" group.long (0x4003EC0+0x90000)++0x03 line.long 0x00 "BCSP9_IIR,BMan Software Portal 9 Interrupt Inhibit Register" bitfld.long 0x00 0. " I ,Interrupt inhibit" "0,1" wgroup.long (0x4003F00+0x90000)++0x03 line.long 0x00 "BCSP9_IFR,BMan Software Portal 9 Interrupt Force Register" bitfld.long 0x00 2. " RCDI ,Release command dispatched interrupt" "0,1" bitfld.long 0x00 1. " RCRI ,Release command ring threshold interrupt" "0,1" bitfld.long 0x00 0. " BSCN ,Buffer pool state change notifications (BSCN) when the depletion state of a buffer pool changes" "0,1" tree.end tree.end base ad:0x0508000000 tree "Pool 0-63" group.long (0x00+0x0)++0x03 "Pool 0" line.long 0x00 "BMAN_POOL0_SWDET,BMan S/W Portal Depletion Entry Threshold Register 0" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x0)++0x03 line.long 0x00 "BMAN_POOL0_HWDET,BMan H/W Portal Depletion Entry Threshold Register 0" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x0)++0x03 line.long 0x00 "BMAN_POOL0_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 0" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x0)++0x03 line.long 0x00 "BMAN_POOL0_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 0" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x0)++0x03 hide.long 0x0 "BMAN_POOL0_SDCNT,BMan S/W Depletion Count Register 0" in hgroup.long (0x500+0x0)++0x03 hide.long 0x00 "BMAN_POOL0_HDCNT,BMan H/W Depletion Count Register 0" in rgroup.long (0x600+0x0)++0x03 line.long 0x00 "BMAN_POOL0_CONTENT,BMan Pool Content Register 0" rgroup.long (0x700+0x0)++0x03 line.long 0x00 "BMAN_POOL0_HDPTR,BMan Free List Head Pointer Register 0" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x4)++0x03 "Pool 1" line.long 0x00 "BMAN_POOL1_SWDET,BMan S/W Portal Depletion Entry Threshold Register 1" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x4)++0x03 line.long 0x00 "BMAN_POOL1_HWDET,BMan H/W Portal Depletion Entry Threshold Register 1" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x4)++0x03 line.long 0x00 "BMAN_POOL1_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 1" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x4)++0x03 line.long 0x00 "BMAN_POOL1_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 1" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x4)++0x03 hide.long 0x4 "BMAN_POOL1_SDCNT,BMan S/W Depletion Count Register 1" in hgroup.long (0x500+0x4)++0x03 hide.long 0x00 "BMAN_POOL1_HDCNT,BMan H/W Depletion Count Register 1" in rgroup.long (0x600+0x4)++0x03 line.long 0x00 "BMAN_POOL1_CONTENT,BMan Pool Content Register 1" rgroup.long (0x700+0x4)++0x03 line.long 0x00 "BMAN_POOL1_HDPTR,BMan Free List Head Pointer Register 1" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x8)++0x03 "Pool 2" line.long 0x00 "BMAN_POOL2_SWDET,BMan S/W Portal Depletion Entry Threshold Register 2" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x8)++0x03 line.long 0x00 "BMAN_POOL2_HWDET,BMan H/W Portal Depletion Entry Threshold Register 2" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x8)++0x03 line.long 0x00 "BMAN_POOL2_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 2" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x8)++0x03 line.long 0x00 "BMAN_POOL2_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 2" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x8)++0x03 hide.long 0x8 "BMAN_POOL2_SDCNT,BMan S/W Depletion Count Register 2" in hgroup.long (0x500+0x8)++0x03 hide.long 0x00 "BMAN_POOL2_HDCNT,BMan H/W Depletion Count Register 2" in rgroup.long (0x600+0x8)++0x03 line.long 0x00 "BMAN_POOL2_CONTENT,BMan Pool Content Register 2" rgroup.long (0x700+0x8)++0x03 line.long 0x00 "BMAN_POOL2_HDPTR,BMan Free List Head Pointer Register 2" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xC)++0x03 "Pool 3" line.long 0x00 "BMAN_POOL3_SWDET,BMan S/W Portal Depletion Entry Threshold Register 3" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xC)++0x03 line.long 0x00 "BMAN_POOL3_HWDET,BMan H/W Portal Depletion Entry Threshold Register 3" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xC)++0x03 line.long 0x00 "BMAN_POOL3_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 3" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xC)++0x03 line.long 0x00 "BMAN_POOL3_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 3" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xC)++0x03 hide.long 0xC "BMAN_POOL3_SDCNT,BMan S/W Depletion Count Register 3" in hgroup.long (0x500+0xC)++0x03 hide.long 0x00 "BMAN_POOL3_HDCNT,BMan H/W Depletion Count Register 3" in rgroup.long (0x600+0xC)++0x03 line.long 0x00 "BMAN_POOL3_CONTENT,BMan Pool Content Register 3" rgroup.long (0x700+0xC)++0x03 line.long 0x00 "BMAN_POOL3_HDPTR,BMan Free List Head Pointer Register 3" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x10)++0x03 "Pool 4" line.long 0x00 "BMAN_POOL4_SWDET,BMan S/W Portal Depletion Entry Threshold Register 4" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x10)++0x03 line.long 0x00 "BMAN_POOL4_HWDET,BMan H/W Portal Depletion Entry Threshold Register 4" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x10)++0x03 line.long 0x00 "BMAN_POOL4_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 4" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x10)++0x03 line.long 0x00 "BMAN_POOL4_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 4" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x10)++0x03 hide.long 0x10 "BMAN_POOL4_SDCNT,BMan S/W Depletion Count Register 4" in hgroup.long (0x500+0x10)++0x03 hide.long 0x00 "BMAN_POOL4_HDCNT,BMan H/W Depletion Count Register 4" in rgroup.long (0x600+0x10)++0x03 line.long 0x00 "BMAN_POOL4_CONTENT,BMan Pool Content Register 4" rgroup.long (0x700+0x10)++0x03 line.long 0x00 "BMAN_POOL4_HDPTR,BMan Free List Head Pointer Register 4" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x14)++0x03 "Pool 5" line.long 0x00 "BMAN_POOL5_SWDET,BMan S/W Portal Depletion Entry Threshold Register 5" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x14)++0x03 line.long 0x00 "BMAN_POOL5_HWDET,BMan H/W Portal Depletion Entry Threshold Register 5" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x14)++0x03 line.long 0x00 "BMAN_POOL5_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 5" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x14)++0x03 line.long 0x00 "BMAN_POOL5_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 5" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x14)++0x03 hide.long 0x14 "BMAN_POOL5_SDCNT,BMan S/W Depletion Count Register 5" in hgroup.long (0x500+0x14)++0x03 hide.long 0x00 "BMAN_POOL5_HDCNT,BMan H/W Depletion Count Register 5" in rgroup.long (0x600+0x14)++0x03 line.long 0x00 "BMAN_POOL5_CONTENT,BMan Pool Content Register 5" rgroup.long (0x700+0x14)++0x03 line.long 0x00 "BMAN_POOL5_HDPTR,BMan Free List Head Pointer Register 5" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x18)++0x03 "Pool 6" line.long 0x00 "BMAN_POOL6_SWDET,BMan S/W Portal Depletion Entry Threshold Register 6" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x18)++0x03 line.long 0x00 "BMAN_POOL6_HWDET,BMan H/W Portal Depletion Entry Threshold Register 6" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x18)++0x03 line.long 0x00 "BMAN_POOL6_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 6" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x18)++0x03 line.long 0x00 "BMAN_POOL6_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 6" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x18)++0x03 hide.long 0x18 "BMAN_POOL6_SDCNT,BMan S/W Depletion Count Register 6" in hgroup.long (0x500+0x18)++0x03 hide.long 0x00 "BMAN_POOL6_HDCNT,BMan H/W Depletion Count Register 6" in rgroup.long (0x600+0x18)++0x03 line.long 0x00 "BMAN_POOL6_CONTENT,BMan Pool Content Register 6" rgroup.long (0x700+0x18)++0x03 line.long 0x00 "BMAN_POOL6_HDPTR,BMan Free List Head Pointer Register 6" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x1C)++0x03 "Pool 7" line.long 0x00 "BMAN_POOL7_SWDET,BMan S/W Portal Depletion Entry Threshold Register 7" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x1C)++0x03 line.long 0x00 "BMAN_POOL7_HWDET,BMan H/W Portal Depletion Entry Threshold Register 7" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x1C)++0x03 line.long 0x00 "BMAN_POOL7_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 7" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x1C)++0x03 line.long 0x00 "BMAN_POOL7_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 7" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x1C)++0x03 hide.long 0x1C "BMAN_POOL7_SDCNT,BMan S/W Depletion Count Register 7" in hgroup.long (0x500+0x1C)++0x03 hide.long 0x00 "BMAN_POOL7_HDCNT,BMan H/W Depletion Count Register 7" in rgroup.long (0x600+0x1C)++0x03 line.long 0x00 "BMAN_POOL7_CONTENT,BMan Pool Content Register 7" rgroup.long (0x700+0x1C)++0x03 line.long 0x00 "BMAN_POOL7_HDPTR,BMan Free List Head Pointer Register 7" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x20)++0x03 "Pool 8" line.long 0x00 "BMAN_POOL8_SWDET,BMan S/W Portal Depletion Entry Threshold Register 8" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x20)++0x03 line.long 0x00 "BMAN_POOL8_HWDET,BMan H/W Portal Depletion Entry Threshold Register 8" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x20)++0x03 line.long 0x00 "BMAN_POOL8_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 8" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x20)++0x03 line.long 0x00 "BMAN_POOL8_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 8" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x20)++0x03 hide.long 0x20 "BMAN_POOL8_SDCNT,BMan S/W Depletion Count Register 8" in hgroup.long (0x500+0x20)++0x03 hide.long 0x00 "BMAN_POOL8_HDCNT,BMan H/W Depletion Count Register 8" in rgroup.long (0x600+0x20)++0x03 line.long 0x00 "BMAN_POOL8_CONTENT,BMan Pool Content Register 8" rgroup.long (0x700+0x20)++0x03 line.long 0x00 "BMAN_POOL8_HDPTR,BMan Free List Head Pointer Register 8" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x24)++0x03 "Pool 9" line.long 0x00 "BMAN_POOL9_SWDET,BMan S/W Portal Depletion Entry Threshold Register 9" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x24)++0x03 line.long 0x00 "BMAN_POOL9_HWDET,BMan H/W Portal Depletion Entry Threshold Register 9" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x24)++0x03 line.long 0x00 "BMAN_POOL9_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 9" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x24)++0x03 line.long 0x00 "BMAN_POOL9_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 9" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x24)++0x03 hide.long 0x24 "BMAN_POOL9_SDCNT,BMan S/W Depletion Count Register 9" in hgroup.long (0x500+0x24)++0x03 hide.long 0x00 "BMAN_POOL9_HDCNT,BMan H/W Depletion Count Register 9" in rgroup.long (0x600+0x24)++0x03 line.long 0x00 "BMAN_POOL9_CONTENT,BMan Pool Content Register 9" rgroup.long (0x700+0x24)++0x03 line.long 0x00 "BMAN_POOL9_HDPTR,BMan Free List Head Pointer Register 9" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x28)++0x03 "Pool 10" line.long 0x00 "BMAN_POOL10_SWDET,BMan S/W Portal Depletion Entry Threshold Register 10" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x28)++0x03 line.long 0x00 "BMAN_POOL10_HWDET,BMan H/W Portal Depletion Entry Threshold Register 10" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x28)++0x03 line.long 0x00 "BMAN_POOL10_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 10" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x28)++0x03 line.long 0x00 "BMAN_POOL10_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 10" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x28)++0x03 hide.long 0x28 "BMAN_POOL10_SDCNT,BMan S/W Depletion Count Register 10" in hgroup.long (0x500+0x28)++0x03 hide.long 0x00 "BMAN_POOL10_HDCNT,BMan H/W Depletion Count Register 10" in rgroup.long (0x600+0x28)++0x03 line.long 0x00 "BMAN_POOL10_CONTENT,BMan Pool Content Register 10" rgroup.long (0x700+0x28)++0x03 line.long 0x00 "BMAN_POOL10_HDPTR,BMan Free List Head Pointer Register 10" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x2C)++0x03 "Pool 11" line.long 0x00 "BMAN_POOL11_SWDET,BMan S/W Portal Depletion Entry Threshold Register 11" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x2C)++0x03 line.long 0x00 "BMAN_POOL11_HWDET,BMan H/W Portal Depletion Entry Threshold Register 11" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x2C)++0x03 line.long 0x00 "BMAN_POOL11_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 11" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x2C)++0x03 line.long 0x00 "BMAN_POOL11_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 11" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x2C)++0x03 hide.long 0x2C "BMAN_POOL11_SDCNT,BMan S/W Depletion Count Register 11" in hgroup.long (0x500+0x2C)++0x03 hide.long 0x00 "BMAN_POOL11_HDCNT,BMan H/W Depletion Count Register 11" in rgroup.long (0x600+0x2C)++0x03 line.long 0x00 "BMAN_POOL11_CONTENT,BMan Pool Content Register 11" rgroup.long (0x700+0x2C)++0x03 line.long 0x00 "BMAN_POOL11_HDPTR,BMan Free List Head Pointer Register 11" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x30)++0x03 "Pool 12" line.long 0x00 "BMAN_POOL12_SWDET,BMan S/W Portal Depletion Entry Threshold Register 12" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x30)++0x03 line.long 0x00 "BMAN_POOL12_HWDET,BMan H/W Portal Depletion Entry Threshold Register 12" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x30)++0x03 line.long 0x00 "BMAN_POOL12_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 12" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x30)++0x03 line.long 0x00 "BMAN_POOL12_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 12" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x30)++0x03 hide.long 0x30 "BMAN_POOL12_SDCNT,BMan S/W Depletion Count Register 12" in hgroup.long (0x500+0x30)++0x03 hide.long 0x00 "BMAN_POOL12_HDCNT,BMan H/W Depletion Count Register 12" in rgroup.long (0x600+0x30)++0x03 line.long 0x00 "BMAN_POOL12_CONTENT,BMan Pool Content Register 12" rgroup.long (0x700+0x30)++0x03 line.long 0x00 "BMAN_POOL12_HDPTR,BMan Free List Head Pointer Register 12" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x34)++0x03 "Pool 13" line.long 0x00 "BMAN_POOL13_SWDET,BMan S/W Portal Depletion Entry Threshold Register 13" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x34)++0x03 line.long 0x00 "BMAN_POOL13_HWDET,BMan H/W Portal Depletion Entry Threshold Register 13" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x34)++0x03 line.long 0x00 "BMAN_POOL13_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 13" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x34)++0x03 line.long 0x00 "BMAN_POOL13_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 13" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x34)++0x03 hide.long 0x34 "BMAN_POOL13_SDCNT,BMan S/W Depletion Count Register 13" in hgroup.long (0x500+0x34)++0x03 hide.long 0x00 "BMAN_POOL13_HDCNT,BMan H/W Depletion Count Register 13" in rgroup.long (0x600+0x34)++0x03 line.long 0x00 "BMAN_POOL13_CONTENT,BMan Pool Content Register 13" rgroup.long (0x700+0x34)++0x03 line.long 0x00 "BMAN_POOL13_HDPTR,BMan Free List Head Pointer Register 13" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x38)++0x03 "Pool 14" line.long 0x00 "BMAN_POOL14_SWDET,BMan S/W Portal Depletion Entry Threshold Register 14" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x38)++0x03 line.long 0x00 "BMAN_POOL14_HWDET,BMan H/W Portal Depletion Entry Threshold Register 14" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x38)++0x03 line.long 0x00 "BMAN_POOL14_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 14" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x38)++0x03 line.long 0x00 "BMAN_POOL14_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 14" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x38)++0x03 hide.long 0x38 "BMAN_POOL14_SDCNT,BMan S/W Depletion Count Register 14" in hgroup.long (0x500+0x38)++0x03 hide.long 0x00 "BMAN_POOL14_HDCNT,BMan H/W Depletion Count Register 14" in rgroup.long (0x600+0x38)++0x03 line.long 0x00 "BMAN_POOL14_CONTENT,BMan Pool Content Register 14" rgroup.long (0x700+0x38)++0x03 line.long 0x00 "BMAN_POOL14_HDPTR,BMan Free List Head Pointer Register 14" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x3C)++0x03 "Pool 15" line.long 0x00 "BMAN_POOL15_SWDET,BMan S/W Portal Depletion Entry Threshold Register 15" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x3C)++0x03 line.long 0x00 "BMAN_POOL15_HWDET,BMan H/W Portal Depletion Entry Threshold Register 15" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x3C)++0x03 line.long 0x00 "BMAN_POOL15_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 15" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x3C)++0x03 line.long 0x00 "BMAN_POOL15_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 15" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x3C)++0x03 hide.long 0x3C "BMAN_POOL15_SDCNT,BMan S/W Depletion Count Register 15" in hgroup.long (0x500+0x3C)++0x03 hide.long 0x00 "BMAN_POOL15_HDCNT,BMan H/W Depletion Count Register 15" in rgroup.long (0x600+0x3C)++0x03 line.long 0x00 "BMAN_POOL15_CONTENT,BMan Pool Content Register 15" rgroup.long (0x700+0x3C)++0x03 line.long 0x00 "BMAN_POOL15_HDPTR,BMan Free List Head Pointer Register 15" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x40)++0x03 "Pool 16" line.long 0x00 "BMAN_POOL16_SWDET,BMan S/W Portal Depletion Entry Threshold Register 16" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x40)++0x03 line.long 0x00 "BMAN_POOL16_HWDET,BMan H/W Portal Depletion Entry Threshold Register 16" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x40)++0x03 line.long 0x00 "BMAN_POOL16_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 16" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x40)++0x03 line.long 0x00 "BMAN_POOL16_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 16" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x40)++0x03 hide.long 0x40 "BMAN_POOL16_SDCNT,BMan S/W Depletion Count Register 16" in hgroup.long (0x500+0x40)++0x03 hide.long 0x00 "BMAN_POOL16_HDCNT,BMan H/W Depletion Count Register 16" in rgroup.long (0x600+0x40)++0x03 line.long 0x00 "BMAN_POOL16_CONTENT,BMan Pool Content Register 16" rgroup.long (0x700+0x40)++0x03 line.long 0x00 "BMAN_POOL16_HDPTR,BMan Free List Head Pointer Register 16" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x44)++0x03 "Pool 17" line.long 0x00 "BMAN_POOL17_SWDET,BMan S/W Portal Depletion Entry Threshold Register 17" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x44)++0x03 line.long 0x00 "BMAN_POOL17_HWDET,BMan H/W Portal Depletion Entry Threshold Register 17" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x44)++0x03 line.long 0x00 "BMAN_POOL17_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 17" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x44)++0x03 line.long 0x00 "BMAN_POOL17_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 17" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x44)++0x03 hide.long 0x44 "BMAN_POOL17_SDCNT,BMan S/W Depletion Count Register 17" in hgroup.long (0x500+0x44)++0x03 hide.long 0x00 "BMAN_POOL17_HDCNT,BMan H/W Depletion Count Register 17" in rgroup.long (0x600+0x44)++0x03 line.long 0x00 "BMAN_POOL17_CONTENT,BMan Pool Content Register 17" rgroup.long (0x700+0x44)++0x03 line.long 0x00 "BMAN_POOL17_HDPTR,BMan Free List Head Pointer Register 17" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x48)++0x03 "Pool 18" line.long 0x00 "BMAN_POOL18_SWDET,BMan S/W Portal Depletion Entry Threshold Register 18" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x48)++0x03 line.long 0x00 "BMAN_POOL18_HWDET,BMan H/W Portal Depletion Entry Threshold Register 18" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x48)++0x03 line.long 0x00 "BMAN_POOL18_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 18" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x48)++0x03 line.long 0x00 "BMAN_POOL18_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 18" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x48)++0x03 hide.long 0x48 "BMAN_POOL18_SDCNT,BMan S/W Depletion Count Register 18" in hgroup.long (0x500+0x48)++0x03 hide.long 0x00 "BMAN_POOL18_HDCNT,BMan H/W Depletion Count Register 18" in rgroup.long (0x600+0x48)++0x03 line.long 0x00 "BMAN_POOL18_CONTENT,BMan Pool Content Register 18" rgroup.long (0x700+0x48)++0x03 line.long 0x00 "BMAN_POOL18_HDPTR,BMan Free List Head Pointer Register 18" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x4C)++0x03 "Pool 19" line.long 0x00 "BMAN_POOL19_SWDET,BMan S/W Portal Depletion Entry Threshold Register 19" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x4C)++0x03 line.long 0x00 "BMAN_POOL19_HWDET,BMan H/W Portal Depletion Entry Threshold Register 19" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x4C)++0x03 line.long 0x00 "BMAN_POOL19_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 19" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x4C)++0x03 line.long 0x00 "BMAN_POOL19_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 19" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x4C)++0x03 hide.long 0x4C "BMAN_POOL19_SDCNT,BMan S/W Depletion Count Register 19" in hgroup.long (0x500+0x4C)++0x03 hide.long 0x00 "BMAN_POOL19_HDCNT,BMan H/W Depletion Count Register 19" in rgroup.long (0x600+0x4C)++0x03 line.long 0x00 "BMAN_POOL19_CONTENT,BMan Pool Content Register 19" rgroup.long (0x700+0x4C)++0x03 line.long 0x00 "BMAN_POOL19_HDPTR,BMan Free List Head Pointer Register 19" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x50)++0x03 "Pool 20" line.long 0x00 "BMAN_POOL20_SWDET,BMan S/W Portal Depletion Entry Threshold Register 20" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x50)++0x03 line.long 0x00 "BMAN_POOL20_HWDET,BMan H/W Portal Depletion Entry Threshold Register 20" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x50)++0x03 line.long 0x00 "BMAN_POOL20_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 20" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x50)++0x03 line.long 0x00 "BMAN_POOL20_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 20" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x50)++0x03 hide.long 0x50 "BMAN_POOL20_SDCNT,BMan S/W Depletion Count Register 20" in hgroup.long (0x500+0x50)++0x03 hide.long 0x00 "BMAN_POOL20_HDCNT,BMan H/W Depletion Count Register 20" in rgroup.long (0x600+0x50)++0x03 line.long 0x00 "BMAN_POOL20_CONTENT,BMan Pool Content Register 20" rgroup.long (0x700+0x50)++0x03 line.long 0x00 "BMAN_POOL20_HDPTR,BMan Free List Head Pointer Register 20" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x54)++0x03 "Pool 21" line.long 0x00 "BMAN_POOL21_SWDET,BMan S/W Portal Depletion Entry Threshold Register 21" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x54)++0x03 line.long 0x00 "BMAN_POOL21_HWDET,BMan H/W Portal Depletion Entry Threshold Register 21" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x54)++0x03 line.long 0x00 "BMAN_POOL21_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 21" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x54)++0x03 line.long 0x00 "BMAN_POOL21_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 21" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x54)++0x03 hide.long 0x54 "BMAN_POOL21_SDCNT,BMan S/W Depletion Count Register 21" in hgroup.long (0x500+0x54)++0x03 hide.long 0x00 "BMAN_POOL21_HDCNT,BMan H/W Depletion Count Register 21" in rgroup.long (0x600+0x54)++0x03 line.long 0x00 "BMAN_POOL21_CONTENT,BMan Pool Content Register 21" rgroup.long (0x700+0x54)++0x03 line.long 0x00 "BMAN_POOL21_HDPTR,BMan Free List Head Pointer Register 21" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x58)++0x03 "Pool 22" line.long 0x00 "BMAN_POOL22_SWDET,BMan S/W Portal Depletion Entry Threshold Register 22" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x58)++0x03 line.long 0x00 "BMAN_POOL22_HWDET,BMan H/W Portal Depletion Entry Threshold Register 22" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x58)++0x03 line.long 0x00 "BMAN_POOL22_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 22" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x58)++0x03 line.long 0x00 "BMAN_POOL22_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 22" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x58)++0x03 hide.long 0x58 "BMAN_POOL22_SDCNT,BMan S/W Depletion Count Register 22" in hgroup.long (0x500+0x58)++0x03 hide.long 0x00 "BMAN_POOL22_HDCNT,BMan H/W Depletion Count Register 22" in rgroup.long (0x600+0x58)++0x03 line.long 0x00 "BMAN_POOL22_CONTENT,BMan Pool Content Register 22" rgroup.long (0x700+0x58)++0x03 line.long 0x00 "BMAN_POOL22_HDPTR,BMan Free List Head Pointer Register 22" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x5C)++0x03 "Pool 23" line.long 0x00 "BMAN_POOL23_SWDET,BMan S/W Portal Depletion Entry Threshold Register 23" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x5C)++0x03 line.long 0x00 "BMAN_POOL23_HWDET,BMan H/W Portal Depletion Entry Threshold Register 23" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x5C)++0x03 line.long 0x00 "BMAN_POOL23_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 23" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x5C)++0x03 line.long 0x00 "BMAN_POOL23_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 23" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x5C)++0x03 hide.long 0x5C "BMAN_POOL23_SDCNT,BMan S/W Depletion Count Register 23" in hgroup.long (0x500+0x5C)++0x03 hide.long 0x00 "BMAN_POOL23_HDCNT,BMan H/W Depletion Count Register 23" in rgroup.long (0x600+0x5C)++0x03 line.long 0x00 "BMAN_POOL23_CONTENT,BMan Pool Content Register 23" rgroup.long (0x700+0x5C)++0x03 line.long 0x00 "BMAN_POOL23_HDPTR,BMan Free List Head Pointer Register 23" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x60)++0x03 "Pool 24" line.long 0x00 "BMAN_POOL24_SWDET,BMan S/W Portal Depletion Entry Threshold Register 24" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x60)++0x03 line.long 0x00 "BMAN_POOL24_HWDET,BMan H/W Portal Depletion Entry Threshold Register 24" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x60)++0x03 line.long 0x00 "BMAN_POOL24_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 24" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x60)++0x03 line.long 0x00 "BMAN_POOL24_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 24" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x60)++0x03 hide.long 0x60 "BMAN_POOL24_SDCNT,BMan S/W Depletion Count Register 24" in hgroup.long (0x500+0x60)++0x03 hide.long 0x00 "BMAN_POOL24_HDCNT,BMan H/W Depletion Count Register 24" in rgroup.long (0x600+0x60)++0x03 line.long 0x00 "BMAN_POOL24_CONTENT,BMan Pool Content Register 24" rgroup.long (0x700+0x60)++0x03 line.long 0x00 "BMAN_POOL24_HDPTR,BMan Free List Head Pointer Register 24" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x64)++0x03 "Pool 25" line.long 0x00 "BMAN_POOL25_SWDET,BMan S/W Portal Depletion Entry Threshold Register 25" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x64)++0x03 line.long 0x00 "BMAN_POOL25_HWDET,BMan H/W Portal Depletion Entry Threshold Register 25" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x64)++0x03 line.long 0x00 "BMAN_POOL25_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 25" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x64)++0x03 line.long 0x00 "BMAN_POOL25_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 25" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x64)++0x03 hide.long 0x64 "BMAN_POOL25_SDCNT,BMan S/W Depletion Count Register 25" in hgroup.long (0x500+0x64)++0x03 hide.long 0x00 "BMAN_POOL25_HDCNT,BMan H/W Depletion Count Register 25" in rgroup.long (0x600+0x64)++0x03 line.long 0x00 "BMAN_POOL25_CONTENT,BMan Pool Content Register 25" rgroup.long (0x700+0x64)++0x03 line.long 0x00 "BMAN_POOL25_HDPTR,BMan Free List Head Pointer Register 25" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x68)++0x03 "Pool 26" line.long 0x00 "BMAN_POOL26_SWDET,BMan S/W Portal Depletion Entry Threshold Register 26" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x68)++0x03 line.long 0x00 "BMAN_POOL26_HWDET,BMan H/W Portal Depletion Entry Threshold Register 26" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x68)++0x03 line.long 0x00 "BMAN_POOL26_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 26" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x68)++0x03 line.long 0x00 "BMAN_POOL26_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 26" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x68)++0x03 hide.long 0x68 "BMAN_POOL26_SDCNT,BMan S/W Depletion Count Register 26" in hgroup.long (0x500+0x68)++0x03 hide.long 0x00 "BMAN_POOL26_HDCNT,BMan H/W Depletion Count Register 26" in rgroup.long (0x600+0x68)++0x03 line.long 0x00 "BMAN_POOL26_CONTENT,BMan Pool Content Register 26" rgroup.long (0x700+0x68)++0x03 line.long 0x00 "BMAN_POOL26_HDPTR,BMan Free List Head Pointer Register 26" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x6C)++0x03 "Pool 27" line.long 0x00 "BMAN_POOL27_SWDET,BMan S/W Portal Depletion Entry Threshold Register 27" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x6C)++0x03 line.long 0x00 "BMAN_POOL27_HWDET,BMan H/W Portal Depletion Entry Threshold Register 27" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x6C)++0x03 line.long 0x00 "BMAN_POOL27_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 27" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x6C)++0x03 line.long 0x00 "BMAN_POOL27_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 27" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x6C)++0x03 hide.long 0x6C "BMAN_POOL27_SDCNT,BMan S/W Depletion Count Register 27" in hgroup.long (0x500+0x6C)++0x03 hide.long 0x00 "BMAN_POOL27_HDCNT,BMan H/W Depletion Count Register 27" in rgroup.long (0x600+0x6C)++0x03 line.long 0x00 "BMAN_POOL27_CONTENT,BMan Pool Content Register 27" rgroup.long (0x700+0x6C)++0x03 line.long 0x00 "BMAN_POOL27_HDPTR,BMan Free List Head Pointer Register 27" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x70)++0x03 "Pool 28" line.long 0x00 "BMAN_POOL28_SWDET,BMan S/W Portal Depletion Entry Threshold Register 28" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x70)++0x03 line.long 0x00 "BMAN_POOL28_HWDET,BMan H/W Portal Depletion Entry Threshold Register 28" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x70)++0x03 line.long 0x00 "BMAN_POOL28_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 28" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x70)++0x03 line.long 0x00 "BMAN_POOL28_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 28" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x70)++0x03 hide.long 0x70 "BMAN_POOL28_SDCNT,BMan S/W Depletion Count Register 28" in hgroup.long (0x500+0x70)++0x03 hide.long 0x00 "BMAN_POOL28_HDCNT,BMan H/W Depletion Count Register 28" in rgroup.long (0x600+0x70)++0x03 line.long 0x00 "BMAN_POOL28_CONTENT,BMan Pool Content Register 28" rgroup.long (0x700+0x70)++0x03 line.long 0x00 "BMAN_POOL28_HDPTR,BMan Free List Head Pointer Register 28" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x74)++0x03 "Pool 29" line.long 0x00 "BMAN_POOL29_SWDET,BMan S/W Portal Depletion Entry Threshold Register 29" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x74)++0x03 line.long 0x00 "BMAN_POOL29_HWDET,BMan H/W Portal Depletion Entry Threshold Register 29" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x74)++0x03 line.long 0x00 "BMAN_POOL29_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 29" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x74)++0x03 line.long 0x00 "BMAN_POOL29_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 29" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x74)++0x03 hide.long 0x74 "BMAN_POOL29_SDCNT,BMan S/W Depletion Count Register 29" in hgroup.long (0x500+0x74)++0x03 hide.long 0x00 "BMAN_POOL29_HDCNT,BMan H/W Depletion Count Register 29" in rgroup.long (0x600+0x74)++0x03 line.long 0x00 "BMAN_POOL29_CONTENT,BMan Pool Content Register 29" rgroup.long (0x700+0x74)++0x03 line.long 0x00 "BMAN_POOL29_HDPTR,BMan Free List Head Pointer Register 29" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x78)++0x03 "Pool 30" line.long 0x00 "BMAN_POOL30_SWDET,BMan S/W Portal Depletion Entry Threshold Register 30" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x78)++0x03 line.long 0x00 "BMAN_POOL30_HWDET,BMan H/W Portal Depletion Entry Threshold Register 30" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x78)++0x03 line.long 0x00 "BMAN_POOL30_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 30" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x78)++0x03 line.long 0x00 "BMAN_POOL30_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 30" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x78)++0x03 hide.long 0x78 "BMAN_POOL30_SDCNT,BMan S/W Depletion Count Register 30" in hgroup.long (0x500+0x78)++0x03 hide.long 0x00 "BMAN_POOL30_HDCNT,BMan H/W Depletion Count Register 30" in rgroup.long (0x600+0x78)++0x03 line.long 0x00 "BMAN_POOL30_CONTENT,BMan Pool Content Register 30" rgroup.long (0x700+0x78)++0x03 line.long 0x00 "BMAN_POOL30_HDPTR,BMan Free List Head Pointer Register 30" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x7C)++0x03 "Pool 31" line.long 0x00 "BMAN_POOL31_SWDET,BMan S/W Portal Depletion Entry Threshold Register 31" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x7C)++0x03 line.long 0x00 "BMAN_POOL31_HWDET,BMan H/W Portal Depletion Entry Threshold Register 31" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x7C)++0x03 line.long 0x00 "BMAN_POOL31_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 31" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x7C)++0x03 line.long 0x00 "BMAN_POOL31_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 31" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x7C)++0x03 hide.long 0x7C "BMAN_POOL31_SDCNT,BMan S/W Depletion Count Register 31" in hgroup.long (0x500+0x7C)++0x03 hide.long 0x00 "BMAN_POOL31_HDCNT,BMan H/W Depletion Count Register 31" in rgroup.long (0x600+0x7C)++0x03 line.long 0x00 "BMAN_POOL31_CONTENT,BMan Pool Content Register 31" rgroup.long (0x700+0x7C)++0x03 line.long 0x00 "BMAN_POOL31_HDPTR,BMan Free List Head Pointer Register 31" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x80)++0x03 "Pool 32" line.long 0x00 "BMAN_POOL32_SWDET,BMan S/W Portal Depletion Entry Threshold Register 32" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x80)++0x03 line.long 0x00 "BMAN_POOL32_HWDET,BMan H/W Portal Depletion Entry Threshold Register 32" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x80)++0x03 line.long 0x00 "BMAN_POOL32_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 32" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x80)++0x03 line.long 0x00 "BMAN_POOL32_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 32" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x80)++0x03 hide.long 0x80 "BMAN_POOL32_SDCNT,BMan S/W Depletion Count Register 32" in hgroup.long (0x500+0x80)++0x03 hide.long 0x00 "BMAN_POOL32_HDCNT,BMan H/W Depletion Count Register 32" in rgroup.long (0x600+0x80)++0x03 line.long 0x00 "BMAN_POOL32_CONTENT,BMan Pool Content Register 32" rgroup.long (0x700+0x80)++0x03 line.long 0x00 "BMAN_POOL32_HDPTR,BMan Free List Head Pointer Register 32" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x84)++0x03 "Pool 33" line.long 0x00 "BMAN_POOL33_SWDET,BMan S/W Portal Depletion Entry Threshold Register 33" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x84)++0x03 line.long 0x00 "BMAN_POOL33_HWDET,BMan H/W Portal Depletion Entry Threshold Register 33" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x84)++0x03 line.long 0x00 "BMAN_POOL33_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 33" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x84)++0x03 line.long 0x00 "BMAN_POOL33_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 33" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x84)++0x03 hide.long 0x84 "BMAN_POOL33_SDCNT,BMan S/W Depletion Count Register 33" in hgroup.long (0x500+0x84)++0x03 hide.long 0x00 "BMAN_POOL33_HDCNT,BMan H/W Depletion Count Register 33" in rgroup.long (0x600+0x84)++0x03 line.long 0x00 "BMAN_POOL33_CONTENT,BMan Pool Content Register 33" rgroup.long (0x700+0x84)++0x03 line.long 0x00 "BMAN_POOL33_HDPTR,BMan Free List Head Pointer Register 33" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x88)++0x03 "Pool 34" line.long 0x00 "BMAN_POOL34_SWDET,BMan S/W Portal Depletion Entry Threshold Register 34" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x88)++0x03 line.long 0x00 "BMAN_POOL34_HWDET,BMan H/W Portal Depletion Entry Threshold Register 34" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x88)++0x03 line.long 0x00 "BMAN_POOL34_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 34" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x88)++0x03 line.long 0x00 "BMAN_POOL34_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 34" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x88)++0x03 hide.long 0x88 "BMAN_POOL34_SDCNT,BMan S/W Depletion Count Register 34" in hgroup.long (0x500+0x88)++0x03 hide.long 0x00 "BMAN_POOL34_HDCNT,BMan H/W Depletion Count Register 34" in rgroup.long (0x600+0x88)++0x03 line.long 0x00 "BMAN_POOL34_CONTENT,BMan Pool Content Register 34" rgroup.long (0x700+0x88)++0x03 line.long 0x00 "BMAN_POOL34_HDPTR,BMan Free List Head Pointer Register 34" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x8C)++0x03 "Pool 35" line.long 0x00 "BMAN_POOL35_SWDET,BMan S/W Portal Depletion Entry Threshold Register 35" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x8C)++0x03 line.long 0x00 "BMAN_POOL35_HWDET,BMan H/W Portal Depletion Entry Threshold Register 35" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x8C)++0x03 line.long 0x00 "BMAN_POOL35_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 35" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x8C)++0x03 line.long 0x00 "BMAN_POOL35_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 35" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x8C)++0x03 hide.long 0x8C "BMAN_POOL35_SDCNT,BMan S/W Depletion Count Register 35" in hgroup.long (0x500+0x8C)++0x03 hide.long 0x00 "BMAN_POOL35_HDCNT,BMan H/W Depletion Count Register 35" in rgroup.long (0x600+0x8C)++0x03 line.long 0x00 "BMAN_POOL35_CONTENT,BMan Pool Content Register 35" rgroup.long (0x700+0x8C)++0x03 line.long 0x00 "BMAN_POOL35_HDPTR,BMan Free List Head Pointer Register 35" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x90)++0x03 "Pool 36" line.long 0x00 "BMAN_POOL36_SWDET,BMan S/W Portal Depletion Entry Threshold Register 36" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x90)++0x03 line.long 0x00 "BMAN_POOL36_HWDET,BMan H/W Portal Depletion Entry Threshold Register 36" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x90)++0x03 line.long 0x00 "BMAN_POOL36_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 36" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x90)++0x03 line.long 0x00 "BMAN_POOL36_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 36" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x90)++0x03 hide.long 0x90 "BMAN_POOL36_SDCNT,BMan S/W Depletion Count Register 36" in hgroup.long (0x500+0x90)++0x03 hide.long 0x00 "BMAN_POOL36_HDCNT,BMan H/W Depletion Count Register 36" in rgroup.long (0x600+0x90)++0x03 line.long 0x00 "BMAN_POOL36_CONTENT,BMan Pool Content Register 36" rgroup.long (0x700+0x90)++0x03 line.long 0x00 "BMAN_POOL36_HDPTR,BMan Free List Head Pointer Register 36" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x94)++0x03 "Pool 37" line.long 0x00 "BMAN_POOL37_SWDET,BMan S/W Portal Depletion Entry Threshold Register 37" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x94)++0x03 line.long 0x00 "BMAN_POOL37_HWDET,BMan H/W Portal Depletion Entry Threshold Register 37" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x94)++0x03 line.long 0x00 "BMAN_POOL37_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 37" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x94)++0x03 line.long 0x00 "BMAN_POOL37_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 37" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x94)++0x03 hide.long 0x94 "BMAN_POOL37_SDCNT,BMan S/W Depletion Count Register 37" in hgroup.long (0x500+0x94)++0x03 hide.long 0x00 "BMAN_POOL37_HDCNT,BMan H/W Depletion Count Register 37" in rgroup.long (0x600+0x94)++0x03 line.long 0x00 "BMAN_POOL37_CONTENT,BMan Pool Content Register 37" rgroup.long (0x700+0x94)++0x03 line.long 0x00 "BMAN_POOL37_HDPTR,BMan Free List Head Pointer Register 37" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x98)++0x03 "Pool 38" line.long 0x00 "BMAN_POOL38_SWDET,BMan S/W Portal Depletion Entry Threshold Register 38" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x98)++0x03 line.long 0x00 "BMAN_POOL38_HWDET,BMan H/W Portal Depletion Entry Threshold Register 38" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x98)++0x03 line.long 0x00 "BMAN_POOL38_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 38" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x98)++0x03 line.long 0x00 "BMAN_POOL38_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 38" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x98)++0x03 hide.long 0x98 "BMAN_POOL38_SDCNT,BMan S/W Depletion Count Register 38" in hgroup.long (0x500+0x98)++0x03 hide.long 0x00 "BMAN_POOL38_HDCNT,BMan H/W Depletion Count Register 38" in rgroup.long (0x600+0x98)++0x03 line.long 0x00 "BMAN_POOL38_CONTENT,BMan Pool Content Register 38" rgroup.long (0x700+0x98)++0x03 line.long 0x00 "BMAN_POOL38_HDPTR,BMan Free List Head Pointer Register 38" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0x9C)++0x03 "Pool 39" line.long 0x00 "BMAN_POOL39_SWDET,BMan S/W Portal Depletion Entry Threshold Register 39" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0x9C)++0x03 line.long 0x00 "BMAN_POOL39_HWDET,BMan H/W Portal Depletion Entry Threshold Register 39" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0x9C)++0x03 line.long 0x00 "BMAN_POOL39_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 39" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0x9C)++0x03 line.long 0x00 "BMAN_POOL39_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 39" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0x9C)++0x03 hide.long 0x9C "BMAN_POOL39_SDCNT,BMan S/W Depletion Count Register 39" in hgroup.long (0x500+0x9C)++0x03 hide.long 0x00 "BMAN_POOL39_HDCNT,BMan H/W Depletion Count Register 39" in rgroup.long (0x600+0x9C)++0x03 line.long 0x00 "BMAN_POOL39_CONTENT,BMan Pool Content Register 39" rgroup.long (0x700+0x9C)++0x03 line.long 0x00 "BMAN_POOL39_HDPTR,BMan Free List Head Pointer Register 39" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xA0)++0x03 "Pool 40" line.long 0x00 "BMAN_POOL40_SWDET,BMan S/W Portal Depletion Entry Threshold Register 40" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xA0)++0x03 line.long 0x00 "BMAN_POOL40_HWDET,BMan H/W Portal Depletion Entry Threshold Register 40" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xA0)++0x03 line.long 0x00 "BMAN_POOL40_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 40" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xA0)++0x03 line.long 0x00 "BMAN_POOL40_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 40" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xA0)++0x03 hide.long 0xA0 "BMAN_POOL40_SDCNT,BMan S/W Depletion Count Register 40" in hgroup.long (0x500+0xA0)++0x03 hide.long 0x00 "BMAN_POOL40_HDCNT,BMan H/W Depletion Count Register 40" in rgroup.long (0x600+0xA0)++0x03 line.long 0x00 "BMAN_POOL40_CONTENT,BMan Pool Content Register 40" rgroup.long (0x700+0xA0)++0x03 line.long 0x00 "BMAN_POOL40_HDPTR,BMan Free List Head Pointer Register 40" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xA4)++0x03 "Pool 41" line.long 0x00 "BMAN_POOL41_SWDET,BMan S/W Portal Depletion Entry Threshold Register 41" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xA4)++0x03 line.long 0x00 "BMAN_POOL41_HWDET,BMan H/W Portal Depletion Entry Threshold Register 41" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xA4)++0x03 line.long 0x00 "BMAN_POOL41_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 41" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xA4)++0x03 line.long 0x00 "BMAN_POOL41_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 41" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xA4)++0x03 hide.long 0xA4 "BMAN_POOL41_SDCNT,BMan S/W Depletion Count Register 41" in hgroup.long (0x500+0xA4)++0x03 hide.long 0x00 "BMAN_POOL41_HDCNT,BMan H/W Depletion Count Register 41" in rgroup.long (0x600+0xA4)++0x03 line.long 0x00 "BMAN_POOL41_CONTENT,BMan Pool Content Register 41" rgroup.long (0x700+0xA4)++0x03 line.long 0x00 "BMAN_POOL41_HDPTR,BMan Free List Head Pointer Register 41" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xA8)++0x03 "Pool 42" line.long 0x00 "BMAN_POOL42_SWDET,BMan S/W Portal Depletion Entry Threshold Register 42" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xA8)++0x03 line.long 0x00 "BMAN_POOL42_HWDET,BMan H/W Portal Depletion Entry Threshold Register 42" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xA8)++0x03 line.long 0x00 "BMAN_POOL42_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 42" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xA8)++0x03 line.long 0x00 "BMAN_POOL42_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 42" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xA8)++0x03 hide.long 0xA8 "BMAN_POOL42_SDCNT,BMan S/W Depletion Count Register 42" in hgroup.long (0x500+0xA8)++0x03 hide.long 0x00 "BMAN_POOL42_HDCNT,BMan H/W Depletion Count Register 42" in rgroup.long (0x600+0xA8)++0x03 line.long 0x00 "BMAN_POOL42_CONTENT,BMan Pool Content Register 42" rgroup.long (0x700+0xA8)++0x03 line.long 0x00 "BMAN_POOL42_HDPTR,BMan Free List Head Pointer Register 42" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xAC)++0x03 "Pool 43" line.long 0x00 "BMAN_POOL43_SWDET,BMan S/W Portal Depletion Entry Threshold Register 43" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xAC)++0x03 line.long 0x00 "BMAN_POOL43_HWDET,BMan H/W Portal Depletion Entry Threshold Register 43" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xAC)++0x03 line.long 0x00 "BMAN_POOL43_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 43" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xAC)++0x03 line.long 0x00 "BMAN_POOL43_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 43" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xAC)++0x03 hide.long 0xAC "BMAN_POOL43_SDCNT,BMan S/W Depletion Count Register 43" in hgroup.long (0x500+0xAC)++0x03 hide.long 0x00 "BMAN_POOL43_HDCNT,BMan H/W Depletion Count Register 43" in rgroup.long (0x600+0xAC)++0x03 line.long 0x00 "BMAN_POOL43_CONTENT,BMan Pool Content Register 43" rgroup.long (0x700+0xAC)++0x03 line.long 0x00 "BMAN_POOL43_HDPTR,BMan Free List Head Pointer Register 43" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xB0)++0x03 "Pool 44" line.long 0x00 "BMAN_POOL44_SWDET,BMan S/W Portal Depletion Entry Threshold Register 44" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xB0)++0x03 line.long 0x00 "BMAN_POOL44_HWDET,BMan H/W Portal Depletion Entry Threshold Register 44" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xB0)++0x03 line.long 0x00 "BMAN_POOL44_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 44" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xB0)++0x03 line.long 0x00 "BMAN_POOL44_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 44" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xB0)++0x03 hide.long 0xB0 "BMAN_POOL44_SDCNT,BMan S/W Depletion Count Register 44" in hgroup.long (0x500+0xB0)++0x03 hide.long 0x00 "BMAN_POOL44_HDCNT,BMan H/W Depletion Count Register 44" in rgroup.long (0x600+0xB0)++0x03 line.long 0x00 "BMAN_POOL44_CONTENT,BMan Pool Content Register 44" rgroup.long (0x700+0xB0)++0x03 line.long 0x00 "BMAN_POOL44_HDPTR,BMan Free List Head Pointer Register 44" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xB4)++0x03 "Pool 45" line.long 0x00 "BMAN_POOL45_SWDET,BMan S/W Portal Depletion Entry Threshold Register 45" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xB4)++0x03 line.long 0x00 "BMAN_POOL45_HWDET,BMan H/W Portal Depletion Entry Threshold Register 45" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xB4)++0x03 line.long 0x00 "BMAN_POOL45_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 45" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xB4)++0x03 line.long 0x00 "BMAN_POOL45_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 45" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xB4)++0x03 hide.long 0xB4 "BMAN_POOL45_SDCNT,BMan S/W Depletion Count Register 45" in hgroup.long (0x500+0xB4)++0x03 hide.long 0x00 "BMAN_POOL45_HDCNT,BMan H/W Depletion Count Register 45" in rgroup.long (0x600+0xB4)++0x03 line.long 0x00 "BMAN_POOL45_CONTENT,BMan Pool Content Register 45" rgroup.long (0x700+0xB4)++0x03 line.long 0x00 "BMAN_POOL45_HDPTR,BMan Free List Head Pointer Register 45" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xB8)++0x03 "Pool 46" line.long 0x00 "BMAN_POOL46_SWDET,BMan S/W Portal Depletion Entry Threshold Register 46" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xB8)++0x03 line.long 0x00 "BMAN_POOL46_HWDET,BMan H/W Portal Depletion Entry Threshold Register 46" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xB8)++0x03 line.long 0x00 "BMAN_POOL46_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 46" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xB8)++0x03 line.long 0x00 "BMAN_POOL46_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 46" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xB8)++0x03 hide.long 0xB8 "BMAN_POOL46_SDCNT,BMan S/W Depletion Count Register 46" in hgroup.long (0x500+0xB8)++0x03 hide.long 0x00 "BMAN_POOL46_HDCNT,BMan H/W Depletion Count Register 46" in rgroup.long (0x600+0xB8)++0x03 line.long 0x00 "BMAN_POOL46_CONTENT,BMan Pool Content Register 46" rgroup.long (0x700+0xB8)++0x03 line.long 0x00 "BMAN_POOL46_HDPTR,BMan Free List Head Pointer Register 46" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xBC)++0x03 "Pool 47" line.long 0x00 "BMAN_POOL47_SWDET,BMan S/W Portal Depletion Entry Threshold Register 47" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xBC)++0x03 line.long 0x00 "BMAN_POOL47_HWDET,BMan H/W Portal Depletion Entry Threshold Register 47" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xBC)++0x03 line.long 0x00 "BMAN_POOL47_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 47" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xBC)++0x03 line.long 0x00 "BMAN_POOL47_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 47" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xBC)++0x03 hide.long 0xBC "BMAN_POOL47_SDCNT,BMan S/W Depletion Count Register 47" in hgroup.long (0x500+0xBC)++0x03 hide.long 0x00 "BMAN_POOL47_HDCNT,BMan H/W Depletion Count Register 47" in rgroup.long (0x600+0xBC)++0x03 line.long 0x00 "BMAN_POOL47_CONTENT,BMan Pool Content Register 47" rgroup.long (0x700+0xBC)++0x03 line.long 0x00 "BMAN_POOL47_HDPTR,BMan Free List Head Pointer Register 47" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xC0)++0x03 "Pool 48" line.long 0x00 "BMAN_POOL48_SWDET,BMan S/W Portal Depletion Entry Threshold Register 48" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xC0)++0x03 line.long 0x00 "BMAN_POOL48_HWDET,BMan H/W Portal Depletion Entry Threshold Register 48" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xC0)++0x03 line.long 0x00 "BMAN_POOL48_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 48" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xC0)++0x03 line.long 0x00 "BMAN_POOL48_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 48" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xC0)++0x03 hide.long 0xC0 "BMAN_POOL48_SDCNT,BMan S/W Depletion Count Register 48" in hgroup.long (0x500+0xC0)++0x03 hide.long 0x00 "BMAN_POOL48_HDCNT,BMan H/W Depletion Count Register 48" in rgroup.long (0x600+0xC0)++0x03 line.long 0x00 "BMAN_POOL48_CONTENT,BMan Pool Content Register 48" rgroup.long (0x700+0xC0)++0x03 line.long 0x00 "BMAN_POOL48_HDPTR,BMan Free List Head Pointer Register 48" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xC4)++0x03 "Pool 49" line.long 0x00 "BMAN_POOL49_SWDET,BMan S/W Portal Depletion Entry Threshold Register 49" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xC4)++0x03 line.long 0x00 "BMAN_POOL49_HWDET,BMan H/W Portal Depletion Entry Threshold Register 49" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xC4)++0x03 line.long 0x00 "BMAN_POOL49_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 49" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xC4)++0x03 line.long 0x00 "BMAN_POOL49_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 49" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xC4)++0x03 hide.long 0xC4 "BMAN_POOL49_SDCNT,BMan S/W Depletion Count Register 49" in hgroup.long (0x500+0xC4)++0x03 hide.long 0x00 "BMAN_POOL49_HDCNT,BMan H/W Depletion Count Register 49" in rgroup.long (0x600+0xC4)++0x03 line.long 0x00 "BMAN_POOL49_CONTENT,BMan Pool Content Register 49" rgroup.long (0x700+0xC4)++0x03 line.long 0x00 "BMAN_POOL49_HDPTR,BMan Free List Head Pointer Register 49" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xC8)++0x03 "Pool 50" line.long 0x00 "BMAN_POOL50_SWDET,BMan S/W Portal Depletion Entry Threshold Register 50" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xC8)++0x03 line.long 0x00 "BMAN_POOL50_HWDET,BMan H/W Portal Depletion Entry Threshold Register 50" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xC8)++0x03 line.long 0x00 "BMAN_POOL50_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 50" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xC8)++0x03 line.long 0x00 "BMAN_POOL50_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 50" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xC8)++0x03 hide.long 0xC8 "BMAN_POOL50_SDCNT,BMan S/W Depletion Count Register 50" in hgroup.long (0x500+0xC8)++0x03 hide.long 0x00 "BMAN_POOL50_HDCNT,BMan H/W Depletion Count Register 50" in rgroup.long (0x600+0xC8)++0x03 line.long 0x00 "BMAN_POOL50_CONTENT,BMan Pool Content Register 50" rgroup.long (0x700+0xC8)++0x03 line.long 0x00 "BMAN_POOL50_HDPTR,BMan Free List Head Pointer Register 50" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xCC)++0x03 "Pool 51" line.long 0x00 "BMAN_POOL51_SWDET,BMan S/W Portal Depletion Entry Threshold Register 51" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xCC)++0x03 line.long 0x00 "BMAN_POOL51_HWDET,BMan H/W Portal Depletion Entry Threshold Register 51" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xCC)++0x03 line.long 0x00 "BMAN_POOL51_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 51" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xCC)++0x03 line.long 0x00 "BMAN_POOL51_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 51" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xCC)++0x03 hide.long 0xCC "BMAN_POOL51_SDCNT,BMan S/W Depletion Count Register 51" in hgroup.long (0x500+0xCC)++0x03 hide.long 0x00 "BMAN_POOL51_HDCNT,BMan H/W Depletion Count Register 51" in rgroup.long (0x600+0xCC)++0x03 line.long 0x00 "BMAN_POOL51_CONTENT,BMan Pool Content Register 51" rgroup.long (0x700+0xCC)++0x03 line.long 0x00 "BMAN_POOL51_HDPTR,BMan Free List Head Pointer Register 51" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xD0)++0x03 "Pool 52" line.long 0x00 "BMAN_POOL52_SWDET,BMan S/W Portal Depletion Entry Threshold Register 52" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xD0)++0x03 line.long 0x00 "BMAN_POOL52_HWDET,BMan H/W Portal Depletion Entry Threshold Register 52" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xD0)++0x03 line.long 0x00 "BMAN_POOL52_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 52" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xD0)++0x03 line.long 0x00 "BMAN_POOL52_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 52" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xD0)++0x03 hide.long 0xD0 "BMAN_POOL52_SDCNT,BMan S/W Depletion Count Register 52" in hgroup.long (0x500+0xD0)++0x03 hide.long 0x00 "BMAN_POOL52_HDCNT,BMan H/W Depletion Count Register 52" in rgroup.long (0x600+0xD0)++0x03 line.long 0x00 "BMAN_POOL52_CONTENT,BMan Pool Content Register 52" rgroup.long (0x700+0xD0)++0x03 line.long 0x00 "BMAN_POOL52_HDPTR,BMan Free List Head Pointer Register 52" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xD4)++0x03 "Pool 53" line.long 0x00 "BMAN_POOL53_SWDET,BMan S/W Portal Depletion Entry Threshold Register 53" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xD4)++0x03 line.long 0x00 "BMAN_POOL53_HWDET,BMan H/W Portal Depletion Entry Threshold Register 53" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xD4)++0x03 line.long 0x00 "BMAN_POOL53_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 53" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xD4)++0x03 line.long 0x00 "BMAN_POOL53_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 53" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xD4)++0x03 hide.long 0xD4 "BMAN_POOL53_SDCNT,BMan S/W Depletion Count Register 53" in hgroup.long (0x500+0xD4)++0x03 hide.long 0x00 "BMAN_POOL53_HDCNT,BMan H/W Depletion Count Register 53" in rgroup.long (0x600+0xD4)++0x03 line.long 0x00 "BMAN_POOL53_CONTENT,BMan Pool Content Register 53" rgroup.long (0x700+0xD4)++0x03 line.long 0x00 "BMAN_POOL53_HDPTR,BMan Free List Head Pointer Register 53" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xD8)++0x03 "Pool 54" line.long 0x00 "BMAN_POOL54_SWDET,BMan S/W Portal Depletion Entry Threshold Register 54" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xD8)++0x03 line.long 0x00 "BMAN_POOL54_HWDET,BMan H/W Portal Depletion Entry Threshold Register 54" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xD8)++0x03 line.long 0x00 "BMAN_POOL54_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 54" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xD8)++0x03 line.long 0x00 "BMAN_POOL54_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 54" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xD8)++0x03 hide.long 0xD8 "BMAN_POOL54_SDCNT,BMan S/W Depletion Count Register 54" in hgroup.long (0x500+0xD8)++0x03 hide.long 0x00 "BMAN_POOL54_HDCNT,BMan H/W Depletion Count Register 54" in rgroup.long (0x600+0xD8)++0x03 line.long 0x00 "BMAN_POOL54_CONTENT,BMan Pool Content Register 54" rgroup.long (0x700+0xD8)++0x03 line.long 0x00 "BMAN_POOL54_HDPTR,BMan Free List Head Pointer Register 54" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xDC)++0x03 "Pool 55" line.long 0x00 "BMAN_POOL55_SWDET,BMan S/W Portal Depletion Entry Threshold Register 55" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xDC)++0x03 line.long 0x00 "BMAN_POOL55_HWDET,BMan H/W Portal Depletion Entry Threshold Register 55" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xDC)++0x03 line.long 0x00 "BMAN_POOL55_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 55" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xDC)++0x03 line.long 0x00 "BMAN_POOL55_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 55" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xDC)++0x03 hide.long 0xDC "BMAN_POOL55_SDCNT,BMan S/W Depletion Count Register 55" in hgroup.long (0x500+0xDC)++0x03 hide.long 0x00 "BMAN_POOL55_HDCNT,BMan H/W Depletion Count Register 55" in rgroup.long (0x600+0xDC)++0x03 line.long 0x00 "BMAN_POOL55_CONTENT,BMan Pool Content Register 55" rgroup.long (0x700+0xDC)++0x03 line.long 0x00 "BMAN_POOL55_HDPTR,BMan Free List Head Pointer Register 55" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xE0)++0x03 "Pool 56" line.long 0x00 "BMAN_POOL56_SWDET,BMan S/W Portal Depletion Entry Threshold Register 56" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xE0)++0x03 line.long 0x00 "BMAN_POOL56_HWDET,BMan H/W Portal Depletion Entry Threshold Register 56" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xE0)++0x03 line.long 0x00 "BMAN_POOL56_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 56" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xE0)++0x03 line.long 0x00 "BMAN_POOL56_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 56" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xE0)++0x03 hide.long 0xE0 "BMAN_POOL56_SDCNT,BMan S/W Depletion Count Register 56" in hgroup.long (0x500+0xE0)++0x03 hide.long 0x00 "BMAN_POOL56_HDCNT,BMan H/W Depletion Count Register 56" in rgroup.long (0x600+0xE0)++0x03 line.long 0x00 "BMAN_POOL56_CONTENT,BMan Pool Content Register 56" rgroup.long (0x700+0xE0)++0x03 line.long 0x00 "BMAN_POOL56_HDPTR,BMan Free List Head Pointer Register 56" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xE4)++0x03 "Pool 57" line.long 0x00 "BMAN_POOL57_SWDET,BMan S/W Portal Depletion Entry Threshold Register 57" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xE4)++0x03 line.long 0x00 "BMAN_POOL57_HWDET,BMan H/W Portal Depletion Entry Threshold Register 57" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xE4)++0x03 line.long 0x00 "BMAN_POOL57_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 57" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xE4)++0x03 line.long 0x00 "BMAN_POOL57_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 57" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xE4)++0x03 hide.long 0xE4 "BMAN_POOL57_SDCNT,BMan S/W Depletion Count Register 57" in hgroup.long (0x500+0xE4)++0x03 hide.long 0x00 "BMAN_POOL57_HDCNT,BMan H/W Depletion Count Register 57" in rgroup.long (0x600+0xE4)++0x03 line.long 0x00 "BMAN_POOL57_CONTENT,BMan Pool Content Register 57" rgroup.long (0x700+0xE4)++0x03 line.long 0x00 "BMAN_POOL57_HDPTR,BMan Free List Head Pointer Register 57" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xE8)++0x03 "Pool 58" line.long 0x00 "BMAN_POOL58_SWDET,BMan S/W Portal Depletion Entry Threshold Register 58" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xE8)++0x03 line.long 0x00 "BMAN_POOL58_HWDET,BMan H/W Portal Depletion Entry Threshold Register 58" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xE8)++0x03 line.long 0x00 "BMAN_POOL58_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 58" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xE8)++0x03 line.long 0x00 "BMAN_POOL58_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 58" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xE8)++0x03 hide.long 0xE8 "BMAN_POOL58_SDCNT,BMan S/W Depletion Count Register 58" in hgroup.long (0x500+0xE8)++0x03 hide.long 0x00 "BMAN_POOL58_HDCNT,BMan H/W Depletion Count Register 58" in rgroup.long (0x600+0xE8)++0x03 line.long 0x00 "BMAN_POOL58_CONTENT,BMan Pool Content Register 58" rgroup.long (0x700+0xE8)++0x03 line.long 0x00 "BMAN_POOL58_HDPTR,BMan Free List Head Pointer Register 58" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xEC)++0x03 "Pool 59" line.long 0x00 "BMAN_POOL59_SWDET,BMan S/W Portal Depletion Entry Threshold Register 59" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xEC)++0x03 line.long 0x00 "BMAN_POOL59_HWDET,BMan H/W Portal Depletion Entry Threshold Register 59" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xEC)++0x03 line.long 0x00 "BMAN_POOL59_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 59" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xEC)++0x03 line.long 0x00 "BMAN_POOL59_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 59" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xEC)++0x03 hide.long 0xEC "BMAN_POOL59_SDCNT,BMan S/W Depletion Count Register 59" in hgroup.long (0x500+0xEC)++0x03 hide.long 0x00 "BMAN_POOL59_HDCNT,BMan H/W Depletion Count Register 59" in rgroup.long (0x600+0xEC)++0x03 line.long 0x00 "BMAN_POOL59_CONTENT,BMan Pool Content Register 59" rgroup.long (0x700+0xEC)++0x03 line.long 0x00 "BMAN_POOL59_HDPTR,BMan Free List Head Pointer Register 59" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xF0)++0x03 "Pool 60" line.long 0x00 "BMAN_POOL60_SWDET,BMan S/W Portal Depletion Entry Threshold Register 60" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xF0)++0x03 line.long 0x00 "BMAN_POOL60_HWDET,BMan H/W Portal Depletion Entry Threshold Register 60" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xF0)++0x03 line.long 0x00 "BMAN_POOL60_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 60" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xF0)++0x03 line.long 0x00 "BMAN_POOL60_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 60" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xF0)++0x03 hide.long 0xF0 "BMAN_POOL60_SDCNT,BMan S/W Depletion Count Register 60" in hgroup.long (0x500+0xF0)++0x03 hide.long 0x00 "BMAN_POOL60_HDCNT,BMan H/W Depletion Count Register 60" in rgroup.long (0x600+0xF0)++0x03 line.long 0x00 "BMAN_POOL60_CONTENT,BMan Pool Content Register 60" rgroup.long (0x700+0xF0)++0x03 line.long 0x00 "BMAN_POOL60_HDPTR,BMan Free List Head Pointer Register 60" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xF4)++0x03 "Pool 61" line.long 0x00 "BMAN_POOL61_SWDET,BMan S/W Portal Depletion Entry Threshold Register 61" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xF4)++0x03 line.long 0x00 "BMAN_POOL61_HWDET,BMan H/W Portal Depletion Entry Threshold Register 61" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xF4)++0x03 line.long 0x00 "BMAN_POOL61_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 61" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xF4)++0x03 line.long 0x00 "BMAN_POOL61_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 61" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xF4)++0x03 hide.long 0xF4 "BMAN_POOL61_SDCNT,BMan S/W Depletion Count Register 61" in hgroup.long (0x500+0xF4)++0x03 hide.long 0x00 "BMAN_POOL61_HDCNT,BMan H/W Depletion Count Register 61" in rgroup.long (0x600+0xF4)++0x03 line.long 0x00 "BMAN_POOL61_CONTENT,BMan Pool Content Register 61" rgroup.long (0x700+0xF4)++0x03 line.long 0x00 "BMAN_POOL61_HDPTR,BMan Free List Head Pointer Register 61" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xF8)++0x03 "Pool 62" line.long 0x00 "BMAN_POOL62_SWDET,BMan S/W Portal Depletion Entry Threshold Register 62" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xF8)++0x03 line.long 0x00 "BMAN_POOL62_HWDET,BMan H/W Portal Depletion Entry Threshold Register 62" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xF8)++0x03 line.long 0x00 "BMAN_POOL62_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 62" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xF8)++0x03 line.long 0x00 "BMAN_POOL62_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 62" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xF8)++0x03 hide.long 0xF8 "BMAN_POOL62_SDCNT,BMan S/W Depletion Count Register 62" in hgroup.long (0x500+0xF8)++0x03 hide.long 0x00 "BMAN_POOL62_HDCNT,BMan H/W Depletion Count Register 62" in rgroup.long (0x600+0xF8)++0x03 line.long 0x00 "BMAN_POOL62_CONTENT,BMan Pool Content Register 62" rgroup.long (0x700+0xF8)++0x03 line.long 0x00 "BMAN_POOL62_HDPTR,BMan Free List Head Pointer Register 62" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long (0x00+0xFC)++0x03 "Pool 63" line.long 0x00 "BMAN_POOL63_SWDET,BMan S/W Portal Depletion Entry Threshold Register 63" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Entry Threshold Coefficient" group.long (0x100+0xFC)++0x03 line.long 0x00 "BMAN_POOL63_HWDET,BMan H/W Portal Depletion Entry Threshold Register 63" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Entry Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Entry Threshold Coefficient" group.long (0x200+0xFC)++0x03 line.long 0x00 "BMAN_POOL63_SWDXT,BMan S/W Portal Depletion Exit Threshold Register 63" bitfld.long 0x00 8.--11. " EXP ,S/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,S/W Depletion Exit Threshold Coefficient" group.long (0x300+0xFC)++0x03 line.long 0x00 "BMAN_POOL63_HWDXT,BMan H/W Portal Depletion Exit Threshold Register 63" bitfld.long 0x00 8.--11. " EXP ,H/W Depletion Exit Threshold Exponent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " COEF ,H/W Depletion Exit Threshold Coefficient" hgroup.long (0x400+0xFC)++0x03 hide.long 0xFC "BMAN_POOL63_SDCNT,BMan S/W Depletion Count Register 63" in hgroup.long (0x500+0xFC)++0x03 hide.long 0x00 "BMAN_POOL63_HDCNT,BMan H/W Depletion Count Register 63" in rgroup.long (0x600+0xFC)++0x03 line.long 0x00 "BMAN_POOL63_CONTENT,BMan Pool Content Register 63" rgroup.long (0x700+0xFC)++0x03 line.long 0x00 "BMAN_POOL63_HDPTR,BMan Free List Head Pointer Register 63" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" tree.end rgroup.long 0x800++0x3 "Free Buffer Proxy Record (FBPR) Manager Query Registers" line.long 0x00 "FBPR_FPC,Free Buffer Proxy Record Free Pool Count Register" group.long 0x804++0x3 line.long 0x00 "FBPR_FP_LWIT,FBPR Low Watermark Interrupt Threshold Register" hexmask.long 0x00 0.--27. 1. " TH ,FBPR Low Watermark Interrupt Threshold" rgroup.long 0x808++0x3 line.long 0x00 "FBPR_HDPTR,Head Pointer For FBPR List Register" hexmask.long 0x00 0.--27. 1. " LAST_IDX ,28-bit index into BMan system memory space" group.long 0x900++0x03 "Performance Monitor 0" line.long 0x00 "BMAN_CMD_PM0_CFG,BMAN Command Performance Monitor Configuration Register 0" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x900)++0x03 line.long 0x00 "BMAN_FL_PM0_CFG,BMAN Free List Performance Monitor Configuration Register 0" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x900)++0x03 line.long 0x00 "BMAN_CMD_PM0_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 0: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x904++0x03 "Performance Monitor 1" line.long 0x00 "BMAN_CMD_PM1_CFG,BMAN Command Performance Monitor Configuration Register 1" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x904)++0x03 line.long 0x00 "BMAN_FL_PM1_CFG,BMAN Free List Performance Monitor Configuration Register 1" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x904)++0x03 line.long 0x00 "BMAN_CMD_PM1_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 1: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x908++0x03 "Performance Monitor 2" line.long 0x00 "BMAN_CMD_PM2_CFG,BMAN Command Performance Monitor Configuration Register 2" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x908)++0x03 line.long 0x00 "BMAN_FL_PM2_CFG,BMAN Free List Performance Monitor Configuration Register 2" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x908)++0x03 line.long 0x00 "BMAN_CMD_PM2_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 2: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x90C++0x03 "Performance Monitor 3" line.long 0x00 "BMAN_CMD_PM3_CFG,BMAN Command Performance Monitor Configuration Register 3" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x90C)++0x03 line.long 0x00 "BMAN_FL_PM3_CFG,BMAN Free List Performance Monitor Configuration Register 3" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x90C)++0x03 line.long 0x00 "BMAN_CMD_PM3_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 3: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x910++0x03 "Performance Monitor 4" line.long 0x00 "BMAN_CMD_PM4_CFG,BMAN Command Performance Monitor Configuration Register 4" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x910)++0x03 line.long 0x00 "BMAN_FL_PM4_CFG,BMAN Free List Performance Monitor Configuration Register 4" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x910)++0x03 line.long 0x00 "BMAN_CMD_PM4_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 4: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x914++0x03 "Performance Monitor 5" line.long 0x00 "BMAN_CMD_PM5_CFG,BMAN Command Performance Monitor Configuration Register 5" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x914)++0x03 line.long 0x00 "BMAN_FL_PM5_CFG,BMAN Free List Performance Monitor Configuration Register 5" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x914)++0x03 line.long 0x00 "BMAN_CMD_PM5_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 5: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x918++0x03 "Performance Monitor 6" line.long 0x00 "BMAN_CMD_PM6_CFG,BMAN Command Performance Monitor Configuration Register 6" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x918)++0x03 line.long 0x00 "BMAN_FL_PM6_CFG,BMAN Free List Performance Monitor Configuration Register 6" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x918)++0x03 line.long 0x00 "BMAN_CMD_PM6_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 6: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" group.long 0x91C++0x03 "Performance Monitor 7" line.long 0x00 "BMAN_CMD_PM7_CFG,BMAN Command Performance Monitor Configuration Register 7" bitfld.long 0x00 28.--31. " DCOEF ,Command wait time threshold coefficient" "0,1,2,3,4,5,6,7,8,9,10,?..." bitfld.long 0x00 25.--27. " DEXP ,Command wait time threshold exponent" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " CBTH ,Acquire command buffer threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17. " RF ,Response service FIFO full" "Not affect,Affect" bitfld.long 0x00 16. " CF ,Command Service FIFO full" "Not full,Full" hexmask.long.byte 0x00 8.--15. 1. " PRS ,Pool ID at start of selected contiguous range" newline hexmask.long.byte 0x00 0.--7. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x20+0x91C)++0x03 line.long 0x00 "BMAN_FL_PM7_CFG,BMAN Free List Performance Monitor Configuration Register 7" bitfld.long 0x00 31. " FP ,Monitor Free Pool of FBPR's" "Disabled,Enabled" hexmask.long.byte 0x00 6.--11. 1. " PRS ,Pool ID at start of selected contiguous range" hexmask.long.byte 0x00 0.--5. 1. " PRE ,Pool ID at end of selected contiguous range" group.long (0x40+0x91C)++0x03 line.long 0x00 "BMAN_CMD_PM7_CFG_CFIFO,BMan Command Performance Monitor Configuration Register 7: Command Fifo Select" bitfld.long 0x00 31. " CFIFO[0] ,Command service FIFO. Hardware command from portal 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Command service FIFO. Hardware command from portal 1 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Command service FIFO. Hardware command from portal 2 enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Command service FIFO. Hardware command from portal 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Command service FIFO. Hardware command from portal 4 enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Command service FIFO. Hardware command from portal 5 enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Command service FIFO. Hardware command from portal 6 enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Command service FIFO. Hardware command from portal 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Command service FIFO. Hardware command from portal 8 enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Command service FIFO. Hardware command from portal 9 enable" "Disabled,Enabled" bitfld.long 0x00 0. " CFIFO ,Command service FIFO. Hardware command from all portals enable" "Disabled,Enabled" rgroup.long 0x960++0x03 "BMan Idle State and Stop Registers" line.long 0x00 "BMAN_STATE_IDLE,BMan Idle State Register" bitfld.long 0x00 3. " A ,Stop Acknowledged" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " S ,Stop Request" "Not requested,Requested" bitfld.long 0x00 1. " E ,Empty" "Not empty,Empty" bitfld.long 0x00 0. " I ,Idle" "No idle,Idle" group.long 0x964++0x03 line.long 0x00 "BMAN_STATE_STOP,BMan Stop State Register" bitfld.long 0x00 31. " D ,Stop servicing hardware portal requests" "Not stopped,Stopped" bitfld.long 0x00 30. " P ,Stop servicing Software Portal requests" "Not stopped,Stopped" bitfld.long 0x00 29. " F ,Stop servicing fetch/flush requests from the stockpile" "Not stopped,Stopped" bitfld.long 0x00 2. " S ,Stop Request" "Not stopped,Stopped" rgroup.long 0xA04++0x03 "BMan Error Capture Registers" line.long 0x00 "BMAN_ECIR,BMan Error Capture Information Register" hexmask.long.word 0x00 16.--25. 1. " PORTAL ,Software Portal associated with the invalid command" bitfld.long 0x00 15. " R ,Software ring associated with the invalid command" "Command,RCR" hexmask.long.byte 0x00 8.--14. 1. " VERB ,Verb associated with the invalid command" hexmask.long.byte 0x00 0.--7. 1. " POOL ,Pool ID" group.long 0xA30++0x3 line.long 0x00 "BMAN_SBET,BMan Single Bit ECC Error Threshold Register" bitfld.long 0x00 31. " ECD[0] ,Error Correction and Detection Disable" "No,Yes" hexmask.long.byte 0x00 0.--7. 1. " SBET ,Single Bit Error Threshold" rgroup.long 0xA34++0x7 line.long 0x00 "BMAN_CECR,BMan Error Fetch Capture Register" hexmask.long.byte 0x00 0.--6. 1. " LID ,List ID" line.long 0x04 "BMAN_CEAR,BMan Error Fetch Capture Register" hexmask.long 0x04 0.--27. 0x01 " ADDR ,Address" rgroup.long 0xA44++0x7 line.long 0x00 "BMAN_AECR,BMan Error Fetch Capture Register" hexmask.long.byte 0x00 0.--6. 1. " LID ,List ID" line.long 0x04 "BMAN_AEAR,BMan Error Fetch Capture Register" hexmask.long 0x04 0.--27. 0x01 " ADDR ,Address" hgroup.long 0xA80++0x3 hide.long 0x00 "BMAN_SBEC$2,BMan Single Bit ECC Error Count Register 0" in rgroup.long 0xBF8++0x07 "BMan ID/Revision Registers" line.long 0x00 "BMAN_IP_REV_1,BMan IP Block Revision 1 Register" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP Block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "BMAN_IP_REV_2,BMan IP Block Revision 2 Register" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,Integration options" hexmask.long.byte 0x04 8.--15. 1. " IP_ERR ,Errata revision level" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,Configuration options" group.long 0xC00++0x7 "CoreNet Initiator Interface Memory Window Configuration Registers" line.long 0x00 "FBPR_BARE,Data Structure Extended Base Address Register" hexmask.long.word 0x00 0.--15. 0x01 " EBA ,Extended Base Address" line.long 0x04 "FBPR_BAR,Data Structure Base Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " BA ,Base Address" group.long 0xC10++0x3 line.long 0x00 "FBPR_AR,Data Structure Attribute Register" bitfld.long 0x00 30. " P ,Data Structure Transaction Priority" "Lower,Higher" bitfld.long 0x00 0.--5. " SIZE ,Size of the window from the base address" ",,,,,,,,,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB,8 GB,16 GB,?..." rgroup.long 0xD04++0x3 line.long 0x00 "BMAN_SRCIDR,BMan Source ID Register" hexmask.long.byte 0x00 0.--7. 1. " SRCID ,BMan's 8-bit Source ID" group.long 0xD08++0x3 line.long 0x00 "BMAN_ICIDR,BMan Logical I/O Device Number Register" hexmask.long.word 0x00 0.--11. 1. " BMAN_ICID ,The BMan's Isolation Context Identifier" group.long 0xE00++0xF "BMan Interrupt and Error Registers" line.long 0x00 "BMAN_ERR_ISR,BMan Error Interrupt Status Register" eventfld.long 0x00 6. " EMAI ,External memory access interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " EMCI ,External memory corruption interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " IVCI ,Invalid Command Verb Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " FLWI ,FBPR Low Watermark Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " MBEI ,Multi Bit ECC Error Interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " SBEI ,Single Bit ECC Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BSCN ,Buffer Pool Availability State change notification interrupt" "No interrupt,Interrupt" line.long 0x04 "BMAN_ERR_IER,BMan Error Interrupt Enable Register" bitfld.long 0x04 6. " EMAI ,External memory access interrupt enable" "No effect,Enabled" bitfld.long 0x04 5. " EMCI ,External memory corruption interrupt enable" "No effect,Enabled" newline bitfld.long 0x04 4. " IVCI ,Invalid Command Verb Interrupt enable" "No effect,Enabled" bitfld.long 0x04 3. " FLWI ,FBPR Low Watermark Interrupt enable" "No effect,Enabled" bitfld.long 0x04 2. " MBEI ,Multi Bit ECC Error Interrupt enable" "No effect,Enabled" newline bitfld.long 0x04 1. " SBEI ,Single Bit ECC Error Interrupt enable" "No effect,Enabled" bitfld.long 0x04 0. " BSCN ,Buffer Pool Availability State change notification interrupt enable" "No effect,Enable" line.long 0x08 "BMAN_ERR_ISDR,BMan Error Interrupt Status Disable Register" bitfld.long 0x08 6. " EMAI ,External memory access Command Verb Interrupt disable" "No effect,Disabled" bitfld.long 0x08 5. " EMCI ,External memory corruption Command Verb Interrupt disable" "No effect,Disabled" bitfld.long 0x08 4. " IVCI ,Invalid Command Verb Interrupt disable" "No effect,Disabled" newline bitfld.long 0x08 3. " FLWI ,FBPR Low Watermark Interrupt disable" "No effect,Disabled" bitfld.long 0x08 2. " MBEI ,Multi Bit ECC Error Interrupt disable" "No effect,Disabled" newline bitfld.long 0x08 1. " SBEI ,Single Bit ECC Error Interrupt disable" "No effect,Disabled" bitfld.long 0x08 0. " BSCN ,Buffer Pool Availability State change notification interrupt disable" "No effect,Disabled" line.long 0x0C "BMAN_ERR_IIR,BMan Error Interrupt Inhibit Register" bitfld.long 0x0C 0. " I ,Interrupt Inhibit" "Not inhibited,Inhibited" wgroup.long 0xE10++0x3 line.long 0x00 "BMAN_ERR_IFR,BMan Error Interrupt Force Register" bitfld.long 0x00 6. " EMAI ,External memory access Command Verb Interrupt" "Not forced,Forced" bitfld.long 0x00 5. " EMCI ,External memory corruption Command Verb Interrupt" "Not forced,Forced" bitfld.long 0x00 4. " IVCI ,Invalid Command Verb Interrupt" "Not forced,Forced" newline bitfld.long 0x00 3. " FLWI ,FBPR Low Watermark Interrupt" "Not forced,Forced" bitfld.long 0x00 2. " MBEI ,Multi Bit ECC Error Interrupt" "Not forced,Forced" newline bitfld.long 0x00 1. " SBEI ,Single Bit ECC Error Interrupt" "Not forced,Forced" bitfld.long 0x00 0. " BSCN ,Buffer Pool Availability State change notification interrupt" "Not forced,Forced" group.long 0xF00++0x7 "BMan Debug" line.long 0x00 "BMAN_DEBUG_CFIFO,Command FIFO Disable Register" bitfld.long 0x00 31. " CFIFO[0] ,Disables hardware portal 0" "Enabled,Disabled" bitfld.long 0x00 30. " CFIFO[1] ,Disables hardware portal 1" "Enabled,Disabled" bitfld.long 0x00 29. " CFIFO[2] ,Disables hardware portal 2" "Enabled,Disabled" bitfld.long 0x00 28. " CFIFO[3] ,Disables hardware portal 3" "Enabled,Disabled" newline bitfld.long 0x00 27. " [4] ,Disables hardware portal 4" "Enabled,Disabled" bitfld.long 0x00 26. " [5] ,Disables hardware portal 5" "Enabled,Disabled" bitfld.long 0x00 25. " [6] ,Disables hardware portal 6" "Enabled,Disabled" bitfld.long 0x00 24. " [7] ,Disables hardware portal 7" "Enabled,Disabled" newline bitfld.long 0x00 23. " [8] ,Disables hardware portal 8" "Enabled,Disabled" bitfld.long 0x00 22. " [9] ,Disables hardware portal 9" "Enabled,Disabled" bitfld.long 0x00 21. " [10] ,Disables hardware portal 10" "Enabled,Disabled" bitfld.long 0x00 20. " [11] ,Disables hardware portal 11" "Enabled,Disabled" newline bitfld.long 0x00 19. " [12] ,Disables hardware portal 12" "Enabled,Disabled" bitfld.long 0x00 18. " [13] ,Disables hardware portal 13" "Enabled,Disabled" bitfld.long 0x00 17. " [14] ,Disables hardware portal 14" "Enabled,Disabled" bitfld.long 0x00 16. " [15] ,Disables hardware portal 15" "Enabled,Disabled" newline bitfld.long 0x00 15. " [16] ,Disables hardware portal 16" "Enabled,Disabled" bitfld.long 0x00 14. " [17] ,Disables hardware portal 17" "Enabled,Disabled" bitfld.long 0x00 13. " [18] ,Disables hardware portal 18" "Enabled,Disabled" bitfld.long 0x00 12. " [19] ,Disables hardware portal 19" "Enabled,Disabled" newline bitfld.long 0x00 11. " [20] ,Disables hardware portal 20" "Enabled,Disabled" bitfld.long 0x00 10. " [21] ,Disables hardware portal 21" "Enabled,Disabled" bitfld.long 0x00 9. " [22] ,Disables hardware portal 22" "Enabled,Disabled" bitfld.long 0x00 8. " [23] ,Disables hardware portal 23" "Enabled,Disabled" newline bitfld.long 0x00 7. " [24] ,Disables hardware portal 24" "Enabled,Disabled" bitfld.long 0x00 6. " [25] ,Disables hardware portal 25" "Enabled,Disabled" bitfld.long 0x00 5. " [26] ,Disables hardware portal 26" "Enabled,Disabled" bitfld.long 0x00 4. " [27] ,Disables hardware portal 27" "Enabled,Disabled" newline bitfld.long 0x00 3. " [28] ,Disables hardware portal 28" "Enabled,Disabled" bitfld.long 0x00 2. " [29] ,Disables hardware portal 29" "Enabled,Disabled" bitfld.long 0x00 1. " [30] ,Disables hardware portal 30" "Enabled,Disabled" bitfld.long 0x00 0. " CFIFO ,Disables all Software Portals" "Enabled,Disabled" line.long 0x04 "BMAN_DEBUG_FSM,State Machine Disable Register" bitfld.long 0x04 1. " F ,Fetch/Flush state machine disable" "No,Yes" bitfld.long 0x04 0. " S ,FIFO service state machine disable" "No,Yes" endian.le width 0x0B tree.end tree "FMan (Frame Manager)" base ad:0x01A00000 tree "Frame Manager BMI" base ad:0x01A00000+0x80000 width 17. endian.be tree "General Registers" wgroup.long 0x00++0x03 line.long 0x00 "FMBM_INIT,BMI Initialization" bitfld.long 0x00 31. " STR ,Start" "Disable,Enable" group.long 0x4++0x7 line.long 0x00 "FMBM_CFG1,BMI Configuration 1" hexmask.long.word 0x00 16.--26. 1. " FBPS ,Free buffer pool size" hexmask.long.word 0x00 0.--10. 0x01 " FBPO ,Free buffer pool offset" line.long 0x04 "FMBM_CFG2,BMI Configuration 2" hexmask.long.byte 0x04 16.--22. 1. " TNTSKS ,Total number of tasks" group.long 0x20++0xB line.long 0x00 "FMBM_IEVR,Interrupt Event Register" eventfld.long 0x00 31. " SPEC ,Storage profile ECC error detected" "No error,Error" eventfld.long 0x00 30. " LEC ,Linked list RAM ECC error" "No error,Error" eventfld.long 0x00 29. " STEC ,Statistics count RAM ECC error" "No error,Error" eventfld.long 0x00 28. " DEC ,Dispatch RAM ECC error" "No error,Error" line.long 0x04 "FMBM_IER,Interrupt Enable Register" bitfld.long 0x04 31. " SPECE ,Storage profile RAM ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " LECE ,Linked list RAM ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 29. " SECE ,Statistics count RAM ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " DECE ,Dispatch RAM ECC error interrupt enable" "Disabled,Enabled" line.long 0x08 "FMBM_IFR,Interrupt Force Register" bitfld.long 0x08 31. " SPECF ,Storage profile ECC error force" "Not forced,Forced" bitfld.long 0x08 30. " LECF ,Statistics count RAM ECC error force" "Not forced,Forced" bitfld.long 0x08 29. " SECF ,Statistics count RAM ECC error force" "Not forced,Forced" bitfld.long 0x08 28. " DECF ,Dispatch RAM ECC error force" "Not forced,Forced" group.long 0x90++0x03 line.long 0x00 "FMBM_DTC_0,Debug Trap Counter 0 (Flow A)" group.long 0x94++0x03 line.long 0x00 "FMBM_DTC_1,Debug Trap Counter 1 (Flow B)" group.long 0x98++0x03 line.long 0x00 "FMBM_DTC_2,Debug Trap Counter 2 (Flow C)" group.long 0xA0++0x03 line.long 0x00 "FMBM_DCV_1_1,Debug Compare Value (FLOW A)" group.long 0xA4++0x03 line.long 0x00 "FMBM_DCV_2_1,Debug Compare Value (FLOW A)" group.long 0xA8++0x03 line.long 0x00 "FMBM_DCV_3_1,Debug Compare Value (FLOW A)" group.long 0xAC++0x03 line.long 0x00 "FMBM_DCV_4_1,Debug Compare Value (FLOW A)" group.long 0xB0++0x03 line.long 0x00 "FMBM_DCV_1_2,Debug Compare Value (FLOW B)" group.long 0xB4++0x03 line.long 0x00 "FMBM_DCV_2_2,Debug Compare Value (FLOW B)" group.long 0xB8++0x03 line.long 0x00 "FMBM_DCV_3_2,Debug Compare Value (FLOW B)" group.long 0xBC++0x03 line.long 0x00 "FMBM_DCV_4_2,Debug Compare Value (FLOW B)" group.long 0xC0++0x03 line.long 0x00 "FMBM_DCV_1_3,Debug Compare Value (FLOW C)" group.long 0xC4++0x03 line.long 0x00 "FMBM_DCV_2_3,Debug Compare Value (FLOW C)" group.long 0xC8++0x03 line.long 0x00 "FMBM_DCV_3_3,Debug Compare Value (FLOW C)" group.long 0xCC++0x03 line.long 0x00 "FMBM_DCV_4_3,Debug Compare Value (FLOW C)" group.long 0xD0++0x03 line.long 0x00 "FMBM_DCM_1_1,Debug Compare Mask (FLOW A)" group.long 0xD4++0x03 line.long 0x00 "FMBM_DCM_2_1,Debug Compare Mask (FLOW A)" group.long 0xD8++0x03 line.long 0x00 "FMBM_DCM_3_1,Debug Compare Mask (FLOW A)" group.long 0xDC++0x03 line.long 0x00 "FMBM_DCM_4_1,Debug Compare Mask (FLOW A)" group.long 0xE0++0x03 line.long 0x00 "FMBM_DCM_1_2,Debug Compare Mask (FLOW B)" group.long 0xE4++0x03 line.long 0x00 "FMBM_DCM_2_2,Debug Compare Mask (FLOW B)" group.long 0xE8++0x03 line.long 0x00 "FMBM_DCM_3_2,Debug Compare Mask (FLOW B)" group.long 0xEC++0x03 line.long 0x00 "FMBM_DCM_4_2,Debug Compare Mask (FLOW B)" group.long 0xF0++0x03 line.long 0x00 "FMBM_DCM_1_3,Debug Compare Mask (FLOW C)" group.long 0xF4++0x03 line.long 0x00 "FMBM_DCM_2_3,Debug Compare Mask (FLOW C)" group.long 0xF8++0x03 line.long 0x00 "FMBM_DCM_3_3,Debug Compare Mask (FLOW C)" group.long 0xFC++0x03 line.long 0x00 "FMBM_DCM_4_3,Debug Compare Mask (FLOW C)" group.long 0x100++0x03 line.long 0x00 "FMBM_GDE,Global Debug Enable" bitfld.long 0x00 31. " EDE ,External debug enable" "Disabled,Enabled" bitfld.long 0x00 30. " IDE ,Internal debug enable" "Disabled,Enabled" newline group.long 0x104++0x03 line.long 0x00 "FMBM_PP_1,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x108++0x03 line.long 0x00 "FMBM_PP_2,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x10C++0x03 line.long 0x00 "FMBM_PP_3,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x110++0x03 line.long 0x00 "FMBM_PP_4,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x114++0x03 line.long 0x00 "FMBM_PP_5,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x118++0x03 line.long 0x00 "FMBM_PP_6,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x11C++0x03 line.long 0x00 "FMBM_PP_7,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x120++0x03 line.long 0x00 "FMBM_PP_8,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x124++0x03 line.long 0x00 "FMBM_PP_9,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x128++0x03 line.long 0x00 "FMBM_PP_10,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x12C++0x03 line.long 0x00 "FMBM_PP_11,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x130++0x03 line.long 0x00 "FMBM_PP_12,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x134++0x03 line.long 0x00 "FMBM_PP_13,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x138++0x03 line.long 0x00 "FMBM_PP_14,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x13C++0x03 line.long 0x00 "FMBM_PP_15,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x140++0x03 line.long 0x00 "FMBM_PP_16,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x144++0x03 line.long 0x00 "FMBM_PP_17,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1A0++0x03 line.long 0x00 "FMBM_PP_40,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1A4++0x03 line.long 0x00 "FMBM_PP_41,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1A8++0x03 line.long 0x00 "FMBM_PP_42,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1AC++0x03 line.long 0x00 "FMBM_PP_43,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1B0++0x03 line.long 0x00 "FMBM_PP_44,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1B4++0x03 line.long 0x00 "FMBM_PP_45,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1B8++0x03 line.long 0x00 "FMBM_PP_46,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1BC++0x03 line.long 0x00 "FMBM_PP_47,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1C0++0x03 line.long 0x00 "FMBM_PP_48,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x1C4++0x03 line.long 0x00 "FMBM_PP_49,Port Parameters" bitfld.long 0x00 24.--29. " MXT ,Maximum number of tasks" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--19. " EXT ,Extra number of tasks" "None,1,2,3,4,5,6,7,8,?..." bitfld.long 0x00 8.--11. " MXD ,Max DMA" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" group.long 0x204++0x03 line.long 0x00 "FMBM_PFS_1,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x208++0x03 line.long 0x00 "FMBM_PFS_2,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x20C++0x03 line.long 0x00 "FMBM_PFS_3,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x210++0x03 line.long 0x00 "FMBM_PFS_4,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x214++0x03 line.long 0x00 "FMBM_PFS_5,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x218++0x03 line.long 0x00 "FMBM_PFS_6,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x21C++0x03 line.long 0x00 "FMBM_PFS_7,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x220++0x03 line.long 0x00 "FMBM_PFS_8,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x224++0x03 line.long 0x00 "FMBM_PFS_9,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x228++0x03 line.long 0x00 "FMBM_PFS_10,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x22C++0x03 line.long 0x00 "FMBM_PFS_11,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x230++0x03 line.long 0x00 "FMBM_PFS_12,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x234++0x03 line.long 0x00 "FMBM_PFS_13,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x238++0x03 line.long 0x00 "FMBM_PFS_14,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x23C++0x03 line.long 0x00 "FMBM_PFS_15,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x240++0x03 line.long 0x00 "FMBM_PFS_16,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x244++0x03 line.long 0x00 "FMBM_PFS_17,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2A0++0x03 line.long 0x00 "FMBM_PFS_40,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2A4++0x03 line.long 0x00 "FMBM_PFS_41,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2A8++0x03 line.long 0x00 "FMBM_PFS_42,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2AC++0x03 line.long 0x00 "FMBM_PFS_43,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2B0++0x03 line.long 0x00 "FMBM_PFS_44,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2B4++0x03 line.long 0x00 "FMBM_PFS_45,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2B8++0x03 line.long 0x00 "FMBM_PFS_46,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2BC++0x03 line.long 0x00 "FMBM_PFS_47,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2C0++0x03 line.long 0x00 "FMBM_PFS_48,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" group.long 0x2C4++0x03 line.long 0x00 "FMBM_PFS_49,Port FIFO Size" hexmask.long.word 0x00 16.--25. 1. " EXBS ,Excessive buffer size" hexmask.long.word 0x00 0.--9. 1. " IFSZ ,Internal FIFO size" newline group.long 0x304++0x03 line.long 0x00 "FMBM_SPICID_1,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x308++0x03 line.long 0x00 "FMBM_SPICID_2,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x30C++0x03 line.long 0x00 "FMBM_SPICID_3,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x310++0x03 line.long 0x00 "FMBM_SPICID_4,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x314++0x03 line.long 0x00 "FMBM_SPICID_5,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x318++0x03 line.long 0x00 "FMBM_SPICID_6,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x31C++0x03 line.long 0x00 "FMBM_SPICID_7,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x320++0x03 line.long 0x00 "FMBM_SPICID_8,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x324++0x03 line.long 0x00 "FMBM_SPICID_9,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x328++0x03 line.long 0x00 "FMBM_SPICID_10,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x32C++0x03 line.long 0x00 "FMBM_SPICID_11,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x330++0x03 line.long 0x00 "FMBM_SPICID_12,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x334++0x03 line.long 0x00 "FMBM_SPICID_13,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x338++0x03 line.long 0x00 "FMBM_SPICID_14,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x33C++0x03 line.long 0x00 "FMBM_SPICID_15,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x340++0x03 line.long 0x00 "FMBM_SPICID_16,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x344++0x03 line.long 0x00 "FMBM_SPICID_17,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3A0++0x03 line.long 0x00 "FMBM_SPICID_40,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3A4++0x03 line.long 0x00 "FMBM_SPICID_41,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3A8++0x03 line.long 0x00 "FMBM_SPICID_42,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3AC++0x03 line.long 0x00 "FMBM_SPICID_43,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3B0++0x03 line.long 0x00 "FMBM_SPICID_44,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3B4++0x03 line.long 0x00 "FMBM_SPICID_45,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3B8++0x03 line.long 0x00 "FMBM_SPICID_46,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3BC++0x03 line.long 0x00 "FMBM_SPICID_47,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3C0++0x03 line.long 0x00 "FMBM_SPICID_48,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" group.long 0x3C4++0x03 line.long 0x00 "FMBM_SPICID_49,SPLICID Register" bitfld.long 0x00 28.--31. " SPBRN ,Storage profile ID bit replacement number" "SPNUM[0:7],SPNUM[0:6];RSPID[5],SPNUM[0:5];RSPID[4:5],SPNUM[0:4];RSPID[3:5],SPNUM[0:3];RSPID[2:5],SPNUM[0:2];RSPID[1:5],SPNUM[0:1];RSPID[0:5],?..." hexmask.long.byte 0x00 16.--23. 1. " SPNUM ,Virtual storage profile base number" hexmask.long.byte 0x00 0.--7. 1. " ICID ,Storage profile isolation context identifier" tree.end width 16. tree "Rx Port Registers" sif cpuis("LS10?6A") tree "Port 1" if (((per.l.be((ad:0x01A00000+0x80000+0x8000)))&0x1000000)==0x1000000) group.long 0x8000++0x03 line.long 0x00 "FMBM_RCFG1,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0x8000++0x03 line.long 0x00 "FMBM_RCFG1,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0x8000+0x4)++0x03 line.long 0x00 "FMBM_RST1,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0x8000+0x08)++0x2B line.long 0x00 "FMBM_RDA1,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP1,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED1,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP1,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM1,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM1,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE1,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA1,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE1,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO1,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP1,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0x8000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_1_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_1_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_1_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_1_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_1_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_1_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_1_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_1_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID1,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID1,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM1,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM1,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0x8000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0x8000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_1_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_1_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_1_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_1_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x8000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_1_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_1_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_1_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_1_4,Allocate Counter" group.long (0x8000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_1_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_1_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_1_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_1_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_1_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_1_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_1_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_1_8,Congestion Group Map" group.long (0x8000+0x180)++0x03 line.long 0x00 "FMBM_RMPD1,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x8000+0x200)++0x27 line.long 0x00 "FMBM_RSTC1,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC1,Rx Frame Counter" line.long 0x08 "FMBM_RBFC1,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC1,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC1,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC1,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC1,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC1,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC1,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x8000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN1,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC1,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC1,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC1,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC1,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC1,Rx Pause Activation Counter" newline group.long (0x8000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_1_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_1_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_1_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x8000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 1" if (((per.l.be((ad:0x01A00000+0x80000+0x8000)))&0x1000000)==0x1000000) group.long 0x8000++0x03 line.long 0x00 "FMBM_RCFG1,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0x8000++0x03 line.long 0x00 "FMBM_RCFG1,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0x8000+0x4)++0x03 line.long 0x00 "FMBM_RST1,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0x8000+0x8)++0x2B line.long 0x00 "FMBM_RDA1,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP1,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED1,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP1,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM1,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM1,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE1,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA1,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE1,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO1,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP1,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0x8000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_1_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_1_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_1_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_1_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_1_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_1_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_1_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_1_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID1,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID1,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM1,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM1,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0x8000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0x8000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_1_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_1_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_1_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_1_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x8000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_1_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_1_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_1_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_1_4,Allocate Counter" group.long (0x8000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_1_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_1_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_1_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_1_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_1_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_1_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_1_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_1_8,Congestion Group Map" group.long (0x8000+0x180)++0x03 line.long 0x00 "FMBM_RMPD1,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x8000+0x200)++0x27 line.long 0x00 "FMBM_RSTC1,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC1,Rx Frame Counter" line.long 0x08 "FMBM_RBFC1,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC1,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC1,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC1,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC1,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC1,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC1,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x8000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN1,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC1,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC1,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC1,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC1,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC1,Rx Pause Activation Counter" newline group.long (0x8000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_1_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_1_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_1_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x8000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 2" if (((per.l.be((ad:0x01A00000+0x80000+0x9000)))&0x1000000)==0x1000000) group.long 0x9000++0x03 line.long 0x00 "FMBM_RCFG2,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0x9000++0x03 line.long 0x00 "FMBM_RCFG2,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0x9000+0x4)++0x03 line.long 0x00 "FMBM_RST2,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0x9000+0x08)++0x2B line.long 0x00 "FMBM_RDA2,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP2,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED2,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP2,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM2,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM2,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE2,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA2,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE2,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO2,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP2,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0x9000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_2_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_2_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_2_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_2_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_2_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_2_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_2_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_2_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID2,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID2,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM2,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM2,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0x9000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0x9000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_2_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_2_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_2_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_2_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x9000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_2_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_2_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_2_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_2_4,Allocate Counter" group.long (0x9000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_2_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_2_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_2_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_2_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_2_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_2_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_2_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_2_8,Congestion Group Map" group.long (0x9000+0x180)++0x03 line.long 0x00 "FMBM_RMPD2,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x9000+0x200)++0x27 line.long 0x00 "FMBM_RSTC2,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC2,Rx Frame Counter" line.long 0x08 "FMBM_RBFC2,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC2,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC2,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC2,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC2,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC2,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC2,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x9000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN2,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC2,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC2,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC2,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC2,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC2,Rx Pause Activation Counter" newline group.long (0x9000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_2_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_2_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_2_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x9000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 2" if (((per.l.be((ad:0x01A00000+0x80000+0x9000)))&0x1000000)==0x1000000) group.long 0x9000++0x03 line.long 0x00 "FMBM_RCFG2,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0x9000++0x03 line.long 0x00 "FMBM_RCFG2,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0x9000+0x4)++0x03 line.long 0x00 "FMBM_RST2,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0x9000+0x8)++0x2B line.long 0x00 "FMBM_RDA2,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP2,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED2,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP2,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM2,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM2,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE2,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA2,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE2,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO2,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP2,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0x9000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_2_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_2_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_2_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_2_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_2_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_2_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_2_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_2_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID2,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID2,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM2,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM2,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0x9000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0x9000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_2_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_2_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_2_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_2_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x9000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_2_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_2_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_2_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_2_4,Allocate Counter" group.long (0x9000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_2_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_2_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_2_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_2_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_2_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_2_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_2_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_2_8,Congestion Group Map" group.long (0x9000+0x180)++0x03 line.long 0x00 "FMBM_RMPD2,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x9000+0x200)++0x27 line.long 0x00 "FMBM_RSTC2,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC2,Rx Frame Counter" line.long 0x08 "FMBM_RBFC2,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC2,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC2,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC2,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC2,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC2,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC2,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x9000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN2,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC2,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC2,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC2,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC2,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC2,Rx Pause Activation Counter" newline group.long (0x9000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_2_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_2_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_2_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x9000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 3" if (((per.l.be((ad:0x01A00000+0x80000+0xA000)))&0x1000000)==0x1000000) group.long 0xA000++0x03 line.long 0x00 "FMBM_RCFG3,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0xA000++0x03 line.long 0x00 "FMBM_RCFG3,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0xA000+0x4)++0x03 line.long 0x00 "FMBM_RST3,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0xA000+0x08)++0x2B line.long 0x00 "FMBM_RDA3,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP3,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED3,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP3,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM3,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM3,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE3,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA3,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE3,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO3,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP3,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0xA000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_3_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_3_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_3_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_3_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_3_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_3_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_3_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_3_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID3,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID3,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM3,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM3,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0xA000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0xA000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_3_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_3_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_3_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_3_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xA000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_3_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_3_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_3_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_3_4,Allocate Counter" group.long (0xA000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_3_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_3_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_3_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_3_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_3_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_3_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_3_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_3_8,Congestion Group Map" group.long (0xA000+0x180)++0x03 line.long 0x00 "FMBM_RMPD3,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xA000+0x200)++0x27 line.long 0x00 "FMBM_RSTC3,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC3,Rx Frame Counter" line.long 0x08 "FMBM_RBFC3,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC3,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC3,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC3,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC3,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC3,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC3,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xA000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN3,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC3,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC3,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC3,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC3,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC3,Rx Pause Activation Counter" newline group.long (0xA000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_3_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_3_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_3_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xA000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 3" if (((per.l.be((ad:0x01A00000+0x80000+0xA000)))&0x1000000)==0x1000000) group.long 0xA000++0x03 line.long 0x00 "FMBM_RCFG3,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0xA000++0x03 line.long 0x00 "FMBM_RCFG3,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0xA000+0x4)++0x03 line.long 0x00 "FMBM_RST3,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0xA000+0x8)++0x2B line.long 0x00 "FMBM_RDA3,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP3,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED3,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP3,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM3,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM3,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE3,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA3,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE3,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO3,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP3,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0xA000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_3_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_3_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_3_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_3_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_3_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_3_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_3_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_3_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID3,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID3,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM3,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM3,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0xA000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0xA000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_3_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_3_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_3_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_3_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xA000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_3_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_3_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_3_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_3_4,Allocate Counter" group.long (0xA000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_3_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_3_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_3_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_3_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_3_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_3_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_3_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_3_8,Congestion Group Map" group.long (0xA000+0x180)++0x03 line.long 0x00 "FMBM_RMPD3,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xA000+0x200)++0x27 line.long 0x00 "FMBM_RSTC3,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC3,Rx Frame Counter" line.long 0x08 "FMBM_RBFC3,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC3,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC3,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC3,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC3,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC3,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC3,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xA000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN3,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC3,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC3,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC3,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC3,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC3,Rx Pause Activation Counter" newline group.long (0xA000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_3_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_3_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_3_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xA000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 4" if (((per.l.be((ad:0x01A00000+0x80000+0xB000)))&0x1000000)==0x1000000) group.long 0xB000++0x03 line.long 0x00 "FMBM_RCFG4,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0xB000++0x03 line.long 0x00 "FMBM_RCFG4,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0xB000+0x4)++0x03 line.long 0x00 "FMBM_RST4,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0xB000+0x08)++0x2B line.long 0x00 "FMBM_RDA4,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP4,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED4,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP4,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM4,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM4,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE4,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA4,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE4,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO4,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP4,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0xB000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_4_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_4_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_4_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_4_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_4_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_4_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_4_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_4_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID4,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID4,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM4,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM4,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0xB000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0xB000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_4_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_4_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_4_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_4_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xB000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_4_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_4_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_4_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_4_4,Allocate Counter" group.long (0xB000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_4_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_4_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_4_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_4_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_4_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_4_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_4_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_4_8,Congestion Group Map" group.long (0xB000+0x180)++0x03 line.long 0x00 "FMBM_RMPD4,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xB000+0x200)++0x27 line.long 0x00 "FMBM_RSTC4,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC4,Rx Frame Counter" line.long 0x08 "FMBM_RBFC4,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC4,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC4,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC4,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC4,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC4,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC4,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xB000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN4,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC4,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC4,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC4,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC4,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC4,Rx Pause Activation Counter" newline group.long (0xB000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_4_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_4_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_4_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xB000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 4" if (((per.l.be((ad:0x01A00000+0x80000+0xB000)))&0x1000000)==0x1000000) group.long 0xB000++0x03 line.long 0x00 "FMBM_RCFG4,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0xB000++0x03 line.long 0x00 "FMBM_RCFG4,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0xB000+0x4)++0x03 line.long 0x00 "FMBM_RST4,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0xB000+0x8)++0x2B line.long 0x00 "FMBM_RDA4,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP4,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED4,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP4,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM4,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM4,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE4,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA4,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE4,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO4,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP4,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0xB000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_4_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_4_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_4_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_4_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_4_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_4_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_4_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_4_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID4,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID4,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM4,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM4,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0xB000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0xB000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_4_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_4_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_4_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_4_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xB000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_4_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_4_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_4_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_4_4,Allocate Counter" group.long (0xB000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_4_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_4_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_4_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_4_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_4_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_4_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_4_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_4_8,Congestion Group Map" group.long (0xB000+0x180)++0x03 line.long 0x00 "FMBM_RMPD4,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xB000+0x200)++0x27 line.long 0x00 "FMBM_RSTC4,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC4,Rx Frame Counter" line.long 0x08 "FMBM_RBFC4,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC4,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC4,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC4,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC4,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC4,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC4,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xB000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN4,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC4,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC4,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC4,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC4,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC4,Rx Pause Activation Counter" newline group.long (0xB000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_4_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_4_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_4_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xB000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 5" if (((per.l.be((ad:0x01A00000+0x80000+0xC000)))&0x1000000)==0x1000000) group.long 0xC000++0x03 line.long 0x00 "FMBM_RCFG5,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0xC000++0x03 line.long 0x00 "FMBM_RCFG5,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0xC000+0x4)++0x03 line.long 0x00 "FMBM_RST5,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0xC000+0x08)++0x2B line.long 0x00 "FMBM_RDA5,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP5,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED5,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP5,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM5,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM5,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE5,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA5,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE5,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO5,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP5,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0xC000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_5_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_5_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_5_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_5_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_5_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_5_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_5_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_5_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID5,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID5,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM5,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM5,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0xC000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0xC000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_5_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_5_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_5_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_5_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xC000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_5_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_5_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_5_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_5_4,Allocate Counter" group.long (0xC000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_5_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_5_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_5_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_5_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_5_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_5_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_5_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_5_8,Congestion Group Map" group.long (0xC000+0x180)++0x03 line.long 0x00 "FMBM_RMPD5,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xC000+0x200)++0x27 line.long 0x00 "FMBM_RSTC5,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC5,Rx Frame Counter" line.long 0x08 "FMBM_RBFC5,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC5,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC5,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC5,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC5,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC5,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC5,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xC000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN5,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC5,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC5,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC5,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC5,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC5,Rx Pause Activation Counter" newline group.long (0xC000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_5_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_5_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_5_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xC000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 5" if (((per.l.be((ad:0x01A00000+0x80000+0xC000)))&0x1000000)==0x1000000) group.long 0xC000++0x03 line.long 0x00 "FMBM_RCFG5,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0xC000++0x03 line.long 0x00 "FMBM_RCFG5,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0xC000+0x4)++0x03 line.long 0x00 "FMBM_RST5,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0xC000+0x8)++0x2B line.long 0x00 "FMBM_RDA5,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP5,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED5,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP5,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM5,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM5,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE5,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA5,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE5,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO5,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP5,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0xC000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_5_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_5_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_5_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_5_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_5_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_5_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_5_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_5_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID5,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID5,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM5,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM5,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0xC000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0xC000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_5_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_5_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_5_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_5_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xC000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_5_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_5_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_5_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_5_4,Allocate Counter" group.long (0xC000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_5_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_5_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_5_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_5_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_5_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_5_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_5_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_5_8,Congestion Group Map" group.long (0xC000+0x180)++0x03 line.long 0x00 "FMBM_RMPD5,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xC000+0x200)++0x27 line.long 0x00 "FMBM_RSTC5,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC5,Rx Frame Counter" line.long 0x08 "FMBM_RBFC5,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC5,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC5,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC5,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC5,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC5,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC5,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xC000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN5,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC5,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC5,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC5,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC5,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC5,Rx Pause Activation Counter" newline group.long (0xC000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_5_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_5_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_5_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xC000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 6" if (((per.l.be((ad:0x01A00000+0x80000+0xD000)))&0x1000000)==0x1000000) group.long 0xD000++0x03 line.long 0x00 "FMBM_RCFG6,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0xD000++0x03 line.long 0x00 "FMBM_RCFG6,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0xD000+0x4)++0x03 line.long 0x00 "FMBM_RST6,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0xD000+0x08)++0x2B line.long 0x00 "FMBM_RDA6,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP6,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED6,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP6,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM6,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM6,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE6,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA6,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE6,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO6,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP6,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0xD000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_6_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_6_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_6_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_6_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_6_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_6_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_6_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_6_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID6,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID6,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM6,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM6,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0xD000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0xD000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_6_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_6_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_6_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_6_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xD000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_6_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_6_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_6_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_6_4,Allocate Counter" group.long (0xD000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_6_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_6_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_6_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_6_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_6_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_6_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_6_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_6_8,Congestion Group Map" group.long (0xD000+0x180)++0x03 line.long 0x00 "FMBM_RMPD6,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xD000+0x200)++0x27 line.long 0x00 "FMBM_RSTC6,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC6,Rx Frame Counter" line.long 0x08 "FMBM_RBFC6,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC6,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC6,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC6,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC6,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC6,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC6,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xD000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN6,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC6,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC6,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC6,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC6,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC6,Rx Pause Activation Counter" newline group.long (0xD000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_6_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_6_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_6_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xD000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 6" if (((per.l.be((ad:0x01A00000+0x80000+0xD000)))&0x1000000)==0x1000000) group.long 0xD000++0x03 line.long 0x00 "FMBM_RCFG6,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0xD000++0x03 line.long 0x00 "FMBM_RCFG6,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0xD000+0x4)++0x03 line.long 0x00 "FMBM_RST6,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0xD000+0x8)++0x2B line.long 0x00 "FMBM_RDA6,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP6,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED6,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP6,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM6,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM6,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE6,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA6,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE6,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO6,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP6,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0xD000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_6_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_6_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_6_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_6_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_6_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_6_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_6_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_6_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID6,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID6,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM6,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM6,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0xD000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0xD000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_6_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_6_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_6_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_6_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0xD000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_6_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_6_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_6_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_6_4,Allocate Counter" group.long (0xD000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_6_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_6_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_6_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_6_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_6_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_6_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_6_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_6_8,Congestion Group Map" group.long (0xD000+0x180)++0x03 line.long 0x00 "FMBM_RMPD6,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0xD000+0x200)++0x27 line.long 0x00 "FMBM_RSTC6,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC6,Rx Frame Counter" line.long 0x08 "FMBM_RBFC6,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC6,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC6,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC6,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC6,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC6,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC6,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0xD000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN6,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC6,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC6,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC6,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC6,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC6,Rx Pause Activation Counter" newline group.long (0xD000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_6_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_6_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_6_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0xD000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "Port 9" if (((per.l.be((ad:0x01A00000+0x80000+0x10000)))&0x1000000)==0x1000000) group.long 0x10000++0x03 line.long 0x00 "FMBM_RCFG9,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0x10000++0x03 line.long 0x00 "FMBM_RCFG9,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0x10000+0x4)++0x03 line.long 0x00 "FMBM_RST9,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0x10000+0x08)++0x2B line.long 0x00 "FMBM_RDA9,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP9,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED9,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP9,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM9,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM9,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE9,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA9,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE9,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO9,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP9,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0x10000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_9_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_9_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_9_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_9_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_9_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_9_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_9_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_9_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID9,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID9,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM9,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM9,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0x10000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0x10000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_9_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_9_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_9_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_9_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x10000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_9_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_9_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_9_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_9_4,Allocate Counter" group.long (0x10000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_9_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_9_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_9_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_9_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_9_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_9_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_9_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_9_8,Congestion Group Map" group.long (0x10000+0x180)++0x03 line.long 0x00 "FMBM_RMPD9,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x10000+0x200)++0x27 line.long 0x00 "FMBM_RSTC9,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC9,Rx Frame Counter" line.long 0x08 "FMBM_RBFC9,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC9,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC9,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC9,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC9,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC9,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC9,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x10000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN9,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC9,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC9,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC9,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC9,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC9,Rx Pause Activation Counter" newline group.long (0x10000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_9_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_9_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_9_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x10000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 9" if (((per.l.be((ad:0x01A00000+0x80000+0x10000)))&0x1000000)==0x1000000) group.long 0x10000++0x03 line.long 0x00 "FMBM_RCFG9,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" else group.long 0x10000++0x03 line.long 0x00 "FMBM_RCFG9,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame Discard Override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent Mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate Mode" "Normal,Accumulate" endif rgroup.long (0x10000+0x4)++0x03 line.long 0x00 "FMBM_RST9,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx Port ID" group.long (0x10000+0x8)++0x2B line.long 0x00 "FMBM_RDA9,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP9,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority Elevation Level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED9,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop Frame's End Data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP9,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM9,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM9,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter Gather Disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer Start Margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer End Margin" line.long 0x18 "FMBM_RFNE9,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD Command bits Set" bitfld.long 0x18 23. " ORR ,Order Restoration Required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action Code" line.long 0x1C "FMBM_RFCA9,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE9,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action Code" line.long 0x24 "FMBM_RPSO9,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 1. " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP9,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame Write Disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer Profile" group.long (0x10000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_9_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_9_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_9_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_9_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_9_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_9_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_9_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_9_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID9,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_REFQID9,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" newline line.long 0x28 "FMBM_RFSDM9,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM9,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" group.long (0x10000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" newline group.long (0x10000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_9_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x04 "FMBM_EBMPI_9_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x08 "FMBM_EBMPI_9_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool Buffer Size" line.long 0x0C "FMBM_EBMPI_9_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate Counter Enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup Pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x10000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_9_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_9_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_9_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_9_4,Allocate Counter" group.long (0x10000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_9_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_9_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_9_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_9_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_9_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_9_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_9_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_9_8,Congestion Group Map" group.long (0x10000+0x180)++0x03 line.long 0x00 "FMBM_RMPD9,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 Enable" "Disabled,Enabled" bitfld.long 0x00 30. " NBPDE[1] ,Pool ID configured in EBMPI2 Enable" "Disabled,Enabled" bitfld.long 0x00 29. " NBPDE[2] ,Pool ID configured in EBMPI3 Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " NBPDE[3] ,Pool ID configured in EBMPI4 Enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of Buffer Pools Depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb Priority Enable Vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " SBPD[1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " SBPD[2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " SBPD[3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x10000+0x200)++0x27 line.long 0x00 "FMBM_RSTC9,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC9,Rx Frame Counter" line.long 0x08 "FMBM_RBFC9,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC9,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC9,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC9,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC9,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC9,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC9,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x10000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_RCCN9,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC9,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC9,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC9,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC9,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC9,Rx Pause Activation Counter" newline group.long (0x10000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_9_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_9_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_9_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x10000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 10" if (((per.l.be((ad:0x01A00000+0x80000+0x11000)))&0x1000000)==0x1000000) group.long 0x11000++0x03 line.long 0x00 "FMBM_RCFG10,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Ignore errors" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" else group.long 0x11000++0x03 line.long 0x00 "FMBM_RCFG10,Rx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDOVR ,Frame discard override" "Discard,Enqueue" bitfld.long 0x00 24. " IM ,Independent mode" "Normal,Independent" bitfld.long 0x00 6. " AM ,Accumulate mode" "Normal,Accumulate" endif rgroup.long (0x11000+0x4)++0x03 line.long 0x00 "FMBM_RST10,Rx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " RPID ,Rx port ID" group.long (0x11000+0x08)++0x2B line.long 0x00 "FMBM_RDA10,Rx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,Scatter gather write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_RFP10,Rx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " PEL ,Priority elevation level" hexmask.long.word 0x04 0.--9. 1. " FTH ,FIFO threshold" line.long 0x08 "FMBM_RFED10,Rx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum ignore" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." bitfld.long 0x08 16.--20. " CFED ,Chop frame's end data" "None,Last 1 byte,Last 2 bytes,Last 3 bytes,Last 4 bytes,Last 5 bytes,Last 6 bytes,Last 7 bytes,Last 8 bytes,Last 9 bytes,Last 10 bytes,Last 11 bytes,Last 12 bytes,Last 13 bytes,Last 14 bytes,Last 15 bytes,Last 16 bytes,?..." line.long 0x0C "FMBM_RICP10,Rx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal context external offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal context internal offset" "Beginning,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal context copy size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_RIM10,Rx Internal Margins" bitfld.long 0x10 28.--31. " FOF ,Frame offset" "Start address,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." line.long 0x14 "FMBM_REBM10,Rx External Buffer Margins" bitfld.long 0x14 31. " SGD ,Scatter gather disable" "No,Yes" newline hexmask.long.word 0x14 16.--24. 1. " BSM ,Buffer start margin" hexmask.long.word 0x14 0.--8. 1. " BEM ,Buffer end margin" line.long 0x18 "FMBM_RFNE10,Rx Frame Next Engine" hexmask.long.byte 0x18 24.--31. 1. " FDCS ,FD command bits set" bitfld.long 0x18 23. " ORR ,Order restoration required" "Not required,Required" newline bitfld.long 0x18 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x18 0.--17. 1. " AC ,Action code" line.long 0x1C "FMBM_RFCA10,Rx Frame Attributes" bitfld.long 0x1C 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x1C 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x1C 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Synchronization request,?..." hexmask.long.byte 0x1C 16.--21. 1. " MR ,Mode attributes" line.long 0x20 "FMBM_RFPNE10,Rx Frame Parser Next Engine" hexmask.long.tbyte 0x20 0.--23. 1. " AC ,Action code" line.long 0x24 "FMBM_RPSO10,Parsing Start Offset" hexmask.long.byte 0x24 0.--7. 0x01 " PSO ,Parsing start offset" line.long 0x28 "FMBM_RPP10,Rx Policer Profile" bitfld.long 0x28 31. " EBD ,External buffer deallocation" "Not deallocated,Deallocated" bitfld.long 0x28 30. " EBAD ,External buffer allocation disable" "Enabled,Disabled" bitfld.long 0x28 29. " FWD ,Frame write disable" "Enabled,Disabled" newline bitfld.long 0x28 28. " NL ,Not last (continuous mode)" "Disabled,Enabled" bitfld.long 0x28 27. " CWD ,Context write disable" "Enabled,Disabled" bitfld.long 0x28 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" newline bitfld.long 0x28 24. " VSPE ,Virtual storage profile enable" "Disabled,Enabled" hexmask.long.byte 0x28 0.--7. 1. " PNUM ,Policer profile" group.long (0x11000+0x40)++0x33 line.long 0x00 "FMBM_RPRI_10_1,Rx Parse Results Array Initialization" line.long 0x04 "FMBM_RPRI_10_2,Rx Parse Results Array Initialization" line.long 0x08 "FMBM_RPRI_10_3,Rx Parse Results Array Initialization" line.long 0x0C "FMBM_RPRI_10_4,Rx Parse Results Array Initialization" line.long 0x10 "FMBM_RPRI_10_5,Rx Parse Results Array Initialization" line.long 0x14 "FMBM_RPRI_10_6,Rx Parse Results Array Initialization" line.long 0x18 "FMBM_RPRI_10_7,Rx Parse Results Array Initialization" line.long 0x1C "FMBM_RPRI_10_8,Rx Parse Results Array Initialization" line.long 0x20 "FMBM_RFQID10,Rx Frame Queue ID" hexmask.long.byte 0x20 24.--29. 1. " RSPID ,Default relative storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default frame queue ID" line.long 0x24 "FMBM_REFQID10,Rx Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error frame queue ID" newline line.long 0x28 "FMBM_RFSDM10,Rx Frame Status Discard Mask" bitfld.long 0x28 31. " FSDM[31:0] ,Frame status discard mask bit 0" "0,1" bitfld.long 0x28 30. ",Frame status discard mask bit 1" "0,1" bitfld.long 0x28 29. ",Frame status discard mask bit 2" "0,1" bitfld.long 0x28 28. ",Frame status discard mask bit 3" "0,1" bitfld.long 0x28 27. ",Frame status discard mask bit 4" "0,1" bitfld.long 0x28 26. ",Frame status discard mask bit 5" "0,1" bitfld.long 0x28 25. ",Frame status discard mask bit 6" "0,1" bitfld.long 0x28 24. ",Frame status discard mask bit 7" "0,1" bitfld.long 0x28 23. ",Frame status discard mask bit 8" "0,1" bitfld.long 0x28 22. ",Frame status discard mask bit 9" "0,1" bitfld.long 0x28 21. ",Frame status discard mask bit 10" "0,1" bitfld.long 0x28 20. ",Frame status discard mask bit 11" "0,1" bitfld.long 0x28 19. ",Frame status discard mask bit 12" "0,1" bitfld.long 0x28 18. ",Frame status discard mask bit 13" "0,1" bitfld.long 0x28 17. ",Frame status discard mask bit 14" "0,1" bitfld.long 0x28 16. ",Frame status discard mask bit 15" "0,1" bitfld.long 0x28 15. ",Frame status discard mask bit 16" "0,1" bitfld.long 0x28 14. ",Frame status discard mask bit 17" "0,1" bitfld.long 0x28 13. ",Frame status discard mask bit 18" "0,1" bitfld.long 0x28 12. ",Frame status discard mask bit 19" "0,1" bitfld.long 0x28 11. ",Frame status discard mask bit 20" "0,1" bitfld.long 0x28 10. ",Frame status discard mask bit 21" "0,1" bitfld.long 0x28 9. ",Frame status discard mask bit 22" "0,1" bitfld.long 0x28 8. ",Frame status discard mask bit 23" "0,1" bitfld.long 0x28 7. ",Frame status discard mask bit 24" "0,1" bitfld.long 0x28 6. ",Frame status discard mask bit 25" "0,1" bitfld.long 0x28 5. ",Frame status discard mask bit 26" "0,1" bitfld.long 0x28 4. ",Frame status discard mask bit 27" "0,1" bitfld.long 0x28 3. ",Frame status discard mask bit 28" "0,1" bitfld.long 0x28 2. ",Frame status discard mask bit 29" "0,1" bitfld.long 0x28 1. ",Frame status discard mask bit 30" "0,1" bitfld.long 0x28 0. ",Frame status discard mask bit 31" "0,1" line.long 0x2C "FMBM_RFSEM10,Rx Frame Status Error Mask" bitfld.long 0x2C 31. " FSEM[31:0] ,Frame status error mask bit 0" "0,1" bitfld.long 0x2C 30. ",Frame status error mask bit 1" "0,1" bitfld.long 0x2C 29. ",Frame status error mask bit 2" "0,1" bitfld.long 0x2C 28. ",Frame status error mask bit 3" "0,1" bitfld.long 0x2C 27. ",Frame status error mask bit 4" "0,1" bitfld.long 0x2C 26. ",Frame status error mask bit 5" "0,1" bitfld.long 0x2C 25. ",Frame status error mask bit 6" "0,1" bitfld.long 0x2C 24. ",Frame status error mask bit 7" "0,1" bitfld.long 0x2C 23. ",Frame status error mask bit 8" "0,1" bitfld.long 0x2C 22. ",Frame status error mask bit 9" "0,1" bitfld.long 0x2C 21. ",Frame status error mask bit 10" "0,1" bitfld.long 0x2C 20. ",Frame status error mask bit 11" "0,1" bitfld.long 0x2C 19. ",Frame status error mask bit 12" "0,1" bitfld.long 0x2C 18. ",Frame status error mask bit 13" "0,1" bitfld.long 0x2C 17. ",Frame status error mask bit 14" "0,1" bitfld.long 0x2C 16. ",Frame status error mask bit 15" "0,1" bitfld.long 0x2C 15. ",Frame status error mask bit 16" "0,1" bitfld.long 0x2C 14. ",Frame status error mask bit 17" "0,1" bitfld.long 0x2C 13. ",Frame status error mask bit 18" "0,1" bitfld.long 0x2C 12. ",Frame status error mask bit 19" "0,1" bitfld.long 0x2C 11. ",Frame status error mask bit 20" "0,1" bitfld.long 0x2C 10. ",Frame status error mask bit 21" "0,1" bitfld.long 0x2C 9. ",Frame status error mask bit 22" "0,1" bitfld.long 0x2C 8. ",Frame status error mask bit 23" "0,1" bitfld.long 0x2C 7. ",Frame status error mask bit 24" "0,1" bitfld.long 0x2C 6. ",Frame status error mask bit 25" "0,1" bitfld.long 0x2C 5. ",Frame status error mask bit 26" "0,1" bitfld.long 0x2C 4. ",Frame status error mask bit 27" "0,1" bitfld.long 0x2C 3. ",Frame status error mask bit 28" "0,1" bitfld.long 0x2C 2. ",Frame status error mask bit 29" "0,1" bitfld.long 0x2C 1. ",Frame status error mask bit 30" "0,1" bitfld.long 0x2C 0. ",Frame status error mask bit 31" "0,1" newline line.long 0x30 "FMBM_RFENE,Rx Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action code" group.long (0x11000+0x7C)++0x03 line.long 0x00 "FMBM_RCMNE,Rx Frame Enqueue Next Engine" bitfld.long 0x0 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action code" newline group.long (0x11000+0x100)++0x0F line.long 0x00 "FMBM_EBMPI_10_1,External Buffers Manager Pool Information" bitfld.long 0x00 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x00 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x00 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x00 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x00 0.--15. 1. " PBS ,Pool buffer Size" line.long 0x04 "FMBM_EBMPI_10_2,External Buffers Manager Pool Information" bitfld.long 0x04 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x04 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x04 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x04 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x04 0.--15. 1. " PBS ,Pool buffer size" line.long 0x08 "FMBM_EBMPI_10_3,External Buffers Manager Pool Information" bitfld.long 0x08 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x08 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x08 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x08 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x08 0.--15. 1. " PBS ,Pool buffer size" line.long 0x0C "FMBM_EBMPI_10_4,External Buffers Manager Pool Information" bitfld.long 0x0C 31. " VAL ,Valid" "Invalid,Valid" bitfld.long 0x0C 30. " ACE ,Allocate counter enable" "Disabled,Enabled" bitfld.long 0x0C 29. " BP ,Backup pool" "Regular,Backup" hexmask.long.byte 0x0C 16.--21. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--15. 1. " PBS ,Pool buffer size" group.long (0x11000+0x120)++0x0F line.long 0x00 "FMBM_RACNT_10_1,Allocate Counter" line.long 0x04 "FMBM_RACNT_10_2,Allocate Counter" line.long 0x08 "FMBM_RACNT_10_3,Allocate Counter" line.long 0x0C "FMBM_RACNT_10_4,Allocate Counter" group.long (0x11000+0x160)++0x1F line.long 0x00 "FMBM_RCGM_10_1,Congestion Group Map" line.long 0x04 "FMBM_RCGM_10_2,Congestion Group Map" line.long 0x08 "FMBM_RCGM_10_3,Congestion Group Map" line.long 0x0C "FMBM_RCGM_10_4,Congestion Group Map" line.long 0x10 "FMBM_RCGM_10_5,Congestion Group Map" line.long 0x14 "FMBM_RCGM_10_6,Congestion Group Map" line.long 0x18 "FMBM_RCGM_10_7,Congestion Group Map" line.long 0x1C "FMBM_RCGM_10_8,Congestion Group Map" group.long (0x11000+0x180)++0x03 line.long 0x00 "FMBM_RMPD10,BMan Pool Depletion" bitfld.long 0x00 31. " NBPDE[0] ,Pool ID configured in EBMPI1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pool ID configured in EBMPI2 enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pool ID configured in EBMPI3 enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " [3] ,Pool ID configured in EBMPI4 enable" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " NBPD ,Number of buffer pools depleted" "1,2,3,4,5,6,7,8" newline hexmask.long.byte 0x00 8.--15. 1. " PFCPEV ,802.1Qbb priority enable vector" newline bitfld.long 0x00 7. " SBPD[0] ,Pause frame signal enable if pool ID configured in EBMPI1 is depleted" "Disabled,Enabled" bitfld.long 0x00 6. " [1] ,Pause frame signal enable if pool ID configured in EBMPI2 is depleted" "Disabled,Enabled" bitfld.long 0x00 5. " [2] ,Pause frame signal enable if pool ID configured in EBMPI3 is depleted" "Disabled,Enabled" newline bitfld.long 0x00 4. " [3] ,Pause frame signal enable if pool ID configured in EBMPI4 is depleted" "Disabled,Enabled" group.long (0x11000+0x200)++0x27 line.long 0x00 "FMBM_RSTC10,Rx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable statistics counters" "Disabled,Enabled" line.long 0x04 "FMBM_RFRC10,Rx Frame Counter" line.long 0x08 "FMBM_RBFC10,Rx Bad Frames Counter" line.long 0x0C "FMBM_RLFC10,Rx Large Frames Counter" line.long 0x10 "FMBM_RFFC10,Rx Filter Frames Counter" line.long 0x14 "FMBM_RFDC10,Rx Frames Discard Counter" line.long 0x18 "FMBM_RFLDEC10,Rx Frames List DMA Error Counter" line.long 0x1C "FMBM_RODC10,Rx Out of Buffers Discard Counter" line.long 0x20 "FMBM_RBDC10,Rx Buffers Deallocate Counter" line.long 0x24 "FMBM_RPEC,RX Prepare to Enqueue Counter" group.long (0x11000+0x280)++0x1F line.long 0x00 "FMBM_RPC,Rx Performance Counters" bitfld.long 0x00 31. " EN ,Enable performance counters" "Disabled,Enabled" line.long 0x04 "FMBM_RPCP,Rx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" hexmask.long.byte 0x04 16.--21. 1. " RCV ,Receive compare value" bitfld.long 0x04 12.--15. " DCV ,DMA compare value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO utilization compare value" line.long 0x08 "FMBM_RCCN10,Rx Cycle Counter" line.long 0x0C "FMBM_RTUC10,Rx Tasks Utilization Counter" line.long 0x10 "FMBM_RRQUC10,Rx Receive Queue Utilization Counter" line.long 0x14 "FMBM_RDUC10,Rx DMA Utilization Counter" line.long 0x18 "FMBM_RFUC10,Rx FIFO Utilization Counter" line.long 0x1C "FMBM_RPAC10,Rx Pause Activation Counter" newline group.long (0x11000+0x300)++0x0B line.long 0x00 "FMBM_RDCFG_10_1,Rx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x00 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_RDCFG_10_2,Rx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x04 24.--25. " TL ,Trace level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_RDCFG_10_3,Rx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare operator" "Trap disabled,Always match,(comp&mask)==(frame FD&mask),?..." newline bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "External memory,Debug port,External memory and Nexus,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug trace offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x11000+0x30C)++0x03 line.long 0x00 "FMBM_RGPR,Rx General Purpose Register" tree.end elif cpuis("LS10?3A") endif tree.end tree "Tx Port Registers" sif cpuis("LS10?6A") tree "Port 1" group.long 0x28000++0x03 line.long 0x00 "FMBM_TCFG1,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x28000+0x04)++0x03 line.long 0x00 "FMBM_TST1,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x28000+0x08)++0x2F line.long 0x00 "FMBM_TDA1,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP1,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED1,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP1,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE1,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA1,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID1,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID1,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE1,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS1,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT1,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x28000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x28000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_1,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x28000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x28000+0x200)++0x17 line.long 0x00 "FMBM_TSTC1,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC1,Tx Frame Counter" line.long 0x08 "FMBM_TFDC1,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC1,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC1,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC1,Tx Buffers Deallocate Counter" group.long (0x28000+0x280)++0x1B line.long 0x00 "FMBM_TPC1,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP1,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN1,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC1,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC1,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC1,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC1,Tx FIFO Utilization Counter" newline group.long (0x28000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_1_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_1_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_1_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x28000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 1" group.long 0x28000++0x03 line.long 0x00 "FMBM_TCFG1,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x28000+0x04)++0x03 line.long 0x00 "FMBM_TST1,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x28000+0x08)++0x2F line.long 0x00 "FMBM_TDA1,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP1,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED1,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP1,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE1,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA1,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID1,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID1,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE1,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS1,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT1,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x28000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x28000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_1,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x28000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x28000+0x200)++0x17 line.long 0x00 "FMBM_TSTC1,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC1,Tx Frame Counter" line.long 0x08 "FMBM_TFDC1,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC1,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC1,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC1,Tx Buffers Deallocate Counter" group.long (0x28000+0x280)++0x1B line.long 0x00 "FMBM_TPC1,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP1,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN1,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC1,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC1,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC1,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC1,Tx FIFO Utilization Counter" newline group.long (0x28000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_1_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_1_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_1_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x28000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 2" group.long 0x29000++0x03 line.long 0x00 "FMBM_TCFG2,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x29000+0x04)++0x03 line.long 0x00 "FMBM_TST2,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x29000+0x08)++0x2F line.long 0x00 "FMBM_TDA2,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP2,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED2,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP2,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE2,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA2,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID2,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID2,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE2,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS2,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT2,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x29000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x29000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_2,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x29000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x29000+0x200)++0x17 line.long 0x00 "FMBM_TSTC2,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC2,Tx Frame Counter" line.long 0x08 "FMBM_TFDC2,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC2,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC2,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC2,Tx Buffers Deallocate Counter" group.long (0x29000+0x280)++0x1B line.long 0x00 "FMBM_TPC2,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP2,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN2,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC2,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC2,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC2,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC2,Tx FIFO Utilization Counter" newline group.long (0x29000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_2_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_2_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_2_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x29000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 2" group.long 0x29000++0x03 line.long 0x00 "FMBM_TCFG2,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x29000+0x04)++0x03 line.long 0x00 "FMBM_TST2,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x29000+0x08)++0x2F line.long 0x00 "FMBM_TDA2,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP2,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED2,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP2,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE2,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA2,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID2,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID2,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE2,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS2,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT2,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x29000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x29000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_2,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x29000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x29000+0x200)++0x17 line.long 0x00 "FMBM_TSTC2,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC2,Tx Frame Counter" line.long 0x08 "FMBM_TFDC2,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC2,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC2,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC2,Tx Buffers Deallocate Counter" group.long (0x29000+0x280)++0x1B line.long 0x00 "FMBM_TPC2,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP2,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN2,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC2,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC2,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC2,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC2,Tx FIFO Utilization Counter" newline group.long (0x29000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_2_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_2_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_2_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x29000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 3" group.long 0x2A000++0x03 line.long 0x00 "FMBM_TCFG3,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2A000+0x04)++0x03 line.long 0x00 "FMBM_TST3,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2A000+0x08)++0x2F line.long 0x00 "FMBM_TDA3,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP3,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED3,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP3,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE3,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA3,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID3,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID3,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE3,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS3,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT3,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2A000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2A000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_3,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2A000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2A000+0x200)++0x17 line.long 0x00 "FMBM_TSTC3,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC3,Tx Frame Counter" line.long 0x08 "FMBM_TFDC3,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC3,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC3,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC3,Tx Buffers Deallocate Counter" group.long (0x2A000+0x280)++0x1B line.long 0x00 "FMBM_TPC3,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP3,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN3,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC3,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC3,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC3,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC3,Tx FIFO Utilization Counter" newline group.long (0x2A000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_3_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_3_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_3_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2A000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 3" group.long 0x2A000++0x03 line.long 0x00 "FMBM_TCFG3,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2A000+0x04)++0x03 line.long 0x00 "FMBM_TST3,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2A000+0x08)++0x2F line.long 0x00 "FMBM_TDA3,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP3,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED3,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP3,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE3,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA3,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID3,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID3,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE3,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS3,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT3,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2A000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2A000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_3,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2A000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2A000+0x200)++0x17 line.long 0x00 "FMBM_TSTC3,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC3,Tx Frame Counter" line.long 0x08 "FMBM_TFDC3,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC3,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC3,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC3,Tx Buffers Deallocate Counter" group.long (0x2A000+0x280)++0x1B line.long 0x00 "FMBM_TPC3,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP3,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN3,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC3,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC3,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC3,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC3,Tx FIFO Utilization Counter" newline group.long (0x2A000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_3_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_3_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_3_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2A000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 4" group.long 0x2B000++0x03 line.long 0x00 "FMBM_TCFG4,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2B000+0x04)++0x03 line.long 0x00 "FMBM_TST4,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2B000+0x08)++0x2F line.long 0x00 "FMBM_TDA4,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP4,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED4,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP4,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE4,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA4,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID4,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID4,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE4,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS4,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT4,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2B000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2B000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_4,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2B000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2B000+0x200)++0x17 line.long 0x00 "FMBM_TSTC4,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC4,Tx Frame Counter" line.long 0x08 "FMBM_TFDC4,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC4,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC4,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC4,Tx Buffers Deallocate Counter" group.long (0x2B000+0x280)++0x1B line.long 0x00 "FMBM_TPC4,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP4,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN4,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC4,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC4,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC4,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC4,Tx FIFO Utilization Counter" newline group.long (0x2B000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_4_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_4_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_4_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2B000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 4" group.long 0x2B000++0x03 line.long 0x00 "FMBM_TCFG4,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2B000+0x04)++0x03 line.long 0x00 "FMBM_TST4,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2B000+0x08)++0x2F line.long 0x00 "FMBM_TDA4,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP4,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED4,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP4,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE4,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA4,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID4,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID4,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE4,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS4,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT4,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2B000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2B000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_4,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2B000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2B000+0x200)++0x17 line.long 0x00 "FMBM_TSTC4,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC4,Tx Frame Counter" line.long 0x08 "FMBM_TFDC4,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC4,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC4,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC4,Tx Buffers Deallocate Counter" group.long (0x2B000+0x280)++0x1B line.long 0x00 "FMBM_TPC4,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP4,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN4,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC4,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC4,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC4,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC4,Tx FIFO Utilization Counter" newline group.long (0x2B000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_4_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_4_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_4_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2B000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 5" group.long 0x2C000++0x03 line.long 0x00 "FMBM_TCFG5,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2C000+0x04)++0x03 line.long 0x00 "FMBM_TST5,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2C000+0x08)++0x2F line.long 0x00 "FMBM_TDA5,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP5,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED5,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP5,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE5,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA5,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID5,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID5,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE5,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS5,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT5,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2C000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2C000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_5,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2C000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2C000+0x200)++0x17 line.long 0x00 "FMBM_TSTC5,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC5,Tx Frame Counter" line.long 0x08 "FMBM_TFDC5,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC5,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC5,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC5,Tx Buffers Deallocate Counter" group.long (0x2C000+0x280)++0x1B line.long 0x00 "FMBM_TPC5,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP5,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN5,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC5,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC5,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC5,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC5,Tx FIFO Utilization Counter" newline group.long (0x2C000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_5_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_5_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_5_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2C000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 5" group.long 0x2C000++0x03 line.long 0x00 "FMBM_TCFG5,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2C000+0x04)++0x03 line.long 0x00 "FMBM_TST5,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2C000+0x08)++0x2F line.long 0x00 "FMBM_TDA5,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP5,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED5,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP5,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE5,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA5,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID5,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID5,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE5,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS5,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT5,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2C000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2C000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_5,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2C000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2C000+0x200)++0x17 line.long 0x00 "FMBM_TSTC5,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC5,Tx Frame Counter" line.long 0x08 "FMBM_TFDC5,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC5,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC5,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC5,Tx Buffers Deallocate Counter" group.long (0x2C000+0x280)++0x1B line.long 0x00 "FMBM_TPC5,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP5,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN5,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC5,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC5,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC5,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC5,Tx FIFO Utilization Counter" newline group.long (0x2C000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_5_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_5_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_5_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2C000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 6" group.long 0x2D000++0x03 line.long 0x00 "FMBM_TCFG6,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2D000+0x04)++0x03 line.long 0x00 "FMBM_TST6,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2D000+0x08)++0x2F line.long 0x00 "FMBM_TDA6,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP6,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED6,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP6,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE6,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA6,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID6,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID6,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE6,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS6,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT6,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2D000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2D000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_6,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2D000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2D000+0x200)++0x17 line.long 0x00 "FMBM_TSTC6,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC6,Tx Frame Counter" line.long 0x08 "FMBM_TFDC6,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC6,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC6,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC6,Tx Buffers Deallocate Counter" group.long (0x2D000+0x280)++0x1B line.long 0x00 "FMBM_TPC6,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP6,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN6,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC6,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC6,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC6,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC6,Tx FIFO Utilization Counter" newline group.long (0x2D000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_6_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_6_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_6_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2D000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 6" group.long 0x2D000++0x03 line.long 0x00 "FMBM_TCFG6,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x2D000+0x04)++0x03 line.long 0x00 "FMBM_TST6,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x2D000+0x08)++0x2F line.long 0x00 "FMBM_TDA6,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP6,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED6,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP6,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE6,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA6,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID6,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID6,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE6,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS6,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT6,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x2D000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2D000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_6,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x2D000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2D000+0x200)++0x17 line.long 0x00 "FMBM_TSTC6,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC6,Tx Frame Counter" line.long 0x08 "FMBM_TFDC6,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC6,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC6,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC6,Tx Buffers Deallocate Counter" group.long (0x2D000+0x280)++0x1B line.long 0x00 "FMBM_TPC6,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP6,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN6,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC6,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC6,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC6,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC6,Tx FIFO Utilization Counter" newline group.long (0x2D000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_6_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_6_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_6_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2D000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "Port 9" group.long 0x30000++0x03 line.long 0x00 "FMBM_TCFG9,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x30000+0x04)++0x03 line.long 0x00 "FMBM_TST9,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x30000+0x08)++0x2F line.long 0x00 "FMBM_TDA9,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP9,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED9,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP9,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE9,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA9,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID9,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID9,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE9,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS9,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT9,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x30000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x30000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_9,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x30000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x30000+0x200)++0x17 line.long 0x00 "FMBM_TSTC9,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC9,Tx Frame Counter" line.long 0x08 "FMBM_TFDC9,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC9,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC9,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC9,Tx Buffers Deallocate Counter" group.long (0x30000+0x280)++0x1B line.long 0x00 "FMBM_TPC9,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP9,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN9,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC9,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC9,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC9,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC9,Tx FIFO Utilization Counter" newline group.long (0x30000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_9_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_9_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_9_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x30000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") tree "Port 9" group.long 0x30000++0x03 line.long 0x00 "FMBM_TCFG9,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x30000+0x04)++0x03 line.long 0x00 "FMBM_TST9,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x30000+0x08)++0x2F line.long 0x00 "FMBM_TDA9,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP9,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED9,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP9,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE9,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA9,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID9,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID9,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE9,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS9,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT9,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x30000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x30000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_9,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x30000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x30000+0x200)++0x17 line.long 0x00 "FMBM_TSTC9,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC9,Tx Frame Counter" line.long 0x08 "FMBM_TFDC9,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC9,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC9,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC9,Tx Buffers Deallocate Counter" group.long (0x30000+0x280)++0x1B line.long 0x00 "FMBM_TPC9,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP9,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN9,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC9,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC9,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC9,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC9,Tx FIFO Utilization Counter" newline group.long (0x30000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_9_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_9_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_9_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x30000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end endif sif cpuis("LS10?6A") tree "Port 10" group.long 0x31000++0x03 line.long 0x00 "FMBM_TCFG10,Tx Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " IM ,Independent Mode" "Low,High" rgroup.long (0x31000+0x04)++0x03 line.long 0x00 "FMBM_TST10,Tx Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " TPID ,Tx Port ID" group.long (0x31000+0x08)++0x2F line.long 0x00 "FMBM_TDA10,Tx DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." line.long 0x04 "FMBM_TFP10,Tx FIFO Parameters" hexmask.long.word 0x04 16.--25. 1. " MFL ,Minimum Fill Level" bitfld.long 0x04 12.--15. " DPDE ,Dequeue Pipeline Depth" "1 frame,2 frames,3 frames,4 frames,5 frames,6 frames,7 frames,8 frames,?..." hexmask.long.word 0x04 0.--9. 1. " FLCL ,FIFO Low Comfort Level" line.long 0x08 "FMBM_TFED10,Tx Frame End Data" bitfld.long 0x08 24.--28. " CSI ,Checksum Ignore" "All,Eliminate last 1 byte,Eliminate last 2 bytes,Eliminate last 3 bytes,Eliminate last 4 bytes,Eliminate last 5 bytes,Eliminate last 6 bytes,Eliminate last 7 bytes,Eliminate last 8 bytes,Eliminate last 9 bytes,Eliminate last 10 bytes,Eliminate last 11 bytes,Eliminate last 12 bytes,Eliminate last 13 bytes,Eliminate last 14 bytes,Eliminate last 15 bytes,Eliminate last 16 bytes,?..." line.long 0x0C "FMBM_TICP10,Tx Internal Context Parameters" bitfld.long 0x0C 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x010,0x020,0x030,0x040,0x050,0x060,0x070,0x080,0x090,0x0A0,0x0B0,0x0C0,0x0D0,0x0E0,0x0F0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x0C 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x0C 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x10 "FMBM_TFDNE10,Tx Frame Dequeue Next Engine Register" bitfld.long 0x10 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x10 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x10 0.--17. 1. " AC ,Action Code" line.long 0x14 "FMBM_TFCA10,Tx Frame Attributes" bitfld.long 0x14 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x14 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline hexmask.long.byte 0x14 16.--21. 1. " MR ,Mode Attributes" hexmask.long.byte 0x14 8.--15. 1. " A0 ,Initial value for ICAD[A0] field" line.long 0x18 "FMBM_TCFQID10,Tx Confirmation Frame Queue ID" hexmask.long.byte 0x18 24.--31. 1. " ASPID ,Absolute Storage Profile ID" hexmask.long.tbyte 0x18 0.--23. 1. " DCFQID ,Default Confirmation Frame Queue ID" line.long 0x1C "FMBM_TEFQID10,Tx Error Frame Queue ID" hexmask.long.tbyte 0x1C 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x20 "FMBM_TFENE10,Tx Frame Enqueue Next Engine" bitfld.long 0x20 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x20 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x20 0.--17. 1. " AC ,Action Code" line.long 0x24 "FMBM_TRLMTS10,Tx Rate Limiter Scale" bitfld.long 0x24 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x24 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" line.long 0x28 "FMBM_TRLMT10,Tx Rate Limiter" hexmask.long.word 0x28 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x28 0.--9. 1. " RLM ,Rate Limit" line.long 0x2C "FMBM_TCCB,Tx Coarse Classification Base Register" group.long (0x31000+0x70)++0x03 line.long 0x00 "FMBM_TFNE,Tx Frame Next Engine" bitfld.long 0x00 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x00 28. " NL ,Not Last" "Disabled,Enabled" newline bitfld.long 0x00 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x31000+0x74)++0x03 line.long 0x00 "FMBM_TPFCM0_10,Tx PFC Mapping Register 0" bitfld.long 0x00 28.--31. " CEVM0 ,Class Enable Vector (CEV) bit 0 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CEVM1 ,Class Enable Vector (CEV) bit 1 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " CEVM2 ,Class Enable Vector (CEV) bit 2 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CEVM3 ,Class Enable Vector (CEV) bit 3 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. " CEVM4 ,Class Enable Vector (CEV) bit 4 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CEVM5 ,Class Enable Vector (CEV) bit 5 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CEVM6 ,Class Enable Vector (CEV) bit 6 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CEVM7 ,Class Enable Vector (CEV) bit 7 to QMan Traffic Class (TC) Mapping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x31000+0x7C)++0x03 line.long 0x00 "FMBM_TCMNE,Tx Frame Continuous Mode Next Engine" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x31000+0x200)++0x17 line.long 0x00 "FMBM_TSTC10,Tx Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TFRC10,Tx Frame Counter" line.long 0x08 "FMBM_TFDC10,Tx Frames Discard Counter" line.long 0x0C "FMBM_TFLEDC10,Tx Frames Length Error Discard Counter" line.long 0x10 "FMBM_TFUFDC10,Tx Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_TBDC10,Tx Buffers Deallocate Counter" group.long (0x31000+0x280)++0x1B line.long 0x00 "FMBM_TPC10,Tx Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_TPCP10,Tx Performance Count Parameters" hexmask.long.byte 0x04 24.--29. 1. " TCV ,Tasks compare value" bitfld.long 0x04 16.--18. " TCCV ,Transmit Confirm Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8" newline bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" ">= 1,>= 2,>= 3,>= 4,>= 5,>= 6,>= 7,>= 8,>= 9,>= 10,>= 11,>= 12,>= 13,>= 14,>= 15,= 16" hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_TCCN10,Tx Cycle Counter" line.long 0x0C "FMBM_TTUC10,Tx Tasks Utilization Counter" line.long 0x10 "FMBM_TTCQUC10,Tx Transmit Confirm Queue Utilization Counter" line.long 0x14 "FMBM_TDUC10,Tx DMA Utilization Counter" line.long 0x18 "FMBM_TFUC10,Tx FIFO Utilization Counter" newline group.long (0x31000+0x300)++0xB line.long 0x00 "FMBM_TDCFG_10_1,Tx Debug Configuration" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_TDCFG_10_2,Tx Debug Configuration" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_TDCFG_10_3,Tx Debug Configuration" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Trap disabled,Always match,(comp& mask)==(frame FD&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Trace disabled,Minimum trace,Verbose trace,Very verbose trace" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x31000+0x30C)++0x03 line.long 0x00 "FMBM_TGPR,Tx General Purpose Register" tree.end elif cpuis("LS10?3A") endif tree.end tree "Offline Parsing/Host Command Port Registers" tree "Port 2" group.long 0x2000++0x03 line.long 0x00 "FMBM_OCFG2,Offline Parsing/Host Command (O/H) Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " FDOVR ,Frame Discard Override" "Discard,Enqueue" rgroup.long (0x2000+0x04)++0x03 line.long 0x00 "FMBM_OST2,O/H Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " OPID ,O/H Port ID" group.long (0x2000+0x08)++0x27 line.long 0x00 "FMBM_ODA2,O/H DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,S/G write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_OICP2,O/H Internal Context Parameters" bitfld.long 0x04 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x04 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x04 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x08 "FMBM_OFDNE2,O/H Frame Dequeue Next Engine" bitfld.long 0x08 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x08 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x08 0.--17. 1. " AC ,Action Code" line.long 0x0C "FMBM_OFNE2,O/H Frame Next Engine" bitfld.long 0x0C 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0C 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " AC ,Action Code" line.long 0x10 "FMBM_OFCA2,O/H Frame Attributes" bitfld.long 0x10 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x10 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x10 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Sync. request,?..." hexmask.long.byte 0x10 16.--21. 1. " MR ,Mode Attributes" line.long 0x14 "FMBM_OFPNE2,O/H Frame Parser Next Engine" bitfld.long 0x14 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x14 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x14 0.--17. 1. " AC ,Action Code" line.long 0x18 "FMBM_OPSO2,O/H Parsing Start Offset" hexmask.long.byte 0x18 0.--7. 1. " PSO ,Parsing start offset" line.long 0x1C "FMBM_OPP2,O/H Policer Profile" bitfld.long 0x1C 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x1C 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x1C 29. " FWD ,Frame Write Disable" "Enabled,Disabled" bitfld.long 0x1C 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" newline bitfld.long 0x1C 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x1C 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" bitfld.long 0x1C 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " PNUM ,Policer Profile" line.long 0x20 "FMBM_OCCB2,O/H Coarse Classification Base" line.long 0x24 "FMBM_OIM2,O/H Internal Margins" bitfld.long 0x24 28.--31. " FOF ,Frame Offset" "0x00,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." group.long (0x2000+0x30)++0x07 line.long 0x00 "FMBM_OFP,O/H FIFO Parameters Register" bitfld.long 0x00 12.--15. " DPDE ,Dequeue Pipeline Depth" "1,2,3,4,5,6,7,8,?..." line.long 0x04 "FMBM_OFED,O/H Frame End Data Register" bitfld.long 0x04 24.--28. " CSI ,Checksum Ignore" "Whole frame,Last 1byte,Last 2bytes,Last 3bytes,Last 4bytes,Last 5bytes,Last 6bytes,Last 7bytes,Last 8bytes,Last 9bytes,Last 10bytes,Last 11bytes,Last 12bytes,Last 13bytes,Last 14bytes,Last 15bytes,Last 16bytes,?..." group.long (0x2000+0x40)++0x3B line.long 0x00 "FMBM_OPRI_2_1,O/H Parse Results Initialization" line.long 0x04 "FMBM_OPRI_2_2,O/H Parse Results Initialization" line.long 0x08 "FMBM_OPRI_2_3,O/H Parse Results Initialization" line.long 0x0C "FMBM_OPRI_2_4,O/H Parse Results Initialization" line.long 0x10 "FMBM_OPRI_2_5,O/H Parse Results Initialization" line.long 0x14 "FMBM_OPRI_2_6,O/H Parse Results Initialization" line.long 0x18 "FMBM_OPRI_2_7,O/H Parse Results Initialization" line.long 0x1C "FMBM_OPRI_2_8,O/H Parse Results Initialization" line.long 0x20 "FMBM_OFQID2,O/H Frame Queue ID" hexmask.long.byte 0x20 24.--31. 1. " ASPID ,Absolute storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_OEFQID2,O/H Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x28 "FMBM_OFSDM2,O/H Frame Status Discard Mask" line.long 0x2C "FMBM_OFSEM2,O/H Frame Status Error Mask" line.long 0x30 "FMBM_OFENE2,O/H Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" line.long 0x34 "FMBM_ORLMTS2,O/H Rate Limiter Scale" bitfld.long 0x34 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x34 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" newline bitfld.long 0x34 0.--1. " LRLS ,Low Rate Limit Scale" "Not scaled down,/2,/4,/8" line.long 0x38 "FMBM_ORLMT2,O/H Rate Limiter" bitfld.long 0x38 31. " BSG ,Burst Size Granularity" "Low,High" hexmask.long.word 0x38 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x38 0.--9. 1. " RLM ,Rate Limit" group.long (0x2000+0x7C)++0x03 line.long 0x00 "FMBM_OCMNE,O/H Continuous Mode Next Enqueue Register" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x2000+0x160)++0x1F line.long 0x00 "FMBM_OCGM_2_1,Observed Congestion Group Map" line.long 0x04 "FMBM_OCGM_2_2,Observed Congestion Group Map" line.long 0x08 "FMBM_OCGM_2_3,Observed Congestion Group Map" line.long 0x0C "FMBM_OCGM_2_4,Observed Congestion Group Map" line.long 0x10 "FMBM_OCGM_2_5,Observed Congestion Group Map" line.long 0x14 "FMBM_OCGM_2_6,Observed Congestion Group Map" line.long 0x18 "FMBM_OCGM_2_7,Observed Congestion Group Map" line.long 0x1C "FMBM_OCGM_2_8,Observed Congestion Group Map" group.long (0x2000+0x200)++0x2B line.long 0x00 "FMBM_OSTC2,O/H Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OFRC2,O/H Frame Counter" line.long 0x08 "FMBM_OFDC2,O/H Frames Discard Counter" line.long 0x0C "FMBM_OFLEDC2,O/H Frames Length Error Discard Counter" line.long 0x10 "FMBM_OFUFDC2,O/H Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_OFFC2,O/H Filtered Frame Counter" line.long 0x18 "FMBM_OFWDC2,O/H Frames WRED Discard Counter" line.long 0x1C "FMBM_OFLDEC2,O/H Frames List DMA Error Counter" line.long 0x20 "FMBM_OBDC2,O/H Buffers Deallocate Counter" line.long 0x24 "FMBM_OODC,O/H Out of Buffers Discard Counter Register" line.long 0x28 "FMBM_OPEC,O/H Prepare to Enqueue Counter" group.long (0x2000+0x280)++0x17 line.long 0x00 "FMBM_OPC2,O/H Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OPCP2,O/H Performance Count Parameters" bitfld.long 0x04 24.--29. " TCV ,Tasks compare value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,=> 16,=> 17,=> 18,=> 19,=> 20,=> 21,=> 22,=> 23,=> 24,=> 25,=> 26,>= 27,=> 28,=> 29,=> 30,=> 31,=> 32,=> 33,=> 34,=> 35,=> 36,=> 37,=> 38,=> 39,=> 40,=> 41,=> 42,>= 43,=> 44,=> 45,=> 46,=> 47,=> 48,=> 49,=> 50,=> 51,=> 52,=> 53,=> 54,=> 55,=> 56,=> 57,=> 58,>= 59,=> 60,=> 61,=> 62,=> 63,>= 64" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,= 16" newline hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_OCCN2,O/H Cycle Counter" line.long 0x0C "FMBM_OTUC,O/H Tasks Utilization Counter" line.long 0x10 "FMBM_ODUC2,O/H DMA Utilization Counter" line.long 0x14 "FMBM_OFUC2,O/H FIFO Utilization Counter" newline group.long (0x2000+0x300)++0xB line.long 0x00 "FMBM_ODCFG_2_1,O/H Debug Configuration (FLOW A)" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_ODCFG_2_2,O/H Debug Configuration (FLOW B)" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_ODCFG_2_3,O/H Debug Configuration (FLOW C)" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x2000+0x30C)++0x03 line.long 0x00 "FMBM_OGPR,O/H General Purpose Register" tree.end tree "Port 3" group.long 0x3000++0x03 line.long 0x00 "FMBM_OCFG3,Offline Parsing/Host Command (O/H) Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " FDOVR ,Frame Discard Override" "Discard,Enqueue" rgroup.long (0x3000+0x04)++0x03 line.long 0x00 "FMBM_OST3,O/H Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " OPID ,O/H Port ID" group.long (0x3000+0x08)++0x27 line.long 0x00 "FMBM_ODA3,O/H DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,S/G write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_OICP3,O/H Internal Context Parameters" bitfld.long 0x04 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x04 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x04 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x08 "FMBM_OFDNE3,O/H Frame Dequeue Next Engine" bitfld.long 0x08 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x08 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x08 0.--17. 1. " AC ,Action Code" line.long 0x0C "FMBM_OFNE3,O/H Frame Next Engine" bitfld.long 0x0C 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0C 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " AC ,Action Code" line.long 0x10 "FMBM_OFCA3,O/H Frame Attributes" bitfld.long 0x10 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x10 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x10 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Sync. request,?..." hexmask.long.byte 0x10 16.--21. 1. " MR ,Mode Attributes" line.long 0x14 "FMBM_OFPNE3,O/H Frame Parser Next Engine" bitfld.long 0x14 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x14 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x14 0.--17. 1. " AC ,Action Code" line.long 0x18 "FMBM_OPSO3,O/H Parsing Start Offset" hexmask.long.byte 0x18 0.--7. 1. " PSO ,Parsing start offset" line.long 0x1C "FMBM_OPP3,O/H Policer Profile" bitfld.long 0x1C 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x1C 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x1C 29. " FWD ,Frame Write Disable" "Enabled,Disabled" bitfld.long 0x1C 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" newline bitfld.long 0x1C 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x1C 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" bitfld.long 0x1C 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " PNUM ,Policer Profile" line.long 0x20 "FMBM_OCCB3,O/H Coarse Classification Base" line.long 0x24 "FMBM_OIM3,O/H Internal Margins" bitfld.long 0x24 28.--31. " FOF ,Frame Offset" "0x00,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." group.long (0x3000+0x30)++0x07 line.long 0x00 "FMBM_OFP,O/H FIFO Parameters Register" bitfld.long 0x00 12.--15. " DPDE ,Dequeue Pipeline Depth" "1,2,3,4,5,6,7,8,?..." line.long 0x04 "FMBM_OFED,O/H Frame End Data Register" bitfld.long 0x04 24.--28. " CSI ,Checksum Ignore" "Whole frame,Last 1byte,Last 2bytes,Last 3bytes,Last 4bytes,Last 5bytes,Last 6bytes,Last 7bytes,Last 8bytes,Last 9bytes,Last 10bytes,Last 11bytes,Last 12bytes,Last 13bytes,Last 14bytes,Last 15bytes,Last 16bytes,?..." group.long (0x3000+0x40)++0x3B line.long 0x00 "FMBM_OPRI_3_1,O/H Parse Results Initialization" line.long 0x04 "FMBM_OPRI_3_2,O/H Parse Results Initialization" line.long 0x08 "FMBM_OPRI_3_3,O/H Parse Results Initialization" line.long 0x0C "FMBM_OPRI_3_4,O/H Parse Results Initialization" line.long 0x10 "FMBM_OPRI_3_5,O/H Parse Results Initialization" line.long 0x14 "FMBM_OPRI_3_6,O/H Parse Results Initialization" line.long 0x18 "FMBM_OPRI_3_7,O/H Parse Results Initialization" line.long 0x1C "FMBM_OPRI_3_8,O/H Parse Results Initialization" line.long 0x20 "FMBM_OFQID3,O/H Frame Queue ID" hexmask.long.byte 0x20 24.--31. 1. " ASPID ,Absolute storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_OEFQID3,O/H Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x28 "FMBM_OFSDM3,O/H Frame Status Discard Mask" line.long 0x2C "FMBM_OFSEM3,O/H Frame Status Error Mask" line.long 0x30 "FMBM_OFENE3,O/H Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" line.long 0x34 "FMBM_ORLMTS3,O/H Rate Limiter Scale" bitfld.long 0x34 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x34 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" newline bitfld.long 0x34 0.--1. " LRLS ,Low Rate Limit Scale" "Not scaled down,/2,/4,/8" line.long 0x38 "FMBM_ORLMT3,O/H Rate Limiter" bitfld.long 0x38 31. " BSG ,Burst Size Granularity" "Low,High" hexmask.long.word 0x38 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x38 0.--9. 1. " RLM ,Rate Limit" group.long (0x3000+0x7C)++0x03 line.long 0x00 "FMBM_OCMNE,O/H Continuous Mode Next Enqueue Register" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x3000+0x160)++0x1F line.long 0x00 "FMBM_OCGM_3_1,Observed Congestion Group Map" line.long 0x04 "FMBM_OCGM_3_2,Observed Congestion Group Map" line.long 0x08 "FMBM_OCGM_3_3,Observed Congestion Group Map" line.long 0x0C "FMBM_OCGM_3_4,Observed Congestion Group Map" line.long 0x10 "FMBM_OCGM_3_5,Observed Congestion Group Map" line.long 0x14 "FMBM_OCGM_3_6,Observed Congestion Group Map" line.long 0x18 "FMBM_OCGM_3_7,Observed Congestion Group Map" line.long 0x1C "FMBM_OCGM_3_8,Observed Congestion Group Map" group.long (0x3000+0x200)++0x2B line.long 0x00 "FMBM_OSTC3,O/H Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OFRC3,O/H Frame Counter" line.long 0x08 "FMBM_OFDC3,O/H Frames Discard Counter" line.long 0x0C "FMBM_OFLEDC3,O/H Frames Length Error Discard Counter" line.long 0x10 "FMBM_OFUFDC3,O/H Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_OFFC3,O/H Filtered Frame Counter" line.long 0x18 "FMBM_OFWDC3,O/H Frames WRED Discard Counter" line.long 0x1C "FMBM_OFLDEC3,O/H Frames List DMA Error Counter" line.long 0x20 "FMBM_OBDC3,O/H Buffers Deallocate Counter" line.long 0x24 "FMBM_OODC,O/H Out of Buffers Discard Counter Register" line.long 0x28 "FMBM_OPEC,O/H Prepare to Enqueue Counter" group.long (0x3000+0x280)++0x17 line.long 0x00 "FMBM_OPC3,O/H Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OPCP3,O/H Performance Count Parameters" bitfld.long 0x04 24.--29. " TCV ,Tasks compare value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,=> 16,=> 17,=> 18,=> 19,=> 20,=> 21,=> 22,=> 23,=> 24,=> 25,=> 26,>= 27,=> 28,=> 29,=> 30,=> 31,=> 32,=> 33,=> 34,=> 35,=> 36,=> 37,=> 38,=> 39,=> 40,=> 41,=> 42,>= 43,=> 44,=> 45,=> 46,=> 47,=> 48,=> 49,=> 50,=> 51,=> 52,=> 53,=> 54,=> 55,=> 56,=> 57,=> 58,>= 59,=> 60,=> 61,=> 62,=> 63,>= 64" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,= 16" newline hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_OCCN3,O/H Cycle Counter" line.long 0x0C "FMBM_OTUC,O/H Tasks Utilization Counter" line.long 0x10 "FMBM_ODUC3,O/H DMA Utilization Counter" line.long 0x14 "FMBM_OFUC3,O/H FIFO Utilization Counter" newline group.long (0x3000+0x300)++0xB line.long 0x00 "FMBM_ODCFG_3_1,O/H Debug Configuration (FLOW A)" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_ODCFG_3_2,O/H Debug Configuration (FLOW B)" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_ODCFG_3_3,O/H Debug Configuration (FLOW C)" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x3000+0x30C)++0x03 line.long 0x00 "FMBM_OGPR,O/H General Purpose Register" tree.end tree "Port 4" group.long 0x4000++0x03 line.long 0x00 "FMBM_OCFG4,Offline Parsing/Host Command (O/H) Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " FDOVR ,Frame Discard Override" "Discard,Enqueue" rgroup.long (0x4000+0x04)++0x03 line.long 0x00 "FMBM_OST4,O/H Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " OPID ,O/H Port ID" group.long (0x4000+0x08)++0x27 line.long 0x00 "FMBM_ODA4,O/H DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,S/G write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_OICP4,O/H Internal Context Parameters" bitfld.long 0x04 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x04 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x04 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x08 "FMBM_OFDNE4,O/H Frame Dequeue Next Engine" bitfld.long 0x08 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x08 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x08 0.--17. 1. " AC ,Action Code" line.long 0x0C "FMBM_OFNE4,O/H Frame Next Engine" bitfld.long 0x0C 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0C 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " AC ,Action Code" line.long 0x10 "FMBM_OFCA4,O/H Frame Attributes" bitfld.long 0x10 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x10 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x10 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Sync. request,?..." hexmask.long.byte 0x10 16.--21. 1. " MR ,Mode Attributes" line.long 0x14 "FMBM_OFPNE4,O/H Frame Parser Next Engine" bitfld.long 0x14 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x14 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x14 0.--17. 1. " AC ,Action Code" line.long 0x18 "FMBM_OPSO4,O/H Parsing Start Offset" hexmask.long.byte 0x18 0.--7. 1. " PSO ,Parsing start offset" line.long 0x1C "FMBM_OPP4,O/H Policer Profile" bitfld.long 0x1C 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x1C 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x1C 29. " FWD ,Frame Write Disable" "Enabled,Disabled" bitfld.long 0x1C 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" newline bitfld.long 0x1C 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x1C 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" bitfld.long 0x1C 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " PNUM ,Policer Profile" line.long 0x20 "FMBM_OCCB4,O/H Coarse Classification Base" line.long 0x24 "FMBM_OIM4,O/H Internal Margins" bitfld.long 0x24 28.--31. " FOF ,Frame Offset" "0x00,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." group.long (0x4000+0x30)++0x07 line.long 0x00 "FMBM_OFP,O/H FIFO Parameters Register" bitfld.long 0x00 12.--15. " DPDE ,Dequeue Pipeline Depth" "1,2,3,4,5,6,7,8,?..." line.long 0x04 "FMBM_OFED,O/H Frame End Data Register" bitfld.long 0x04 24.--28. " CSI ,Checksum Ignore" "Whole frame,Last 1byte,Last 2bytes,Last 3bytes,Last 4bytes,Last 5bytes,Last 6bytes,Last 7bytes,Last 8bytes,Last 9bytes,Last 10bytes,Last 11bytes,Last 12bytes,Last 13bytes,Last 14bytes,Last 15bytes,Last 16bytes,?..." group.long (0x4000+0x40)++0x3B line.long 0x00 "FMBM_OPRI_4_1,O/H Parse Results Initialization" line.long 0x04 "FMBM_OPRI_4_2,O/H Parse Results Initialization" line.long 0x08 "FMBM_OPRI_4_3,O/H Parse Results Initialization" line.long 0x0C "FMBM_OPRI_4_4,O/H Parse Results Initialization" line.long 0x10 "FMBM_OPRI_4_5,O/H Parse Results Initialization" line.long 0x14 "FMBM_OPRI_4_6,O/H Parse Results Initialization" line.long 0x18 "FMBM_OPRI_4_7,O/H Parse Results Initialization" line.long 0x1C "FMBM_OPRI_4_8,O/H Parse Results Initialization" line.long 0x20 "FMBM_OFQID4,O/H Frame Queue ID" hexmask.long.byte 0x20 24.--31. 1. " ASPID ,Absolute storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_OEFQID4,O/H Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x28 "FMBM_OFSDM4,O/H Frame Status Discard Mask" line.long 0x2C "FMBM_OFSEM4,O/H Frame Status Error Mask" line.long 0x30 "FMBM_OFENE4,O/H Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" line.long 0x34 "FMBM_ORLMTS4,O/H Rate Limiter Scale" bitfld.long 0x34 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x34 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" newline bitfld.long 0x34 0.--1. " LRLS ,Low Rate Limit Scale" "Not scaled down,/2,/4,/8" line.long 0x38 "FMBM_ORLMT4,O/H Rate Limiter" bitfld.long 0x38 31. " BSG ,Burst Size Granularity" "Low,High" hexmask.long.word 0x38 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x38 0.--9. 1. " RLM ,Rate Limit" group.long (0x4000+0x7C)++0x03 line.long 0x00 "FMBM_OCMNE,O/H Continuous Mode Next Enqueue Register" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x4000+0x160)++0x1F line.long 0x00 "FMBM_OCGM_4_1,Observed Congestion Group Map" line.long 0x04 "FMBM_OCGM_4_2,Observed Congestion Group Map" line.long 0x08 "FMBM_OCGM_4_3,Observed Congestion Group Map" line.long 0x0C "FMBM_OCGM_4_4,Observed Congestion Group Map" line.long 0x10 "FMBM_OCGM_4_5,Observed Congestion Group Map" line.long 0x14 "FMBM_OCGM_4_6,Observed Congestion Group Map" line.long 0x18 "FMBM_OCGM_4_7,Observed Congestion Group Map" line.long 0x1C "FMBM_OCGM_4_8,Observed Congestion Group Map" group.long (0x4000+0x200)++0x2B line.long 0x00 "FMBM_OSTC4,O/H Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OFRC4,O/H Frame Counter" line.long 0x08 "FMBM_OFDC4,O/H Frames Discard Counter" line.long 0x0C "FMBM_OFLEDC4,O/H Frames Length Error Discard Counter" line.long 0x10 "FMBM_OFUFDC4,O/H Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_OFFC4,O/H Filtered Frame Counter" line.long 0x18 "FMBM_OFWDC4,O/H Frames WRED Discard Counter" line.long 0x1C "FMBM_OFLDEC4,O/H Frames List DMA Error Counter" line.long 0x20 "FMBM_OBDC4,O/H Buffers Deallocate Counter" line.long 0x24 "FMBM_OODC,O/H Out of Buffers Discard Counter Register" line.long 0x28 "FMBM_OPEC,O/H Prepare to Enqueue Counter" group.long (0x4000+0x280)++0x17 line.long 0x00 "FMBM_OPC4,O/H Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OPCP4,O/H Performance Count Parameters" bitfld.long 0x04 24.--29. " TCV ,Tasks compare value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,=> 16,=> 17,=> 18,=> 19,=> 20,=> 21,=> 22,=> 23,=> 24,=> 25,=> 26,>= 27,=> 28,=> 29,=> 30,=> 31,=> 32,=> 33,=> 34,=> 35,=> 36,=> 37,=> 38,=> 39,=> 40,=> 41,=> 42,>= 43,=> 44,=> 45,=> 46,=> 47,=> 48,=> 49,=> 50,=> 51,=> 52,=> 53,=> 54,=> 55,=> 56,=> 57,=> 58,>= 59,=> 60,=> 61,=> 62,=> 63,>= 64" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,= 16" newline hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_OCCN4,O/H Cycle Counter" line.long 0x0C "FMBM_OTUC,O/H Tasks Utilization Counter" line.long 0x10 "FMBM_ODUC4,O/H DMA Utilization Counter" line.long 0x14 "FMBM_OFUC4,O/H FIFO Utilization Counter" newline group.long (0x4000+0x300)++0xB line.long 0x00 "FMBM_ODCFG_4_1,O/H Debug Configuration (FLOW A)" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_ODCFG_4_2,O/H Debug Configuration (FLOW B)" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_ODCFG_4_3,O/H Debug Configuration (FLOW C)" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x4000+0x30C)++0x03 line.long 0x00 "FMBM_OGPR,O/H General Purpose Register" tree.end tree "Port 5" group.long 0x5000++0x03 line.long 0x00 "FMBM_OCFG5,Offline Parsing/Host Command (O/H) Configuration" bitfld.long 0x00 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x00 24. " FDOVR ,Frame Discard Override" "Discard,Enqueue" rgroup.long (0x5000+0x04)++0x03 line.long 0x00 "FMBM_OST5,O/H Status" bitfld.long 0x00 31. " BSY ,Busy" "Not busy,Busy" hexmask.long.byte 0x00 16.--21. 1. " OPID ,O/H Port ID" group.long (0x5000+0x08)++0x27 line.long 0x00 "FMBM_ODA5,O/H DMA Attributes" bitfld.long 0x00 30.--31. " SWAP ,Swap payload data" "No swap,?..." bitfld.long 0x00 28.--29. " ICC ,IC write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 26.--27. " FHC ,Frame Header write cache attributes" "No Stashing,Stashing,?..." newline bitfld.long 0x00 24.--25. " SGC ,S/G write cache attributes" "No Stashing,Stashing,?..." bitfld.long 0x00 20.--21. " WOPT ,Optimize on write" "No optimization,Write more bytes,?..." line.long 0x04 "FMBM_OICP5,O/H Internal Context Parameters" bitfld.long 0x04 16.--20. " ICEOF ,Internal Context External Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0,0x100,0x110,0x120,0x130,0x140,0x150,0x160,0x170,0x180,0x190,0x1A0,0x1B0,0x1C0,0x1D0,0x1E0,0x1F0" bitfld.long 0x04 8.--11. " ICIOF ,Internal Context Internal Offset" "0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" bitfld.long 0x04 0.--4. " ICSZ ,Internal Context copy Size" "No transfer,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes,128 bytes,144 bytes,160 bytes,176 bytes,192 bytes,208 bytes,224 bytes,240 bytes,256 bytes,?..." line.long 0x08 "FMBM_OFDNE5,O/H Frame Dequeue Next Engine" bitfld.long 0x08 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x08 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x08 0.--17. 1. " AC ,Action Code" line.long 0x0C "FMBM_OFNE5,O/H Frame Next Engine" bitfld.long 0x0C 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0C 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " AC ,Action Code" line.long 0x10 "FMBM_OFCA5,O/H Frame Attributes" bitfld.long 0x10 31. " OR ,Order definition" "Not needed,Needed" bitfld.long 0x10 26.--27. " COLOR ,Default color" "Green,Yellow,Red,Override" newline bitfld.long 0x10 24.--25. " SYNC ,Synchronization attributes" "Inactive,,Sync. request,?..." hexmask.long.byte 0x10 16.--21. 1. " MR ,Mode Attributes" line.long 0x14 "FMBM_OFPNE5,O/H Frame Parser Next Engine" bitfld.long 0x14 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x14 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x14 0.--17. 1. " AC ,Action Code" line.long 0x18 "FMBM_OPSO5,O/H Parsing Start Offset" hexmask.long.byte 0x18 0.--7. 1. " PSO ,Parsing start offset" line.long 0x1C "FMBM_OPP5,O/H Policer Profile" bitfld.long 0x1C 31. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" bitfld.long 0x1C 30. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x1C 29. " FWD ,Frame Write Disable" "Enabled,Disabled" bitfld.long 0x1C 28. " NL ,Not Last (continuous mode)" "Disabled,Enabled" newline bitfld.long 0x1C 27. " CWD ,Context Write Disable" "Enabled,Disabled" bitfld.long 0x1C 26. " NENQ ,No ENQueue" "FMBM_OFENE,Automatically" bitfld.long 0x1C 24. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" hexmask.long.byte 0x1C 0.--7. 1. " PNUM ,Policer Profile" line.long 0x20 "FMBM_OCCB5,O/H Coarse Classification Base" line.long 0x24 "FMBM_OIM5,O/H Internal Margins" bitfld.long 0x24 28.--31. " FOF ,Frame Offset" "0x00,0x10 (16 bytes),0x20 (32 bytes),0x30 (48 bytes),0x40 (64 bytes),0x50 (80 bytes),0x60 (96 bytes),0x70 (112 bytes),0x80 (128 bytes),0x90 (144 bytes),0xA0 (160 bytes),0xB0 (176 bytes),0xC0 (192 bytes),?..." group.long (0x5000+0x30)++0x07 line.long 0x00 "FMBM_OFP,O/H FIFO Parameters Register" bitfld.long 0x00 12.--15. " DPDE ,Dequeue Pipeline Depth" "1,2,3,4,5,6,7,8,?..." line.long 0x04 "FMBM_OFED,O/H Frame End Data Register" bitfld.long 0x04 24.--28. " CSI ,Checksum Ignore" "Whole frame,Last 1byte,Last 2bytes,Last 3bytes,Last 4bytes,Last 5bytes,Last 6bytes,Last 7bytes,Last 8bytes,Last 9bytes,Last 10bytes,Last 11bytes,Last 12bytes,Last 13bytes,Last 14bytes,Last 15bytes,Last 16bytes,?..." group.long (0x5000+0x40)++0x3B line.long 0x00 "FMBM_OPRI_5_1,O/H Parse Results Initialization" line.long 0x04 "FMBM_OPRI_5_2,O/H Parse Results Initialization" line.long 0x08 "FMBM_OPRI_5_3,O/H Parse Results Initialization" line.long 0x0C "FMBM_OPRI_5_4,O/H Parse Results Initialization" line.long 0x10 "FMBM_OPRI_5_5,O/H Parse Results Initialization" line.long 0x14 "FMBM_OPRI_5_6,O/H Parse Results Initialization" line.long 0x18 "FMBM_OPRI_5_7,O/H Parse Results Initialization" line.long 0x1C "FMBM_OPRI_5_8,O/H Parse Results Initialization" line.long 0x20 "FMBM_OFQID5,O/H Frame Queue ID" hexmask.long.byte 0x20 24.--31. 1. " ASPID ,Absolute storage profile ID" hexmask.long.tbyte 0x20 0.--23. 1. " DFQID ,Default Frame Queue ID" line.long 0x24 "FMBM_OEFQID5,O/H Error Frame Queue ID" hexmask.long.tbyte 0x24 0.--23. 1. " EFQID ,Error Frame Queue ID" line.long 0x28 "FMBM_OFSDM5,O/H Frame Status Discard Mask" line.long 0x2C "FMBM_OFSEM5,O/H Frame Status Error Mask" line.long 0x30 "FMBM_OFENE5,O/H Frame Enqueue Next Engine" bitfld.long 0x30 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x30 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x30 0.--17. 1. " AC ,Action Code" line.long 0x34 "FMBM_ORLMTS5,O/H Rate Limiter Scale" bitfld.long 0x34 31. " EN ,Enable" "Disabled,Enabled" bitfld.long 0x34 16.--20. " TSBS ,Time Stamp Bus Scale" "TSB count period / 2^31,TSB count period / 2^30,TSB count period / 2^29,TSB count period / 2^28,TSB count period / 2^27,TSB count period / 2^26,TSB count period / 2^25,TSB count period / 2^24,TSB count period / 2^23,TSB count period / 2^22,TSB count period / 2^21,TSB count period / 2^20,TSB count period / 2^19,TSB count period / 2^18,TSB count period / 2^17,TSB count period / 2^16,TSB count period / 2^15,TSB count period / 2^14,TSB count period / 2^13,TSB count period / 2^12,TSB count period / 2^11,TSB count period / 1024,TSB count period / 512,TSB count period / 256,TSB count period / 128,TSB count period / 64,TSB count period / 32,TSB count period / 16,TSB count period / 8,TSB count period / 4,TSB count period / 2,TSB count period" newline bitfld.long 0x34 0.--1. " LRLS ,Low Rate Limit Scale" "Not scaled down,/2,/4,/8" line.long 0x38 "FMBM_ORLMT5,O/H Rate Limiter" bitfld.long 0x38 31. " BSG ,Burst Size Granularity" "Low,High" hexmask.long.word 0x38 16.--25. 1. " MBS ,Maximum Burst Size" hexmask.long.word 0x38 0.--9. 1. " RLM ,Rate Limit" group.long (0x5000+0x7C)++0x03 line.long 0x00 "FMBM_OCMNE,O/H Continuous Mode Next Enqueue Register" bitfld.long 0x0 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x0 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x0 0.--17. 1. " AC ,Action Code" group.long (0x5000+0x160)++0x1F line.long 0x00 "FMBM_OCGM_5_1,Observed Congestion Group Map" line.long 0x04 "FMBM_OCGM_5_2,Observed Congestion Group Map" line.long 0x08 "FMBM_OCGM_5_3,Observed Congestion Group Map" line.long 0x0C "FMBM_OCGM_5_4,Observed Congestion Group Map" line.long 0x10 "FMBM_OCGM_5_5,Observed Congestion Group Map" line.long 0x14 "FMBM_OCGM_5_6,Observed Congestion Group Map" line.long 0x18 "FMBM_OCGM_5_7,Observed Congestion Group Map" line.long 0x1C "FMBM_OCGM_5_8,Observed Congestion Group Map" group.long (0x5000+0x200)++0x2B line.long 0x00 "FMBM_OSTC5,O/H Statistics Counters" bitfld.long 0x00 31. " EN ,Enable Statistics Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OFRC5,O/H Frame Counter" line.long 0x08 "FMBM_OFDC5,O/H Frames Discard Counter" line.long 0x0C "FMBM_OFLEDC5,O/H Frames Length Error Discard Counter" line.long 0x10 "FMBM_OFUFDC5,O/H Frames Unsupported Format Discard Counter" line.long 0x14 "FMBM_OFFC5,O/H Filtered Frame Counter" line.long 0x18 "FMBM_OFWDC5,O/H Frames WRED Discard Counter" line.long 0x1C "FMBM_OFLDEC5,O/H Frames List DMA Error Counter" line.long 0x20 "FMBM_OBDC5,O/H Buffers Deallocate Counter" line.long 0x24 "FMBM_OODC,O/H Out of Buffers Discard Counter Register" line.long 0x28 "FMBM_OPEC,O/H Prepare to Enqueue Counter" group.long (0x5000+0x280)++0x17 line.long 0x00 "FMBM_OPC5,O/H Performance Counters" bitfld.long 0x00 31. " EN ,Enable Performance Counters" "Disabled,Enabled" line.long 0x04 "FMBM_OPCP5,O/H Performance Count Parameters" bitfld.long 0x04 24.--29. " TCV ,Tasks compare value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,=> 16,=> 17,=> 18,=> 19,=> 20,=> 21,=> 22,=> 23,=> 24,=> 25,=> 26,>= 27,=> 28,=> 29,=> 30,=> 31,=> 32,=> 33,=> 34,=> 35,=> 36,=> 37,=> 38,=> 39,=> 40,=> 41,=> 42,>= 43,=> 44,=> 45,=> 46,=> 47,=> 48,=> 49,=> 50,=> 51,=> 52,=> 53,=> 54,=> 55,=> 56,=> 57,=> 58,>= 59,=> 60,=> 61,=> 62,=> 63,>= 64" bitfld.long 0x04 12.--15. " DCV ,DMA Compare Value" "=> 1,=> 2,=> 3,=> 4,=> 5,=> 6,=> 7,=> 8,=> 9,=> 10,>= 11,=> 12,=> 13,=> 14,=> 15,= 16" newline hexmask.long.word 0x04 0.--9. 1. " FUCV ,FIFO Utilization Compare Value" line.long 0x08 "FMBM_OCCN5,O/H Cycle Counter" line.long 0x0C "FMBM_OTUC,O/H Tasks Utilization Counter" line.long 0x10 "FMBM_ODUC5,O/H DMA Utilization Counter" line.long 0x14 "FMBM_OFUC5,O/H FIFO Utilization Counter" newline group.long (0x5000+0x300)++0xB line.long 0x00 "FMBM_ODCFG_5_1,O/H Debug Configuration (FLOW A)" bitfld.long 0x00 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x00 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x00 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x00 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x04 "FMBM_ODCFG_5_2,O/H Debug Configuration (FLOW B)" bitfld.long 0x04 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x04 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x04 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x04 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x04 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" line.long 0x08 "FMBM_ODCFG_5_3,O/H Debug Configuration (FLOW C)" bitfld.long 0x08 28.--30. " CMPOP ,Compare Operator" "Disabled,Always match,(comp&&mask)==(frame FD&&mask),?..." bitfld.long 0x08 24.--25. " TL ,Trace Level" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x08 20.--21. " TR_DST ,Trace Destination" "Memory,Debug port (Nexus),Both,?..." newline bitfld.long 0x08 16.--17. " HALT ,Halt execution" "No halt,This task,This port,All ports" bitfld.long 0x08 4.--7. " DTO ,Debug Trace Offset" ",,,,,,,,0x80,0x90,0xA0,0xB0,0xC0,0xD0,0xE0,0xF0" group.long (0x5000+0x30C)++0x03 line.long 0x00 "FMBM_OGPR,O/H General Purpose Register" tree.end tree.end endian.le width 0x0B tree.end tree "Frame Manager QMI" base ad:0x01A00000+0x80400 width 16. endian.be group.long 0x00++0x3 line.long 0x00 "FMQM_GC,General Configuration Register" bitfld.long 0x00 28. " STEN ,QMI global statistic counters enable" "Disabled,Enabled" bitfld.long 0x00 8.--13. " ENQ_THR ,Enqueue threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " DEQ_THR ,Dequeue threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x08++0x7 line.long 0x00 "FMQM_EIE,Error Interrupt Event Register" eventfld.long 0x00 31. " DEE ,Double-bit ECC error detection on the QMI internal RAM read access" "No error,Error" eventfld.long 0x00 30. " DFUPE ,Dequeue From Unknown PortID Error" "No error,Error" line.long 0x04 "FMQM_EIEN,Error Interrupt Enable Register" bitfld.long 0x04 31. " DEEN ,Double-bit ECC Error Interrupt Enable (for the internal RAM)" "Disabled,Enabled" bitfld.long 0x04 30. " DFUPEN ,Dequeue From Unknown PortID Event Interrupt Enable" "Disabled,Enabled" wgroup.long 0x10++0x3 line.long 0x00 "FMQM_EIF,Error Interrupt Force Register" bitfld.long 0x00 31. " FDEE ,Force Double ECC Error" "No effect,Forced" bitfld.long 0x00 30. " FDFUPE ,Force Dequeue From Unknown PortID Error" "No effect,Forced" rgroup.long 0x20++0x3 line.long 0x00 "FMQM_GS,Global Status Register" bitfld.long 0x00 31. " BSY_DT ,QMI Busy Dequeue Tnum Indication" "Not busy,Busy" bitfld.long 0x00 30. " BSY_ET ,QMI Busy Enqueue Tnum Indication" "Not busy,Busy" bitfld.long 0x00 29. " BSY_DF ,QMI Busy Dequeue FD Indication" "Not busy,Busy" bitfld.long 0x00 28. " BSY_EF ,QMI Busy Enqueue FD Indication" "Not busy,Busy" newline bitfld.long 0x00 16. " SRS ,Soft Reset Sequence" "Not in reset,In reset" bitfld.long 0x00 1. " HNB ,Halt Not Busy" "Disabled,Enabled" group.long 0x28++0x07 line.long 0x00 "FMQM_ETFC,Enqueue Total Frame Counter" line.long 0x04 "FMQM_DTFC,Dequeue Total Frame Counter" group.long 0x30++0x03 line.long 0x0 "FMQM_DC0,FMQM_DC0-Dequeue Counter 0 Register" group.long 0x80++0x7 line.long 0x00 "FMQM_DTRC,Debug Trace Configuration Register" bitfld.long 0x00 28.--29. " TL_A ,Trace Level flow A" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 26.--27. " TL_B ,Trace Level flow B" "Disabled,Minimum,Verbose,Very verbose" newline bitfld.long 0x00 24.--25. " TL_C ,Trace Level flow C" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--21. " TR_CO ,Trap Collaboration" "No collaboration,Flow A - Flow B,Flow A - Flow C,Flow A - Flow B - Flow C" line.long 0x04 "FMQM_EFDDD,Enqueue Frame Descriptor Dynamic Debug" bitfld.long 0x04 30. " DOE0 ,Dynamic Debug field Override Enable 0" "Disabled,Enabled" bitfld.long 0x04 28.--29. " DV0 ,Dynamic Debug field Value 0" "0,1,2,3" bitfld.long 0x04 26. " DOE1 ,Dynamic Debug field Override Enable 1" "Disabled,Enabled" bitfld.long 0x04 24.--25. " DV1 ,Dynamic Debug field Value 1" "0,1,2,3" newline bitfld.long 0x04 22. " DOE2 ,Dynamic Debug field Override Enable 2" "Disabled,Enabled" bitfld.long 0x04 20.--21. " DV2 ,Dynamic Debug field Value 2" "0,1,2,3" bitfld.long 0x04 18. " DOE3 ,Dynamic Debug field Override Enable 3" "Disabled,Enabled" bitfld.long 0x04 16.--17. " DV3 ,Dynamic Debug field Value 3" "0,1,2,3" newline bitfld.long 0x04 14. " DOE4 ,Dynamic Debug field Override Enable 4" "Disabled,Enabled" bitfld.long 0x04 12.--13. " DV4 ,Dynamic Debug field Value 4" "0,1,2,3" bitfld.long 0x04 10. " DOE5 ,Dynamic Debug field Override Enable 5" "Disabled,Enabled" bitfld.long 0x04 8.--9. " DV5 ,Dynamic Debug field Value 5" "0,1,2,3" newline bitfld.long 0x04 6. " DOE6 ,Dynamic Debug field Override Enable 6" "Disabled,Enabled" bitfld.long 0x04 4.--5. " DV6 ,Dynamic Debug field Value 6" "0,1,2,3" bitfld.long 0x04 2. " DOE7 ,Dynamic Debug field Override Enable 7" "Disabled,Enabled" bitfld.long 0x04 0.--1. " DV7 ,Dynamic Debug field Value 7" "0,1,2,3" group.long 0x90++0xB line.long 0x00 "FMQM_DTCA1,Debug Trap Configuration A1 Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always match,== FMQM_DTV1[VAL],!= FMQM_DTV1[VAL],> FMQM_DTV1[VAL],<= FMQM_DTV1[VAL],< FMQM_DTV1[VAL],>= FMQM_DTV1[VAL]" bitfld.long 0x00 28. " AND ,Combining trap results into a trap equation" "OR,AND" bitfld.long 0x00 16.--17. " FSEL ,Field selection" "FSEL1,FSEL2,FSEL3,?..." line.long 0x04 "FMQM_DTVA1,Debug Trap Value A1 Register" line.long 0x08 "FMQM_DTMA1,Debug Trap Mask A1 Register" group.long 0xA0++0xB line.long 0x00 "FMQM_DTCA2,Debug Trap Configuration A2 Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always match,== FMQM_DTV2[VAL],!= FMQM_DTV2[VAL],> FMQM_DTV2[VAL],<= FMQM_DTV2[VAL],< FMQM_DTV2[VAL],>= FMQM_DTV2[VAL]" bitfld.long 0x00 28. " AND ,Combining trap results into a trap equation" "OR,AND" bitfld.long 0x00 16.--17. " FSEL ,Field selection" "FSEL1,FSEL2,FSEL3,?..." line.long 0x04 "FMQM_DTVA2,Debug Trap Value A2 Register" line.long 0x08 "FMQM_DTMA2,Debug Trap Mask A2 Register" group.long 0x9C++0x03 line.long 0x00 "FMQM_DTCA,Debug Trap Counter A Register" tree "QMI Offline/Host Command Port Register 2" group.long (0x1000*2)++0x3 line.long 0x00 "FMQM_P2C,PortID 2 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*2+0x4)++0x7 line.long 0x00 "FMQM_P2S,PortID 2 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P2TS,PortID 2 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*2+0x1C)++0x7 line.long 0x00 "FMQM_P2EN,PortID 2 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P2ETFC,PortID 2 Enqueue Total Frame Counter Register" group.long (0x1000*2+0x2C)++0x13 line.long 0x00 "FMQM_P2DN,PortID 2 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P2DC,PortID 2 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P2DTFC,PortID 2 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P2DFNOC,PortID 2 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P2DCC,PortID 2 Dequeue Confirmation Counter Register" tree.end tree "QMI Offline/Host Command Port Register 3" group.long (0x1000*3)++0x3 line.long 0x00 "FMQM_P3C,PortID 3 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*3+0x4)++0x7 line.long 0x00 "FMQM_P3S,PortID 3 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P3TS,PortID 3 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*3+0x1C)++0x7 line.long 0x00 "FMQM_P3EN,PortID 3 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P3ETFC,PortID 3 Enqueue Total Frame Counter Register" group.long (0x1000*3+0x2C)++0x13 line.long 0x00 "FMQM_P3DN,PortID 3 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P3DC,PortID 3 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P3DTFC,PortID 3 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P3DFNOC,PortID 3 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P3DCC,PortID 3 Dequeue Confirmation Counter Register" tree.end tree "QMI Offline/Host Command Port Register 4" group.long (0x1000*4)++0x3 line.long 0x00 "FMQM_P4C,PortID 4 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*4+0x4)++0x7 line.long 0x00 "FMQM_P4S,PortID 4 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P4TS,PortID 4 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*4+0x1C)++0x7 line.long 0x00 "FMQM_P4EN,PortID 4 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P4ETFC,PortID 4 Enqueue Total Frame Counter Register" group.long (0x1000*4+0x2C)++0x13 line.long 0x00 "FMQM_P4DN,PortID 4 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P4DC,PortID 4 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P4DTFC,PortID 4 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P4DFNOC,PortID 4 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P4DCC,PortID 4 Dequeue Confirmation Counter Register" tree.end tree "QMI Offline/Host Command Port Register 5" group.long (0x1000*5)++0x3 line.long 0x00 "FMQM_P5C,PortID 5 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*5+0x4)++0x7 line.long 0x00 "FMQM_P5S,PortID 5 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P5TS,PortID 5 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*5+0x1C)++0x7 line.long 0x00 "FMQM_P5EN,PortID 5 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P5ETFC,PortID 5 Enqueue Total Frame Counter Register" group.long (0x1000*5+0x2C)++0x13 line.long 0x00 "FMQM_P5DN,PortID 5 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P5DC,PortID 5 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P5DTFC,PortID 5 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P5DFNOC,PortID 5 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P5DCC,PortID 5 Dequeue Confirmation Counter Register" tree.end sif cpuis("LS10?6A") tree "QMI Tx Port Register 1" group.long (0x1000*0x28)++0x3 line.long 0x00 "FMQM_P40C,PortID 40 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x28+0x4)++0x7 line.long 0x00 "FMQM_P40S,PortID 40 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P40TS,PortID 40 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x28+0x1C)++0x7 line.long 0x00 "FMQM_P40EN,PortID 40 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P40ETFC,PortID 40 Enqueue Total Frame Counter Register" group.long (0x1000*0x28+0x2C)++0x13 line.long 0x00 "FMQM_P40DN,PortID 40 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P40DC,PortID 40 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P40DTFC,PortID 40 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P40DFNOC,PortID 40 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P40DCC,PortID 40 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 1" group.long (0x1000*0x28)++0x3 line.long 0x00 "FMQM_P40C,PortID 40 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x28+0x04)++0x7 line.long 0x00 "FMQM_P40S,PortID 40 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P40TS,PortID 40 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x28+0x1C)++0x7 line.long 0x00 "FMQM_P40EN,PortID 40 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P40ETFC,PortID 40 Enqueue Total Frame Counter Register" group.long (0x1000*0x28+0x2C)++0x13 line.long 0x00 "FMQM_P40DN,PortID 40 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P40DC,PortID 40 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P40DTFC,PortID 40 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P40DFNOC,PortID 40 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P40DCC,PortID 40 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 2" group.long (0x1000*0x29)++0x3 line.long 0x00 "FMQM_P41C,PortID 41 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x29+0x4)++0x7 line.long 0x00 "FMQM_P41S,PortID 41 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P41TS,PortID 41 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x29+0x1C)++0x7 line.long 0x00 "FMQM_P41EN,PortID 41 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P41ETFC,PortID 41 Enqueue Total Frame Counter Register" group.long (0x1000*0x29+0x2C)++0x13 line.long 0x00 "FMQM_P41DN,PortID 41 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P41DC,PortID 41 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P41DTFC,PortID 41 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P41DFNOC,PortID 41 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P41DCC,PortID 41 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 2" group.long (0x1000*0x29)++0x3 line.long 0x00 "FMQM_P41C,PortID 41 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x29+0x04)++0x7 line.long 0x00 "FMQM_P41S,PortID 41 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P41TS,PortID 41 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x29+0x1C)++0x7 line.long 0x00 "FMQM_P41EN,PortID 41 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P41ETFC,PortID 41 Enqueue Total Frame Counter Register" group.long (0x1000*0x29+0x2C)++0x13 line.long 0x00 "FMQM_P41DN,PortID 41 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P41DC,PortID 41 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P41DTFC,PortID 41 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P41DFNOC,PortID 41 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P41DCC,PortID 41 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 3" group.long (0x1000*0x2A)++0x3 line.long 0x00 "FMQM_P42C,PortID 42 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2A+0x4)++0x7 line.long 0x00 "FMQM_P42S,PortID 42 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P42TS,PortID 42 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2A+0x1C)++0x7 line.long 0x00 "FMQM_P42EN,PortID 42 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P42ETFC,PortID 42 Enqueue Total Frame Counter Register" group.long (0x1000*0x2A+0x2C)++0x13 line.long 0x00 "FMQM_P42DN,PortID 42 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P42DC,PortID 42 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P42DTFC,PortID 42 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P42DFNOC,PortID 42 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P42DCC,PortID 42 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 3" group.long (0x1000*0x2A)++0x3 line.long 0x00 "FMQM_P42C,PortID 42 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2A+0x04)++0x7 line.long 0x00 "FMQM_P42S,PortID 42 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P42TS,PortID 42 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2A+0x1C)++0x7 line.long 0x00 "FMQM_P42EN,PortID 42 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P42ETFC,PortID 42 Enqueue Total Frame Counter Register" group.long (0x1000*0x2A+0x2C)++0x13 line.long 0x00 "FMQM_P42DN,PortID 42 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P42DC,PortID 42 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P42DTFC,PortID 42 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P42DFNOC,PortID 42 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P42DCC,PortID 42 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 4" group.long (0x1000*0x2B)++0x3 line.long 0x00 "FMQM_P43C,PortID 43 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2B+0x4)++0x7 line.long 0x00 "FMQM_P43S,PortID 43 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P43TS,PortID 43 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2B+0x1C)++0x7 line.long 0x00 "FMQM_P43EN,PortID 43 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P43ETFC,PortID 43 Enqueue Total Frame Counter Register" group.long (0x1000*0x2B+0x2C)++0x13 line.long 0x00 "FMQM_P43DN,PortID 43 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P43DC,PortID 43 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P43DTFC,PortID 43 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P43DFNOC,PortID 43 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P43DCC,PortID 43 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 4" group.long (0x1000*0x2B)++0x3 line.long 0x00 "FMQM_P43C,PortID 43 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2B+0x04)++0x7 line.long 0x00 "FMQM_P43S,PortID 43 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P43TS,PortID 43 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2B+0x1C)++0x7 line.long 0x00 "FMQM_P43EN,PortID 43 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P43ETFC,PortID 43 Enqueue Total Frame Counter Register" group.long (0x1000*0x2B+0x2C)++0x13 line.long 0x00 "FMQM_P43DN,PortID 43 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P43DC,PortID 43 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P43DTFC,PortID 43 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P43DFNOC,PortID 43 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P43DCC,PortID 43 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 5" group.long (0x1000*0x2C)++0x3 line.long 0x00 "FMQM_P44C,PortID 44 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2C+0x4)++0x7 line.long 0x00 "FMQM_P44S,PortID 44 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P44TS,PortID 44 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2C+0x1C)++0x7 line.long 0x00 "FMQM_P44EN,PortID 44 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P44ETFC,PortID 44 Enqueue Total Frame Counter Register" group.long (0x1000*0x2C+0x2C)++0x13 line.long 0x00 "FMQM_P44DN,PortID 44 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P44DC,PortID 44 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P44DTFC,PortID 44 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P44DFNOC,PortID 44 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P44DCC,PortID 44 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 5" group.long (0x1000*0x2C)++0x3 line.long 0x00 "FMQM_P44C,PortID 44 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2C+0x04)++0x7 line.long 0x00 "FMQM_P44S,PortID 44 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P44TS,PortID 44 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2C+0x1C)++0x7 line.long 0x00 "FMQM_P44EN,PortID 44 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P44ETFC,PortID 44 Enqueue Total Frame Counter Register" group.long (0x1000*0x2C+0x2C)++0x13 line.long 0x00 "FMQM_P44DN,PortID 44 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P44DC,PortID 44 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P44DTFC,PortID 44 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P44DFNOC,PortID 44 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P44DCC,PortID 44 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 6" group.long (0x1000*0x2D)++0x3 line.long 0x00 "FMQM_P45C,PortID 45 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2D+0x4)++0x7 line.long 0x00 "FMQM_P45S,PortID 45 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P45TS,PortID 45 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2D+0x1C)++0x7 line.long 0x00 "FMQM_P45EN,PortID 45 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P45ETFC,PortID 45 Enqueue Total Frame Counter Register" group.long (0x1000*0x2D+0x2C)++0x13 line.long 0x00 "FMQM_P45DN,PortID 45 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P45DC,PortID 45 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P45DTFC,PortID 45 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P45DFNOC,PortID 45 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P45DCC,PortID 45 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 6" group.long (0x1000*0x2D)++0x3 line.long 0x00 "FMQM_P45C,PortID 45 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x2D+0x04)++0x7 line.long 0x00 "FMQM_P45S,PortID 45 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P45TS,PortID 45 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x2D+0x1C)++0x7 line.long 0x00 "FMQM_P45EN,PortID 45 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P45ETFC,PortID 45 Enqueue Total Frame Counter Register" group.long (0x1000*0x2D+0x2C)++0x13 line.long 0x00 "FMQM_P45DN,PortID 45 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P45DC,PortID 45 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P45DTFC,PortID 45 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P45DFNOC,PortID 45 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P45DCC,PortID 45 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 9" group.long (0x1000*0x30)++0x3 line.long 0x00 "FMQM_P48C,PortID 48 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x30+0x4)++0x7 line.long 0x00 "FMQM_P48S,PortID 48 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P48TS,PortID 48 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x30+0x1C)++0x7 line.long 0x00 "FMQM_P48EN,PortID 48 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P48ETFC,PortID 48 Enqueue Total Frame Counter Register" group.long (0x1000*0x30+0x2C)++0x13 line.long 0x00 "FMQM_P48DN,PortID 48 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P48DC,PortID 48 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P48DTFC,PortID 48 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P48DFNOC,PortID 48 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P48DCC,PortID 48 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Tx Port Register 9" group.long (0x1000*0x30)++0x3 line.long 0x00 "FMQM_P48C,PortID 48 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x30+0x04)++0x7 line.long 0x00 "FMQM_P48S,PortID 48 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P48TS,PortID 48 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x30+0x1C)++0x7 line.long 0x00 "FMQM_P48EN,PortID 48 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P48ETFC,PortID 48 Enqueue Total Frame Counter Register" group.long (0x1000*0x30+0x2C)++0x13 line.long 0x00 "FMQM_P48DN,PortID 48 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P48DC,PortID 48 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P48DTFC,PortID 48 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P48DFNOC,PortID 48 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P48DCC,PortID 48 Dequeue Confirmation Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Tx Port Register 10" group.long (0x1000*0x31)++0x3 line.long 0x00 "FMQM_P49C,PortID 49 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x31+0x4)++0x7 line.long 0x00 "FMQM_P49S,PortID 49 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P49TS,PortID 49 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x31+0x1C)++0x7 line.long 0x00 "FMQM_P49EN,PortID 49 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P49ETFC,PortID 49 Enqueue Total Frame Counter Register" group.long (0x1000*0x31+0x2C)++0x13 line.long 0x00 "FMQM_P49DN,PortID 49 Dequeue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P49DC,PortID 49 Dequeue NIA Register" bitfld.long 0x04 31. " PRI ,Priority option" "Normal,High" bitfld.long 0x04 28.--30. " OPT ,Options for dequeue source and type (precedence/Intra-Class Scheduling)" ",Priority/Respected,Active FQ/Respected,Active FQ/Override,?..." bitfld.long 0x04 25. " PF ,Pre-Fetch control" "Not full control,Full control" newline bitfld.long 0x04 20.--23. " SP ,Sub Portal (Channel) number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--15. 1. " BC ,Byte Count Level Control" line.long 0x08 "FMQM_P49DTFC,PortID 49 Dequeue Total Frame Counter" line.long 0x0C "FMQM_P49DFNOC,PortID 49 Dequeue FQID Not Override Counter Register" line.long 0x10 "FMQM_P49DCC,PortID 49 Dequeue Confirmation Counter Register" tree.end elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 1" group.long (0x1000*0x8)++0x3 line.long 0x00 "FMQM_P8C,PortID 8 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x8+0x4)++0x7 line.long 0x00 "FMQM_P8S,PortID 8 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P8TS,PortID 8 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x8+0x1C)++0x7 line.long 0x00 "FMQM_P8EN,PortID 8 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P8ETFC,PortID 8 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 1" group.long (0x1000*0x8)++0x3 line.long 0x00 "FMQM_P8C,PortID 8 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x8+0x4)++0x7 line.long 0x00 "FMQM_P8S,PortID 8 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P8TS,PortID 8 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x8+0x1C)++0x7 line.long 0x00 "FMQM_P8EN,PortID 8 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P8ETFC,PortID 8 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 2" group.long (0x1000*0x9)++0x3 line.long 0x00 "FMQM_P9C,PortID 9 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x9+0x4)++0x7 line.long 0x00 "FMQM_P9S,PortID 9 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P9TS,PortID 9 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x9+0x1C)++0x7 line.long 0x00 "FMQM_P9EN,PortID 9 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P9ETFC,PortID 9 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 2" group.long (0x1000*0x9)++0x3 line.long 0x00 "FMQM_P9C,PortID 9 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x9+0x4)++0x7 line.long 0x00 "FMQM_P9S,PortID 9 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P9TS,PortID 9 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x9+0x1C)++0x7 line.long 0x00 "FMQM_P9EN,PortID 9 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P9ETFC,PortID 9 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 3" group.long (0x1000*0xA)++0x3 line.long 0x00 "FMQM_P10C,PortID 10 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xA+0x4)++0x7 line.long 0x00 "FMQM_P10S,PortID 10 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P10TS,PortID 10 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xA+0x1C)++0x7 line.long 0x00 "FMQM_P10EN,PortID 10 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P10ETFC,PortID 10 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 3" group.long (0x1000*0xA)++0x3 line.long 0x00 "FMQM_P10C,PortID 10 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xA+0x4)++0x7 line.long 0x00 "FMQM_P10S,PortID 10 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P10TS,PortID 10 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xA+0x1C)++0x7 line.long 0x00 "FMQM_P10EN,PortID 10 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P10ETFC,PortID 10 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 4" group.long (0x1000*0xB)++0x3 line.long 0x00 "FMQM_P11C,PortID 11 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xB+0x4)++0x7 line.long 0x00 "FMQM_P11S,PortID 11 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P11TS,PortID 11 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xB+0x1C)++0x7 line.long 0x00 "FMQM_P11EN,PortID 11 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P11ETFC,PortID 11 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 4" group.long (0x1000*0xB)++0x3 line.long 0x00 "FMQM_P11C,PortID 11 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xB+0x4)++0x7 line.long 0x00 "FMQM_P11S,PortID 11 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P11TS,PortID 11 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xB+0x1C)++0x7 line.long 0x00 "FMQM_P11EN,PortID 11 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P11ETFC,PortID 11 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 5" group.long (0x1000*0xC)++0x3 line.long 0x00 "FMQM_P12C,PortID 12 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xC+0x4)++0x7 line.long 0x00 "FMQM_P12S,PortID 12 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P12TS,PortID 12 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xC+0x1C)++0x7 line.long 0x00 "FMQM_P12EN,PortID 12 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P12ETFC,PortID 12 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 5" group.long (0x1000*0xC)++0x3 line.long 0x00 "FMQM_P12C,PortID 12 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xC+0x4)++0x7 line.long 0x00 "FMQM_P12S,PortID 12 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P12TS,PortID 12 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xC+0x1C)++0x7 line.long 0x00 "FMQM_P12EN,PortID 12 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P12ETFC,PortID 12 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 6" group.long (0x1000*0xD)++0x3 line.long 0x00 "FMQM_P13C,PortID 13 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xD+0x4)++0x7 line.long 0x00 "FMQM_P13S,PortID 13 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P13TS,PortID 13 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xD+0x1C)++0x7 line.long 0x00 "FMQM_P13EN,PortID 13 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P13ETFC,PortID 13 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 6" group.long (0x1000*0xD)++0x3 line.long 0x00 "FMQM_P13C,PortID 13 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0xD+0x4)++0x7 line.long 0x00 "FMQM_P13S,PortID 13 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P13TS,PortID 13 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0xD+0x1C)++0x7 line.long 0x00 "FMQM_P13EN,PortID 13 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P13ETFC,PortID 13 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 9" group.long (0x1000*0x10)++0x3 line.long 0x00 "FMQM_P16C,PortID 16 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x10+0x4)++0x7 line.long 0x00 "FMQM_P16S,PortID 16 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P16TS,PortID 16 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x10+0x1C)++0x7 line.long 0x00 "FMQM_P16EN,PortID 16 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P16ETFC,PortID 16 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") tree "QMI Rx Port Register 9" group.long (0x1000*0x10)++0x3 line.long 0x00 "FMQM_P16C,PortID 16 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x10+0x4)++0x7 line.long 0x00 "FMQM_P16S,PortID 16 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P16TS,PortID 16 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x10+0x1C)++0x7 line.long 0x00 "FMQM_P16EN,PortID 16 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P16ETFC,PortID 16 Enqueue Total Frame Counter Register" tree.end endif sif cpuis("LS10?6A") tree "QMI Rx Port Register 10" group.long (0x1000*0x11)++0x3 line.long 0x00 "FMQM_P17C,PortID 17 Configuration Register" bitfld.long 0x00 31. " EN ,Enable portID" "Disabled,Enabled" bitfld.long 0x00 28. " STEN ,PortID counters enabled" "Disabled,Enabled" rgroup.long (0x1000*0x11+0x4)++0x7 line.long 0x00 "FMQM_P17S,PortID 17 Status Register" bitfld.long 0x00 31. " PBSY_DT ,PortID Busy Dequeue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 30. " PBSY_ET ,PortID Busy Enqueue TNUM Indication" "Not busy,Busy" bitfld.long 0x00 29. " PBSY_DF ,PortID Busy Dequeue FD Indication" "Not busy,Busy" line.long 0x04 "FMQM_P17TS,PortID 17 Task Status Register" hexmask.long.byte 0x04 24.--30. 1. " PETS ,PortID Enqueue TNUM Status" hexmask.long.byte 0x04 8.--14. 1. " PDTS ,PortID Dequeue TNUM Status" hexmask.long.byte 0x04 0.--6. 1. " PDFS ,PortID Dequeue FD Status" group.long (0x1000*0x11+0x1C)++0x7 line.long 0x00 "FMQM_P17EN,PortID 17 Enqueue NIA Register" bitfld.long 0x00 23. " ORR ,Order Restoration Required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine Code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." newline hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action Code" line.long 0x04 "FMQM_P17ETFC,PortID 17 Enqueue Total Frame Counter Register" tree.end elif cpuis("LS10?3A") endif endian.le width 0x0B tree.end tree "Frame Processing Manager" base ad:0x01A00000+0xC3000 width 14. endian.be wgroup.long 0x04++0x03 line.long 0x00 "FMFP_PRC,FPM Port_ID Control register" hexmask.long.byte 0x00 24.--29. 1. " PORT_ID ,Port_ID selection" bitfld.long 0x00 23. " RSP ,Release stalled Port_ID" "No effect,Release" newline bitfld.long 0x00 16.--17. " ORA ,FMan controllers association for order restoration" "No effect,FMan 1,FMan 2,?..." bitfld.long 0x00 0.--1. " CPA ,FMan controllers PORT_ID association" "No effect,FMan 1,FMan 2,Both" group.long 0xC++0x0B line.long 0x00 "FMFP_MXD,FPM Maximum Dispatches register" bitfld.long 0x00 24.--28. " DISP_LIM ,Dispatch limit" "No limit,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "FMFP_DIST1,FPM Dispatch Thresholds1 register" hexmask.long.byte 0x04 24.--31. 1. " PARTHR ,Parser dispatch threshold" hexmask.long.byte 0x04 16.--23. 1. " KGNTHR ,KeyGen dispatch threshold" hexmask.long.byte 0x04 8.--15. 1. " POLTHR ,Policer dispatch threshold" hexmask.long.byte 0x04 0.--7. 1. " BMITHR ,BMI dispatch threshold" line.long 0x08 "FMFP_DIST2,FPM Dispatch Thresholds2 register" hexmask.long.byte 0x08 24.--31. 1. " QENQTHR ,QMI_ENQ dispatch threshold" hexmask.long.byte 0x08 16.--23. 1. " FMC1THR ,FMan controller 1 dispatch threshold" hexmask.long.byte 0x08 8.--15. 1. " FMC2THR ,FMan controller 2 dispatch threshold" hexmask.long.byte 0x08 0.--7. 1. " QDEQTHR ,QMI_DEQ dispatch threshold" rgroup.long 0x18++0x03 line.long 0x00 "FM_EPI,FMan Error Pending Interrupt register" bitfld.long 0x00 31. " FPM_ERR ,Pending FPM error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " PMU_ERR ,Pending PMU error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 23. " BMI_ERR ,Pending BMI error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 22. " QMI_ERR ,Pending QMI error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 21. " PRSR_ERR ,Pending Parser error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 20. " KGN_ERR ,Pending KeyGen error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 19. " PLCR_ERR ,Pending Policer error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 18. " MUR_ERR ,Pending FMan internal memory error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRM_ERR ,Pending FMan controller configuration memory error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 16. " DMA_ERR ,Pending DMA error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 15. " P10G1_ERR ,Pending EMAC9 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " P1G0_ERR ,Pending EMAC1 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 13. " P1G1_ERR ,Pending EMAC2 error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 12. " P1G2_ERR ,Pending EMAC3 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 11. " P1G3_ERR ,Pending EMAC4 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " P1G4_ERR ,Pending EMAC5 error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " P1G5_ERR ,Pending EMAC6 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " P1G6_ERR ,Pending EMAC7 error interrupt" "No interrupt,Interrupt" bitfld.long 0x00 7. " P1G7_ERR ,Pending EMAC8 error interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " P10G2_ERR ,Pending EMAC10 error interrupt" "No interrupt,Interrupt" group.long 0x1C++0x03 line.long 0x00 "FM_RIE,FMan Rams Interrupt Enable register" bitfld.long 0x00 18. " MUR_ERR ,Multi-user ram error interrupt enable" "Masked,Enabled" bitfld.long 0x00 17. " IRM_ERR ,Instruction ram error interrupt enable" "Masked,Enabled" group.long 0x4++0x03 line.long 0x00 "FMFP_FCEV0,FPM FMan controller Event register 0" bitfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" bitfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" bitfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline bitfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" bitfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" bitfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline bitfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" bitfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" bitfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline bitfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" bitfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" bitfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline bitfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" bitfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" bitfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline bitfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" bitfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" bitfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline bitfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" bitfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" bitfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline bitfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" bitfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" bitfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline bitfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" bitfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" bitfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline bitfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" bitfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" bitfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline bitfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0x8++0x03 line.long 0x00 "FMFP_FCEV1,FPM FMan controller Event register 1" bitfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" bitfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" bitfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline bitfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" bitfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" bitfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline bitfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" bitfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" bitfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline bitfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" bitfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" bitfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline bitfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" bitfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" bitfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline bitfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" bitfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" bitfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline bitfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" bitfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" bitfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline bitfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" bitfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" bitfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline bitfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" bitfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" bitfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline bitfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" bitfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" bitfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline bitfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0xC++0x03 line.long 0x00 "FMFP_FCEV2,FPM FMan controller Event register 2" bitfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" bitfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" bitfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline bitfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" bitfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" bitfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline bitfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" bitfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" bitfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline bitfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" bitfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" bitfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline bitfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" bitfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" bitfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline bitfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" bitfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" bitfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline bitfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" bitfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" bitfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline bitfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" bitfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" bitfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline bitfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" bitfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" bitfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline bitfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" bitfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" bitfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline bitfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0x10++0x03 line.long 0x00 "FMFP_FCEV3,FPM FMan controller Event register 3" bitfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" bitfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" bitfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline bitfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" bitfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" bitfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline bitfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" bitfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" bitfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline bitfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" bitfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" bitfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline bitfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" bitfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" bitfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline bitfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" bitfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" bitfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline bitfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" bitfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" bitfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline bitfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" bitfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" bitfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline bitfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" bitfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" bitfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline bitfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" bitfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" bitfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline bitfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" bitfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0x40++0x03 line.long 0x00 "FMFP_CEE0,FPM FMan controller Event Enable register 0" bitfld.long 0x00 31. " MASK0 ,Mask bit 0" "Masked,Not masked" bitfld.long 0x00 30. " MASK1 ,Mask bit 1" "Masked,Not masked" bitfld.long 0x00 29. " MASK2 ,Mask bit 2" "Masked,Not masked" newline bitfld.long 0x00 28. " MASK3 ,Mask bit 3" "Masked,Not masked" bitfld.long 0x00 27. " MASK4 ,Mask bit 4" "Masked,Not masked" bitfld.long 0x00 26. " MASK5 ,Mask bit 5" "Masked,Not masked" newline bitfld.long 0x00 25. " MASK6 ,Mask bit 6" "Masked,Not masked" bitfld.long 0x00 24. " MASK7 ,Mask bit 7" "Masked,Not masked" bitfld.long 0x00 23. " MASK8 ,Mask bit 8" "Masked,Not masked" newline bitfld.long 0x00 22. " MASK9 ,Mask bit 9" "Masked,Not masked" bitfld.long 0x00 21. " MASK10 ,Mask bit 10" "Masked,Not masked" bitfld.long 0x00 20. " MASK11 ,Mask bit 11" "Masked,Not masked" newline bitfld.long 0x00 19. " MASK12 ,Mask bit 12" "Masked,Not masked" bitfld.long 0x00 18. " MASK13 ,Mask bit 13" "Masked,Not masked" bitfld.long 0x00 17. " MASK14 ,Mask bit 14" "Masked,Not masked" newline bitfld.long 0x00 16. " MASK15 ,Mask bit 15" "Masked,Not masked" bitfld.long 0x00 15. " MASK16 ,Mask bit 16" "Masked,Not masked" bitfld.long 0x00 14. " MASK17 ,Mask bit 17" "Masked,Not masked" newline bitfld.long 0x00 13. " MASK18 ,Mask bit 18" "Masked,Not masked" bitfld.long 0x00 12. " MASK19 ,Mask bit 19" "Masked,Not masked" bitfld.long 0x00 11. " MASK20 ,Mask bit 20" "Masked,Not masked" newline bitfld.long 0x00 10. " MASK21 ,Mask bit 21" "Masked,Not masked" bitfld.long 0x00 9. " MASK22 ,Mask bit 22" "Masked,Not masked" bitfld.long 0x00 8. " MASK23 ,Mask bit 23" "Masked,Not masked" newline bitfld.long 0x00 7. " MASK24 ,Mask bit 24" "Masked,Not masked" bitfld.long 0x00 6. " MASK25 ,Mask bit 25" "Masked,Not masked" bitfld.long 0x00 5. " MASK26 ,Mask bit 26" "Masked,Not masked" newline bitfld.long 0x00 4. " MASK27 ,Mask bit 27" "Masked,Not masked" bitfld.long 0x00 3. " MASK28 ,Mask bit 28" "Masked,Not masked" bitfld.long 0x00 2. " MASK29 ,Mask bit 29" "Masked,Not masked" newline bitfld.long 0x00 1. " MASK30 ,Mask bit 30" "Masked,Not masked" bitfld.long 0x00 0. " MASK31 ,Mask bit 31" "Masked,Not masked" group.long 0x44++0x03 line.long 0x00 "FMFP_CEE1,FPM FMan controller Event Enable register 1" bitfld.long 0x00 31. " MASK0 ,Mask bit 0" "Masked,Not masked" bitfld.long 0x00 30. " MASK1 ,Mask bit 1" "Masked,Not masked" bitfld.long 0x00 29. " MASK2 ,Mask bit 2" "Masked,Not masked" newline bitfld.long 0x00 28. " MASK3 ,Mask bit 3" "Masked,Not masked" bitfld.long 0x00 27. " MASK4 ,Mask bit 4" "Masked,Not masked" bitfld.long 0x00 26. " MASK5 ,Mask bit 5" "Masked,Not masked" newline bitfld.long 0x00 25. " MASK6 ,Mask bit 6" "Masked,Not masked" bitfld.long 0x00 24. " MASK7 ,Mask bit 7" "Masked,Not masked" bitfld.long 0x00 23. " MASK8 ,Mask bit 8" "Masked,Not masked" newline bitfld.long 0x00 22. " MASK9 ,Mask bit 9" "Masked,Not masked" bitfld.long 0x00 21. " MASK10 ,Mask bit 10" "Masked,Not masked" bitfld.long 0x00 20. " MASK11 ,Mask bit 11" "Masked,Not masked" newline bitfld.long 0x00 19. " MASK12 ,Mask bit 12" "Masked,Not masked" bitfld.long 0x00 18. " MASK13 ,Mask bit 13" "Masked,Not masked" bitfld.long 0x00 17. " MASK14 ,Mask bit 14" "Masked,Not masked" newline bitfld.long 0x00 16. " MASK15 ,Mask bit 15" "Masked,Not masked" bitfld.long 0x00 15. " MASK16 ,Mask bit 16" "Masked,Not masked" bitfld.long 0x00 14. " MASK17 ,Mask bit 17" "Masked,Not masked" newline bitfld.long 0x00 13. " MASK18 ,Mask bit 18" "Masked,Not masked" bitfld.long 0x00 12. " MASK19 ,Mask bit 19" "Masked,Not masked" bitfld.long 0x00 11. " MASK20 ,Mask bit 20" "Masked,Not masked" newline bitfld.long 0x00 10. " MASK21 ,Mask bit 21" "Masked,Not masked" bitfld.long 0x00 9. " MASK22 ,Mask bit 22" "Masked,Not masked" bitfld.long 0x00 8. " MASK23 ,Mask bit 23" "Masked,Not masked" newline bitfld.long 0x00 7. " MASK24 ,Mask bit 24" "Masked,Not masked" bitfld.long 0x00 6. " MASK25 ,Mask bit 25" "Masked,Not masked" bitfld.long 0x00 5. " MASK26 ,Mask bit 26" "Masked,Not masked" newline bitfld.long 0x00 4. " MASK27 ,Mask bit 27" "Masked,Not masked" bitfld.long 0x00 3. " MASK28 ,Mask bit 28" "Masked,Not masked" bitfld.long 0x00 2. " MASK29 ,Mask bit 29" "Masked,Not masked" newline bitfld.long 0x00 1. " MASK30 ,Mask bit 30" "Masked,Not masked" bitfld.long 0x00 0. " MASK31 ,Mask bit 31" "Masked,Not masked" group.long 0x48++0x03 line.long 0x00 "FMFP_CEE2,FPM FMan controller Event Enable register 2" bitfld.long 0x00 31. " MASK0 ,Mask bit 0" "Masked,Not masked" bitfld.long 0x00 30. " MASK1 ,Mask bit 1" "Masked,Not masked" bitfld.long 0x00 29. " MASK2 ,Mask bit 2" "Masked,Not masked" newline bitfld.long 0x00 28. " MASK3 ,Mask bit 3" "Masked,Not masked" bitfld.long 0x00 27. " MASK4 ,Mask bit 4" "Masked,Not masked" bitfld.long 0x00 26. " MASK5 ,Mask bit 5" "Masked,Not masked" newline bitfld.long 0x00 25. " MASK6 ,Mask bit 6" "Masked,Not masked" bitfld.long 0x00 24. " MASK7 ,Mask bit 7" "Masked,Not masked" bitfld.long 0x00 23. " MASK8 ,Mask bit 8" "Masked,Not masked" newline bitfld.long 0x00 22. " MASK9 ,Mask bit 9" "Masked,Not masked" bitfld.long 0x00 21. " MASK10 ,Mask bit 10" "Masked,Not masked" bitfld.long 0x00 20. " MASK11 ,Mask bit 11" "Masked,Not masked" newline bitfld.long 0x00 19. " MASK12 ,Mask bit 12" "Masked,Not masked" bitfld.long 0x00 18. " MASK13 ,Mask bit 13" "Masked,Not masked" bitfld.long 0x00 17. " MASK14 ,Mask bit 14" "Masked,Not masked" newline bitfld.long 0x00 16. " MASK15 ,Mask bit 15" "Masked,Not masked" bitfld.long 0x00 15. " MASK16 ,Mask bit 16" "Masked,Not masked" bitfld.long 0x00 14. " MASK17 ,Mask bit 17" "Masked,Not masked" newline bitfld.long 0x00 13. " MASK18 ,Mask bit 18" "Masked,Not masked" bitfld.long 0x00 12. " MASK19 ,Mask bit 19" "Masked,Not masked" bitfld.long 0x00 11. " MASK20 ,Mask bit 20" "Masked,Not masked" newline bitfld.long 0x00 10. " MASK21 ,Mask bit 21" "Masked,Not masked" bitfld.long 0x00 9. " MASK22 ,Mask bit 22" "Masked,Not masked" bitfld.long 0x00 8. " MASK23 ,Mask bit 23" "Masked,Not masked" newline bitfld.long 0x00 7. " MASK24 ,Mask bit 24" "Masked,Not masked" bitfld.long 0x00 6. " MASK25 ,Mask bit 25" "Masked,Not masked" bitfld.long 0x00 5. " MASK26 ,Mask bit 26" "Masked,Not masked" newline bitfld.long 0x00 4. " MASK27 ,Mask bit 27" "Masked,Not masked" bitfld.long 0x00 3. " MASK28 ,Mask bit 28" "Masked,Not masked" bitfld.long 0x00 2. " MASK29 ,Mask bit 29" "Masked,Not masked" newline bitfld.long 0x00 1. " MASK30 ,Mask bit 30" "Masked,Not masked" bitfld.long 0x00 0. " MASK31 ,Mask bit 31" "Masked,Not masked" group.long 0x4C++0x03 line.long 0x00 "FMFP_CEE3,FPM FMan controller Event Enable register 3" bitfld.long 0x00 31. " MASK0 ,Mask bit 0" "Masked,Not masked" bitfld.long 0x00 30. " MASK1 ,Mask bit 1" "Masked,Not masked" bitfld.long 0x00 29. " MASK2 ,Mask bit 2" "Masked,Not masked" newline bitfld.long 0x00 28. " MASK3 ,Mask bit 3" "Masked,Not masked" bitfld.long 0x00 27. " MASK4 ,Mask bit 4" "Masked,Not masked" bitfld.long 0x00 26. " MASK5 ,Mask bit 5" "Masked,Not masked" newline bitfld.long 0x00 25. " MASK6 ,Mask bit 6" "Masked,Not masked" bitfld.long 0x00 24. " MASK7 ,Mask bit 7" "Masked,Not masked" bitfld.long 0x00 23. " MASK8 ,Mask bit 8" "Masked,Not masked" newline bitfld.long 0x00 22. " MASK9 ,Mask bit 9" "Masked,Not masked" bitfld.long 0x00 21. " MASK10 ,Mask bit 10" "Masked,Not masked" bitfld.long 0x00 20. " MASK11 ,Mask bit 11" "Masked,Not masked" newline bitfld.long 0x00 19. " MASK12 ,Mask bit 12" "Masked,Not masked" bitfld.long 0x00 18. " MASK13 ,Mask bit 13" "Masked,Not masked" bitfld.long 0x00 17. " MASK14 ,Mask bit 14" "Masked,Not masked" newline bitfld.long 0x00 16. " MASK15 ,Mask bit 15" "Masked,Not masked" bitfld.long 0x00 15. " MASK16 ,Mask bit 16" "Masked,Not masked" bitfld.long 0x00 14. " MASK17 ,Mask bit 17" "Masked,Not masked" newline bitfld.long 0x00 13. " MASK18 ,Mask bit 18" "Masked,Not masked" bitfld.long 0x00 12. " MASK19 ,Mask bit 19" "Masked,Not masked" bitfld.long 0x00 11. " MASK20 ,Mask bit 20" "Masked,Not masked" newline bitfld.long 0x00 10. " MASK21 ,Mask bit 21" "Masked,Not masked" bitfld.long 0x00 9. " MASK22 ,Mask bit 22" "Masked,Not masked" bitfld.long 0x00 8. " MASK23 ,Mask bit 23" "Masked,Not masked" newline bitfld.long 0x00 7. " MASK24 ,Mask bit 24" "Masked,Not masked" bitfld.long 0x00 6. " MASK25 ,Mask bit 25" "Masked,Not masked" bitfld.long 0x00 5. " MASK26 ,Mask bit 26" "Masked,Not masked" newline bitfld.long 0x00 4. " MASK27 ,Mask bit 27" "Masked,Not masked" bitfld.long 0x00 3. " MASK28 ,Mask bit 28" "Masked,Not masked" bitfld.long 0x00 2. " MASK29 ,Mask bit 29" "Masked,Not masked" newline bitfld.long 0x00 1. " MASK30 ,Mask bit 30" "Masked,Not masked" bitfld.long 0x00 0. " MASK31 ,Mask bit 31" "Masked,Not masked" group.long 0x60++0x07 line.long 0x00 "FMFP_TSC1,FPM TimeStamp Control1 register" bitfld.long 0x00 31. " TEN ,Timestamp enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TSPV ,Timestamp Pre-scale value" line.long 0x04 "FMFP_TSC2,FPM TimeStamp Control2 register" hexmask.long.byte 0x04 16.--23. 1. " TSIV_INT ,Timestamp increment value integer" hexmask.long.word 0x04 0.--15. 1. " TSIV_FRAC ,Timestamp increment value fraction" rgroup.long 0x68++0x07 line.long 0x00 "FMFP_TSP,FPM TimeStamp register" line.long 0x04 "FMFP_TSF,FPM TimeStamp Fraction register" hexmask.long.word 0x04 16.--31. 1. " TS_FRACT ,Time stamp counter fraction bits value" group.long 0x70++0x03 line.long 0x00 "FM_RCR,FMan Rams Control and Event register" bitfld.long 0x00 31. " FEE ,FMan RAMs ECC enable" "Disabled,Enabled" bitfld.long 0x00 30. " IEE ,Instruction RAM ECC enable" "Disabled,Enabled" bitfld.long 0x00 27. " SFE ,Select FMan RAMS ECC enable source" "FEE,COP DCFG ECCCR" newline eventfld.long 0x00 15. " MDEC ,Double ECC error on multi-user ram access" "No error,Error" eventfld.long 0x00 14. " IDEC ,Double ECC error on instruction ram access" "No error,Error" group.long 0x74++0x03 line.long 0x00 "FMFP_EXTC,FPM External Requests Control register" bitfld.long 0x00 31. " INV0 ,Invoke external request 0" "Not invoked,Invoked" bitfld.long 0x00 30. " INV1 ,Invoke external request 1" "Not invoked,Invoked" bitfld.long 0x00 29. " INV2 ,Invoke external request 2" "Not invoked,Invoked" newline bitfld.long 0x00 28. " INV3 ,Invoke external request 3" "Not invoked,Invoked" bitfld.long 0x00 27. " INV4 ,Invoke external request 4" "Not invoked,Invoked" bitfld.long 0x00 26. " INV5 ,Invoke external request 5" "Not invoked,Invoked" newline bitfld.long 0x00 25. " INV6 ,Invoke external request 6" "Not invoked,Invoked" bitfld.long 0x00 24. " INV7 ,Invoke external request 7" "Not invoked,Invoked" hgroup.long 0x80++0x3 hide.long 0x00 "FMFP_DRD0,FPM Data Ram Data0" in hgroup.long 0x84++0x3 hide.long 0x00 "FMFP_DRD1,FPM Data Ram Data1" in hgroup.long 0x88++0x3 hide.long 0x00 "FMFP_DRD2,FPM Data Ram Data2" in hgroup.long 0x8C++0x3 hide.long 0x00 "FMFP_DRD3,FPM Data Ram Data3" in group.long 0xBC++0x03 line.long 0x00 "FM_DECCES,FM Double ECC Error Source register" bitfld.long 0x00 31. " BMI ,Non-masked BMI double ECC error" "No error,Error" bitfld.long 0x00 30. " QMI ,Non-masked QMI double ECC error" "No error,Error" bitfld.long 0x00 29. " DMA ,Non-masked DMA double ECC error" "No error,Error" bitfld.long 0x00 28. " POL ,Non-masked Policer double ECC error" "No error,Error" newline bitfld.long 0x00 27. " PAR ,Non-masked Parser double ECC error" "No error,Error" bitfld.long 0x00 26. " KGN ,Non-masked Keygen double ECC error" "No error,Error" bitfld.long 0x00 25. " MUR ,Non-masked Multi-User RAM double ECC error" "No error,Error" bitfld.long 0x00 24. " IR ,Non-masked Instruction RAM double ECC error" "No error,Error" newline bitfld.long 0x00 23. " X1GR ,Non-masked EMAC9 Rx double ECC error" "No error,Error" bitfld.long 0x00 22. " X1GT ,Non-masked EMAC9 Tx double ECC error" "No error,Error" bitfld.long 0x00 21. " X2GR ,Non-masked EMAC10 Rx double ECC error" "No error,Error" bitfld.long 0x00 20. " X2GT ,Non-masked EMAC10 Tx double ECC error" "No error,Error" newline bitfld.long 0x00 18. " FPM ,Non-masked FPM double ECC error" "No error,Error" bitfld.long 0x00 15. " TS1R ,Non-masked EMAC1 Rx double ECC error" "No error,Error" bitfld.long 0x00 14. " TS1T ,Non-masked EMAC1 Tx double ECC error" "No error,Error" bitfld.long 0x00 13. " TS2R ,Non-masked EMAC2 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 12. " TS2T ,Non-masked EMAC2 Tx double ECC error" "No error,Error" bitfld.long 0x00 11. " TS3R ,Non-masked EMAC3 Rx double ECC error" "No error,Error" bitfld.long 0x00 10. " TS3T ,Non-masked EMAC3 Tx double ECC error" "No error,Error" bitfld.long 0x00 9. " TS4R ,Non-masked EMAC4 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 8. " TS4T ,Non-masked EMAC4 Tx double ECC error" "No error,Error" bitfld.long 0x00 7. " TS5R ,Non-masked EMAC5 Rx double ECC error" "No error,Error" bitfld.long 0x00 6. " TS5T ,Non-masked EMAC5 Tx double ECC error" "No error,Error" bitfld.long 0x00 5. " TS6R ,Non-masked EMAC6 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 4. " TS6T ,Non-masked EMAC6 Tx double ECC error" "No error,Error" bitfld.long 0x00 3. " TS7R ,Non-masked EMAC7 Rx double ECC error" "No error,Error" bitfld.long 0x00 2. " TS7T ,Non-masked EMAC7 Tx double ECC error" "No error,Error" newline bitfld.long 0x00 1. " TS8R ,Non-masked EMAC8 Rx double ECC error" "No error,Error" bitfld.long 0x00 0. " TS8T ,Non-masked EMAC8 Tx double ECC error" "No error,Error" newline group.long 0xC0++0x03 line.long 0x00 "FMFP_DRA,FPM Data RAM Access register" hexmask.long.byte 0x00 24.--31. 1. " TNUM ,Task number" rgroup.long 0xC4++0x07 line.long 0x00 "FM_IP_REV_1,FMan IP Block Revision 1 register" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "FM_IP_REV_2,FMan IP Block Revision 2 register" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,Integration options" hexmask.long.byte 0x04 8.--15. 1. " IP_ERR ,Errata revision level" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,Configuration options" wgroup.long 0xCC++0x03 line.long 0x00 "FM_RSTC,FMan Reset Command register" bitfld.long 0x00 31. " RFM ,Entire FMan reset command" "No reset,Reset" group.long 0xD0++0x03 line.long 0x00 "FMFP_CLDC,FMan classifier Debug Control register" bitfld.long 0x00 28.--29. " TL_A ,Trace level flow A" "Disabled,Minimum,Verbose,?..." bitfld.long 0x00 26.--27. " TL_B ,Trace level flow B" "Disabled,Minimum,Verbose,?..." bitfld.long 0x00 24.--25. " TL_C ,Trace level flow C" "Disabled,Minimum,Verbose,?..." newline bitfld.long 0x00 20.--23. " TR_CO ,Trap collaboration" "No collaboration,flow A -> flow B,flow A -> flow C,flow A -> flow B -> flow C,?..." bitfld.long 0x00 15. " TPFE ,Tnum prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " CDD ,Dynamic clock disable for dma" "Disabled,Enabled" bitfld.long 0x00 10. " CDK ,Dynamic clock disable for keygen" "Disabled,Enabled" bitfld.long 0x00 9. " CDP ,Dynamic clock disable for parser" "Disabled,Enabled" newline bitfld.long 0x00 3. " FD3 ,FMan controller 3 Disable" "Disabled,Enabled" bitfld.long 0x00 2. " FD2 ,FMan controller 2 Disable" "Disabled,Enabled" bitfld.long 0x00 1. " FD1 ,FMan controller 1 Disable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FD0 ,FMan controller 0 Disable" "Disabled,Enabled" rgroup.long 0xD4++0x3 line.long 0x00 "FM_NPI,FMan Normal Pending Interrupt register" bitfld.long 0x00 29. " PRSR ,Pending Parser interrupt" "No interrupt,Interrupt" bitfld.long 0x00 28. " PMU ,Pending PMU interrupt" "No interrupt,Interrupt" bitfld.long 0x00 27. " PLCR ,Pending Policer interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 24. " TMR ,Pending 1588 Timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 21. " P10G2 ,Pending EMAC10 normal interrupt" "No interrupt,Interrupt" bitfld.long 0x00 20. " P10G1 ,Pending EMAC9 normal interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 19. " P1G0 ,Pending EMAC1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 18. " P1G1 ,Pending EMAC2 interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 17. " P1G2 ,Pending EMAC3 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 16. " P1G3 ,Pending EMAC4 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 15. " FCEVT0 ,Pending FMan controller Event0 interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 14. " FCEVT1 ,Pending FMan controller Event1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 13. " FCEVT2 ,Pending FMan controller Event2 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 12. " FCEVT3 ,Pending FMan controller Event3 interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 6. " P1G4T ,Pending EMAC4 interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " P1G5 ,Pending EMAC6 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " P1G6 ,Pending EMAC7 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " P1G7 ,Pending EMAC8 interrupt" "No interrupt,Interrupt" group.long 0xDC++0x03 line.long 0x00 "FMFP_EE,FPM Event and Enable register" eventfld.long 0x00 31. " DECC ,Double ECC error on FPM RAM access" "No error,Error" eventfld.long 0x00 30. " STL ,Stall of task(s)/Port_ID(s) on FPM" "No stall,Stall" eventfld.long 0x00 29. " SECC ,Single ECC error on FPM RAM access" "No error,Error" newline bitfld.long 0x00 16. " RFM ,Release FMan after halt FMan command or after unrecoverable ECC error" "Normal,Release FMan" bitfld.long 0x00 15. " DECC_EN ,Double ECC error (on FPM RAM access) interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " STL_EN ,Stall of task(s)/Port_ID(s) on FPM interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " SECC_EN ,Single ECC error (on FPM RAM access) interrupt mask" "Masked,Enabled" bitfld.long 0x00 3. " EHM ,External halt mask" "Halted,Not halted" newline bitfld.long 0x00 1. " CER ,Catastrophic error behavior" "Port_ID stalled,Task stalled" bitfld.long 0x00 0. " DER ,DMA error behavior" "Catastrophic,Reported" group.long 0xE0++0x03 line.long 0x00 "FMFP_CEV_0,Event Bit" eventfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" eventfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" eventfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline eventfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" eventfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" eventfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline eventfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" eventfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" eventfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline eventfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" eventfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" eventfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline eventfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" eventfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" eventfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline eventfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" eventfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" eventfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" eventfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" eventfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline eventfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" eventfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" eventfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline eventfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" eventfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" eventfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline eventfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" eventfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" eventfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline eventfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" eventfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0xE4++0x03 line.long 0x00 "FMFP_CEV_1,Event Bit" eventfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" eventfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" eventfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline eventfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" eventfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" eventfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline eventfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" eventfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" eventfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline eventfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" eventfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" eventfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline eventfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" eventfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" eventfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline eventfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" eventfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" eventfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" eventfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" eventfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline eventfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" eventfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" eventfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline eventfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" eventfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" eventfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline eventfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" eventfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" eventfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline eventfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" eventfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0xE8++0x03 line.long 0x00 "FMFP_CEV_2,Event Bit" eventfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" eventfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" eventfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline eventfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" eventfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" eventfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline eventfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" eventfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" eventfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline eventfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" eventfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" eventfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline eventfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" eventfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" eventfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline eventfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" eventfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" eventfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" eventfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" eventfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline eventfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" eventfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" eventfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline eventfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" eventfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" eventfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline eventfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" eventfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" eventfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline eventfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" eventfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" group.long 0xEC++0x03 line.long 0x00 "FMFP_CEV_3,Event Bit" eventfld.long 0x00 31. " EVENT0 ,Event bit 0" "Not occurred,Occurred" eventfld.long 0x00 30. " EVENT1 ,Event bit 1" "Not occurred,Occurred" eventfld.long 0x00 29. " EVENT2 ,Event bit 2" "Not occurred,Occurred" newline eventfld.long 0x00 28. " EVENT3 ,Event bit 3" "Not occurred,Occurred" eventfld.long 0x00 27. " EVENT4 ,Event bit 4" "Not occurred,Occurred" eventfld.long 0x00 26. " EVENT5 ,Event bit 5" "Not occurred,Occurred" newline eventfld.long 0x00 25. " EVENT6 ,Event bit 6" "Not occurred,Occurred" eventfld.long 0x00 24. " EVENT7 ,Event bit 7" "Not occurred,Occurred" eventfld.long 0x00 23. " EVENT8 ,Event bit 8" "Not occurred,Occurred" newline eventfld.long 0x00 22. " EVENT9 ,Event bit 9" "Not occurred,Occurred" eventfld.long 0x00 21. " EVENT10 ,Event bit 10" "Not occurred,Occurred" eventfld.long 0x00 20. " EVENT11 ,Event bit 11" "Not occurred,Occurred" newline eventfld.long 0x00 19. " EVENT12 ,Event bit 12" "Not occurred,Occurred" eventfld.long 0x00 18. " EVENT13 ,Event bit 13" "Not occurred,Occurred" eventfld.long 0x00 17. " EVENT14 ,Event bit 14" "Not occurred,Occurred" newline eventfld.long 0x00 16. " EVENT15 ,Event bit 15" "Not occurred,Occurred" eventfld.long 0x00 15. " EVENT16 ,Event bit 16" "Not occurred,Occurred" eventfld.long 0x00 14. " EVENT17 ,Event bit 17" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EVENT18 ,Event bit 18" "Not occurred,Occurred" eventfld.long 0x00 12. " EVENT19 ,Event bit 19" "Not occurred,Occurred" eventfld.long 0x00 11. " EVENT20 ,Event bit 20" "Not occurred,Occurred" newline eventfld.long 0x00 10. " EVENT21 ,Event bit 21" "Not occurred,Occurred" eventfld.long 0x00 9. " EVENT22 ,Event bit 22" "Not occurred,Occurred" eventfld.long 0x00 8. " EVENT23 ,Event bit 23" "Not occurred,Occurred" newline eventfld.long 0x00 7. " EVENT24 ,Event bit 24" "Not occurred,Occurred" eventfld.long 0x00 6. " EVENT25 ,Event bit 25" "Not occurred,Occurred" eventfld.long 0x00 5. " EVENT26 ,Event bit 26" "Not occurred,Occurred" newline eventfld.long 0x00 4. " EVENT27 ,Event bit 27" "Not occurred,Occurred" eventfld.long 0x00 3. " EVENT28 ,Event bit 28" "Not occurred,Occurred" eventfld.long 0x00 2. " EVENT29 ,Event bit 29" "Not occurred,Occurred" newline eventfld.long 0x00 1. " EVENT30 ,Event bit 30" "Not occurred,Occurred" eventfld.long 0x00 0. " EVENT31 ,Event bit 31" "Not occurred,Occurred" rgroup.long 0x100++0x03 line.long 0x00 "FMFP_PS_0,FPM Port_ID Status0 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x104++0x03 line.long 0x00 "FMFP_PS_1,FPM Port_ID Status1 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x108++0x03 line.long 0x00 "FMFP_PS_2,FPM Port_ID Status2 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x10C++0x03 line.long 0x00 "FMFP_PS_3,FPM Port_ID Status3 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x110++0x03 line.long 0x00 "FMFP_PS_4,FPM Port_ID Status4 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x114++0x03 line.long 0x00 "FMFP_PS_5,FPM Port_ID Status5 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x118++0x03 line.long 0x00 "FMFP_PS_6,FPM Port_ID Status6 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x11C++0x03 line.long 0x00 "FMFP_PS_7,FPM Port_ID Status7 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x120++0x03 line.long 0x00 "FMFP_PS_8,FPM Port_ID Status8 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x124++0x03 line.long 0x00 "FMFP_PS_9,FPM Port_ID Status9 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x128++0x03 line.long 0x00 "FMFP_PS_10,FPM Port_ID Status10 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x12C++0x03 line.long 0x00 "FMFP_PS_11,FPM Port_ID Status11 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x130++0x03 line.long 0x00 "FMFP_PS_12,FPM Port_ID Status12 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x134++0x03 line.long 0x00 "FMFP_PS_13,FPM Port_ID Status13 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x138++0x03 line.long 0x00 "FMFP_PS_14,FPM Port_ID Status14 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x13C++0x03 line.long 0x00 "FMFP_PS_15,FPM Port_ID Status15 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x140++0x03 line.long 0x00 "FMFP_PS_16,FPM Port_ID Status16 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x144++0x03 line.long 0x00 "FMFP_PS_17,FPM Port_ID Status17 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x148++0x03 line.long 0x00 "FMFP_PS_18,FPM Port_ID Status18 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x14C++0x03 line.long 0x00 "FMFP_PS_19,FPM Port_ID Status19 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x150++0x03 line.long 0x00 "FMFP_PS_20,FPM Port_ID Status20 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x154++0x03 line.long 0x00 "FMFP_PS_21,FPM Port_ID Status21 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x158++0x03 line.long 0x00 "FMFP_PS_22,FPM Port_ID Status22 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x15C++0x03 line.long 0x00 "FMFP_PS_23,FPM Port_ID Status23 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x160++0x03 line.long 0x00 "FMFP_PS_24,FPM Port_ID Status24 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x164++0x03 line.long 0x00 "FMFP_PS_25,FPM Port_ID Status25 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x168++0x03 line.long 0x00 "FMFP_PS_26,FPM Port_ID Status26 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x16C++0x03 line.long 0x00 "FMFP_PS_27,FPM Port_ID Status27 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x170++0x03 line.long 0x00 "FMFP_PS_28,FPM Port_ID Status28 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x174++0x03 line.long 0x00 "FMFP_PS_29,FPM Port_ID Status29 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x178++0x03 line.long 0x00 "FMFP_PS_30,FPM Port_ID Status30 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x17C++0x03 line.long 0x00 "FMFP_PS_31,FPM Port_ID Status31 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x180++0x03 line.long 0x00 "FMFP_PS_32,FPM Port_ID Status32 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x184++0x03 line.long 0x00 "FMFP_PS_33,FPM Port_ID Status33 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x188++0x03 line.long 0x00 "FMFP_PS_34,FPM Port_ID Status34 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x18C++0x03 line.long 0x00 "FMFP_PS_35,FPM Port_ID Status35 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x190++0x03 line.long 0x00 "FMFP_PS_36,FPM Port_ID Status36 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x194++0x03 line.long 0x00 "FMFP_PS_37,FPM Port_ID Status37 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x198++0x03 line.long 0x00 "FMFP_PS_38,FPM Port_ID Status38 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x19C++0x03 line.long 0x00 "FMFP_PS_39,FPM Port_ID Status39 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1A0++0x03 line.long 0x00 "FMFP_PS_40,FPM Port_ID Status40 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1A4++0x03 line.long 0x00 "FMFP_PS_41,FPM Port_ID Status41 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1A8++0x03 line.long 0x00 "FMFP_PS_42,FPM Port_ID Status42 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1AC++0x03 line.long 0x00 "FMFP_PS_43,FPM Port_ID Status43 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1B0++0x03 line.long 0x00 "FMFP_PS_44,FPM Port_ID Status44 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1B4++0x03 line.long 0x00 "FMFP_PS_45,FPM Port_ID Status45 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1B8++0x03 line.long 0x00 "FMFP_PS_46,FPM Port_ID Status46 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1BC++0x03 line.long 0x00 "FMFP_PS_47,FPM Port_ID Status47 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1C0++0x03 line.long 0x00 "FMFP_PS_48,FPM Port_ID Status48 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" rgroup.long 0x1C4++0x03 line.long 0x00 "FMFP_PS_49,FPM Port_ID Status49 register" bitfld.long 0x00 30.--31. " CPA ,FMan controller PortID association" "Constrained,,Unconstrained,?..." bitfld.long 0x00 23. " STL ,Stalled Port_ID" "Normal,Stalled" group.long 0x200++0x1F line.long 0x00 "FMFP_CLFABC,FMan classifier flow AB Control" bitfld.long 0x00 29.--31. " CMPOP_A ,Compare operator flow A" "Disabled,Always match,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND_A ,AND flow A" "OR,AND" newline bitfld.long 0x00 16.--20. " FSEL_A ,Field selection flow A" "Start color/Port ID/NIA,Start color/Port ID/FQID,,,End color/Port ID/NIA,End color/Port ID/FQID,?..." newline bitfld.long 0x00 13.--15. " CMPOP_B ,Compare Operator flow B" "Disabled,Always match,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 12. " AND_B ,AND flow B" "OR,AND" newline bitfld.long 0x00 0.--4. " FSEL_B ,Field selection flow B" "Start color/Port ID/NIA,Start color/Port ID/FQID,,,End color/Port ID/NIA,End color/Port ID/FQID,?..." line.long 0x04 "FMFP_CLFCC,FMan classifier flow C Control register" bitfld.long 0x04 29.--31. " CMPOP_C ,Compare Operator flow C" "Disabled,Always match,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x04 16.--20. " FSEL_C ,Field selection flow C" "Start color/Port ID/NIA,Start color/Port ID/FQID,,,End color/Port ID/NIA,End color/Port ID/FQID,?..." line.long 0x08 "FMFP_CLFAVAL,FMan classifier flow A value register" line.long 0x0C "FMFP_CLFBVAL,FMan classifier flow B value register" line.long 0x10 "FMFP_CLFCVAL,FMan classifier flow C value register" line.long 0x14 "FMFP_CLFAMSK,FMan classifier flow A mask register" line.long 0x18 "FMFP_CLFBMSK,FMan classifier flow B mask register" line.long 0x1C "FMFP_CLFCMSK,FMan classifier flow C mask register" rgroup.long 0x220++0x0B line.long 0x00 "FMFP_CLFAMC,FMan classifier flow A match count register" line.long 0x04 "FMFP_CLFBMC,FMan classifier flow B match count register" line.long 0x08 "FMFP_CLFCMC,FMan classifier flow C match count register" group.long 0x22C++0x03 line.long 0x00 "FM_DECCEH,FM Double ECC Error Halt register" bitfld.long 0x00 31. " BMI ,BMI double ECC error" "No error,Error" bitfld.long 0x00 30. " QMI ,QMI double ECC error" "No error,Error" bitfld.long 0x00 29. " DMA ,DMA double ECC error" "No error,Error" bitfld.long 0x00 28. " POL ,Policer double ECC error" "No error,Error" newline bitfld.long 0x00 27. " PAR ,Parser double ECC error" "No error,Error" bitfld.long 0x00 26. " KGN ,KeyGen double ECC error" "No error,Error" bitfld.long 0x00 25. " MUR ,Multi-User RAM double ECC error" "No error,Error" bitfld.long 0x00 24. " IR ,Instruction RAM double ECC error" "No error,Error" newline bitfld.long 0x00 23. " X1GR ,EMAC9 Rx double ECC error" "No error,Error" bitfld.long 0x00 22. " X1GT ,EMAC9 Tx double ECC error" "No error,Error" bitfld.long 0x00 21. " X2GR ,EMAC10 Rx double ECC error" "No error,Error" bitfld.long 0x00 20. " X2GT ,EMAC10 Tx double ECC error" "No error,Error" newline bitfld.long 0x00 18. " FPM ,FPM double ECC error" "No error,Error" bitfld.long 0x00 15. " TS1R ,EMAC1 Rx double ECC error" "No error,Error" bitfld.long 0x00 14. " TS1T ,EMAC1 Tx double ECC error" "No error,Error" bitfld.long 0x00 13. " TS2R ,EMAC2 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 12. " TS2T ,EMAC2 Tx double ECC error" "No error,Error" bitfld.long 0x00 11. " TS3R ,EMAC3 Rx double ECC error" "No error,Error" bitfld.long 0x00 10. " TS3T ,EMAC3 Tx double ECC error" "No error,Error" bitfld.long 0x00 9. " TS4R ,EMAC4 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 8. " TS4T ,EMAC4 Tx double ECC error" "No error,Error" bitfld.long 0x00 7. " TS5R ,EMAC5 Rx double ECC error" "No error,Error" bitfld.long 0x00 6. " TS5T ,EMAC5 Tx double ECC error" "No error,Error" bitfld.long 0x00 5. " TS6R ,EMAC6 Rx double ECC error" "No error,Error" newline bitfld.long 0x00 4. " TS6T ,EMAC6 Tx double ECC error" "No error,Error" bitfld.long 0x00 3. " TS7R ,EMAC7 Rx double ECC error" "No error,Error" bitfld.long 0x00 2. " TS7T ,EMAC7 Tx double ECC error" "No error,Error" newline bitfld.long 0x00 1. " TS8R ,EMAC8 Rx double ECC error" "No error,Error" bitfld.long 0x00 0. " TS8T ,EMAC8 Tx double ECC error" "No error,Error" tree "TNUM status" group.long 0x400++0x03 line.long 0x00 "FMFP_TS_0,FPM TNUM Status 0 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x404++0x03 line.long 0x00 "FMFP_TS_1,FPM TNUM Status 1 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x408++0x03 line.long 0x00 "FMFP_TS_2,FPM TNUM Status 2 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40C++0x03 line.long 0x00 "FMFP_TS_3,FPM TNUM Status 3 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x410++0x03 line.long 0x00 "FMFP_TS_4,FPM TNUM Status 4 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x414++0x03 line.long 0x00 "FMFP_TS_5,FPM TNUM Status 5 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x418++0x03 line.long 0x00 "FMFP_TS_6,FPM TNUM Status 6 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x41C++0x03 line.long 0x00 "FMFP_TS_7,FPM TNUM Status 7 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x420++0x03 line.long 0x00 "FMFP_TS_8,FPM TNUM Status 8 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x424++0x03 line.long 0x00 "FMFP_TS_9,FPM TNUM Status 9 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x428++0x03 line.long 0x00 "FMFP_TS_10,FPM TNUM Status 10 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x42C++0x03 line.long 0x00 "FMFP_TS_11,FPM TNUM Status 11 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x430++0x03 line.long 0x00 "FMFP_TS_12,FPM TNUM Status 12 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x434++0x03 line.long 0x00 "FMFP_TS_13,FPM TNUM Status 13 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x438++0x03 line.long 0x00 "FMFP_TS_14,FPM TNUM Status 14 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x43C++0x03 line.long 0x00 "FMFP_TS_15,FPM TNUM Status 15 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x440++0x03 line.long 0x00 "FMFP_TS_16,FPM TNUM Status 16 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x444++0x03 line.long 0x00 "FMFP_TS_17,FPM TNUM Status 17 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x448++0x03 line.long 0x00 "FMFP_TS_18,FPM TNUM Status 18 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x44C++0x03 line.long 0x00 "FMFP_TS_19,FPM TNUM Status 19 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x450++0x03 line.long 0x00 "FMFP_TS_20,FPM TNUM Status 20 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x454++0x03 line.long 0x00 "FMFP_TS_21,FPM TNUM Status 21 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x458++0x03 line.long 0x00 "FMFP_TS_22,FPM TNUM Status 22 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x45C++0x03 line.long 0x00 "FMFP_TS_23,FPM TNUM Status 23 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x460++0x03 line.long 0x00 "FMFP_TS_24,FPM TNUM Status 24 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x464++0x03 line.long 0x00 "FMFP_TS_25,FPM TNUM Status 25 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x468++0x03 line.long 0x00 "FMFP_TS_26,FPM TNUM Status 26 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x46C++0x03 line.long 0x00 "FMFP_TS_27,FPM TNUM Status 27 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x470++0x03 line.long 0x00 "FMFP_TS_28,FPM TNUM Status 28 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x474++0x03 line.long 0x00 "FMFP_TS_29,FPM TNUM Status 29 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x478++0x03 line.long 0x00 "FMFP_TS_30,FPM TNUM Status 30 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x47C++0x03 line.long 0x00 "FMFP_TS_31,FPM TNUM Status 31 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x480++0x03 line.long 0x00 "FMFP_TS_32,FPM TNUM Status 32 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x484++0x03 line.long 0x00 "FMFP_TS_33,FPM TNUM Status 33 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x488++0x03 line.long 0x00 "FMFP_TS_34,FPM TNUM Status 34 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x48C++0x03 line.long 0x00 "FMFP_TS_35,FPM TNUM Status 35 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x490++0x03 line.long 0x00 "FMFP_TS_36,FPM TNUM Status 36 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x494++0x03 line.long 0x00 "FMFP_TS_37,FPM TNUM Status 37 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x498++0x03 line.long 0x00 "FMFP_TS_38,FPM TNUM Status 38 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x49C++0x03 line.long 0x00 "FMFP_TS_39,FPM TNUM Status 39 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4A0++0x03 line.long 0x00 "FMFP_TS_40,FPM TNUM Status 40 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4A4++0x03 line.long 0x00 "FMFP_TS_41,FPM TNUM Status 41 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4A8++0x03 line.long 0x00 "FMFP_TS_42,FPM TNUM Status 42 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4AC++0x03 line.long 0x00 "FMFP_TS_43,FPM TNUM Status 43 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4B0++0x03 line.long 0x00 "FMFP_TS_44,FPM TNUM Status 44 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4B4++0x03 line.long 0x00 "FMFP_TS_45,FPM TNUM Status 45 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4B8++0x03 line.long 0x00 "FMFP_TS_46,FPM TNUM Status 46 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4BC++0x03 line.long 0x00 "FMFP_TS_47,FPM TNUM Status 47 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C0++0x03 line.long 0x00 "FMFP_TS_48,FPM TNUM Status 48 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C4++0x03 line.long 0x00 "FMFP_TS_49,FPM TNUM Status 49 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4C8++0x03 line.long 0x00 "FMFP_TS_50,FPM TNUM Status 50 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4CC++0x03 line.long 0x00 "FMFP_TS_51,FPM TNUM Status 51 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4D0++0x03 line.long 0x00 "FMFP_TS_52,FPM TNUM Status 52 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4D4++0x03 line.long 0x00 "FMFP_TS_53,FPM TNUM Status 53 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4D8++0x03 line.long 0x00 "FMFP_TS_54,FPM TNUM Status 54 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4DC++0x03 line.long 0x00 "FMFP_TS_55,FPM TNUM Status 55 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4E0++0x03 line.long 0x00 "FMFP_TS_56,FPM TNUM Status 56 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4E4++0x03 line.long 0x00 "FMFP_TS_57,FPM TNUM Status 57 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4E8++0x03 line.long 0x00 "FMFP_TS_58,FPM TNUM Status 58 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4EC++0x03 line.long 0x00 "FMFP_TS_59,FPM TNUM Status 59 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F0++0x03 line.long 0x00 "FMFP_TS_60,FPM TNUM Status 60 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F4++0x03 line.long 0x00 "FMFP_TS_61,FPM TNUM Status 61 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4F8++0x03 line.long 0x00 "FMFP_TS_62,FPM TNUM Status 62 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x4FC++0x03 line.long 0x00 "FMFP_TS_63,FPM TNUM Status 63 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x500++0x03 line.long 0x00 "FMFP_TS_64,FPM TNUM Status 64 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x504++0x03 line.long 0x00 "FMFP_TS_65,FPM TNUM Status 65 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x508++0x03 line.long 0x00 "FMFP_TS_66,FPM TNUM Status 66 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50C++0x03 line.long 0x00 "FMFP_TS_67,FPM TNUM Status 67 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x510++0x03 line.long 0x00 "FMFP_TS_68,FPM TNUM Status 68 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x514++0x03 line.long 0x00 "FMFP_TS_69,FPM TNUM Status 69 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x518++0x03 line.long 0x00 "FMFP_TS_70,FPM TNUM Status 70 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x51C++0x03 line.long 0x00 "FMFP_TS_71,FPM TNUM Status 71 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x520++0x03 line.long 0x00 "FMFP_TS_72,FPM TNUM Status 72 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x524++0x03 line.long 0x00 "FMFP_TS_73,FPM TNUM Status 73 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x528++0x03 line.long 0x00 "FMFP_TS_74,FPM TNUM Status 74 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x52C++0x03 line.long 0x00 "FMFP_TS_75,FPM TNUM Status 75 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x530++0x03 line.long 0x00 "FMFP_TS_76,FPM TNUM Status 76 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x534++0x03 line.long 0x00 "FMFP_TS_77,FPM TNUM Status 77 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x538++0x03 line.long 0x00 "FMFP_TS_78,FPM TNUM Status 78 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x53C++0x03 line.long 0x00 "FMFP_TS_79,FPM TNUM Status 79 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x540++0x03 line.long 0x00 "FMFP_TS_80,FPM TNUM Status 80 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x544++0x03 line.long 0x00 "FMFP_TS_81,FPM TNUM Status 81 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x548++0x03 line.long 0x00 "FMFP_TS_82,FPM TNUM Status 82 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x54C++0x03 line.long 0x00 "FMFP_TS_83,FPM TNUM Status 83 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x550++0x03 line.long 0x00 "FMFP_TS_84,FPM TNUM Status 84 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x554++0x03 line.long 0x00 "FMFP_TS_85,FPM TNUM Status 85 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x558++0x03 line.long 0x00 "FMFP_TS_86,FPM TNUM Status 86 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x55C++0x03 line.long 0x00 "FMFP_TS_87,FPM TNUM Status 87 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x560++0x03 line.long 0x00 "FMFP_TS_88,FPM TNUM Status 88 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x564++0x03 line.long 0x00 "FMFP_TS_89,FPM TNUM Status 89 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x568++0x03 line.long 0x00 "FMFP_TS_90,FPM TNUM Status 90 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x56C++0x03 line.long 0x00 "FMFP_TS_91,FPM TNUM Status 91 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x570++0x03 line.long 0x00 "FMFP_TS_92,FPM TNUM Status 92 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x574++0x03 line.long 0x00 "FMFP_TS_93,FPM TNUM Status 93 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x578++0x03 line.long 0x00 "FMFP_TS_94,FPM TNUM Status 94 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x57C++0x03 line.long 0x00 "FMFP_TS_95,FPM TNUM Status 95 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x580++0x03 line.long 0x00 "FMFP_TS_96,FPM TNUM Status 96 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x584++0x03 line.long 0x00 "FMFP_TS_97,FPM TNUM Status 97 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x588++0x03 line.long 0x00 "FMFP_TS_98,FPM TNUM Status 98 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58C++0x03 line.long 0x00 "FMFP_TS_99,FPM TNUM Status 99 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x590++0x03 line.long 0x00 "FMFP_TS_100,FPM TNUM Status 100 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x594++0x03 line.long 0x00 "FMFP_TS_101,FPM TNUM Status 101 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x598++0x03 line.long 0x00 "FMFP_TS_102,FPM TNUM Status 102 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x59C++0x03 line.long 0x00 "FMFP_TS_103,FPM TNUM Status 103 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5A0++0x03 line.long 0x00 "FMFP_TS_104,FPM TNUM Status 104 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5A4++0x03 line.long 0x00 "FMFP_TS_105,FPM TNUM Status 105 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5A8++0x03 line.long 0x00 "FMFP_TS_106,FPM TNUM Status 106 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5AC++0x03 line.long 0x00 "FMFP_TS_107,FPM TNUM Status 107 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B0++0x03 line.long 0x00 "FMFP_TS_108,FPM TNUM Status 108 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B4++0x03 line.long 0x00 "FMFP_TS_109,FPM TNUM Status 109 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B8++0x03 line.long 0x00 "FMFP_TS_110,FPM TNUM Status 110 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5BC++0x03 line.long 0x00 "FMFP_TS_111,FPM TNUM Status 111 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C0++0x03 line.long 0x00 "FMFP_TS_112,FPM TNUM Status 112 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C4++0x03 line.long 0x00 "FMFP_TS_113,FPM TNUM Status 113 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C8++0x03 line.long 0x00 "FMFP_TS_114,FPM TNUM Status 114 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5CC++0x03 line.long 0x00 "FMFP_TS_115,FPM TNUM Status 115 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5D0++0x03 line.long 0x00 "FMFP_TS_116,FPM TNUM Status 116 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5D4++0x03 line.long 0x00 "FMFP_TS_117,FPM TNUM Status 117 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5D8++0x03 line.long 0x00 "FMFP_TS_118,FPM TNUM Status 118 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5DC++0x03 line.long 0x00 "FMFP_TS_119,FPM TNUM Status 119 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5E0++0x03 line.long 0x00 "FMFP_TS_120,FPM TNUM Status 120 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5E4++0x03 line.long 0x00 "FMFP_TS_121,FPM TNUM Status 121 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5E8++0x03 line.long 0x00 "FMFP_TS_122,FPM TNUM Status 122 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5EC++0x03 line.long 0x00 "FMFP_TS_123,FPM TNUM Status 123 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5F0++0x03 line.long 0x00 "FMFP_TS_124,FPM TNUM Status 124 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5F4++0x03 line.long 0x00 "FMFP_TS_125,FPM TNUM Status 125 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5F8++0x03 line.long 0x00 "FMFP_TS_126,FPM TNUM Status 126 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5FC++0x03 line.long 0x00 "FMFP_TS_127,FPM TNUM Status 127 register" bitfld.long 0x00 30.--31. " CTA ,FMan controller task association" "Port_ID FMan,Constrained,Unconstrained,?..." bitfld.long 0x00 25. " STL ,Stalled task" "Normal,Stalled" bitfld.long 0x00 24. " PRK ,Parked task" "Not parked,Parked" newline bitfld.long 0x00 23. " INEX ,Task in execution" "Normal,Executing" bitfld.long 0x00 22. " EXEC ,Task should be executed" "Normal,Execute" bitfld.long 0x00 21. " EOT ,Task should end" "Normal,End" newline bitfld.long 0x00 20. " SYNC ,Syncable task" "Not syncable,Syncable" bitfld.long 0x00 19. " ORD ,Ordered task" "Not ordered,Ordered" bitfld.long 0x00 18. " NIG ,Task should be ignited" "Normal,Ignite" newline bitfld.long 0x00 17. " DER ,Task with Error" "No error,Error" bitfld.long 0x00 16. " ORR ,Task with order restoration" "Not requested,Requested" hexmask.long.byte 0x00 8.--14. 1. " ODC ,Open DMA Count" newline bitfld.long 0x00 0.--4. " DISPC ,Dispatches Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end endian.le width 0x0B tree.end tree "Frame Manager DMA" base ad:0x01A00000+0xC2000 width 11. endian.be group.long 0x00++0x13 line.long 0x00 "FMDM_SR,FMan DMA Status Register" rbitfld.long 0x00 28. " CMDQNE ,Indication that the command queue is not empty" "No error,Error" eventfld.long 0x00 27. " BER ,Bus error event" "No error,Error" eventfld.long 0x00 26. " RDB_ECC ,Read buffer ECC error" "No error,Error" eventfld.long 0x00 25. " WRB_SECC ,Write buffer ECC error on system side" "No error,Error" newline eventfld.long 0x00 24. " WRB_FECC ,Write buffer ECC error on FMan side" "No error,Error" eventfld.long 0x00 23. " DPEXT_SECC ,Dual port external add ECC error on system side" "No error,Error" eventfld.long 0x00 22. " DPEXT_FECC ,Dual port external add ECC error on FMan side" "No error,Error" newline eventfld.long 0x00 21. " DPDAT_SECC ,Dual port data ECC error on system side" "No error,Error" eventfld.long 0x00 20. " DPDAT_FECC ,Dual port data ECC error on FMan side" "No error,Error" eventfld.long 0x00 19. " SPDAT_FECC ,Single port data ECC error on FMan side" "No error,Error" line.long 0x04 "FMDM_MR,FMan DMA Mode Register" bitfld.long 0x04 30.--31. " CACHE_OVRD ,Override the cache field on the command bus" "No override,Not stashed,Can be stashed,Must be stashed" bitfld.long 0x04 29. " AID_OVRD ,AID override" "Normal,Override" bitfld.long 0x04 21. " BER_MSK ,Mask external bus error events" "Masked,Enabled" newline bitfld.long 0x04 20. " EB_MSK ,Mask emergency on external bus" "Masked,Enabled" bitfld.long 0x04 16.--17. " EB_EME ,Set priority on external bus" "Normal,EBS,SOS,EBS + SOS" bitfld.long 0x04 13.--15. " CEN ,DMA buffer size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7.--9. " DBG_CNT ,Set the debug counter to count the following signal" "No counting,DONE commands,CMDQ emergency,,,FPM WAIT,Single bit ECC errors,?..." bitfld.long 0x04 6. " BMI_EMR ,Emergency level that is set by BMI emergency signal" "EBS,SOS" bitfld.long 0x04 5. " ECC_MSK ,Mask ECC error events" "Masked,Enabled" line.long 0x08 "FMDM_TR,FMan DMA Threshold Register" hexmask.long.byte 0x08 24.--31. 1. " CQTH ,Command queue threshold" line.long 0x0C "FMDM_HY,FMan DMA Bus Hysteresis Register" hexmask.long.byte 0x0C 24.--31. 1. " CQHY ,Command queue hysteresis" line.long 0x10 "FMDM_SETR,FMan DMA SOS Emergency Threshold Register" newline rgroup.long 0x14++0x0B line.long 0x00 "FMDM_TAH,FMan DMA Transfer Bus Address High Register" hexmask.long.word 0x00 0.--15. 0x01 " TRANSFER_ADDRESS_HIGH ,16 MSB bits of the address accessed during current bus transaction" line.long 0x04 "FMDM_TAL,FMan DMA Transfer Bus Address Low Register" line.long 0x08 "FMDM_TCID,FMan DMA Transfer Bus Communication ID Register" hexmask.long.byte 0x08 24.--31. 1. " PORT_ID ,Port ID served during current bus transaction" hexmask.long.byte 0x08 16.--23. 1. " TNUM ,TNUM served during current bus transaction" bitfld.long 0x08 12.--15. " DONET ,DONE TAG served during current bus transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 0.--7. 1. " ICID ,ICID served during current bus transaction" group.long 0x28++0x07 line.long 0x00 "FMDMWCR,FMan DMA Buffer Watchdog Counter Value" line.long 0x04 "FMDMEBCR,FMan DMA Buffer Base in FMan Memory Value Register" hexmask.long.tbyte 0x04 0.--23. 0x01 " BA ,DMA buffer base address in Fman memory" group.long 0x54++0x07 line.long 0x00 "FMDMDCR,FMan DMA Debug Counter" line.long 0x04 "FMDMEMSR,FMan DMA EMergency Smoother Register" hexmask.long.word 0x04 0.--15. 1. " EMSTR ,Preprogrammed value for the emergency switching counter" newline group.long 0x60++0x03 line.long 0x00 "FMDMPLR0,FMan DMA PID-LIODN 0 Register" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE1 ,Port ID 1 base address" group.long 0x64++0x03 line.long 0x00 "FMDMPLR1,FMan DMA PID-LIODN 1 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE2 ,Port ID 2 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE3 ,Port ID 3 base address" group.long 0x68++0x03 line.long 0x00 "FMDMPLR2,FMan DMA PID-LIODN 2 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE4 ,Port ID 4 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE5 ,Port ID 5 base address" group.long 0x6C++0x03 line.long 0x00 "FMDMPLR3,FMan DMA PID-LIODN 3 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE6 ,Port ID 6 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE7 ,Port ID 7 base address" group.long 0x70++0x03 line.long 0x00 "FMDMPLR4,FMan DMA PID-LIODN 4 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE8 ,Port ID 8 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE9 ,Port ID 9 base address" group.long 0x74++0x03 line.long 0x00 "FMDMPLR5,FMan DMA PID-LIODN 5 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE10 ,Port ID 10 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE11 ,Port ID 11 base address" group.long 0x78++0x03 line.long 0x00 "FMDMPLR6,FMan DMA PID-LIODN 6 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE12 ,Port ID 12 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE13 ,Port ID 13 base address" group.long 0x7C++0x03 line.long 0x00 "FMDMPLR7,FMan DMA PID-LIODN 7 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE14 ,Port ID 14 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE15 ,Port ID 15 base address" group.long 0x80++0x03 line.long 0x00 "FMDMPLR8,FMan DMA PID-LIODN 8 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE16 ,Port ID 16 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE17 ,Port ID 17 base address" group.long 0x84++0x03 line.long 0x00 "FMDMPLR9,FMan DMA PID-LIODN 9 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE18 ,Port ID 18 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE19 ,Port ID 19 base address" group.long 0x88++0x03 line.long 0x00 "FMDMPLR10,FMan DMA PID-LIODN 10 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE20 ,Port ID 20 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE21 ,Port ID 21 base address" group.long 0x8C++0x03 line.long 0x00 "FMDMPLR11,FMan DMA PID-LIODN 11 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE22 ,Port ID 22 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE23 ,Port ID 23 base address" group.long 0x90++0x03 line.long 0x00 "FMDMPLR12,FMan DMA PID-LIODN 12 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE24 ,Port ID 24 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE25 ,Port ID 25 base address" group.long 0x94++0x03 line.long 0x00 "FMDMPLR13,FMan DMA PID-LIODN 13 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE26 ,Port ID 26 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE27 ,Port ID 27 base address" group.long 0x98++0x03 line.long 0x00 "FMDMPLR14,FMan DMA PID-LIODN 14 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE28 ,Port ID 28 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE29 ,Port ID 29 base address" group.long 0x9C++0x03 line.long 0x00 "FMDMPLR15,FMan DMA PID-LIODN 15 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE30 ,Port ID 30 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE31 ,Port ID 31 base address" group.long 0xA0++0x03 line.long 0x00 "FMDMPLR16,FMan DMA PID-LIODN 16 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE32 ,Port ID 32 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE33 ,Port ID 33 base address" group.long 0xA4++0x03 line.long 0x00 "FMDMPLR17,FMan DMA PID-LIODN 17 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE34 ,Port ID 34 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE35 ,Port ID 35 base address" group.long 0xA8++0x03 line.long 0x00 "FMDMPLR18,FMan DMA PID-LIODN 18 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE36 ,Port ID 36 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE37 ,Port ID 37 base address" group.long 0xAC++0x03 line.long 0x00 "FMDMPLR19,FMan DMA PID-LIODN 19 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE38 ,Port ID 38 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE39 ,Port ID 39 base address" group.long 0xB0++0x03 line.long 0x00 "FMDMPLR20,FMan DMA PID-LIODN 20 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE40 ,Port ID 40 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE41 ,Port ID 41 base address" group.long 0xB4++0x03 line.long 0x00 "FMDMPLR21,FMan DMA PID-LIODN 21 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE42 ,Port ID 42 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE43 ,Port ID 43 base address" group.long 0xB8++0x03 line.long 0x00 "FMDMPLR22,FMan DMA PID-LIODN 22 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE44 ,Port ID 44 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE45 ,Port ID 45 base address" group.long 0xBC++0x03 line.long 0x00 "FMDMPLR23,FMan DMA PID-LIODN 23 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE46 ,Port ID 46 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE47 ,Port ID 47 base address" group.long 0xC0++0x03 line.long 0x00 "FMDMPLR24,FMan DMA PID-LIODN 24 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE48 ,Port ID 48 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE49 ,Port ID 49 base address" group.long 0xC4++0x03 line.long 0x00 "FMDMPLR25,FMan DMA PID-LIODN 25 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE50 ,Port ID 50 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE51 ,Port ID 51 base address" group.long 0xC8++0x03 line.long 0x00 "FMDMPLR26,FMan DMA PID-LIODN 26 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE52 ,Port ID 52 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE53 ,Port ID 53 base address" group.long 0xCC++0x03 line.long 0x00 "FMDMPLR27,FMan DMA PID-LIODN 27 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE54 ,Port ID 54 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE55 ,Port ID 55 base address" group.long 0xD0++0x03 line.long 0x00 "FMDMPLR28,FMan DMA PID-LIODN 28 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE56 ,Port ID 56 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE57 ,Port ID 57 base address" group.long 0xD4++0x03 line.long 0x00 "FMDMPLR29,FMan DMA PID-LIODN 29 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE58 ,Port ID 58 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE59 ,Port ID 59 base address" group.long 0xD8++0x03 line.long 0x00 "FMDMPLR30,FMan DMA PID-LIODN 30 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE60 ,Port ID 60 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE61 ,Port ID 61 base address" group.long 0xDC++0x03 line.long 0x00 "FMDMPLR31,FMan DMA PID-LIODN 31 Register" hexmask.long.word 0x00 16.--27. 0x01 " PORTID_BASE62 ,Port ID 62 base address" hexmask.long.word 0x00 0.--11. 0x01 " PORTID_BASE63 ,Port ID 63 base address" endian.le width 0x0B tree.end tree "Frame Manager Parser" base ad:0x01A00000+0x81800 width 15. endian.be tree "Ports Configuration" tree "Port 2" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x1000+0x3F8)++0x07 line.long 0x00 "FMPR_P2CAC,Port 2 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 2" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 2" "Not stopped,Stopped" line.long 0x04 "FMPR_P2CTPID,Port 2 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 3" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x2000+0x3F8)++0x07 line.long 0x00 "FMPR_P3CAC,Port 3 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 3" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 3" "Not stopped,Stopped" line.long 0x04 "FMPR_P3CTPID,Port 3 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 4" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x3000+0x3F8)++0x07 line.long 0x00 "FMPR_P4CAC,Port 4 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 4" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 4" "Not stopped,Stopped" line.long 0x04 "FMPR_P4CTPID,Port 4 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 5" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x4000+0x3F8)++0x07 line.long 0x00 "FMPR_P5CAC,Port 5 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 5" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 5" "Not stopped,Stopped" line.long 0x04 "FMPR_P5CTPID,Port 5 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 8" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x7000+0x3F8)++0x07 line.long 0x00 "FMPR_P8CAC,Port 8 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 8" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 8" "Not stopped,Stopped" line.long 0x04 "FMPR_P8CTPID,Port 8 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 9" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x8000+0x3F8)++0x07 line.long 0x00 "FMPR_P9CAC,Port 9 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 9" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 9" "Not stopped,Stopped" line.long 0x04 "FMPR_P9CTPID,Port 9 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 10" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0x9000+0x3F8)++0x07 line.long 0x00 "FMPR_P10CAC,Port 10 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 10" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 10" "Not stopped,Stopped" line.long 0x04 "FMPR_P10CTPID,Port 10 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 11" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0xA000+0x3F8)++0x07 line.long 0x00 "FMPR_P11CAC,Port 11 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 11" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 11" "Not stopped,Stopped" line.long 0x04 "FMPR_P11CTPID,Port 11 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 12" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0xB000+0x3F8)++0x07 line.long 0x00 "FMPR_P12CAC,Port 12 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 12" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 12" "Not stopped,Stopped" line.long 0x04 "FMPR_P12CTPID,Port 12 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 13" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0xC000+0x3F8)++0x07 line.long 0x00 "FMPR_P13CAC,Port 13 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 13" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 13" "Not stopped,Stopped" line.long 0x04 "FMPR_P13CTPID,Port 13 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end tree "Port 16" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" group.long (0xF000+0x3F8)++0x07 line.long 0x00 "FMPR_P16CAC,Port 16 Configuration Access Control" bitfld.long 0x00 8. " PSTAT ,Parser Status port 16" "Idle,Active" bitfld.long 0x00 0. " PSTOP ,Parser Stop port 16" "Not stopped,Stopped" line.long 0x04 "FMPR_P16CTPID,Port 16 Configured TPID" hexmask.long.word 0x04 16.--31. 1. " CONFIGTPID1 ,Configured TPID 1" hexmask.long.word 0x04 0.--15. 1. " CONFIGTPID2 ,Configured TPID 2" tree.end sif cpuis("LS10?6A") tree "Port 17" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "Port 40" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 40" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 41" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 41" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 42" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 42" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 43" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 43" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 44" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 44" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 45" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 45" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") elif cpuis("LS10?3A") endif sif cpuis("LS10?6A") tree "Port 48" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") tree "Port 48" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end endif sif cpuis("LS10?6A") tree "Port 49" group.long 0x00++0x7F line.long 0x00 "EHSSA,Ethernet HXS Soft Sequence Attachment" hexmask.long.byte 0x00 28.--31. 0x10 " BCPO ,broadcast classification plan ID offset" hexmask.long.byte 0x00 24.--27. 0x01 " MCPO ,multicast classification plan ID offset" bitfld.long 0x00 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x00 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " SSS ,Soft sequence start" line.long 0x04 "EHLECM,Ethernet HXS Line-up Enable Confirmation Mask" line.long 0x08 "LSHSSA,LLC SNAP HXS Soft Sequence Attachment" bitfld.long 0x08 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x08 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--9. 1. " SSS ,Soft sequence start" line.long 0x0C "LSHLECM,LLC SNAP HXS Line-up Enable Confirmation Mask" line.long 0x10 "VHSSA,VLAN HXS Soft Sequence Attachment" hexmask.long.byte 0x10 16.--19. 0x01 " SVLANPO ,Stacked VLAN classification plan ID offset" bitfld.long 0x10 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x10 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x10 0.--9. 1. " SSS ,Soft sequence start" line.long 0x14 "VHLECM,VLAN HXS Line-up Enable Confirmation Mask" line.long 0x18 "PPSHSA,PPPoE PPP HXS Soft Sequence Attachment" bitfld.long 0x18 31. " ENMTUCHK ,Enable MTU checking" "Disabled,Enabled" bitfld.long 0x18 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x18 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x18 0.--9. 1. " SSS ,Soft sequence start" line.long 0x1C "PPHLECM,PPPoE PPP HXS Line-up Enable Confirmation Mask" line.long 0x20 "MHSSA,MPLS HXS Soft Sequence Attachment" hexmask.long.word 0x20 22.--31. 0x40 " MPLSDNP ,MPLS default next parse index" bitfld.long 0x20 21. " MPLSLIEN ,MPLS label interpretation enable" "Disabled,Enabled" hexmask.long.byte 0x20 16.--19. 0x01 " SMPLSPO ,Stacked MPLS classification plan ID offset" bitfld.long 0x20 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x20 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x20 0.--9. 1. " SSS ,Soft sequence start" line.long 0x24 "MHLECM,MPLS HXS Line-up Enable Confirmation Mask" line.long 0x28 "I4HSSA,IPv4 HXS Soft Sequence Attachment" hexmask.long.byte 0x28 28.--31. 0x10 " IPV4_1BCPO ,IPV4_1 broadcast classification plan ID offset" hexmask.long.byte 0x28 24.--27. 0x01 " IPV4_1MCPO ,IPV4_1 multicast classification plan ID offset" hexmask.long.byte 0x28 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x28 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x28 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x28 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x28 0.--9. 1. " SSS ,Soft sequence start" line.long 0x2C "I4HLECM,IPv4 HXS Line-up Enable Confirmation Mask" line.long 0x30 "I6HSSA,IPv6 HXS Soft Sequence Attachment" hexmask.long.byte 0x30 28.--31. 0x10 " IPV6_1BCPO ,IPV6_1 broadcast classification plan ID offset" hexmask.long.byte 0x30 24.--27. 0x01 " IPV6_1MCPO ,IPV6_1 multicast classification plan ID offset" hexmask.long.byte 0x30 20.--23. 0x10 " IP2UCPO ,IP2 Unicast classification plan ID offset" hexmask.long.byte 0x30 16.--19. 0x01 " IP2MCBCPO ,IP2 multicast/broadcast classification plan ID offset" newline bitfld.long 0x30 15. " RHE ,Routing header enable" "Disabled,Enabled" bitfld.long 0x30 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x30 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x30 0.--9. 1. " SSS ,Soft sequence start" line.long 0x34 "I6HLECM,IPv6 HXS Line-up Enable Confirmation Mask" line.long 0x38 "GHSSA,GRE HXS Soft Sequence Attachment" bitfld.long 0x38 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x38 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x38 0.--9. 1. " SSS ,Soft sequence start" line.long 0x3C "GHLECM,GRE HXS Line-up Enable Confirmation Mask" line.long 0x40 "MEHSSA,MinEncap HXS Soft Sequence Attachment" bitfld.long 0x40 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x40 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x40 0.--9. 1. " SSS ,Soft sequence start" line.long 0x44 "MEHLECM,MinEncap HXS Line-up Enable Confirmation Mask" line.long 0x48 "OL3SHSSA,Other L3 Shell HXS Soft Sequence Attachment" bitfld.long 0x48 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x48 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x48 0.--9. 1. " SSS ,Soft sequence start" line.long 0x4C "OL3SHLECM,Other L3 Shell HXS Line-up Enable Confirmation Mask" line.long 0x50 "THSSA,TCP HXS Soft Sequence Attachment" bitfld.long 0x50 31. " SPPRFCC ,TCPShort Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x50 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x50 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x50 0.--9. 1. " SSS ,Soft sequence start" line.long 0x54 "THLECM,TCP HXS Line-up Enable Confirmation Mask" line.long 0x58 "UHSSA,UDP HXS Soft Sequence Attachment" bitfld.long 0x58 31. " SPPRFCC ,UDP Short Packet Padding Removal From Checksum Calculation enable" "Disabled,Enabled" bitfld.long 0x58 11. " ERM ,Error reporting mask" "Disabled,Enabled" newline bitfld.long 0x58 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x58 0.--9. 1. " SSS ,Soft sequence start" line.long 0x5C "UHLECM,UDP HXS Line-up Enable Confirmation Mask" line.long 0x60 "IHSSA,IPSec HXS Soft Sequence Attachment" bitfld.long 0x60 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x60 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x60 0.--9. 1. " SSS ,Soft sequence start" line.long 0x64 "IHLECM,IPSec HXS Line-up Enable Confirmation Mask" line.long 0x68 "SHSSA,SCTP HXS Soft Sequence Attachment" bitfld.long 0x68 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x68 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x68 0.--9. 1. " SSS ,Soft sequence start" line.long 0x6C "SHLECM,SCTP HXS Line-up Enable Confirmation Mask" line.long 0x70 "DHSSA,DCCP HXS Soft Sequence Attachment" bitfld.long 0x70 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x70 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x70 0.--9. 1. " SSS ,Soft sequence start" line.long 0x74 "DHLECM,DCCP HXS Line-up Enable Confirmation Mask" line.long 0x78 "OL4SHSSA,Other L4 Shell HXS Soft Sequence Attachment" bitfld.long 0x78 11. " ERM ,Error reporting mask" "Disabled,Enabled" bitfld.long 0x78 10. " EN ,Enable" "Disabled,Enabled" hexmask.long.word 0x78 0.--9. 1. " SSS ,Soft sequence start" line.long 0x7C "OL4SHLECM,Other L4 Shell HXS Line-up Enable Confirmation Mask" tree.end elif cpuis("LS10?3A") endif tree.end base ad:0x01A00000+0xC7000 tree "Parser Global Configuration Registers" tree "Configuration registers" group.long 0x800++0x03 line.long 0x00 "FMPR_SXPAW0,Soft Examination Parameter Array W0 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 0" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 0" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 0" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 0" group.long 0x804++0x03 line.long 0x00 "FMPR_SXPAW1,Soft Examination Parameter Array W1 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 1" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 1" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 1" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 1" group.long 0x808++0x03 line.long 0x00 "FMPR_SXPAW2,Soft Examination Parameter Array W2 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 2" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 2" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 2" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 2" group.long 0x80C++0x03 line.long 0x00 "FMPR_SXPAW3,Soft Examination Parameter Array W3 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 3" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 3" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 3" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 3" group.long 0x810++0x03 line.long 0x00 "FMPR_SXPAW4,Soft Examination Parameter Array W4 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 4" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 4" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 4" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 4" group.long 0x814++0x03 line.long 0x00 "FMPR_SXPAW5,Soft Examination Parameter Array W5 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 5" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 5" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 5" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 5" group.long 0x818++0x03 line.long 0x00 "FMPR_SXPAW6,Soft Examination Parameter Array W6 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 6" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 6" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 6" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 6" group.long 0x81C++0x03 line.long 0x00 "FMPR_SXPAW7,Soft Examination Parameter Array W7 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 7" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 7" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 7" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 7" group.long 0x820++0x03 line.long 0x00 "FMPR_SXPAW8,Soft Examination Parameter Array W8 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 8" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 8" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 8" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 8" group.long 0x824++0x03 line.long 0x00 "FMPR_SXPAW9,Soft Examination Parameter Array W9 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 9" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 9" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 9" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 9" group.long 0x828++0x03 line.long 0x00 "FMPR_SXPAW10,Soft Examination Parameter Array W10 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 10" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 10" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 10" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 10" group.long 0x82C++0x03 line.long 0x00 "FMPR_SXPAW11,Soft Examination Parameter Array W11 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 11" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 11" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 11" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 11" group.long 0x830++0x03 line.long 0x00 "FMPR_SXPAW12,Soft Examination Parameter Array W12 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 12" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 12" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 12" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 12" group.long 0x834++0x03 line.long 0x00 "FMPR_SXPAW13,Soft Examination Parameter Array W13 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 13" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 13" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 13" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 13" group.long 0x838++0x03 line.long 0x00 "FMPR_SXPAW14,Soft Examination Parameter Array W14 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 14" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 14" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 14" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 14" group.long 0x83C++0x03 line.long 0x00 "FMPR_SXPAW15,Soft Examination Parameter Array W15 Register" hexmask.long.byte 0x00 24.--31. 1. " B0 ,Array Byte 0 of Word 15" hexmask.long.byte 0x00 16.--23. 1. " B1 ,Array Byte 1 of Word 15" hexmask.long.byte 0x00 8.--15. 1. " B2 ,Array Byte 2 of Word 15" hexmask.long.byte 0x00 0.--7. 1. " B3 ,Array Byte 3 of Word 15" group.long 0x840++0x07 line.long 0x00 "FMPR_RPCLIM,Rx Parsing Cycle Limit" hexmask.long.word 0x00 0.--12. 1. " RPCLIM ,Maximum parse cycle limit" line.long 0x04 "FMPR_RPIMAC,Rx Parse Internal Memory Access Control" rbitfld.long 0x04 8. " PSTAT ,Parser Status" "Idle,Active" bitfld.long 0x04 0. " PEN ,Parser Enable" "Disabled,Enabled" hgroup.long 0x848++0x03 hide.long 0x00 "FMPR_PMEEC,Parse Memory ECC Error Capture Register" in tree.end tree "Interrupt registers" group.long 0x860++0x07 line.long 0x00 "FMPR_PEVR,Parser Event Register" eventfld.long 0x00 31. " SPI16 ,Stopped port 16 is now Idle" "Not idle,Idle" eventfld.long 0x00 30. " SPI1 ,Stopped port 1 is now Idle" "Not idle,Idle" eventfld.long 0x00 29. " SPI2 ,Stopped port 2 is now Idle" "Not idle,Idle" newline eventfld.long 0x00 28. " SPI3 ,Stopped port 3 is now Idle" "Not idle,Idle" eventfld.long 0x00 27. " SPI4 ,Stopped port 4 is now Idle" "Not idle,Idle" eventfld.long 0x00 26. " SPI5 ,Stopped port 5 is now Idle" "Not idle,Idle" newline eventfld.long 0x00 25. " SPI6 ,Stopped port 6 is now Idle" "Not idle,Idle" eventfld.long 0x00 24. " SPI7 ,Stopped port 7 is now Idle" "Not idle,Idle" eventfld.long 0x00 23. " SPI8 ,Stopped port 8 is now Idle" "Not idle,Idle" newline eventfld.long 0x00 22. " SPI9 ,Stopped port 9 is now Idle" "Not idle,Idle" eventfld.long 0x00 21. " SPI10 ,Stopped port 10 is now Idle" "Not idle,Idle" eventfld.long 0x00 20. " SPI11 ,Stopped port 11 is now Idle" "Not idle,Idle" newline eventfld.long 0x00 19. " SPI12 ,Stopped port 12 is now Idle" "Not idle,Idle" eventfld.long 0x00 18. " SPI13 ,Stopped port 13 is now Idle" "Not idle,Idle" eventfld.long 0x00 17. " SPI14 ,Stopped port 14 is now Idle" "Not idle,Idle" newline eventfld.long 0x00 16. " SPI15 ,Stopped port 15 is now Idle" "Not idle,Idle" eventfld.long 0x00 14. " SCM ,Single-event ECC error counter FMPR_PMEEC[SERCNT] is at max" "Not max,Max" line.long 0x04 "FFMPR_PEVER,Parser Event Enable Register" bitfld.long 0x04 31. " SPI16 ,Stopped port 16 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 30. " SPI1 ,Stopped port 1 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 29. " SPI2 ,Stopped port 2 is now Idle Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " SPI3 ,Stopped port 3 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 27. " SPI4 ,Stopped port 4 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 26. " SPI5 ,Stopped port 5 is now Idle Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " SPI6 ,Stopped port 6 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 24. " SPI7 ,Stopped port 7 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 23. " SPI8 ,Stopped port 8 is now Idle Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x04 22. " SPI9 ,Stopped port 9 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 21. " SPI10 ,Stopped port 10 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 20. " SPI11 ,Stopped port 11 is now Idle Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x04 19. " SPI12 ,Stopped port 12 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 18. " SPI13 ,Stopped port 13 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 17. " SPI14 ,Stopped port 14 is now Idle Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x04 16. " SPI15 ,Stopped port 15 is now Idle Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 14. " SCM ,Single-bit ECC error counter FMPR_PMEEC[SERCNT] is at max Interrupt Enable" "Disabled,Enabled" group.long 0x86C++0x07 line.long 0x00 "FMPR_PERR,Parser Error Enable Register" eventfld.long 0x00 14. " ECCE ,Parser memory ECC multiple-bit error detected" "Not detected,Detected" line.long 0x04 "FMPR_PERER,Parser Error Register" bitfld.long 0x04 14. " ECCE ,Parser memory ECC multiple-bit error Interrupt Enable" "Disabled,Enabled" tree.end tree "Parse Statistic Registers" group.long 0x8A0++0x03 line.long 0x00 "FMPR_PPSC,Per Port Parser Statistic Control Register" bitfld.long 0x00 31. " SE16 ,Port 16 statistic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SE1 ,Port 1 statistic enable" "Disabled,Enabled" bitfld.long 0x00 29. " SE2 ,Port 2 statistic enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " SE3 ,Port 3 statistic enable" "Disabled,Enabled" bitfld.long 0x00 27. " SE4 ,Port 4 statistic enable" "Disabled,Enabled" bitfld.long 0x00 26. " SE5 ,Port 5 statistic enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " SE6 ,Port 6 statistic enable" "Disabled,Enabled" bitfld.long 0x00 24. " SE7 ,Port 7 statistic enable" "Disabled,Enabled" bitfld.long 0x00 23. " SE8 ,Port 8 statistic enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " SE9 ,Port 9 statistic enable" "Disabled,Enabled" bitfld.long 0x00 21. " SE10 ,Port 10 statistic enable" "Disabled,Enabled" bitfld.long 0x00 20. " SE11 ,Port 11 statistic enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " SE12 ,Port 12 statistic enable" "Disabled,Enabled" bitfld.long 0x00 18. " SE13 ,Port 13 statistic enable" "Disabled,Enabled" bitfld.long 0x00 17. " SE14 ,Port 14 statistic enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " SE15 ,Port 15 statistic enable" "Disabled,Enabled" group.long 0x8A8++0x43 line.long 0x00 "FMPR_PDS,Parse Dispatch Statistic Register" line.long 0x04 "FMPR_L2RRS,L2 Result Returned Statistic Register" line.long 0x08 "FMPR_L3RRS,L3 Result Returned Statistic Register" line.long 0x0C "FMPR_L4RRS,L4 Result Returned Statistic Register" line.long 0x10 "FMPR_SRRS,Shim Result Returned Statistic Register" line.long 0x14 "FMPR_L2RRES,L2 Result Returned with Error Statistic Register" line.long 0x18 "FMPR_L3RRES,L3 Result Returned with Error Statistic Register" line.long 0x1C "FMPR_L4RRES,L4 Result Returned with Error Statistic Register" line.long 0x20 "FMPR_SRRES,Shim Result Returned with Error Statistic Register" line.long 0x24 "FMPR_SPCS,Soft Parser Cycle Statistic Register" line.long 0x28 "FMPR_SPSCS,Soft Parser Stall Cycle Statistic Register" line.long 0x2C "FMPR_HXSCS,HXS Cycle Statistic Register" line.long 0x30 "FMPR_MRCS,FMan Memory Read Cycle Statistic Register" line.long 0x34 "FMPR_MWCS,FMan Memory Write Cycle Statistic Register" line.long 0x38 "FMPR_MRSCS,FMan Memory Read Stall Cycle Statistic Register" line.long 0x3C "FMPR_MWSCS,FMan Memory Write Stalled Cycle Statistic Register" line.long 0x40 "FMPR_FCSCS,FPM Command Stall Cycle Statistic Register" group.long 0x8EC++0x03 line.long 0x00 "FMPR_PDATES,Parser Debug Flow A Trap Event Statistic Register" group.long 0x8F0++0x03 line.long 0x00 "FMPR_PDBTES,Parser Debug Flow B Trap Event Statistic Register" group.long 0x8F4++0x03 line.long 0x00 "FMPR_PDCTES,Parser Debug Flow C Trap Event Statistic Register" group.long 0x900++0x03 line.long 0x00 "FMPR_PDC,Parser Debug Control Register" bitfld.long 0x00 28.--29. " TL_A ,Trace level flow A" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 26.--27. " TL_B ,Trace level flow B" "Disabled,Minimum,Verbose,Very verbose" newline bitfld.long 0x00 24.--25. " TL_C ,Trace level flow C" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--23. " TR_CO ,Trap Collaboration" "No collaboration,A to B,A to C,A to B to C,?..." group.long 0x904++0x2F line.long 0x00 "FMPR_PDAT0C,Parser debug flow A trap 0 configuration register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" line.long 0x04 "FMPR_PDAT0V,Parser Debug Flow A Trap 0 Value Register" line.long 0x08 "FMPR_PDAT0M,Parser Debug Flow A Trap 0 Mask Register" line.long 0x0C "FMPR_PDAT1C,Parser Debug Flow A Trap 1 Configuration Register" bitfld.long 0x0C 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x0C 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x0C 16.--21. 1. " FSEL ,Field selection" line.long 0x10 "FMPR_PDAT1V,Parser Debug Flow A Trap 1 Value Register" line.long 0x14 "FMPR_PDAT1M,Parser Debug Flow A Trap 1 Mask Register" line.long 0x18 "FMPR_PDAT2C,Parser Debug Flow A Trap 2 Configuration Register" bitfld.long 0x18 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x18 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x18 16.--21. 1. " FSEL ,Field selection" line.long 0x1C "FMPR_PDAT2V,Parser Debug Flow A Trap 2 Value Register" line.long 0x20 "FMPR_PDAT2M,Parser Debug Flow A Trap 2 Mask Register" line.long 0x24 "FMPR_PDAT3C,Parser Debug Flow A Trap 3 Configuration Register" bitfld.long 0x24 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x24 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x24 16.--21. 1. " FSEL ,Field selection" line.long 0x28 "FMPR_PDAT3V,Parser Debug Flow A Trap 3 Value Register" line.long 0x2C "FMPR_PDAT3M,Parser Debug Flow A Trap 3 Mask Register" group.long 0x934++0x2F line.long 0x00 "FMPR_PDBT0C,Parser debug flow B trap 0 configuration register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" line.long 0x04 "FMPR_PDBT0V,Parser Debug Flow B Trap 0 Value Register" line.long 0x08 "FMPR_PDBT0M,Parser Debug Flow B Trap 0 Mask Register" line.long 0x0C "FMPR_PDBT1C,Parser Debug Flow B Trap 1 Configuration Register" bitfld.long 0x0C 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x0C 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x0C 16.--21. 1. " FSEL ,Field selection" line.long 0x10 "FMPR_PDBT1V,Parser Debug Flow B Trap 1 Value Register" line.long 0x14 "FMPR_PDBT1M,Parser Debug Flow B Trap 1 Mask Register" line.long 0x18 "FMPR_PDBT2C,Parser Debug Flow B Trap 2 Configuration Register" bitfld.long 0x18 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x18 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x18 16.--21. 1. " FSEL ,Field selection" line.long 0x1C "FMPR_PDBT2V,Parser Debug Flow B Trap 2 Value Register" line.long 0x20 "FMPR_PDBT2M,Parser Debug Flow B Trap 2 Mask Register" line.long 0x24 "FMPR_PDBT3C,Parser Debug Flow B Trap 3 Configuration Register" bitfld.long 0x24 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x24 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x24 16.--21. 1. " FSEL ,Field selection" line.long 0x28 "FMPR_PDBT3V,Parser Debug Flow B Trap 3 Value Register" line.long 0x2C "FMPR_PDBT3M,Parser Debug Flow B Trap 3 Mask Register" group.long 0x964++0x2F line.long 0x00 "FMPR_PDCT0C,Parser debug flow C trap 0 configuration register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" line.long 0x04 "FMPR_PDCT0V,Parser Debug Flow C Trap 0 Value Register" line.long 0x08 "FMPR_PDCT0M,Parser Debug Flow C Trap 0 Mask Register" line.long 0x0C "FMPR_PDCT1C,Parser Debug Flow C Trap 1 Configuration Register" bitfld.long 0x0C 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x0C 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x0C 16.--21. 1. " FSEL ,Field selection" line.long 0x10 "FMPR_PDCT1V,Parser Debug Flow C Trap 1 Value Register" line.long 0x14 "FMPR_PDCT1M,Parser Debug Flow C Trap 1 Mask Register" line.long 0x18 "FMPR_PDCT2C,Parser Debug Flow C Trap 2 Configuration Register" bitfld.long 0x18 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x18 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x18 16.--21. 1. " FSEL ,Field selection" line.long 0x1C "FMPR_PDCT2V,Parser Debug Flow C Trap 2 Value Register" line.long 0x20 "FMPR_PDCT2M,Parser Debug Flow C Trap 2 Mask Register" line.long 0x24 "FMPR_PDCT3C,Parser Debug Flow C Trap 3 Configuration Register" bitfld.long 0x24 29.--31. " CMPOP ,Compare operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x24 28. " AND ,AND" "OR,AND" hexmask.long.byte 0x24 16.--21. 1. " FSEL ,Field selection" line.long 0x28 "FMPR_PDCT3V,Parser Debug Flow C Trap 3 Value Register" line.long 0x2C "FMPR_PDCT3M,Parser Debug Flow C Trap 3 Mask Register" tree.end tree.end endian.le width 0x0B tree.end tree "Frame Manager Key Generator" base ad:0x01A00000+0xC1000 width 27. endian.be group.long 0x00++0x03 "General Configuration and Status Registers" line.long 0x00 "FMKG_GCR,KeyGen General Configuration Register" bitfld.long 0x00 31. " EN ,Enable KeyGen" "Disabled,Enabled" bitfld.long 0x00 17. " CCEN ,Custom classifier enable" "Disabled,Enabled" bitfld.long 0x00 16. " SS ,Scheme selector" "Parse result,SCHEME" bitfld.long 0x00 8.--12. " SCHEME ,Scheme ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x0C++0x03 line.long 0x00 "FMKG_EER,KeyGen Error Event Register" eventfld.long 0x00 31. " DECC ,Double-bit ECC error has been detected on KRAM read access" "Not detected,Detected" eventfld.long 0x00 30. " KSO ,Key Size Overflow" "No overflow,Overflow" group.long 0x10++0x03 line.long 0x00 "FMKG_EEER,KeyGen Error Event Enable Register" bitfld.long 0x00 31. " DECC ,Double-bit ECC Error interrupt mask" "Masked,Enabled" bitfld.long 0x00 30. " KSO ,Key Size Overflow mask" "Masked,Enabled" group.long 0x1C++0x03 line.long 0x00 "FMKG_SEER,KeyGen Scheme Error Event Register" eventfld.long 0x00 31. " SC0 ,Scheme 0 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 30. " [1] ,Scheme 1 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 29. " [2] ,Scheme 2 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 28. " [3] ,Scheme 3 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 27. " [4] ,Scheme 4 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 26. " [5] ,Scheme 5 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 25. " [6] ,Scheme 6 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 24. " [7] ,Scheme 7 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 23. " [8] ,Scheme 8 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 22. " [9] ,Scheme 9 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 21. " [10] ,Scheme 10 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 20. " [11] ,Scheme 11 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 19. " [12] ,Scheme 12 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 18. " [13] ,Scheme 13 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 17. " [14] ,Scheme 14 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 16. " [15] ,Scheme 15 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 15. " [16] ,Scheme 16 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 14. " [17] ,Scheme 17 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 13. " [18] ,Scheme 18 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 12. " [19] ,Scheme 19 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 11. " [20] ,Scheme 20 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 10. " [21] ,Scheme 21 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 9. " [22] ,Scheme 22 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 8. " [23] ,Scheme 23 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 7. " [24] ,Scheme 24 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 6. " [25] ,Scheme 25 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 5. " [26] ,Scheme 26 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 4. " [27] ,Scheme 27 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 3. " [28] ,Scheme 28 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 2. " [29] ,Scheme 29 interrupt has been detected" "Not detected,Detected" newline eventfld.long 0x00 1. " [30] ,Scheme 30 interrupt has been detected" "Not detected,Detected" eventfld.long 0x00 0. " [31] ,Scheme 31 interrupt has been detected" "Not detected,Detected" rgroup.long 0x24++0x03 line.long 0x00 "FMKG_GSR,KeyGen Global Status Register" bitfld.long 0x00 31. " BSY ,KeyGen busy indication" "Not busy,Busy" rgroup.long 0x28++0x03 "Global Statistic Counters" line.long 0x00 "FMKG_TPC,KeyGen Total Packet Counter" group.long 0x2C++0x03 line.long 0x00 "FMKG_SERC,KeyGen Soft Error Capture" eventfld.long 0x00 31. " CAP ,Captured Error Indication" "No error,Error" rbitfld.long 0x00 30. " CET ,Captured Error Type" "Single,Double" hexmask.long.byte 0x00 16.--23. 1. " SERCNT ,Soft Error Counter" newline hexmask.long.word 0x00 0.--9. 1. " MEMADDR ,Captured memory address of access that caused ECC error" group.long 0x40++0x03 "KeyGen Global Registers" line.long 0x00 "FMKG_FDOR,KeyGen Frame Data Offset Register" hexmask.long.byte 0x00 0.--7. 0x01 " OFFSET ,Offset to the end of the parsing point" group.long 0x44++0x03 line.long 0x00 "FMKG_GDV0R,KeyGen Global Default Value 0 Register" group.long 0x48++0x03 line.long 0x00 "FMKG_GDV1R,KeyGen Global Default Value 1 Register" wgroup.long 0x64++0x03 "Internal Debug Registers" line.long 0x00 "FMKG_FEER,KeyGen Force Error Event Register" bitfld.long 0x00 31. " FEDECC ,Force event double ECC error" "Not forced,Forced" bitfld.long 0x00 30. " FEKSO ,Force event key size overflow mask" "Not forced,Forced" if ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x00) group.long 0x1FC++0x03 "Indirect Access Register" line.long 0x00 "FMKG_AR,KeyGen Action Register" bitfld.long 0x00 31. " GO ,GO activate the atomic scheme entry access" "Idle,In progress" bitfld.long 0x00 30. " RW ,Read/Write access type" "Write,Read" bitfld.long 0x00 29. " ER ,Error bit" "No Error,Error" newline bitfld.long 0x00 24.--25. " SEL ,Select Read/Write Entry" "Scheme,Classification Plan,Port Partition,?..." bitfld.long 0x00 16.--20. " NUM ,Scheme Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " WSEL[0] ,Word Select (FMKG_SE_SPC)" "Not written,Written" newline hexmask.long.byte 0x00 0.--5. 1. " HPORTID ,Port ID" elif ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x1000000) group.long (0x1FC)++0x03 "Indirect Access Register" line.long 0x00 "FMKG_AR,KeyGen Action Register" bitfld.long 0x00 31. " GO ,GO activate the atomic scheme entry access" "Idle,In progress" bitfld.long 0x00 30. " RW ,Read/Write access type" "Write,Read" bitfld.long 0x00 29. " ER ,Error bit" "No Error,Error" newline bitfld.long 0x00 24.--25. " SEL ,Select Read/Write Entry" "Scheme,Classification Plan,Port Partition,?..." bitfld.long 0x00 16.--20. " NUM ,Classification Plan Group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " WSEL[0] ,Word Select (FMKG_CPE0)" "Not written,Written" newline bitfld.long 0x00 14. " WSEL[1] ,Word Select (FMKG_CPE1)" "Not written,Written" bitfld.long 0x00 13. " WSEL[2] ,Word Select (FMKG_CPE2)" "Not written,Written" bitfld.long 0x00 12. " WSEL[3] ,Word Select (FMKG_CPE3)" "Not written,Written" newline bitfld.long 0x00 11. " WSEL[4] ,Word Select (FMKG_CPE4)" "Not written,Written" bitfld.long 0x00 10. " WSEL[5] ,Word Select (FMKG_CPE5)" "Not written,Written" bitfld.long 0x00 9. " WSEL[6] ,Word Select (FMKG_CPE6)" "Not written,Written" newline bitfld.long 0x00 8. " WSEL[7] ,Word Select (FMKG_CPE7)" "Not written,Written" hexmask.long.byte 0x00 0.--5. 1. " HPORTID ,Port ID" elif ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x2000000) group.long 0x1FC++0x03 "Indirect Access Register" line.long 0x00 "FMKG_AR,KeyGen Action Register" bitfld.long 0x00 31. " GO ,GO activate the atomic scheme entry access" "Idle,In progress" bitfld.long 0x00 30. " RW ,Read/Write access type" "Write,Read" bitfld.long 0x00 29. " ER ,Error bit" "No Error,Error" newline bitfld.long 0x00 24.--25. " SEL ,Select Read/Write Entry" "Scheme,Classification Plan,Port Partition,?..." bitfld.long 0x00 15. " WSEL[0] ,Word Select (FMKG_PE_SP)" "Not written,Written" bitfld.long 0x00 14. " WSEL[1] ,Word Select (FMKG_PE_CPP)" "Not written,Written" newline hexmask.long.byte 0x00 0.--5. 1. " HPORTID ,Port ID" else group.long 0x1FC++0x03 "Indirect Access Register" line.long 0x00 "FMKG_AR,KeyGen Action Register" bitfld.long 0x00 31. " GO ,GO activate the atomic scheme entry access" "Idle,In progress" bitfld.long 0x00 30. " RW ,Read/Write access type" "Write,Read" bitfld.long 0x00 29. " ER ,Error bit" "No Error,Error" newline bitfld.long 0x00 24.--25. " SEL ,Select Read/Write Entry" "Scheme,Classification Plan,Port Partition,?..." hexmask.long.byte 0x00 0.--5. 1. " HPORTID ,Port ID" endif if ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x0) group.long 0x100++0x1F "Scheme Configuration RAM Registers" line.long 0x00 "AWR1_RFMODE_FMKG_SE_MODE,KeyGen scheme Entry MODE Register" bitfld.long 0x00 31. " SI ,Scheme Initialization bit" "Not initialized,Initialized" bitfld.long 0x00 30. " PL ,Policer Type" "No policer,Policer" newline bitfld.long 0x00 24.--27. " CCOBASE ,Coarse Classification Offset Base" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CCEN ,Custom classifier enable" "Disabled,Enabled" bitfld.long 0x00 16. " SS ,Scheme selector" "Parse result,SCHEME" bitfld.long 0x00 8.--12. " SCHEME ,Scheme ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "AWR2_RFMODE_FMKG_SE_EKFC,KeyGen scheme Entry Extract Known Fields Command Register" bitfld.long 0x04 31. " PORTID ,Extract 1 Byte of Port ID from the Parse Result first byte and add it to the Key" "Disabled,Enabled" bitfld.long 0x04 30. " MACDST ,Extract 48-bit (6 Bytes) MAC Destination Address for Key" "Disabled,Enabled" bitfld.long 0x04 29. " MACSRC ,Extract 48-bit (6 Bytes) MAC Source Address for Key" "Disabled,Enabled" newline bitfld.long 0x04 28. " VLANTCI_1 ,Extract 16-bit (2 Bytes) VLAN TCI from the first Q-Tag in the frame" "Disabled,Enabled" bitfld.long 0x04 27. " VLANTCI_N ,Extract 16-bit (2 Bytes) VLAN TCI from the last Q-Tag in the frame" "Disabled,Enabled" bitfld.long 0x04 26. " ETYPE ,Extract 16-bit (2 Bytes) Ethernet Type field from frame" "Disabled,Enabled" newline bitfld.long 0x04 25. " PPPSID ,Extract 16-bit (2 Bytes) PPPoE Session ID Field" "Disabled,Enabled" bitfld.long 0x04 24. " PPPPID ,Extract 16-bit (2 Bytes) PPP Protocol ID Field" "Disabled,Enabled" bitfld.long 0x04 23. " MPLSL_1 ,Extract 32 bits (4 Bytes) of MPLS first label" "Disabled,Enabled" newline bitfld.long 0x04 22. " MPLSL_2 ,Extract 32 bits (4 Bytes) of MPLS second label" "Disabled,Enabled" bitfld.long 0x04 21. " MPLSL_N ,Extract 32 bits (4 Bytes) of MPLS last label" "Disabled,Enabled" bitfld.long 0x04 20. " IPSRC_1 ,Extract 32/128-bit (4/16 Bytes) IPv4/6 Source Address Field of the first (outer) IP header" "Disabled,Enabled" newline bitfld.long 0x04 19. " IPDST_1 ,Extract 32/128-bit (4/16 Bytes) IPv4/6 Destination Address Field of the first (outer) IP header" "Disabled,Enabled" bitfld.long 0x04 18. " PTYPE_1 ,Extract 8-bit (1 Byte) IPv4 Protocol Type Field or IPv6 the next header type of the first (outer) IP header" "Disabled,Enabled" bitfld.long 0x04 17. " IPTOS_TC_1 ,Extract TOS (IPv4) or Traffic Class(IPv6) of the first (outer) IP header" "Disabled,Enabled" newline bitfld.long 0x04 16. " IPV6FL_1 ,Extract IPv6 Flow Label of the first (outer) IP header" "Disabled,Enabled" bitfld.long 0x04 15. " IPSRC_N ,Extract 32/128-bit (4/16 Bytes) IPv4/6 Source Address Field of the last (inner) IP header or Min Encap Source Address Field" "Disabled,Enabled" bitfld.long 0x04 14. " IPDST_N ,Extract 32/128-bit (4/16 Bytes) IPv4/6 of the last (inner) IP header or Min Encap Destination Address field" "Disabled,Enabled" newline bitfld.long 0x04 13. " PTYPE_N ,Extract 8-bit (1 Byte) IPv4 Protocol Type Field or IPv6 next header type of the last (inner) IP header or Min Encap protocol type" "Disabled,Enabled" bitfld.long 0x04 12. " IPTOS_TC_N ,Extract TOS (IPv4) or Traffic Class(IPv6) of the last (inner) IP header" "Disabled,Enabled" bitfld.long 0x04 11. " IPV6FL_N ,Extract IPv6 Flow Label of the last (inner) IP header" "Disabled,Enabled" newline bitfld.long 0x04 10. " GREPTYPE ,Extract 16-bit (2 Bytes) GRE Protocol Type field" "Disabled,Enabled" bitfld.long 0x04 9. " IPSECSPI ,Extract 32 bits (4 bytes) of IPSec SPI field" "Disabled,Enabled" bitfld.long 0x04 8. " IPSECNH ,Extract 8 bits (1 byte) of IPSec (AH only) Next Header field" "Disabled,Enabled" newline bitfld.long 0x04 7. " IPPID ,Extract an 8-bit (1-byte) IP Protocol identifier" "Disabled,Enabled" newline bitfld.long 0x04 2. " L4PSRC ,Extract 16-bit (2 Bytes) TCP or UDP or SCTP or DCCP source Port Field" "Disabled,Enabled" bitfld.long 0x04 1. " L4PDST ,Extract 16-bit (2 Bytes) TCP or UDP or SCTP or DCCP destination Port Field" "Disabled,Enabled" bitfld.long 0x04 0. " TFLG ,Extract the 14th byte of the TCP header which contains TCP flags" "Disabled,Enabled" line.long 0x08 "AWR3_RFMODE_FMKG_SE_EKDV,KeyGen scheme Entry Extract Known Default Value Register" bitfld.long 0x08 30.--31. " MACADV ,Mac Address Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 28.--29. " VLANTCIDV ,VLAN TCI Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 26.--27. " ETYPEDV ,Etype Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 24.--25. " PPPSIDDV ,PPPSID Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 22.--23. " PPPPIDDV ,PPPPID Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 20.--21. " MPLSLDV ,MPLS Label Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 18.--19. " IPADV ,IP Address Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 16.--17. " PTYPEDV ,IP Protocol Type Default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 14.--15. " IPTOSDV ,IP Type of Service (TOS) default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 12.--13. " IP6FLDV ,IPv6 Flow Label default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 10.--11. " IPSECSPIDV ,IPsec SPI default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 8.--9. " L4PDV ,Layer 4 Port default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" newline bitfld.long 0x08 6.--7. " TFLGDV ,TCP Flag default Value Selection" "FMKG_GDV0R,FMKG_GDV1R,AWR_RFMODE_FMKG_SE_DV0,AWR_RFMODE_FMKG_SE_DV1" line.long 0x0C "AWR4_RFMODE_FMKG_SE_BMCH,KeyGen scheme Bit Mask Command High Register" hexmask.long.byte 0x0C 26.--31. 1. " MCS0 ,Mask Command Select 0" hexmask.long.byte 0x0C 20.--25. 1. " MCS1 ,Mask Command Select 1" bitfld.long 0x0C 16.--19. " MO0 ,Mask Offset 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0C 10.--15. 1. " MCS2 ,Mask Command Select 2" newline hexmask.long.byte 0x0C 4.--9. 1. " MCS3 ,Mask Command Select 3" bitfld.long 0x0C 0.--3. " MO1 ,Mask Offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "AWR5_RFMODE_FMKG_SE_BMCL,KeyGen scheme Bit Mask Command Low Register" hexmask.long.byte 0x10 24.--31. 1. " BM0 ,Bit Mask 0" hexmask.long.byte 0x10 16.--23. 1. " BM1 ,Bit Mask 1" hexmask.long.byte 0x10 8.--15. 1. " BM2 ,Bit Mask 2" hexmask.long.byte 0x10 0.--7. 1. " BM3 ,Bit Mask 3" line.long 0x14 "AWR6_RFMODE_FMKG_SE_FQB,KeyGen scheme Entry Frame Queue Base" bitfld.long 0x14 28.--31. " MO2 ,Mask Offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. " MO3 ,Mask Offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x14 0.--23. 1. " FQBASE ,Frame Queue Base" line.long 0x18 "AWR7_RFMODE_FMKG_SE_HC,KeyGen scheme Entry Hash Configuration Register" bitfld.long 0x18 31. " NO_FQID_GEN ,Do not generate FQID" "Generated,Not generated" bitfld.long 0x18 30. " SYM ,Symmetric Hash" "Disabled,Enabled" newline hexmask.long.byte 0x18 24.--29. 1. " HSHIFT ,Hash Shift Right" hexmask.long.tbyte 0x18 0.--23. 1. " HMASK ,Hash Mask" line.long 0x1C "AWR8_RFMODE_FMKG_SE_PPC,KeyGen scheme Entry Policer Profile Command Register" bitfld.long 0x1C 31. " PPSH ,Policer Profile Shift High bit" "0,1" bitfld.long 0x1C 28. " NO_PNUM_GEN ,Don't generate Policer Profile" "Generated,Not generated" hexmask.long.byte 0x1C 16.--23. 1. " PPMASK ,Policer Profile Mask" newline bitfld.long 0x1C 12.--15. " PPSL ,Policer Profile Shift Low bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x1C 0.--7. 1. " PPBASE ,Policer Profile Base" group.long 0x120++0x03 line.long 0x00 "AWR9_RFMODE_FMKG_SE_GEC0,KeyGen scheme Entry Generic Extract Command 0 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x124++0x03 line.long 0x00 "AWR10_RFMODE_FMKG_SE_GEC1,KeyGen scheme Entry Generic Extract Command 1 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x128++0x03 line.long 0x00 "AWR11_RFMODE_FMKG_SE_GEC2,KeyGen scheme Entry Generic Extract Command 2 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x12C++0x03 line.long 0x00 "AWR12_RFMODE_FMKG_SE_GEC3,KeyGen scheme Entry Generic Extract Command 3 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x130++0x03 line.long 0x00 "AWR13_RFMODE_FMKG_SE_GEC4,KeyGen scheme Entry Generic Extract Command 4 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x134++0x03 line.long 0x00 "AWR14_RFMODE_FMKG_SE_GEC5,KeyGen scheme Entry Generic Extract Command 5 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x138++0x03 line.long 0x00 "AWR15_RFMODE_FMKG_SE_GEC6,KeyGen scheme Entry Generic Extract Command 6 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x13C++0x03 line.long 0x00 "AWR16_RFMODE_FMKG_SE_GEC7,KeyGen scheme Entry Generic Extract Command 7 Register" bitfld.long 0x00 31. " V ,Valid bit" "Not valid,Valid" bitfld.long 0x00 29.--30. " DV ,Default Value" "FMKG_GDV0R,FMKG_GDV1R,FMKG_SE_DV0,FMKG_SE_DV1" bitfld.long 0x00 24.--28. " SIZE ,Byte size/ROTATE Right" "1 byte/0,2 bytes/1,3 bytes/2,4 bytes/3,5 bytes/4,6 bytes/5,7 bytes/6,8 bytes/7,9 bytes/8,10 bytes/9,11 bytes/10,12 bytes/11,13 bytes/12,14 bytes/13,15 bytes/14,16 bytes/15,Invalid/16,Invalid/17,Invalid/18,Invalid/19,Invalid/20,Invalid/21,Invalid/22,Invalid/23,Invalid/24,Invalid/25,Invalid/26,Invalid/27,Invalid/28,Invalid/29,Invalid/30,Invalid/31" hexmask.long.byte 0x00 16.--23. 1. " MASK ,Bit Mask" newline bitfld.long 0x00 15. " TYPE ,Command Type" "Generic,Or" hexmask.long.byte 0x00 8.--14. 1. " HT ,Header Type" hexmask.long.byte 0x00 0.--7. 0x01 " EO ,Extract Offset" group.long 0x140++0x03 line.long 0x00 "AWR17_RFMODE_FMKG_SE_SPC,KeyGen scheme Entry Statistic Packet Counter Register" group.long 0x144++0x03 line.long 0x00 "AWR18_RFMODE_FMKG_SE_DV0,KeyGen scheme Entry Default Value 0 Register" group.long 0x148++0x03 line.long 0x00 "AWR19_RFMODE_FMKG_SE_DV1,KeyGen scheme Entry Default Value 1 Register" group.long 0x14C++0x07 line.long 0x00 "AWR20_RFMODE_FMKG_SE_CCBS,KeyGen Scheme Entry Coarse Classification Bit Select Register" line.long 0x04 "AWR21_RFMODE_FMKG_SE_MV,KeyGen Scheme Entry Match Vector Register" group.long 0x154++0x07 line.long 0x00 "AWR21_RFMODE_FMKG_SE_OM,KeyGen scheme Entry Operational Mode bits Register" bitfld.long 0x00 31. " KOMV ,KeyGen Operational Mode bits Valid" "Not valid,Valid" bitfld.long 0x00 30. " OVOM ,OVerride Operational Mode bits" "Not overridden,Overridden" bitfld.long 0x00 7. " EBD ,External Buffer Deallocation" "Not deallocated,Deallocated" newline bitfld.long 0x00 6. " EBAD ,External Buffer Allocation Disable" "Enabled,Disabled" bitfld.long 0x00 5. " FWD ,Frame Write Disable" "No,Yes" bitfld.long 0x00 4. " NL ,Not Last" "Not realesed,Released" newline bitfld.long 0x00 3. " CWD ,Context Write Disable" "No,Yes" bitfld.long 0x00 2. " NENQ ,No ENQueue" "Disabled,Enabled" bitfld.long 0x00 0. " VSPE ,Virtual Storage Profile Enable" "Disabled,Enabled" line.long 0x04 "AWR8_RFMODE_FMKG_SE_VSP,KeyGen scheme Entry Virtual Storage Profile Register" bitfld.long 0x04 31. " NO_KSPEN ,No KeyGen virtual Storage Profile Enable" "Disabled,Enabled" bitfld.long 0x04 24.--28. " KSPS ,KeyGen virtual Storage Profile Shift" "No shift,1 bit (right),2 bit (right),3 bit (right),4 bit (right),5 bit (right),6 bit (right),7 bit (right),8 bit (right),9 bit (right),10 bit (right),11 bit (right),12 bit (right),13 bit (right),14 bit (right),15 bit (right),16 bit (right),17 bit (right),18 bit (right),19 bit (right),20 bit (right),21 bit (right),22 bit (right),23 bit (right),?..." newline hexmask.long.byte 0x04 12.--17. 0x10 " KSPMASK ,KeyGen virtual Storage Profile Mask" hexmask.long.byte 0x04 0.--5. 0x01 " KSPID ,KeyGen virtual Storage Profile ID" elif ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x1000000) group.long 0x100++0x03 "Classification Plan Table Access" line.long 0x00 "AWR1_RFMODE_FMKG_CPE0,KeyGen Classification Plan Entry Register 0" group.long 0x104++0x03 "Classification Plan Table Access" line.long 0x00 "AWR2_RFMODE_FMKG_CPE1,KeyGen Classification Plan Entry Register 1" group.long 0x108++0x03 "Classification Plan Table Access" line.long 0x00 "AWR3_RFMODE_FMKG_CPE2,KeyGen Classification Plan Entry Register 2" group.long 0x10C++0x03 "Classification Plan Table Access" line.long 0x00 "AWR4_RFMODE_FMKG_CPE3,KeyGen Classification Plan Entry Register 3" group.long 0x110++0x03 "Classification Plan Table Access" line.long 0x00 "AWR5_RFMODE_FMKG_CPE4,KeyGen Classification Plan Entry Register 4" group.long 0x114++0x03 "Classification Plan Table Access" line.long 0x00 "AWR6_RFMODE_FMKG_CPE5,KeyGen Classification Plan Entry Register 5" group.long 0x118++0x03 "Classification Plan Table Access" line.long 0x00 "AWR7_RFMODE_FMKG_CPE6,KeyGen Classification Plan Entry Register 6" group.long 0x11C++0x03 "Classification Plan Table Access" line.long 0x00 "AWR8_RFMODE_FMKG_CPE7,KeyGen Classification Plan Entry Register 7" elif ((per.l.be(ad:0x01A00000+0xC1000+0x1FC)&0x3000000)==0x2000000) group.long 0x100++0x07 "Port Partition Configuration" line.long 0x00 "AWR1_RFMODE_FMKG_PE_SP,KeyGen Port Entry scheme Partition" bitfld.long 0x00 31. " SC0 ,Scheme 0 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 30. " [1] ,Scheme 1 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 29. " [2] ,Scheme 2 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 28. " [3] ,Scheme 3 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 27. " [4] ,Scheme 4 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 26. " [5] ,Scheme 5 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 25. " [6] ,Scheme 6 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 24. " [7] ,Scheme 7 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 23. " [8] ,Scheme 8 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 22. " [9] ,Scheme 9 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 21. " [10] ,Scheme 10 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 20. " [11] ,Scheme 11 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 19. " [12] ,Scheme 12 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 18. " [13] ,Scheme 13 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 17. " [14] ,Scheme 14 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 16. " [15] ,Scheme 15 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 15. " [16] ,Scheme 16 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 14. " [17] ,Scheme 17 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 13. " [18] ,Scheme 18 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 12. " [19] ,Scheme 19 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 11. " [20] ,Scheme 20 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 10. " [21] ,Scheme 21 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 9. " [22] ,Scheme 22 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 8. " [23] ,Scheme 23 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 7. " [24] ,Scheme 24 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 6. " [25] ,Scheme 25 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 5. " [26] ,Scheme 26 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 4. " [27] ,Scheme 27 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 3. " [28] ,Scheme 28 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 2. " [29] ,Scheme 29 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" newline bitfld.long 0x00 1. " [30] ,Scheme 30 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" bitfld.long 0x00 0. " [31] ,Scheme 31 belong to the partition of the selected port in FMKG_AR[PORTID]" "Notbelong,Belong" line.long 0x04 "AWR2_RFMODE_FMKG_PE_CPP,KeyGen Port Entry Classification Plan Partition" bitfld.long 0x04 16.--20. " CPGMASK ,Classification Plan Group Mask" "1 group,2 groups,3 groups,4 groups,5 groups,6 groups,7 groups,8 groups,9 groups,10 groups,11 groups,12 groups,13 groups,14 groups,15 groups,16 groups,17 groups,18 groups,19 groups,20 groups,21 groups,22 groups,23 groups,24 groups,25 groups,26 groups,27 groups,28 groups,29 groups,30 groups,31 groups,32 groups" bitfld.long 0x04 0.--4. " CPGBASE ,Classification Plan Group Base" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x100++0x03 "" newline newline newline textline "Choose appropriate Read/Write Entry" endif group.long 0x200++0x03 "Debug Registers" line.long 0x00 "FMKG_DCR,KeyGen Debug Control Register" bitfld.long 0x00 28.--29. " TL_A ,Trace Level flow A" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 26.--27. " TL_B ,Trace Level flow B" "Disabled,Minimum,Verbose,Very verbose" newline bitfld.long 0x00 24.--25. " TL_C ,Trace Level flow C" "Disabled,Minimum,Verbose,Very verbose" bitfld.long 0x00 20.--23. " TR_CO ,Trap Collaboration" "No collaboration,A to B,A to C,A to B to C,?..." rgroup.long 0x204++0x03 line.long 0x00 "FMKG_D1TC,KeyGen Debug flow 1 Trap Counter Register" rgroup.long 0x208++0x03 line.long 0x00 "FMKG_D2TC,KeyGen Debug flow 2 Trap Counter Register" rgroup.long 0x20C++0x03 line.long 0x00 "FMKG_D3TC,KeyGen Debug flow 3 Trap Counter Register" group.long 0x210++0x0B line.long 0x00 "FMKG_D1T1CR,KeyGen Debug flow 1 Trap 1 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D1T1VR,KeyGen Debug flow 1 Trap 1 Value Register" line.long 0x08 "FMKG_D1T1MR,KeyGen Debug flow 1 Trap 1 Mask Register" group.long 0x220++0x0B line.long 0x00 "FMKG_D1T2CR,KeyGen Debug flow 1 Trap 2 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D1T2VR,KeyGen Debug flow 1 Trap 2 Value Register" line.long 0x08 "FMKG_D1T2MR,KeyGen Debug flow 1 Trap 2 Mask Register" group.long 0x230++0x0B line.long 0x00 "FMKG_D1T3CR,KeyGen Debug flow 1 Trap 3 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D1T3VR,KeyGen Debug flow 1 Trap 3 Value Register" line.long 0x08 "FMKG_D1T3MR,KeyGen Debug flow 1 Trap 3 Mask Register" group.long 0x240++0x0B line.long 0x00 "FMKG_D1T4CR,KeyGen Debug flow 1 Trap 4 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D1T4VR,KeyGen Debug flow 1 Trap 4 Value Register" line.long 0x08 "FMKG_D1T4MR,KeyGen Debug flow 1 Trap 4 Mask Register" group.long 0x250++0x0B line.long 0x00 "FMKG_D1T5CR,KeyGen Debug flow 1 Trap 5 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D1T5VR,KeyGen Debug flow 1 Trap 5 Value Register" line.long 0x08 "FMKG_D1T5MR,KeyGen Debug flow 1 Trap 5 Mask Register" group.long 0x260++0x0B line.long 0x00 "FMKG_D2T1CR,KeyGen Debug flow 2 Trap 1 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D2T1VR,KeyGen Debug flow 2 Trap 1 Value Register" line.long 0x08 "FMKG_D2T1MR,KeyGen Debug flow 2 Trap 1 Mask Register" group.long 0x270++0x0B line.long 0x00 "FMKG_D2T2CR,KeyGen Debug flow 2 Trap 2 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D2T2VR,KeyGen Debug flow 2 Trap 2 Value Register" line.long 0x08 "FMKG_D2T2MR,KeyGen Debug flow 2 Trap 2 Mask Register" group.long 0x280++0x0B line.long 0x00 "FMKG_D2T3CR,KeyGen Debug flow 2 Trap 3 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D2T3VR,KeyGen Debug flow 2 Trap 3 Value Register" line.long 0x08 "FMKG_D2T3MR,KeyGen Debug flow 2 Trap 3 Mask Register" group.long 0x290++0x0B line.long 0x00 "FMKG_D2T4CR,KeyGen Debug flow 2 Trap 4 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D2T4VR,KeyGen Debug flow 2 Trap 4 Value Register" line.long 0x08 "FMKG_D2T4MR,KeyGen Debug flow 2 Trap 4 Mask Register" group.long 0x2A0++0x0B line.long 0x00 "FMKG_D2T5CR,KeyGen Debug flow 2 Trap 5 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D2T5VR,KeyGen Debug flow 2 Trap 5 Value Register" line.long 0x08 "FMKG_D2T5MR,KeyGen Debug flow 2 Trap 5 Mask Register" group.long 0x2B0++0x0B line.long 0x00 "FMKG_D3T1CR,KeyGen Debug flow 3 Trap 1 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D3T1VR,KeyGen Debug flow 3 Trap 1 Value Register" line.long 0x08 "FMKG_D3T1MR,KeyGen Debug flow 3 Trap 1 Mask Register" group.long 0x2C0++0x0B line.long 0x00 "FMKG_D3T2CR,KeyGen Debug flow 3 Trap 2 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D3T2VR,KeyGen Debug flow 3 Trap 2 Value Register" line.long 0x08 "FMKG_D3T2MR,KeyGen Debug flow 3 Trap 2 Mask Register" group.long 0x2D0++0x0B line.long 0x00 "FMKG_D3T3CR,KeyGen Debug flow 3 Trap 3 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D3T3VR,KeyGen Debug flow 3 Trap 3 Value Register" line.long 0x08 "FMKG_D3T3MR,KeyGen Debug flow 3 Trap 3 Mask Register" group.long 0x2E0++0x0B line.long 0x00 "FMKG_D3T4CR,KeyGen Debug flow 3 Trap 4 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D3T4VR,KeyGen Debug flow 3 Trap 4 Value Register" line.long 0x08 "FMKG_D3T4MR,KeyGen Debug flow 3 Trap 4 Mask Register" group.long 0x2F0++0x0B line.long 0x00 "FMKG_D3T5CR,KeyGen Debug flow 3 Trap 5 Configuration Register" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" newline hexmask.long.byte 0x00 16.--21. 1. " FSEL ,Field selection" hexmask.long.byte 0x00 0.--5. 1. " SHIFT ,Extracted data SHIFT lest" line.long 0x04 "FMKG_D3T5VR,KeyGen Debug flow 3 Trap 5 Value Register" line.long 0x08 "FMKG_D3T5MR,KeyGen Debug flow 3 Trap 5 Mask Register" endian.le width 0x0B tree.end tree "Frame Manager Policer" base ad:0x01A00000+0xC0000 width 11. endian.be group.long 0x00++0x03 "General Configuration and Status Registers" line.long 0x00 "FMPL_GCR,FMan Policer General Configuration" bitfld.long 0x00 31. " EN ,Enable policer" "Disabled,Enabled" bitfld.long 0x00 30. " STEN ,Policer global statistic counters enable" "Disabled,Enabled" bitfld.long 0x00 29. " DAR ,Disable auto refresh" "Enabled,Disabled" newline bitfld.long 0x00 23. " ORR ,Order restoration required" "Not required,Required" bitfld.long 0x00 18.--22. " ENG ,Engine code" "FMan Controller,,,,,,,,,,,,,,,,,Parser,KeyGen,Policer,BMI,QMI enqueue,QMI dequeue,?..." hexmask.long.tbyte 0x00 0.--17. 1. " AC ,Action code" rgroup.long 0x04++0x03 line.long 0x00 "FMPL_GSR,FMan Policer Global Status Register" bitfld.long 0x00 31. " BSY ,Policer busy indication" "Idle,Busy" bitfld.long 0x00 29.--30. " DQS ,Policer input queue status" "Empty,Not empty,Full,?..." bitfld.long 0x00 28. " RPB ,Policer rate processor busy" "Idle,Busy" bitfld.long 0x00 26.--27. " FQS ,Policer output queue status" "Empty,Not empty,Full,?..." newline bitfld.long 0x00 14.--15. " LPALG ,Last profile algorithm" "Pass-Through,RFC-2698,RFC-4115,?..." bitfld.long 0x00 12.--13. " LPCA ,Last profile coloring action" "No Change,GREEN to YELLOW,GREEN to RED,YELLOW to RED" hexmask.long.byte 0x00 0.--7. 1. " LPNUM ,Last profile number" group.long 0x08++0x07 line.long 0x00 "FMPL_EVR,FMan Policer Event Register" eventfld.long 0x00 31. " PSIC ,PRAM self-initialization complete status" "Not completed,Completed" eventfld.long 0x00 30. " AAC ,Atomic action complete" "Not completed,Completed" line.long 0x04 "FMPL_IER,FMan Policer Interrupt Enable Register" bitfld.long 0x04 31. " PSIC ,PRAM self-initialization complete interrupt enable" "Masked,Enabled" bitfld.long 0x04 30. " AAC ,Atomic action complete interrupt enable" "Masked,Enabled" wgroup.long 0x10++0x03 line.long 0x00 "FMPL_IFR,FMan Policer Interrupt Force Register" bitfld.long 0x00 31. " PSIC ,Sets the FMPL_EVR[PSIC] status bit" "Not set,Set" bitfld.long 0x00 30. " AAC ,Sets the FMPL_EVR[AAC] status bit" "Not set,Set" group.long 0x14++0x07 line.long 0x00 "FMPL_EEVR,FMan Policer Error Event Register" eventfld.long 0x00 31. " DECC ,Double-bit ECC error has been detected on PRAM read access" "Not detected,Detected" eventfld.long 0x00 30. " IEE ,Initialization entry error" "No error,Error" line.long 0x04 "FMPL_EIER,FMan Policer Error Interrupt Enable Register" bitfld.long 0x04 31. " DECC ,Double-bit ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x04 30. " IEE ,Initialization entry error interrupt mask" "Masked,Enabled" group.long 0x20++0x17 "Global Statistic Counters" line.long 0x00 "FMPL_RPC,FMan Policer RED Packet Counter" line.long 0x04 "FMPL_YPC,FMan Policer YELLOW Packet Counter" line.long 0x08 "FMPL_RRPC,FMan Policer Recolored RED Packet Counter" line.long 0x0C "FMPL_RYPC,FMan Policer Recolored YELLOW Packet Counter" line.long 0x10 "FMPL_TPC,FMan Policer Total Packet Counter" line.long 0x14 "FMPL_FLMC,FMan Policer Frame Length Mismatch Counter" width 18. group.long 0x8C++0x03 "Profile RAM Access Registers" line.long 0x00 "FMPL_PAR,FMan Policer Profile Action Register" bitfld.long 0x00 31. " GO ,Activate the atomic profile entry access or PRAM self initialization" "Idle,Active" bitfld.long 0x00 30. " RW ,Read/Write access type" "Write,Read" bitfld.long 0x00 29. " PSI ,PRAM (Profile RAM) self initialization" "Inactive,Active" hexmask.long.byte 0x00 16.--23. 1. " PNUM ,Profile Number" newline bitfld.long 0x00 15. " PWSEL[0] ,MODE profile write select" "Not written,Written" bitfld.long 0x00 14. " [1] ,GREEN next invoked action profile write select" "Not written,Written" bitfld.long 0x00 13. " [2] ,YELLOW next invoked action profile write select" "Not written,Written" bitfld.long 0x00 12. " [3] ,RED next invoked action profile write select" "Not written,Written" newline bitfld.long 0x00 11. " [4] ,CIR committed burst rate profile write select" "Not written,Written" bitfld.long 0x00 10. " [5] ,CBS committed burst size profile write select" "Not written,Written" bitfld.long 0x00 9. " [6] ,PIR_EIR Peak/Excess information rate profile write select" "Not written,Written" bitfld.long 0x00 8. " [7] ,PBS_EBS Peak/Excess burst size profile write select" "Not written,Written" newline bitfld.long 0x00 7. " [8] ,LTS last timestamp profile write select" "Not written,Written" bitfld.long 0x00 6. " [9] ,CTS committed token status profile write select" "Not written,Written" bitfld.long 0x00 5. " [10] ,PTS_ETS Peak/Excess token status profile write select" "Not written,Written" bitfld.long 0x00 4. " [11] ,GPC GREEN packet counter profile write select" "Not written,Written" newline bitfld.long 0x00 3. " [12] ,YPC YELLOW packet counter profile write select" "Not written,Written" bitfld.long 0x00 2. " [13] ,RPC RED packet counter profile write select" "Not written,Written" bitfld.long 0x00 1. " [14] ,Recolored YELLOW packet counter profile write select" "Not written,Written" bitfld.long 0x00 0. " [15] ,Recolored RED packet counter profile write select" "Not written,Written" group.long 0x90++0x3F line.long 0x00 "FMPL_PEMODE,FMan Policer Profile Entry Mode Register" line.long 0x04 "FMPL_PEGNIA,FMan Policer Profile Entry GREEN Next Invoked Action Register" line.long 0x08 "FMPL_PEYNIA,FMan Policer Profile Entry YELLOW Next Invoked Action Register" line.long 0x0C "FMPL_PERNIA,FMan Policer Profile Entry RED Next Invoked Action Register" line.long 0x10 "FMPL_PECIR,FMan Policer Profile Entry Committed Information Rate Register" line.long 0x14 "FMPL_PECBS,FMan Policer Profile Entry Committed Burst Size Register" line.long 0x18 "FMPL_PEPIR_EIR,FMan Policer Profile Entry Peak/Excess Information Rate Register" line.long 0x1C "FMPL_PEPBS_EBS,FMan Policer Profile Entry Peak/Excess Information Rate Register" line.long 0x20 "FMPL_PELTS,FMan Policer Profile Entry Last Timestamp Register" line.long 0x24 "FMPL_PECTS,FMan Policer Profile Entry Committed Token Status Register" line.long 0x28 "FMPL_PEPTS_ETS,FMan Policer Profile Entry Peak/Excess Token Status Register" line.long 0x2C "FMPL_PEGPC,FMan Policer Profile Entry GREEN Packet Counter Register" line.long 0x30 "FMPL_PEYPC,FMan Policer Profile Entry YELLOW Packet Counter Register" line.long 0x34 "FMPL_PERPC,FMan Policer Profile Entry RED Packet Counter Register" line.long 0x38 "FMPL_PERYPC,FMan Policer Profile Entry Recolored YELLOW Packet Counter Register" line.long 0x3C "FMPL_PERRPC,FMan Policer Profile Entry Recolored RED Packet Counter Register" group.long 0x100++0x07 "Error Capture Registers" line.long 0x00 "FMPL_SERC,FMan Policer Soft Error Capture Register" eventfld.long 0x00 31. " CAP ,Captured Error Indication" "No error,Error" rbitfld.long 0x00 30. " CET ,Captured Error Type" "Single,Double" hexmask.long.byte 0x00 16.--23. 1. " SERCNT ,Soft Error Counter" newline hexmask.long.byte 0x00 4.--11. 1. " PNUM ,Profile Number Capture" rbitfld.long 0x00 0.--3. " POFS ,Profile Offset Capture" "0,1,2,3,4,5,6,7,8,,10,11,12,13,14,15" line.long 0x04 "FMPL_UPCR,FMan Policer Uninitialized Profile Capture Register" eventfld.long 0x04 31. " CAP ,Captured Error Indication" "No error,Error" hexmask.long.byte 0x04 16.--21. 1. " POID ,Port-ID" rbitfld.long 0x04 15. " PMO ,Profile Mapping Option" "Low,High" hexmask.long.byte 0x04 0.--7. 1. " PNUM ,Profile Number" group.long 0x10C++0x03 line.long 0x00 "FMPL_DTRCR,FMan Policer Debug Trace Configuration Register" bitfld.long 0x00 28.--29. " TLA ,Trace Level of Flow A" "Disabled,Minimum,More,Verbose" bitfld.long 0x00 26.--27. " TLB ,Trace Level of Flow B" "Disabled,Minimum,More,Verbose" bitfld.long 0x00 24.--25. " TLC ,Trace Level of Flow C" "Disabled,Minimum,More,Verbose" bitfld.long 0x00 20.--23. " TRCO ,Trap Collaboration" "No collaboration,A to B,A to C,A to B to C,?..." group.long 0x110++0x1B line.long 0x00 "FMPL_FADBTCR0,FMan Policer Flow A Debug Trap Configuration Register 0" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" bitfld.long 0x00 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x04 "FMPL_FADBVALR0,FMan Policer Flow A Debug Value Register 0" line.long 0x08 "FMPL_FADBTMR0,FMan Policer Flow A Debug Trap Mask Register 0" line.long 0x0C "FMPL_FADBTMC,FMan Policer Flow A Debug Trap Match Counter" line.long 0x10 "FMPL_FADBTCR1,FMan Policer Flow A Debug Trap Configuration Register 1" bitfld.long 0x10 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x10 28. " AND ,AND" "OR,AND" bitfld.long 0x10 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x14 "FMPL_FADBVALR1,FMan Policer Flow A Debug Value Register 1" line.long 0x18 "FMPL_FADBTMR1,FMan Policer Flow A Debug Trap Mask Register 1" group.long 0x130++0x1B line.long 0x00 "FMPL_FBDBTCR0,FMan Policer Flow B Debug Trap Configuration Register 0" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" bitfld.long 0x00 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x04 "FMPL_FBDBVALR0,FMan Policer Flow B Debug Value Register 0" line.long 0x08 "FMPL_FBDBTMR0,FMan Policer Flow B Debug Trap Mask Register 0" line.long 0x0C "FMPL_FBDBTMC,FMan Policer Flow B Debug Trap Match Counter" line.long 0x10 "FMPL_FBDBTCR1,FMan Policer Flow B Debug Trap Configuration Register 1" bitfld.long 0x10 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x10 28. " AND ,AND" "OR,AND" bitfld.long 0x10 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x14 "FMPL_FBDBVALR1,FMan Policer Flow B Debug Value Register 1" line.long 0x18 "FMPL_FBDBTMR1,FMan Policer Flow B Debug Trap Mask Register 1" group.long 0x150++0x1B line.long 0x00 "FMPL_FCDBTCR0,FMan Policer Flow C Debug Trap Configuration Register 0" bitfld.long 0x00 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x00 28. " AND ,AND" "OR,AND" bitfld.long 0x00 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x04 "FMPL_FCDBVALR0,FMan Policer Flow C Debug Value Register 0" line.long 0x08 "FMPL_FCDBTMR0,FMan Policer Flow C Debug Trap Mask Register 0" line.long 0x0C "FMPL_FCDBTMC,FMan Policer Flow C Debug Trap Match Counter" line.long 0x10 "FMPL_FCDBTCR1,FMan Policer Flow C Debug Trap Configuration Register 1" bitfld.long 0x10 29.--31. " CMPOP ,Compare Operator" "Disabled,Always,Equal,Not equal,Greater,Less or equal,Less,Greater or equal" bitfld.long 0x10 28. " AND ,AND" "OR,AND" bitfld.long 0x10 16.--20. " FSEL ,Field selection" "Received NIA,Received Port-ID,Absolute Profile Number,Concatenated Input Color,Timestamp value,CTS updated bucket status,PTS_ETS updated bucket status,?..." line.long 0x14 "FMPL_FCDBVALR1,FMan Policer Flow C Debug Value Register 1" line.long 0x18 "FMPL_FCDBTMR1,FMan Policer Flow C Debug Trap Mask Register 1" group.long 0x200++0x03 "Profile Selection Mapping Registers Per Port" line.long 0x00 "FMPL_DPMR,FMan Policer Default Profile Mapping Register" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x204++0x03 line.long 0x00 "FMPL_PMR1,FMan Policer Profile Mapping Register 1" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x208++0x03 line.long 0x00 "FMPL_PMR2,FMan Policer Profile Mapping Register 2" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x20C++0x03 line.long 0x00 "FMPL_PMR3,FMan Policer Profile Mapping Register 3" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x210++0x03 line.long 0x00 "FMPL_PMR4,FMan Policer Profile Mapping Register 4" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x214++0x03 line.long 0x00 "FMPL_PMR5,FMan Policer Profile Mapping Register 5" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x218++0x03 line.long 0x00 "FMPL_PMR6,FMan Policer Profile Mapping Register 6" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x21C++0x03 line.long 0x00 "FMPL_PMR7,FMan Policer Profile Mapping Register 7" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x220++0x03 line.long 0x00 "FMPL_PMR8,FMan Policer Profile Mapping Register 8" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x224++0x03 line.long 0x00 "FMPL_PMR9,FMan Policer Profile Mapping Register 9" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x228++0x03 line.long 0x00 "FMPL_PMR10,FMan Policer Profile Mapping Register 10" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x22C++0x03 line.long 0x00 "FMPL_PMR11,FMan Policer Profile Mapping Register 11" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" group.long 0x240++0x03 line.long 0x00 "FMPL_PMR16,FMan Policer Profile Mapping Register16" bitfld.long 0x00 31. " V ,Port-ID Valid Bit" "Invalid,Valid" bitfld.long 0x00 16.--19. " BRN ,Bit Replacement Number" "Single profile,2 profiles,4 profiles,8 profiles,16 profiles,32 profiles,64 profiles,128 profiles,All profiles,?..." hexmask.long.byte 0x00 0.--7. 0x01 " PBNUM ,Profile Base Number" endian.le width 0x0B tree.end tree "Frame Manager Controller" base ad:0x01A00000+0xC4000 width 11. endian.be group.long 0x00++0x0B line.long 0x00 "FMCDADDR,FMan Controller Configuration Data, Address Register" bitfld.long 0x00 31. " AIE ,Auto increment enable" "Disabled,Enabled" hexmask.long 0x00 0.--30. 1. " ADDR ,Address" line.long 0x04 "FMCDDATA,FMan Controller Configuration Data Register" line.long 0x08 "FMCDREADY,FMan Controller Configuration Data Ready Register" bitfld.long 0x08 31. " READY ,FMan controller configuration data ready" "Not ready,Ready" endian.le width 0x0B tree.end tree "mEMAC (Multirate Ethernet Media Access Controller)" tree "mEMAC1" base ad:0x01A00000+0xE0000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xE0000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xE0000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xE0000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xE0000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xE0000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC2" base ad:0x01A00000+0xE2000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xE2000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xE2000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xE2000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xE2000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xE2000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC3" base ad:0x01A00000+0xE4000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xE4000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xE4000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xE4000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xE4000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xE4000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC4" base ad:0x01A00000+0xE6000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xE6000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xE6000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xE6000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xE6000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xE6000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC5" base ad:0x01A00000+0xE8000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xE8000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xE8000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xE8000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xE8000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xE8000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC6" base ad:0x01A00000+0xEA000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" if (((per.l.be(ad:0x01A00000+0xEA000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xEA000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xEA000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xEA000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SETSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" ",,GMII,?..." endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xEA000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC9" base ad:0x01A00000+0xF0000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" if (((per.l.be(ad:0x01A00000+0xF0000+0x300))&0x03)==0x00) group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,PCS event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,Link Training event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" rbitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline rbitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" rbitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" else group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" endif if (((per.l.be(ad:0x01A00000+0xF0000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif if (((per.l.be(ad:0x01A00000+0xF0000+0x300))&0x03)==0x00) group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,PCS event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation event interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " LT ,Link Training event interrupt mask" "Masked,Enabled" else group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" endif width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xF0000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xF0000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xF0000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xF0000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree "mEMAC10" base ad:0x01A00000+0xF2000 width 18. endian.be tree "mEMAC General Control and Status Registers" group.long 0x08++0x0F line.long 0x00 "COMMAND_CONFIG,Command and Configuration Register" bitfld.long 0x00 31. " MG ,Magic Packet detection enable" "Disabled,Enabled" bitfld.long 0x00 29. " RXSTP ,Rx stop" "Normal,Stopped" bitfld.long 0x00 24. " REG_LOWP_RXETY ,Rx low power indication" "Not empty,Empty" newline bitfld.long 0x00 23. " TX_LOWP_ENA ,Transmit Low Power Idle Enable" "Disabled,Enabled" bitfld.long 0x00 21. " SFD ,Disable check of SFD (0xD5) character at frame start" "No,Yes" bitfld.long 0x00 19. " PFC_MODE ,Enable Priority Flow Control (PFC) mode of operation" "Disabled,Enabled" newline bitfld.long 0x00 17. " NO_LEN_CHK ,Payload length check disable" "No,Yes" bitfld.long 0x00 16. " SEND_IDLE ,Force idle generation" "Normal,Forced" bitfld.long 0x00 13. " CNT_FRM_EN ,Control frame reception enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " SWR ,Software reset" "No reset,Reset" bitfld.long 0x00 11. " TXP ,Enable padding of frames in transmit direction" "Disabled,Enabled" bitfld.long 0x00 10. " XGLP ,10G interface/GMII loopback enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " TX_ADDR_INS ,Transmit source MAC address insertion" "Not inserted,Inserted" bitfld.long 0x00 8. " PAUSE_IGN ,Ignore Pause frame quanta" "Not ignored,Ignored" bitfld.long 0x00 7. " PAUSE_FWD ,Terminate/forward received Pause frames" "Terminated,Forwarded" newline bitfld.long 0x00 6. " CRC ,Terminate/forward CRC of received frames" "Terminated,Forwarded" bitfld.long 0x00 5. " PAD ,Frame padding removal in receive path enable" "Disabled,Enabled" bitfld.long 0x00 4. " PROMIS ,Promiscuous operation enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAN ,WAN mode enable" "LAN,WAN" bitfld.long 0x00 1. " RX_EN ,MAC receive path enable" "Disabled,Enabled" bitfld.long 0x00 0. " TX_EN ,MAC transmit path enable" "Disabled,Enabled" line.long 0x04 "MAC_ADDR_0,First MAC Lower Address Register" line.long 0x08 "MAC_ADDR_1,First MAC Upper Address Register" hexmask.long.word 0x08 0.--15. 0x01 " MAC_ADDR_1 ,The upper 16 bits of the first 48-bit MAC address" line.long 0x0C "MAXFRM,Maximum Frame Length Register" hexmask.long.word 0x0C 16.--31. 1. " TX_MTU ,Allows to set a different maximum length on transmit" hexmask.long.word 0x0C 0.--15. 1. " MAXFRM ,Maximum supported received frame length" group.long 0x1C++0x07 line.long 0x00 "RX_FIFO_SECTIONS,Receive FIFO Sections Register" hexmask.long.word 0x00 0.--15. 1. " RX_SECTION_AVAIL ,RX section available threshold" hexmask.long.word 0x00 16.--31. 1. " RX_SECTION_EMPTY ,RX section empty threshold" line.long 0x04 "TX_FIFO_SECTIONS,Transmit FIFO Sections Register" hexmask.long.word 0x04 16.--31. 1. " TX_SECTION_EMPTY ,TX section empty threshold" hexmask.long.word 0x04 0.--15. 1. " TX_SECTION_AVAIL ,TX section available threshold" wgroup.long 0x2C++0x03 line.long 0x00 "HASHTABLE_CTRL,Hashtable Control Register" hexmask.long.byte 0x00 26.--31. 0x04 " HASH_ADDR ,Hash table address code" bitfld.long 0x00 23. " MCAST ,Multicast frame acceptance for the specified hash entry" "Reject,Accept" if (((per.l.be(ad:0x01A00000+0xF2000+0x300))&0x03)==0x00) group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,PCS event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,Link Training event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" rbitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline rbitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" rbitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" else group.long 0x40++0x03 line.long 0x00 "IEVENT,Interrupt Event Register" eventfld.long 0x00 31. " PCS ,Link synchronization event interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " AN ,Auto-negotiation status interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " LT ,New page received by auto-negotiation function interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 14. " MGI ,Magic packet detection indication event" "Not detected,Detected" eventfld.long 0x00 13. " TS_ECC_ER ,Timestamp FIFO ECC error event" "No error,Error" eventfld.long 0x00 12. " RX_FIFO_OVFL ,Receive FIFO overflow event" "No overflow,Overflow" newline eventfld.long 0x00 11. " TX_FIFO_UNFL ,Transmit FIFO underflow event" "No underflow,Underflow" eventfld.long 0x00 10. " TX_FIFO_OVFL ,Transmit FIFO overflow event" "No overflow,Overflow" eventfld.long 0x00 9. " TX_ECC_ER ,Transmit frame error event" "No error,Error" newline eventfld.long 0x00 8. " RX_ECC_ER ,Receive frame ECC error event" "No error,Error" eventfld.long 0x00 7. " LI_FAULT ,Link Interruption fault event" "No fault,Fault" bitfld.long 0x00 6. " RX_EMPTY ,Receive fifo empty event" "Not empty,Empty" newline bitfld.long 0x00 5. " TX_EMPTY ,Transmit fifo empty event" "Not empty,Empty" bitfld.long 0x00 4. " RX_LOWP ,Low Power Idle event interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 1. " REM_FAULT ,Remote fault event" "No fault,Fault" eventfld.long 0x00 0. " LOC_FAULT ,Local fault event" "No fault,Fault" endif if (((per.l.be(ad:0x01A00000+0xF2000+0x08))&0x8)==0x8) group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x44++0x03 line.long 0x00 "TX_LENGTH,Transmit Inter-Packet Gap Length Register" bitfld.long 0x00 0.--5. " LEN ,Transmit inter-packet gap value" ",,,,40,48,56,64,72,80,88,96,104,112,120,128,?..." endif if (((per.l.be(ad:0x01A00000+0xF2000+0x300))&0x03)==0x00) group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,PCS event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation event interrupt mask" "Masked,Enabled" bitfld.long 0x00 13. " LT ,Link Training event interrupt mask" "Masked,Enabled" else group.long 0x4C++0x03 line.long 0x00 "IMASK,Interrupt Mask Register" bitfld.long 0x00 30. " MGI ,Magic packet detection indication normal interrupt mask" "Masked,Enabled" bitfld.long 0x00 29. " TSECC_ER ,Timestamp FIFO ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 25. " TECC_ER ,Transmit frame ECC error interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 24. " RECC_ER ,Receive frame ECC error interrupt mask" "Masked,Enabled" bitfld.long 0x00 15. " PCS ,Link synchronization event interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " AN ,Auto-negotiation status interrupt mask" "Masked,Enabled" newline bitfld.long 0x00 13. " LT ,New page received by auto-negotiation function interrupt mask" "Masked,Enabled" endif width 19. newline group.long 0x54++0x03 line.long 0x00 "CL01_PAUSE_QUANTA,CL01 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL1_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL0_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x58++0x03 line.long 0x00 "CL23_PAUSE_QUANTA,CL23 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL3_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL2_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x5C++0x03 line.long 0x00 "CL45_PAUSE_QUANTA,CL45 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL5_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL4_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x60++0x03 line.long 0x00 "CL67_PAUSE_QUANTA,CL67 Pause Quanta Register" hexmask.long.word 0x00 16.--31. 1. " CL7_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" hexmask.long.word 0x00 0.--15. 1. " CL6_PQNT ,Value to be sent for the PFC quanta value for that class when a class XOFF is triggered" group.long 0x64++0x03 line.long 0x00 "CL01_PAUSE_THRESH,CL01 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL1_QTH ,CL1 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL0_QTH ,CL01 Pause Quanta Threshold" group.long 0x68++0x03 line.long 0x00 "CL23_PAUSE_THRESH,CL23 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL3_QTH ,CL3 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL2_QTH ,CL23 Pause Quanta Threshold" group.long 0x6C++0x03 line.long 0x00 "CL45_PAUSE_THRESH,CL45 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL5_QTH ,CL5 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL4_QTH ,CL45 Pause Quanta Threshold" group.long 0x70++0x03 line.long 0x00 "CL67_PAUSE_THRESH,CL67 Pause Quanta Threshold Register" hexmask.long.word 0x00 16.--31. 1. " CL7_QTH ,CL7 Pause Quanta Threshold" hexmask.long.word 0x00 0.--15. 1. " CL6_QTH ,CL67 Pause Quanta Threshold" newline rgroup.long 0x74++0x03 line.long 0x00 "RX_PAUSE_STATUS,Receive Pause Status Register" bitfld.long 0x00 7. " [7] ,Pause status - class 7" "Not paused,Paused" bitfld.long 0x00 6. " [6] ,Pause status - class 6" "Not paused,Paused" bitfld.long 0x00 5. " [5] ,Pause status - class 5" "Not paused,Paused" bitfld.long 0x00 4. " [4] ,Pause status - class 4" "Not paused,Paused" newline bitfld.long 0x00 3. " [3] ,Pause status - class 3" "Not paused,Paused" bitfld.long 0x00 2. " [2] ,Pause status - class 2" "Not paused,Paused" bitfld.long 0x00 1. " [1] ,Pause status - class 1" "Not paused,Paused" bitfld.long 0x00 0. " PSTAT[0] ,Pause status - class 0" "Not paused,Paused" group.long 0x80++0x07 line.long 0x00 "MAC_ADDR_2,2nd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_3 ,2nd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_3 ,The upper 16 bits of the 2nd 48-bit MAC address" group.long 0x88++0x07 line.long 0x00 "MAC_ADDR_4,3rd MAC Lower Address Register" line.long 0x04 "MAC_ADDR_5 ,3rd MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_5 ,The upper 16 bits of the 3rd 48-bit MAC address" group.long 0x90++0x07 line.long 0x00 "MAC_ADDR_6,4th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_7 ,4th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_7 ,The upper 16 bits of the 4th 48-bit MAC address" group.long 0x98++0x07 line.long 0x00 "MAC_ADDR_8,5th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_9 ,5th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_9 ,The upper 16 bits of the 5th 48-bit MAC address" group.long 0xA0++0x07 line.long 0x00 "MAC_ADDR_10,6th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_11,6th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_11 ,The upper 16 bits of the 6th 48-bit MAC address" group.long 0xA8++0x07 line.long 0x00 "MAC_ADDR_12,7th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_13,7th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_13 ,The upper 16 bits of the 7th 48-bit MAC address" group.long 0xB0++0x07 line.long 0x00 "MAC_ADDR_14,8th MAC Lower Address Register" line.long 0x04 "MAC_ADDR_15,8th MAC Upper Address Register" hexmask.long.word 0x04 0.--15. 0x01 " MAC_ADDR_15 ,The upper 16 bits of the 8th 48-bit MAC address" group.long 0xB8++0x07 line.long 0x00 "LPWAKE_TIMER,EEE Low Power Wakeup Timer Register" hexmask.long.tbyte 0x00 0.--23. 1. " TW_SYS_TX ,Number of FMan clock cycles" line.long 0x04 "SLEEP_TIMER,Transmit EEE Low Power Timer Register" hexmask.long.tbyte 0x04 0.--23. 1. " SLEEPT ,Sleep timer" group.long 0xE0++0x03 line.long 0x00 "STATN_CONFIG,Statistics Configuration Register" bitfld.long 0x00 0. " SATURATE ,Disable wrapping around" "Enabled,Disabled" bitfld.long 0x00 1. " CLR_ON_RD ,Clear counters on read" "No effect,Clear" bitfld.long 0x00 2. " CLR ,Clear all counters" "No effect,Clear" tree.end width 10. tree "mEMAC Statistics Counter Registers" if (((per.l.be(ad:0x01A00000+0xF2000+0xE0))&0x02)==0x00) rgroup.long 0x100++0xCF line.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" line.long 0x04 "REOCT_U,Receive Upper Ethernet Octets Counter" line.long 0x08 "ROCT_L,Receive Lower Octets Counter" line.long 0x0C "ROCT_U,Receive Upper Octets Counter" line.long 0x10 "RALN_L,Receive Lower Alignment Error Counter" line.long 0x14 "RALN_U,Receive Upper Alignment Error Counter" line.long 0x18 "RXPF_L,Receive Lower Valid Pause Frame Counter" line.long 0x1C "RXPF_U,Receive Upper Valid Pause Frame Counter" line.long 0x20 "RFRM_L,Receive Lower Frame Counter" line.long 0x24 "RFRM_U,Receive Upper Frame Counter" line.long 0x28 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" line.long 0x2C "RFCS_U,Receive Upper Frame Check Sequence Error Counter" line.long 0x30 "RVLAN_L,Receive Lower VLAN Frame Counter" line.long 0x34 "RVLAN_U,Receive Upper VLAN Frame Counter" line.long 0x38 "RERR_L,Receive Lower Error Counter" line.long 0x3C "RERR_U,Receive Upper Error Counter" line.long 0x40 "RUCA_L,Receive Lower Unicast Frame Counter" line.long 0x44 "RUCA_U,Receive Upper Unicast Frame Counter" line.long 0x48 "RMCA_L,Receive Lower Multicast Frame Counter" line.long 0x4C "RMCA_U,Receive Upper Multicast Frame Counter" line.long 0x50 "RBCA_L,Receive Lower Broadcast Frame Counter" line.long 0x54 "RBCA_U,Receive Upper Broadcast Frame Counter" line.long 0x58 "RDRP_L,Receive Lower Dropped Packets Counter" line.long 0x5C "RDRP_U,Receive Upper Dropped Packets Counter" line.long 0x60 "RPKT_L,Receive Lower Packets Counter" line.long 0x64 "RPKT_U,Receive Upper Packets Counter" line.long 0x68 "RUND_L,Undersized Lower Packet Counter" line.long 0x6C "RUND_U,Undersized Upper Packet Counter" line.long 0x70 "R64_L,Receive Lower 64-Octet Packet Counter" line.long 0x74 "R64_U,Receive Upper 64-Octet Packet Counter" line.long 0x78 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" line.long 0x7C "R127_U,Receive Upper 65- to 127-Octet Packet Counter" line.long 0x80 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" line.long 0x84 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" line.long 0x88 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" line.long 0x8C "R511_U,Receive Upper 256- to 511-Octet Packet Counter" line.long 0x90 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" line.long 0x94 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" line.long 0x98 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" line.long 0x9C "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" line.long 0xA0 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" line.long 0xA4 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" line.long 0xA8 "ROVR_L,Oversized Lower Packet Counter" line.long 0xAC "ROVR_U,Oversized Upper Packet Counter" line.long 0xB0 "RJBR_L,Jabber Lower Packet Counter" line.long 0xB4 "RJBR_U,Jabber Upper Packet Counter" line.long 0xB8 "RFRG_L,Fragment Lower Packet Counter" line.long 0xBC "RFRG_U,Fragment Upper Packet Counter" line.long 0xC0 "RCNP_L,Receive Lower Control Packet Counter" line.long 0xC4 "RCNP_U,Receive Upper Control Packet Counter" line.long 0xC8 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" line.long 0xCC "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" rgroup.long 0x200++0x0F line.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" line.long 0x04 "TEOCT_U,Transmit Upper Ethernet Octets Counter" line.long 0x08 "TOCT_L,Transmit Lower Octets Counter" line.long 0x0C "TOCT_U,Transmit Upper Octets Counter" rgroup.long 0x218++0x3F line.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" line.long 0x04 "TXPF_U,Transmit Upper Valid Pause Frame Counter" line.long 0x08 "TFRM_L,Transmit Lower Frame Counter" line.long 0x0C "TFRM_U,Transmit Upper Frame Counter" line.long 0x10 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" line.long 0x14 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" line.long 0x18 "TVLAN_L,Transmit Lower VLAN Frame Counter" line.long 0x1C "TVLAN_U,Transmit Upper VLAN Frame Counter" line.long 0x20 "TERR_L,Transmit Lower Frame Error Counter" line.long 0x24 "TERR_U,Transmit Upper Frame Error Counter" line.long 0x28 "TUCA_L,Transmit Lower Unicast Frame Counter" line.long 0x2C "TUCA_U,Transmit Upper Unicast Frame Counter" line.long 0x30 "TMCA_L,Transmit Lower Multicast Frame Counter" line.long 0x34 "TMCA_U,Transmit Upper Multicast Frame Counter" line.long 0x38 "TBCA_L,Transmit Lower Broadcast Frame Counter" line.long 0x3C "TBCA_U,Transmit Upper Broadcast Frame Counter" rgroup.long 0x260++0x47 line.long 0x00 "TPKT_L,Transmit Lower Packets Counter" line.long 0x04 "TPKT_U,Transmit Upper Packets Counter" line.long 0x08 "TUND_L,Undersized Lower Packet Counter" line.long 0x0C "TUND_U,Undersized Upper Packet Counter" line.long 0x10 "T64_L,Transmit Lower 64-Octet Packet Counter" line.long 0x14 "T64_U,Transmit Upper 64-Octet Packet Counter" line.long 0x18 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" line.long 0x1C "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" line.long 0x20 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" line.long 0x24 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" line.long 0x28 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" line.long 0x2C "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" line.long 0x30 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" line.long 0x34 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" line.long 0x38 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" line.long 0x3C "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" line.long 0x40 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" line.long 0x44 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" rgroup.long 0x2C0++0x07 line.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" line.long 0x04 "TCNP_U,Transmit Upper Control Packet Counter" else hgroup.long 0x100++0x03 hide.long 0x00 "REOCT_L,Receive Lower Ethernet Octets Counter" in hgroup.long 0x104++0x03 hide.long 0x00 "REOCT_U,Receive Upper Ethernet Octets Counter" in hgroup.long 0x108++0x03 hide.long 0x00 "ROCT_L,Receive Lower Octets Counter" in hgroup.long 0x10C++0x03 hide.long 0x00 "ROCT_U,Receive Upper Octets Counter" in hgroup.long 0x110++0x03 hide.long 0x00 "RALN_L,Receive Lower Alignment Error Counter" in hgroup.long 0x114++0x03 hide.long 0x00 "RALN_U,Receive Upper Alignment Error Counter" in hgroup.long 0x118++0x03 hide.long 0x00 "RXPF_L,Receive Lower Valid Pause Frame Counter" in hgroup.long 0x11C++0x03 hide.long 0x00 "RXPF_U,Receive Upper Valid Pause Frame Counter" in hgroup.long 0x120++0x03 hide.long 0x00 "RFRM_L,Receive Lower Frame Counter" in hgroup.long 0x124++0x03 hide.long 0x00 "RFRM_U,Receive Upper Frame Counter" in hgroup.long 0x128++0x03 hide.long 0x00 "RFCS_L,Receive Lower Frame Check Sequence Error Counter" in hgroup.long 0x12C++0x03 hide.long 0x00 "RFCS_U,Receive Upper Frame Check Sequence Error Counter" in hgroup.long 0x130++0x03 hide.long 0x00 "RVLAN_L,Receive Lower VLAN Frame Counter" in hgroup.long 0x134++0x03 hide.long 0x00 "RVLAN_U,Receive Upper VLAN Frame Counter" in hgroup.long 0x138++0x03 hide.long 0x00 "RERR_L,Receive Lower Error Counter" in hgroup.long 0x13C++0x03 hide.long 0x00 "RERR_U,Receive Upper Error Counter" in hgroup.long 0x140++0x03 hide.long 0x00 "RUCA_L,Receive Lower Unicast Frame Counter" in hgroup.long 0x144++0x03 hide.long 0x00 "RUCA_U,Receive Upper Unicast Frame Counter" in hgroup.long 0x148++0x03 hide.long 0x00 "RMCA_L,Receive Lower Multicast Frame Counter" in hgroup.long 0x14C++0x03 hide.long 0x00 "RMCA_U,Receive Upper Multicast Frame Counter" in hgroup.long 0x150++0x03 hide.long 0x00 "RBCA_L,Receive Lower Broadcast Frame Counter" in hgroup.long 0x154++0x03 hide.long 0x00 "RBCA_U,Receive Upper Broadcast Frame Counter" in hgroup.long 0x158++0x03 hide.long 0x00 "RDRP_L,Receive Lower Dropped Packets Counter" in hgroup.long 0x15C++0x03 hide.long 0x00 "RDRP_U,Receive Upper Dropped Packets Counter" in hgroup.long 0x160++0x03 hide.long 0x00 "RPKT_L,Receive Lower Packets Counter" in hgroup.long 0x164++0x03 hide.long 0x00 "RPKT_U,Receive Upper Packets Counter" in hgroup.long 0x168++0x03 hide.long 0x00 "RUND_L,Undersized Lower Packet Counter" in hgroup.long 0x16C++0x03 hide.long 0x00 "RUND_U,Undersized Upper Packet Counter" in hgroup.long 0x170++0x03 hide.long 0x00 "R64_L,Receive Lower 64-Octet Packet Counter" in hgroup.long 0x174++0x03 hide.long 0x00 "R64_U,Receive Upper 64-Octet Packet Counter" in hgroup.long 0x178++0x03 hide.long 0x00 "R127_L,Receive Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x17C++0x03 hide.long 0x00 "R127_U,Receive Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x180++0x03 hide.long 0x00 "R255_L,Receive Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x184++0x03 hide.long 0x00 "R255_U,Receive Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x188++0x03 hide.long 0x00 "R511_L,Receive Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x18C++0x03 hide.long 0x00 "R511_U,Receive Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x190++0x03 hide.long 0x00 "R1023_L,Receive Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x194++0x03 hide.long 0x00 "R1023_U,Receive Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x198++0x03 hide.long 0x00 "R1518_L,Receive Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x19C++0x03 hide.long 0x00 "R1518_U,Receive Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x1A0++0x03 hide.long 0x00 "R1519X_L,Receive Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x1A4++0x03 hide.long 0x00 "R1519X_U,Receive Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x1A8++0x03 hide.long 0x00 "ROVR_L,Oversized Lower Packet Counter" in hgroup.long 0x1AC++0x03 hide.long 0x00 "ROVR_U,Oversized Upper Packet Counter" in hgroup.long 0x1B0++0x03 hide.long 0x00 "RJBR_L,Jabber Lower Packet Counter" in hgroup.long 0x1B4++0x03 hide.long 0x00 "RJBR_U,Jabber Upper Packet Counter" in hgroup.long 0x1B8++0x03 hide.long 0x00 "RFRG_L,Fragment Lower Packet Counter" in hgroup.long 0x1BC++0x03 hide.long 0x00 "RFRG_U,Fragment Upper Packet Counter" in hgroup.long 0x1C0++0x03 hide.long 0x00 "RCNP_L,Receive Lower Control Packet Counter" in hgroup.long 0x1C4++0x03 hide.long 0x00 "RCNP_U,Receive Upper Control Packet Counter" in hgroup.long 0x1C8++0x03 hide.long 0x00 "RDRNTP_L,Receive Lower Dropped Not Truncated Packets Counter" in hgroup.long 0x1CC++0x03 hide.long 0x00 "RDRNTP_U,Receive Upper Dropped Not Truncated Packets Counter" in hgroup.long 0x200++0x03 hide.long 0x00 "TEOCT_L,Transmit Lower Ethernet Octets Counter" in hgroup.long 0x204++0x03 hide.long 0x00 "TEOCT_U,Transmit Upper Ethernet Octets Counter" in hgroup.long 0x208++0x03 hide.long 0x00 "TOCT_L,Transmit Lower Octets Counter" in hgroup.long 0x20C++0x03 hide.long 0x00 "TOCT_U,Transmit Upper Octets Counter" in hgroup.long 0x218++0x03 hide.long 0x00 "TXPF_L,Transmit Lower Valid Pause Frame Counter" in hgroup.long 0x21C++0x03 hide.long 0x00 "TXPF_U,Transmit Upper Valid Pause Frame Counter" in hgroup.long 0x220++0x03 hide.long 0x00 "TFRM_L,Transmit Lower Frame Counter" in hgroup.long 0x224++0x03 hide.long 0x00 "TFRM_U,Transmit Upper Frame Counter" in hgroup.long 0x228++0x03 hide.long 0x00 "TFCS_L,Transmit Lower Frame Check Sequence Error Counter" in hgroup.long 0x22C++0x03 hide.long 0x00 "TFCS_U,Transmit Upper Frame Check Sequence Error Counter" in hgroup.long 0x230++0x03 hide.long 0x00 "TVLAN_L,Transmit Lower VLAN Frame Counter" in hgroup.long 0x234++0x03 hide.long 0x00 "TVLAN_U,Transmit Upper VLAN Frame Counter" in hgroup.long 0x238++0x03 hide.long 0x00 "TERR_L,Transmit Lower Frame Error Counter" in hgroup.long 0x23C++0x03 hide.long 0x00 "TERR_U,Transmit Upper Frame Error Counter" in hgroup.long 0x240++0x03 hide.long 0x00 "TUCA_L,Transmit Lower Unicast Frame Counter" in hgroup.long 0x244++0x03 hide.long 0x00 "TUCA_U,Transmit Upper Unicast Frame Counter" in hgroup.long 0x248++0x03 hide.long 0x00 "TMCA_L,Transmit Lower Multicast Frame Counter" in hgroup.long 0x24C++0x03 hide.long 0x00 "TMCA_U,Transmit Upper Multicast Frame Counter" in hgroup.long 0x250++0x03 hide.long 0x00 "TBCA_L,Transmit Lower Broadcast Frame Counter" in hgroup.long 0x254++0x03 hide.long 0x00 "TBCA_U,Transmit Upper Broadcast Frame Counter" in hgroup.long 0x260++0x03 hide.long 0x00 "TPKT_L,Transmit Lower Packets Counter" in hgroup.long 0x264++0x03 hide.long 0x00 "TPKT_U,Transmit Upper Packets Counter" in hgroup.long 0x268++0x03 hide.long 0x00 "TUND_L,Undersized Lower Packet Counter" in hgroup.long 0x26C++0x03 hide.long 0x00 "TUND_U,Undersized Upper Packet Counter" in hgroup.long 0x270++0x03 hide.long 0x00 "T64_L,Transmit Lower 64-Octet Packet Counter" in hgroup.long 0x274++0x03 hide.long 0x00 "T64_U,Transmit Upper 64-Octet Packet Counter" in hgroup.long 0x278++0x03 hide.long 0x00 "T127_L,Transmit Lower 65- to 127-Octet Packet Counter" in hgroup.long 0x27C++0x03 hide.long 0x00 "T127_U,Transmit Upper 65- to 127-Octet Packet Counter" in hgroup.long 0x280++0x03 hide.long 0x00 "T255_L,Transmit Lower 128- to 255-Octet Packet Counter" in hgroup.long 0x284++0x03 hide.long 0x00 "T255_U,Transmit Upper 128- to 255-Octet Packet Counter" in hgroup.long 0x288++0x03 hide.long 0x00 "T511_L,Transmit Lower 256- to 511-Octet Packet Counter" in hgroup.long 0x28C++0x03 hide.long 0x00 "T511_U,Transmit Upper 256- to 511-Octet Packet Counter" in hgroup.long 0x290++0x03 hide.long 0x00 "T1023_L,Transmit Lower 512- to 1023-Octet Packet Counter" in hgroup.long 0x294++0x03 hide.long 0x00 "T1023_U,Transmit Upper 512- to 1023-Octet Packet Counter" in hgroup.long 0x298++0x03 hide.long 0x00 "T1518_L,Transmit Lower 1024- to 1518-Octet Packet Counter" in hgroup.long 0x29C++0x03 hide.long 0x00 "T1518_U,Transmit Upper 1024- to 1518-Octet Packet Counter" in hgroup.long 0x2A0++0x03 hide.long 0x00 "T1519X_L,Transmit Lower 1519- to Max-Octet Packet Counter" in hgroup.long 0x2A4++0x03 hide.long 0x00 "T1519X_U,Transmit Upper 1024- to Max-Octet Packet Counter" in hgroup.long 0x2C0++0x03 hide.long 0x00 "TCNP_L,Transmit Lower Control Packet Counter" in hgroup.long 0x2C4++0x03 hide.long 0x00 "TCNP_U,Transmit Upper Control Packet Counter" in endif tree.end width 11. tree "Line Interface Control Registers" if (((per.l.be(ad:0x01A00000+0xF2000+0x300))&0x20010000)==0x20000000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" bitfld.long 0x00 13.--14. " SSP ,SETSP" "100 Mbps RGMII,10 Mbps RGMII,1 Gbps RGMII,?..." bitfld.long 0x00 12. " SFD ,Force full duplex RGMII mode" "Not forced,Forced" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." elif (((per.l.be(ad:0x01A00000+0xF2000+0x300))&0x20010000)==0x20010000) group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 15. " ENA ,Enable automatic speed selection" "Disabled,Enabled" newline bitfld.long 0x00 5. " RLP ,RMII/RGMII internal loopback" "Disabled,Enabled" bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." else group.long 0x300++0x03 line.long 0x00 "IF_MODE,Interface Mode Register" bitfld.long 0x00 0.--1. " IF_MODE ,Interface Mode" "10G,,GMII,?..." bitfld.long 0x00 2. " RG ,RGMII mode" "Disabled,Enabled" endif rgroup.long 0x304++0x03 line.long 0x00 "IF_STATUS,Interface Status Register" bitfld.long 0x00 15. " RGLINK ,RG link valid" "Not valid,Valid" bitfld.long 0x00 13.--14. " RGSP ,RGSP" "10 Mbps,100 Mbps,1 Gbps,?..." bitfld.long 0x00 12. " RGFD ,RGMII full duplex established" "No,Yes" tree.end width 11. tree "MDIO Ethernet Management Interface Registers" group.long 0x1030++0x03 line.long 0x00 "MDIO_CFG,MDIO Configuration Register" rbitfld.long 0x00 31. " BSY ,MDIO busy" "Not busy,Busy" eventfld.long 0x00 30. " CMP ,MDIO command completion event" "Not occurred,Occurred" bitfld.long 0x00 29. " CIM ,MDIO command completion interrupt mask" "Masked,Enabled" bitfld.long 0x00 23. " NEG ,Negative edge enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " EHOLD ,MDIO hold time extend" "Not extended,Extended" hexmask.long.word 0x00 7.--15. 1. " MDIO_CLK_DIV ,MDIO clock divisor" bitfld.long 0x00 6. " ENC45 ,Enable Clause 45 support" "Clause 22,Clause 45" newline bitfld.long 0x00 5. " PRE ,MDIO preamble disable" "Enabled,Disabled" bitfld.long 0x00 2.--4. " MDIO_HOLD ,MDIO hold time [FMAN clock cycles]" "1,9,17,25,33,41,49,57" rbitfld.long 0x00 1. " MDIO_RD_ER ,MDIO read error" "No error,Error" if (((per.l.be(ad:0x01A00000+0xF2000+0x1030))&0x40)==0x40) group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PORT_ADDR ,Five-bit MDIO port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " DEV_ADDR ,Five-bit MDIO device address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x1034++0x03 line.long 0x00 "MDIO_CTL,MDIO Control Register" bitfld.long 0x00 15. " READ ,MDIO read initiation" "Default,Initiated" bitfld.long 0x00 14. " POST_INC ,MDIO read with address post-increment initiation" "Default,Initiated" newline bitfld.long 0x00 5.--9. " PHY_ADDR ,Five-bit MDIO PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " REG_ADDR ,Five-bit MDIO register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x1038++0x03 line.long 0x00 "MDIO_DATA,MDIO Data Register" hexmask.long.word 0x00 0.--15. 1. " MDIO_DATA ,16-bit MDIO data" wgroup.long 0x103C++0x03 line.long 0x00 "MDIO_ADDR,MDIO Register Address Register" tree.end endian.le width 0x0B tree.end tree.end tree "IEEE 1588 Timer Module" base ad:0x01A00000+0xFE000 endian.be width 14. rgroup.long 0x00++0x03 line.long 0x00 "TMR_ID,Module ID Register" hexmask.long.word 0x00 16.--31. 1. " TMR_ID ,Value identifying the 1588 timer module" hexmask.long.byte 0x00 8.--15. 1. " REV_MJ ,Value identifies the major revision of the 1588 timer module" hexmask.long.byte 0x00 0.--7. 1. " REV_MN ,Value identifies the minor revision of the 1588 timer module" sif !cpuis("LS2088A")&&!cpuis("LS2084A")&&!cpuis("LS2048A")&&!cpuis("LS2044A") hgroup.long 0x04++0x03 hide.long 0x00 "TMR_ID2,Controller ID Register" endif group.long 0x80++0x0B line.long 0x00 "TMR_CTRL,Timer Control Register" bitfld.long 0x00 31. " ALM1P ,Alarm 1 output polarity" "Active high,Active low" bitfld.long 0x00 30. " ALM2P ,Alarm 2 output polarity" "Active high,Active low" bitfld.long 0x00 28. " FS ,FIPER start indication" "Timer,Timer/Alarm" newline bitfld.long 0x00 27. " PP1L ,Fiper 1 pulse loopback mode enabled" "Disabled,Enabled" bitfld.long 0x00 26. " PP2L ,Fiper 2 pulse loopback mode enabled" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " TCLK_PERIOD ,1588 timer reference clock period" newline bitfld.long 0x00 14. " FRD ,FIPER realignment disable" "No,Yes" bitfld.long 0x00 13. " SLV ,Timer master/slave mode" "Master,Slave" bitfld.long 0x00 9. " ETEP2 ,External trigger 2 edge polarity" "Rising,Falling" newline bitfld.long 0x00 8. " ETEP1 ,External trigger 1 edge polarity" "Rising,Falling" bitfld.long 0x00 7. " COPH ,Generated clock (TMR_GCLK) output phase" "Not inverted,Inverted" bitfld.long 0x00 6. " CIPH ,External oscillator input clock phase" "Not inverted,Inverted" newline bitfld.long 0x00 5. " TMSR ,Timer soft reset" "Normal,Reset" bitfld.long 0x00 3. " BYP ,Bypass drift compensated clock" "Normal,Bypassed" bitfld.long 0x00 2. " TE ,1588 timer enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " CKSEL ,1588 Timer reference clock source select" "TMR_1588_CLK,MAC system clock,,RTC oscillator" line.long 0x04 "TMR_TEVENT,Timer Event Register" sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") eventfld.long 0x04 29. " ETS2_OV ,External trigger 2 timestamp FIFO overflow" "Not overflowed,Overflowed" eventfld.long 0x04 28. " ETS1_OV ,External trigger 1 timestamp FIFO overflow" "Not overflowed,Overflowed" endif newline eventfld.long 0x04 25. " ETS2 ,External trigger 2 timestamp sampled" "Not sampled,Sampled" eventfld.long 0x04 24. " ETS1 ,External trigger 1 timestamp sampled" "Not sampled,Sampled" newline sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") eventfld.long 0x04 21. " ETS2_THR ,External trigger 2 timestamp FIFO threshold level hit" "No hit,Hit" eventfld.long 0x04 20. " ETS1_THR ,External trigger 1 timestamp FIFO threshold level hit" "No hit,Hit" endif newline eventfld.long 0x04 17. " ALM2 ,Current time equaled alarm time register 2" "Not reached,Reached" eventfld.long 0x04 16. " ALM1 ,Current time equaled alarm time register 1" "Not reached,Reached" newline eventfld.long 0x04 7. " PP1 ,Indicates that a periodic pulse has been generated based on FIPER1 register" "Not generated,Generated" eventfld.long 0x04 6. " PP2 ,Indicates that a periodic pulse has been generated based on FIPER2 register" "Not generated,Generated" eventfld.long 0x04 5. " PP3 ,Periodic pulse has been generated based on FIPER3 register" "Not generated,Generated" line.long 0x08 "TMR_TEMASK,Timer Event Mask Register" sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") bitfld.long 0x08 29. " ETS2_OVEN ,External trigger 2 timestamp overflow event enable" "Disabled,Enabled" bitfld.long 0x08 28. " ETS1_OVEN ,External trigger 2 timestamp overflow event enable" "Disabled,Enabled" endif newline bitfld.long 0x08 25. " ETS2EN ,External trigger 2 timestamp sample event enable" "Disabled,Enabled" bitfld.long 0x08 24. " ETS1EN ,External trigger 1 timestamp sample event enable" "Disabled,Enabled" newline sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") bitfld.long 0x08 21. " ETS2_THREN ,External trigger 2 timestamp FIFO threshold level hit sample event enable" "Disabled,Enabled" bitfld.long 0x08 20. " ETS1_THREN ,External trigger 1 timestamp FIFO threshold level hit sample event enable" "Disabled,Enabled" newline endif bitfld.long 0x08 17. " ALM2EN ,Timer ALM2 event enable" "Disabled,Enabled" bitfld.long 0x08 16. " ALM1EN ,Timer ALM1 event enable" "Disabled,Enabled" newline bitfld.long 0x08 7. " PP1EN ,Periodic pulse event 1 enable" "Disabled,Enabled" bitfld.long 0x08 6. " PP2EN ,Periodic pulse event 2 enable" "Disabled,Enabled" bitfld.long 0x08 5. " PP3EN ,Periodic pulse event 3 enable" "Disabled,Enabled" sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") rgroup.long 0x94++0x03 line.long 0x00 "TMR_STAT,Timer Status Register" bitfld.long 0x00 31. " RCD ,Timer reference clock detected" "Not detected,Detected" bitfld.long 0x00 25. " ETS2_VLD ,External trigger 2 valid time-stamp read" "All read,Not all read" bitfld.long 0x00 24. " ETS1_VLD ,External trigger 1 valid time-stamp read" "All read,Not all read" else group.long 0x94++0x03 line.long 0x00 "TMR_STAT,Timer Status Register" bitfld.long 0x00 31. " RCD ,Timer reference clock detected" "Not detected,Detected" endif if (((per.l.be(ad:0x01A00000+0xFE000+0x80))&0x2000)==0x0000) group.long 0x98++0x07 line.long 0x00 "TMR_CNT_H,Timer Counter High Register" line.long 0x04 "TMR_CNT_L,Timer Counter Low Register" else hgroup.long 0x98++0x03 hide.long 0x00 "TMR_CNT_H,Timer Counter High Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TMR_CNT_L,Timer Counter Low Register" endif group.long 0xA0++0x03 line.long 0x00 "TMR_ADD,Timer Drift Compensation Addend Register" rgroup.long 0xA4++0x03 line.long 0x00 "TMR_ACC,Timer Accumulator Register" group.long 0xA8++0x03 line.long 0x00 "TMR_PRSC,Timer Prescale Register" hexmask.long.word 0x00 0.--15. 1. " PRSC_OCK ,Output clock division/prescale factor" sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") group.long 0xAC++0x03 line.long 0x00 "TMR_ECTRL,Extended Timer Control Register" bitfld.long 0x00 0.--3. " ETFF_THR ,External trigger FIFO interrupt threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((per.l.be(ad:0x01A00000+0xFE000+0x80))&0x2000)==0x0000) group.long 0xB0++0x07 line.long 0x00 "TMROFF_H,Timer Offset High Register" line.long 0x04 "TMROFF_L,Timer Offset Low Register" else hgroup.long 0xB0++0x03 hide.long 0x00 "TMROFF_H,Timer Offset High Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TMROFF_L,Timer Offset Low Register" endif group.long 0xB8++0x0F line.long 0x00 "TMR_ALARM1_H,Alarm 1 Time Comparator High Register" line.long 0x04 "TMR_ALARM1_L,Alarm 1 Time Comparator Low Register" line.long 0x08 "TMR_ALARM2_H,Alarm 2 Time Comparator High Register" line.long 0x0C "TMR_ALARM2_L,Alarm 2 Time Comparator Low Register" group.long 0xD0++0x0B line.long 0x00 "TMR_FIPER1,Timer Fixed Interval Period Register 1" line.long 0x04 "TMR_FIPER2,Timer Fixed Interval Period Register 2" line.long 0x08 "TMR_FIPER3,Timer Fixed Interval Period Register 3" sif cpuis("LS2088A")||cpuis("LS2084A")||cpuis("LS2048A")||cpuis("LS2044A") hgroup.quad 0xE0++0x07 hide.quad 0x00 "TMR_ETTS1,External Trigger Stamp 1 Register" in hgroup.quad 0xE8++0x07 hide.quad 0x00 "TMR_ETTS2,External Trigger Stamp 2 Register" in else group.long 0xE0++0x0F line.long 0x00 "TMR_ETTS1_H,External Trigger Stamp 1 High Register" line.long 0x04 "TMR_ETTS1_L,External Trigger Stamp 1 Low Register" line.long 0x08 "TMR_ETTS2_H,External Trigger Stamp 2 High Register" line.long 0x0C "TMR_ETTS2_L,External Trigger Stamp 2 Low Register" endif endian.le width 0x0B tree.end width 0x0B tree.end tree.end endif sif cpuis("LS10?3A")||cpuis("LS1012*")||cpuis("LS10?6A") tree "SEC (Security And Encryption Engine)" base ad:0x1700000 width 8. endian.be group.long 0x04++0x03 line.long 0x00 "MCFGR,Master Configuration Register" bitfld.long 0x00 31. " SWRST ,Software reset" "Normal,Reset" bitfld.long 0x00 30. " WDE ,DECO watchdog enable" "Disabled,Enabled" bitfld.long 0x00 29. " WDF ,Watchdog fast" "Normal,Fast" newline bitfld.long 0x00 28. " DMA_RST ,DMA reset" "No effect,Reset" bitfld.long 0x00 27. " WRHD ,Write handoff disable" "No,Yes" bitfld.long 0x00 21. " DJPC ,Disable job performance counters" "No,Yes" newline bitfld.long 0x00 20. " DBPC ,Disable byte performance counters" "No,Yes" bitfld.long 0x00 19. " DWT ,Double word transpose" "Low,High" bitfld.long 0x00 17. " NSP ,No snoop" "Snooped,Not snooped" newline bitfld.long 0x00 16. " PS ,Pointer size" "32-bit,49-bit" bitfld.long 0x00 15. " ARCACHE[3] ,Check for already cached" "Not cached,Cached" bitfld.long 0x00 14. " [2] ,Read data allocate recommended" "Not recommended,Recommended" newline bitfld.long 0x00 13. " [1] ,Cacheable/modifiable" "Not modified,Modified" bitfld.long 0x00 12. " [0] ,Bufferable" "Not Fetched,Fetched" bitfld.long 0x00 11. " AWCACHE[3] ,Write data allocate recommended" "Not Recommended,Recommended" newline bitfld.long 0x00 10. " [2] ,Check for already cached" "Not cached,Cached" bitfld.long 0x00 9. " [1] ,Cacheable/modifiable" "Not modified,Modified" bitfld.long 0x00 8. " [0] ,Bufferable" "Not Generated,Generated" newline bitfld.long 0x00 4.--7. " AXIPIPE ,AXI pipeline depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " LARGE_BURST ,Enable large bursts" "Disabled,Enabled" rbitfld.long 0x00 0. " NORMAL_BURST ,Maximum burst size" "32 byte,64 byte" group.long 0x0C++0x03 line.long 0x00 "SCFGR,Security Configuration Register" rbitfld.long 0x00 28.--31. " MPCURVE ,Manufacturing protection curve" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " MPPKRC ,Manufacturing protection private key register clear" "No effect,Clear" bitfld.long 0x00 26. " MPMRL ,Manufacturing protection message register lock" "Not locked,Locked" newline bitfld.long 0x00 15. " VIRT_EN ,Virtualization enable" "Disabled,Enabled" bitfld.long 0x00 11. " LCK_TRNG ,Lock TRNG program mode" "Not locked,Locked" bitfld.long 0x00 10. " RDB ,Enable random data buffer" "Disabled,Enabled" newline bitfld.long 0x00 9. " RNGSH0 ,Random number generator state handle 0" "Any mode,Not in deterministic mode" bitfld.long 0x00 8. " RANDDPAR ,Random differential power analysis resistance (DPAR) mask" "Default seed,State Handle 0" newline bitfld.long 0x00 0.--1. " PRIBLOB ,Private blob type during trusted mode selection" "Secure boot,Provisioning type 1,Provisioning type 2,Normal operation" width 12. tree "Job ring ICID Registers" if ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x80000000) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x80000000) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x00) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x00) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x80000000) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x80000000) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x00) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x00) group.long 0x10++0x03 line.long 0x00 "JR0ICID_MS,Job Ring 0 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" endif if ((per.l.be(ad:0x1700000+0x10)&0x80000000)==0x80000000) rgroup.long (0x10+0x04)++0x03 line.long 0x00 "JR0ICID_LS,Job Ring 0 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" else group.long (0x10+0x04)++0x03 line.long 0x00 "JR0ICID_LS,Job Ring 0 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" endif if ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x80000000) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x80000000) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x80000000) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x80000000) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x00) group.long 0x18++0x03 line.long 0x00 "JR1ICID_MS,Job Ring 1 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" endif if ((per.l.be(ad:0x1700000+0x18)&0x80000000)==0x80000000) rgroup.long (0x18+0x04)++0x03 line.long 0x00 "JR1ICID_LS,Job Ring 1 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" else group.long (0x18+0x04)++0x03 line.long 0x00 "JR1ICID_LS,Job Ring 1 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" endif if ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x80000000) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x80000000) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x00) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x00) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x80000000) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x80000000) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x00) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x00) group.long 0x20++0x03 line.long 0x00 "JR2ICID_MS,Job Ring 2 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" endif if ((per.l.be(ad:0x1700000+0x20)&0x80000000)==0x80000000) rgroup.long (0x20+0x04)++0x03 line.long 0x00 "JR2ICID_LS,Job Ring 2 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" else group.long (0x20+0x04)++0x03 line.long 0x00 "JR2ICID_LS,Job Ring 2 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" endif if ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x80000000) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x80000000) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x00) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x8000)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x00) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" rbitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x80000000) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x80000000) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" rbitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x20000)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x00) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" rbitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" elif ((per.l.be(ad:0x1700000+0x0C)&0x8000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x20000)==0x00)&&((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x00) group.long 0x28++0x03 line.long 0x00 "JR3ICID_MS,Job Ring 3 ICID Register - Most Significant Half" bitfld.long 0x00 31. " LICID ,Lock ICID" "Not locked,Locked" bitfld.long 0x00 17. " LAMTD ,Lock AMTD" "Not locked,Locked" bitfld.long 0x00 16. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 15. " TZ ,TrustZone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" endif if ((per.l.be(ad:0x1700000+0x28)&0x80000000)==0x80000000) rgroup.long (0x28+0x04)++0x03 line.long 0x00 "JR3ICID_LS,Job Ring 3 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" else group.long (0x28+0x04)++0x03 line.long 0x00 "JR3ICID_LS,Job Ring 3 ICID Register - Least Significant Half" hexmask.long.word 0x00 16.--27. 1. " NONSEQ_ICID ,Job ring non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQ_ICID ,SEQ ICID" endif tree.end newline width 18. group.long 0x50++0x03 line.long 0x00 "QISDID,Queue Manager Interface SDID Register" bitfld.long 0x00 15. " TZ ,Trustzone secureworld" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " SDID ,Security domain identifier" group.long 0x58++0x03 line.long 0x00 "DEBUGCTL,Debug Control Register" rbitfld.long 0x00 17. " STOP_ACK ,Job queue controller stop acknowledge" "Not stopped,Stopped" bitfld.long 0x00 16. " STOP ,Stop jobs processing request" "Not requested,Requested" if (((per.l.be(ad:0x1700000+0x0C))&0x8000)==0x8000) group.long 0x5C++0x03 line.long 0x00 "JRSTARTR,Job Ring Start Register" bitfld.long 0x00 3. " START_JR3 ,Start job ring 3" "Stop mode,Start mode" bitfld.long 0x00 2. " START_JR2 ,Start job ring 2" "Stop mode,Start mode" newline bitfld.long 0x00 1. " START_JR1 ,Start job ring 1" "Stop mode,Start mode" bitfld.long 0x00 0. " START_JR0 ,Start job ring 0" "Stop mode,Start mode" else rgroup.long 0x5C++0x03 line.long 0x00 "JRSTARTR,Job Ring Start Register" bitfld.long 0x00 3. " START_JR3 ,Start job ring 3" "Stop mode,Start mode" bitfld.long 0x00 2. " START_JR2 ,Start job ring 2" "Stop mode,Start mode" newline bitfld.long 0x00 1. " START_JR1 ,Start job ring 1" "Stop mode,Start mode" bitfld.long 0x00 0. " START_JR0 ,Start job ring 0" "Stop mode,Start mode" endif group.long 0x60++0x07 line.long 0x00 "RTICAICID_MS,RTIC ICID Register For Block A" bitfld.long 0x00 31. " LCK ,RTIC ICID lock" "Not locked,Locked" bitfld.long 0x00 30. " TZCTL ,TrustZone control" "Disabled,Enabled" line.long 0x04 "RTICAICID_LS,RTIC ICID Register For Block A" hexmask.long.word 0x04 0.--11. 1. " R_ICID ,RTIC ICID" group.long 0x68++0x07 line.long 0x00 "RTICBICID_MS,RTIC ICID Register For Block B" bitfld.long 0x00 31. " LCK ,RTIC ICID lock" "Not locked,Locked" line.long 0x04 "RTICBICID_LS,RTIC ICID Register For Block B" hexmask.long.word 0x04 0.--11. 1. " R_ICID ,RTIC ICID" group.long 0x70++0x07 line.long 0x00 "RTICCICID_MS,RTIC ICID Register For Block C" bitfld.long 0x00 31. " LCK ,RTIC ICID lock" "Not locked,Locked" line.long 0x04 "RTICCICID_LS,RTIC ICID Register For Block C" hexmask.long.word 0x04 0.--11. 1. " R_ICID ,RTIC ICID" group.long 0x78++0x07 line.long 0x00 "RTICDICID_MS,RTIC ICID Register For Block D" bitfld.long 0x00 31. " LCK ,RTIC ICID lock" "Not locked,Locked" line.long 0x04 "RTICDICID_LS,RTIC ICID Register For Block D" hexmask.long.word 0x04 0.--11. 1. " R_ICID ,RTIC ICID" if (((per.l.be(ad:0x1700000+0x0C))&0x8000)==0x8000) group.long 0x94++0x03 line.long 0x00 "DECORSR,DECO Request Source Register" rbitfld.long 0x00 31. " VALID ,Job ring number in JR field validity" "Invalid,Valid" bitfld.long 0x00 0.--1. " JR ,Job ring number" "0,1,2,3" else rgroup.long 0x94++0x03 line.long 0x00 "DECORSR,DECO Request Source Register" bitfld.long 0x00 31. " VALID ,Job ring number in JR field validity" "Invalid,Valid" bitfld.long 0x00 0.--1. " JR ,Job ring number" "0,1,2,3" endif if (((per.l.be(ad:0x1700000+0x94))&0x80000000)==0x80000000) group.long 0x9C++0x03 line.long 0x00 "DECORR,DECO Request Register" rbitfld.long 0x00 18. " DEN2 ,Permission for the software to directly access DECO 2/CCB 2 granted" "Not granted,Granted" rbitfld.long 0x00 17. " DEN1 ,Permission for the software to directly access DECO 1/CCB 1 granted" "Not granted,Granted" rbitfld.long 0x00 16. " DEN0 ,Permission for the software to directly access DECO 0/CCB 0 granted" "Not granted,Granted" newline bitfld.long 0x00 2. " RQD2 ,Direct access to DECO 2/CCB 2 request" "Not requested,Requested" bitfld.long 0x00 1. " RQD1 ,Direct access to DECO 1/CCB 1 request" "Not requested,Requested" bitfld.long 0x00 0. " RQD0 ,Direct access to DECO 0/CCB 0 request" "Not requested,Requested" else rgroup.long 0x9C++0x03 line.long 0x00 "DECORR,DECO Request Register" bitfld.long 0x00 18. " DEN2 ,Permission for the software to directly access DECO 2/CCB 2 granted" "Not granted,Granted" bitfld.long 0x00 17. " DEN1 ,Permission for the software to directly access DECO 1/CCB 1 granted" "Not granted,Granted" bitfld.long 0x00 16. " DEN0 ,Permission for the software to directly access DECO 0/CCB 0 granted" "Not granted,Granted" newline bitfld.long 0x00 2. " RQD2 ,Direct access to DECO 2/CCB 2 request" "Not requested,Requested" bitfld.long 0x00 1. " RQD1 ,Direct access to DECO 1/CCB 1 request" "Not requested,Requested" bitfld.long 0x00 0. " RQD0 ,Direct access to DECO 0/CCB 0 request" "Not requested,Requested" endif width 14. tree "DECO ICID Registers" if (((per.l.be(ad:0x1700000+0x0C))&0x8000)==0x8000) rgroup.long 0xA0++0x07 line.long 0x00 "DECO0ICID_MS,DECO0 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO0ICID_LS,DECO0 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" else group.long 0xA0++0x07 line.long 0x00 "DECO0ICID_MS,DECO0 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO0ICID_LS,DECO0 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" endif if (((per.l.be(ad:0x1700000+0x0C))&0x8000)==0x8000) rgroup.long 0xA8++0x07 line.long 0x00 "DECO1ICID_MS,DECO1 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO1ICID_LS,DECO1 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" else group.long 0xA8++0x07 line.long 0x00 "DECO1ICID_MS,DECO1 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO1ICID_LS,DECO1 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" endif if (((per.l.be(ad:0x1700000+0x0C))&0x8000)==0x8000) rgroup.long 0xB0++0x07 line.long 0x00 "DECO2ICID_MS,DECO2 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO2ICID_LS,DECO2 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" else group.long 0xB0++0x07 line.long 0x00 "DECO2ICID_MS,DECO2 ICID Most Significant Half Register" bitfld.long 0x00 31. " LCK ,Lock" "Not locked,Locked" line.long 0x04 "DECO2ICID_LS,DECO2 ICID Least Significant Half Register" hexmask.long.word 0x04 16.--27. 1. " DNSEQ_ICID ,DECO non-SEQ ICID" hexmask.long.word 0x04 0.--11. 1. " DSEQ_ICID ,DECO SEQ ICID" endif tree.end newline width 10. group.long 0x120++0x03 line.long 0x00 "DAR,DECO Availability Register" bitfld.long 0x00 2. " NYA2 ,Start polling for the availability of DECO 2" "Not started,Started" bitfld.long 0x00 1. " NYA1 ,Start polling for the availability of DECO 1" "Not started,Started" bitfld.long 0x00 0. " NYA0 ,Start polling for the availability of DECO 0" "Not started,Started" wgroup.long 0x124++0x03 line.long 0x00 "DRR,DECO Reset Register" bitfld.long 0x00 2. " RST2 ,Soft reset of DECO 2" "No reset,Reset" bitfld.long 0x00 1. " RST1 ,Soft reset of DECO 1" "No reset,Reset" bitfld.long 0x00 0. " RST0 ,Soft reset of DECO 0" "No reset,Reset" group.long 0x204++0x03 line.long 0x00 "DMAC,DMA Control Register" bitfld.long 0x00 1. " WSE ,Write safe enable" "Disabled,Enabled" bitfld.long 0x00 0. " RSE ,Read safe enable" "Disabled,Enabled" group.long 0x504++0x03 line.long 0x00 "DMA_CTRL,DMA Control Register" bitfld.long 0x00 1. " WSE ,Write safe enable" "Disabled,Enabled" bitfld.long 0x00 0. " RSE ,Read safe enable" "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "PBSL,Peak Bandwidth Smoothing Limit Register" hexmask.long.byte 0x00 0.--6. 1. " PBSL ,Read safe enable" width 17. tree "DMA AXI ID Mapping Low Registers" rgroup.long 0x240++0x13 line.long 0x00 "DMA0_AIDL_MAP_MS,Mapping For DMA AXI ID 7-4" hexmask.long.byte 0x00 24.--31. 1. " AID7_BID ,SEC block ID using AXI ID 7" hexmask.long.byte 0x00 16.--23. 1. " AID6_BID ,SEC block ID using AXI ID 6" hexmask.long.byte 0x00 8.--15. 1. " AID5_BID ,SEC block ID using AXI ID 5" newline hexmask.long.byte 0x00 0.--7. 1. " AID4_BID ,SEC block ID using AXI ID 4" line.long 0x04 "DMA0_AIDL_MAP_LS,Mapping For DMA AXI ID 3-0" hexmask.long.byte 0x04 24.--31. 1. " AID3_BID ,SEC block ID using AXI ID 3" hexmask.long.byte 0x04 16.--23. 1. " AID2_BID ,SEC block ID using AXI ID 2" hexmask.long.byte 0x04 8.--15. 1. " AID1_BID ,SEC block ID using AXI ID 1" newline hexmask.long.byte 0x04 0.--7. 1. " AID0_BID ,SEC block ID using AXI ID 0" line.long 0x08 "DMA0_AIDM_MAP_MS,Mapping For DMA AXI ID 15-12" hexmask.long.byte 0x08 24.--31. 1. " AID15_BID ,SEC block ID using AXI ID 15" hexmask.long.byte 0x08 16.--23. 1. " AID14_BID ,SEC block ID using AXI ID 14" hexmask.long.byte 0x08 8.--15. 1. " AID13_BID ,SEC block ID using AXI ID 13" newline hexmask.long.byte 0x08 0.--7. 1. " AID12_BID ,SEC block ID using AXI ID 12" line.long 0x0C "DMA0_AIDM_MAP_LS,Mapping For DMA AXI ID 11-8" hexmask.long.byte 0x0C 24.--31. 1. " AID11_BID ,SEC block ID using AXI ID 11" hexmask.long.byte 0x0C 16.--23. 1. " AID10_BID ,SEC block ID using AXI ID 10" hexmask.long.byte 0x0C 8.--15. 1. " AID9_BID ,SEC block ID using AXI ID 9" newline hexmask.long.byte 0x0C 0.--7. 1. " AID8_BID ,SEC block ID using AXI ID 8" line.long 0x10 "DMA0_AID_ENB,DMA$2 AXI ID Enable Register" bitfld.long 0x10 15. " AID15E ,AXI ID 15 enable" "Disabled,Enabled" bitfld.long 0x10 14. " AID14E ,AXI ID 14 enable" "Disabled,Enabled" bitfld.long 0x10 13. " AID13E ,AXI ID 13 enable" "Disabled,Enabled" newline bitfld.long 0x10 12. " AID12E ,AXI ID 12 enable" "Disabled,Enabled" bitfld.long 0x10 11. " AID11E ,AXI ID 11 enable" "Disabled,Enabled" bitfld.long 0x10 10. " AID10E ,AXI ID 10 enable" "Disabled,Enabled" newline bitfld.long 0x10 9. " AID9E ,AXI ID 9 enable" "Disabled,Enabled" bitfld.long 0x10 8. " AID8E ,AXI ID 8 enable" "Disabled,Enabled" bitfld.long 0x10 7. " AID7E ,AXI ID 7 enable" "Disabled,Enabled" newline bitfld.long 0x10 6. " AID6E ,AXI ID 6 enable" "Disabled,Enabled" bitfld.long 0x10 5. " AID5E ,AXI ID 5 enable" "Disabled,Enabled" bitfld.long 0x10 4. " AID4E ,AXI ID 4 enable" "Disabled,Enabled" newline bitfld.long 0x10 3. " AID3E ,AXI ID 3 enable" "Disabled,Enabled" bitfld.long 0x10 2. " AID2E ,AXI ID 2 enable" "Disabled,Enabled" bitfld.long 0x10 1. " AID1E ,AXI ID 1 enable" "Disabled,Enabled" newline bitfld.long 0x10 0. " AID0E ,AXI ID 0 enable" "Disabled,Enabled" newline group.quad 0x260++0x07 line.quad 0x00 "DMA0_ARD_TC,DMA$2 AXI Read Timing Check Register" bitfld.quad 0x00 63. " ARTCE ,AXI read timing check enable" "Disabled,Enabled" bitfld.quad 0x00 62. " ARCT ,AXI read counter test" "No test,Test" bitfld.quad 0x00 61. " ARTT ,AXI read timer test" "No test,Test" newline bitfld.quad 0x00 60. " ARTL ,AXI read timer last" "First,Last" hexmask.quad.word 0x00 48.--59. 1. " ARL ,AXI read limit" hexmask.quad.tbyte 0x00 24.--43. 1. " ARLC ,AXI read late count" newline hexmask.quad.tbyte 0x00 0.--19. 1. " ARSC ,AXI read sample count" if (((per.l.be(ad:0x1700000+0x260))&0x8000000000000000)==0x00) group.long 0x26C++0x03 line.long 0x00 "DMA0_ARD_LAT,DMA$2 Read Timing Check Latency Register" else rgroup.long 0x26C++0x03 line.long 0x00 "DMA0_ARD_LAT,DMA$2 Read Timing Check Latency Register" endif group.quad 0x270++0x07 line.quad 0x00 "DMA0_AWR_TC,DMA$2 AXI Write Timing Check Register" bitfld.quad 0x00 63. " AWTCE ,AXI write timing check enable" "Disabled,Enabled" bitfld.quad 0x00 62. " AWCT ,AXI write counter test" "No test,Test" newline bitfld.quad 0x00 61. " AWTT ,AXI write timer test" "No test,Test" hexmask.quad.word 0x00 48.--59. 1. " AWL ,AXI write limit" newline hexmask.quad.tbyte 0x00 24.--43. 1. " AWLC ,AXI write late count" hexmask.quad.tbyte 0x00 0.--19. 1. " AWSC ,AXI write sample count" if (((per.l.be(ad:0x1700000+0x270))&0x8000000000000000)==0x00) group.long 0x27C++0x03 line.long 0x00 "DMA0_AWR_LAT,DMA$2 Write Timing Check Latency Register" else rgroup.long 0x27C++0x03 line.long 0x00 "DMA0_AWR_LAT,DMA$2 Write Timing Check Latency Register" endif tree.end width 10. tree "Manufacturing Protection Registers" group.byte 0x300++0x00 line.byte 0x00 "MPPKR0,Manufacturing Protection Private Key Register" group.byte 0x301++0x00 line.byte 0x00 "MPPKR1,Manufacturing Protection Private Key Register" group.byte 0x302++0x00 line.byte 0x00 "MPPKR2,Manufacturing Protection Private Key Register" group.byte 0x303++0x00 line.byte 0x00 "MPPKR3,Manufacturing Protection Private Key Register" group.byte 0x304++0x00 line.byte 0x00 "MPPKR4,Manufacturing Protection Private Key Register" group.byte 0x305++0x00 line.byte 0x00 "MPPKR5,Manufacturing Protection Private Key Register" group.byte 0x306++0x00 line.byte 0x00 "MPPKR6,Manufacturing Protection Private Key Register" group.byte 0x307++0x00 line.byte 0x00 "MPPKR7,Manufacturing Protection Private Key Register" group.byte 0x308++0x00 line.byte 0x00 "MPPKR8,Manufacturing Protection Private Key Register" group.byte 0x309++0x00 line.byte 0x00 "MPPKR9,Manufacturing Protection Private Key Register" group.byte 0x30A++0x00 line.byte 0x00 "MPPKR10,Manufacturing Protection Private Key Register" group.byte 0x30B++0x00 line.byte 0x00 "MPPKR11,Manufacturing Protection Private Key Register" group.byte 0x30C++0x00 line.byte 0x00 "MPPKR12,Manufacturing Protection Private Key Register" group.byte 0x30D++0x00 line.byte 0x00 "MPPKR13,Manufacturing Protection Private Key Register" group.byte 0x30E++0x00 line.byte 0x00 "MPPKR14,Manufacturing Protection Private Key Register" group.byte 0x30F++0x00 line.byte 0x00 "MPPKR15,Manufacturing Protection Private Key Register" group.byte 0x310++0x00 line.byte 0x00 "MPPKR16,Manufacturing Protection Private Key Register" group.byte 0x311++0x00 line.byte 0x00 "MPPKR17,Manufacturing Protection Private Key Register" group.byte 0x312++0x00 line.byte 0x00 "MPPKR18,Manufacturing Protection Private Key Register" group.byte 0x313++0x00 line.byte 0x00 "MPPKR19,Manufacturing Protection Private Key Register" group.byte 0x314++0x00 line.byte 0x00 "MPPKR20,Manufacturing Protection Private Key Register" group.byte 0x315++0x00 line.byte 0x00 "MPPKR21,Manufacturing Protection Private Key Register" group.byte 0x316++0x00 line.byte 0x00 "MPPKR22,Manufacturing Protection Private Key Register" group.byte 0x317++0x00 line.byte 0x00 "MPPKR23,Manufacturing Protection Private Key Register" group.byte 0x318++0x00 line.byte 0x00 "MPPKR24,Manufacturing Protection Private Key Register" group.byte 0x319++0x00 line.byte 0x00 "MPPKR25,Manufacturing Protection Private Key Register" group.byte 0x31A++0x00 line.byte 0x00 "MPPKR26,Manufacturing Protection Private Key Register" group.byte 0x31B++0x00 line.byte 0x00 "MPPKR27,Manufacturing Protection Private Key Register" group.byte 0x31C++0x00 line.byte 0x00 "MPPKR28,Manufacturing Protection Private Key Register" group.byte 0x31D++0x00 line.byte 0x00 "MPPKR29,Manufacturing Protection Private Key Register" group.byte 0x31E++0x00 line.byte 0x00 "MPPKR30,Manufacturing Protection Private Key Register" group.byte 0x31F++0x00 line.byte 0x00 "MPPKR31,Manufacturing Protection Private Key Register" group.byte 0x320++0x00 line.byte 0x00 "MPPKR32,Manufacturing Protection Private Key Register" group.byte 0x321++0x00 line.byte 0x00 "MPPKR33,Manufacturing Protection Private Key Register" group.byte 0x322++0x00 line.byte 0x00 "MPPKR34,Manufacturing Protection Private Key Register" group.byte 0x323++0x00 line.byte 0x00 "MPPKR35,Manufacturing Protection Private Key Register" group.byte 0x324++0x00 line.byte 0x00 "MPPKR36,Manufacturing Protection Private Key Register" group.byte 0x325++0x00 line.byte 0x00 "MPPKR37,Manufacturing Protection Private Key Register" group.byte 0x326++0x00 line.byte 0x00 "MPPKR38,Manufacturing Protection Private Key Register" group.byte 0x327++0x00 line.byte 0x00 "MPPKR39,Manufacturing Protection Private Key Register" group.byte 0x328++0x00 line.byte 0x00 "MPPKR40,Manufacturing Protection Private Key Register" group.byte 0x329++0x00 line.byte 0x00 "MPPKR41,Manufacturing Protection Private Key Register" group.byte 0x32A++0x00 line.byte 0x00 "MPPKR42,Manufacturing Protection Private Key Register" group.byte 0x32B++0x00 line.byte 0x00 "MPPKR43,Manufacturing Protection Private Key Register" group.byte 0x32C++0x00 line.byte 0x00 "MPPKR44,Manufacturing Protection Private Key Register" group.byte 0x32D++0x00 line.byte 0x00 "MPPKR45,Manufacturing Protection Private Key Register" group.byte 0x32E++0x00 line.byte 0x00 "MPPKR46,Manufacturing Protection Private Key Register" group.byte 0x32F++0x00 line.byte 0x00 "MPPKR47,Manufacturing Protection Private Key Register" group.byte 0x330++0x00 line.byte 0x00 "MPPKR48,Manufacturing Protection Private Key Register" group.byte 0x331++0x00 line.byte 0x00 "MPPKR49,Manufacturing Protection Private Key Register" group.byte 0x332++0x00 line.byte 0x00 "MPPKR50,Manufacturing Protection Private Key Register" group.byte 0x333++0x00 line.byte 0x00 "MPPKR51,Manufacturing Protection Private Key Register" group.byte 0x334++0x00 line.byte 0x00 "MPPKR52,Manufacturing Protection Private Key Register" group.byte 0x335++0x00 line.byte 0x00 "MPPKR53,Manufacturing Protection Private Key Register" group.byte 0x336++0x00 line.byte 0x00 "MPPKR54,Manufacturing Protection Private Key Register" group.byte 0x337++0x00 line.byte 0x00 "MPPKR55,Manufacturing Protection Private Key Register" group.byte 0x338++0x00 line.byte 0x00 "MPPKR56,Manufacturing Protection Private Key Register" group.byte 0x339++0x00 line.byte 0x00 "MPPKR57,Manufacturing Protection Private Key Register" group.byte 0x33A++0x00 line.byte 0x00 "MPPKR58,Manufacturing Protection Private Key Register" group.byte 0x33B++0x00 line.byte 0x00 "MPPKR59,Manufacturing Protection Private Key Register" group.byte 0x33C++0x00 line.byte 0x00 "MPPKR60,Manufacturing Protection Private Key Register" group.byte 0x33D++0x00 line.byte 0x00 "MPPKR61,Manufacturing Protection Private Key Register" group.byte 0x33E++0x00 line.byte 0x00 "MPPKR62,Manufacturing Protection Private Key Register" group.byte 0x33F++0x00 line.byte 0x00 "MPPKR63,Manufacturing Protection Private Key Register" group.byte 0x380++0x00 line.byte 0x00 "MPMR0,Manufacturing Protection Message Register" rgroup.byte (0x380+0x40)++0x00 line.byte 0x00 "MPTESTR0,Manufacturing Protection Test Register" group.byte 0x381++0x00 line.byte 0x00 "MPMR1,Manufacturing Protection Message Register" rgroup.byte (0x381+0x40)++0x00 line.byte 0x00 "MPTESTR1,Manufacturing Protection Test Register" group.byte 0x382++0x00 line.byte 0x00 "MPMR2,Manufacturing Protection Message Register" rgroup.byte (0x382+0x40)++0x00 line.byte 0x00 "MPTESTR2,Manufacturing Protection Test Register" group.byte 0x383++0x00 line.byte 0x00 "MPMR3,Manufacturing Protection Message Register" rgroup.byte (0x383+0x40)++0x00 line.byte 0x00 "MPTESTR3,Manufacturing Protection Test Register" group.byte 0x384++0x00 line.byte 0x00 "MPMR4,Manufacturing Protection Message Register" rgroup.byte (0x384+0x40)++0x00 line.byte 0x00 "MPTESTR4,Manufacturing Protection Test Register" group.byte 0x385++0x00 line.byte 0x00 "MPMR5,Manufacturing Protection Message Register" rgroup.byte (0x385+0x40)++0x00 line.byte 0x00 "MPTESTR5,Manufacturing Protection Test Register" group.byte 0x386++0x00 line.byte 0x00 "MPMR6,Manufacturing Protection Message Register" rgroup.byte (0x386+0x40)++0x00 line.byte 0x00 "MPTESTR6,Manufacturing Protection Test Register" group.byte 0x387++0x00 line.byte 0x00 "MPMR7,Manufacturing Protection Message Register" rgroup.byte (0x387+0x40)++0x00 line.byte 0x00 "MPTESTR7,Manufacturing Protection Test Register" group.byte 0x388++0x00 line.byte 0x00 "MPMR8,Manufacturing Protection Message Register" rgroup.byte (0x388+0x40)++0x00 line.byte 0x00 "MPTESTR8,Manufacturing Protection Test Register" group.byte 0x389++0x00 line.byte 0x00 "MPMR9,Manufacturing Protection Message Register" rgroup.byte (0x389+0x40)++0x00 line.byte 0x00 "MPTESTR9,Manufacturing Protection Test Register" group.byte 0x38A++0x00 line.byte 0x00 "MPMR10,Manufacturing Protection Message Register" rgroup.byte (0x38A+0x40)++0x00 line.byte 0x00 "MPTESTR10,Manufacturing Protection Test Register" group.byte 0x38B++0x00 line.byte 0x00 "MPMR11,Manufacturing Protection Message Register" rgroup.byte (0x38B+0x40)++0x00 line.byte 0x00 "MPTESTR11,Manufacturing Protection Test Register" group.byte 0x38C++0x00 line.byte 0x00 "MPMR12,Manufacturing Protection Message Register" rgroup.byte (0x38C+0x40)++0x00 line.byte 0x00 "MPTESTR12,Manufacturing Protection Test Register" group.byte 0x38D++0x00 line.byte 0x00 "MPMR13,Manufacturing Protection Message Register" rgroup.byte (0x38D+0x40)++0x00 line.byte 0x00 "MPTESTR13,Manufacturing Protection Test Register" group.byte 0x38E++0x00 line.byte 0x00 "MPMR14,Manufacturing Protection Message Register" rgroup.byte (0x38E+0x40)++0x00 line.byte 0x00 "MPTESTR14,Manufacturing Protection Test Register" group.byte 0x38F++0x00 line.byte 0x00 "MPMR15,Manufacturing Protection Message Register" rgroup.byte (0x38F+0x40)++0x00 line.byte 0x00 "MPTESTR15,Manufacturing Protection Test Register" group.byte 0x390++0x00 line.byte 0x00 "MPMR16,Manufacturing Protection Message Register" rgroup.byte (0x390+0x40)++0x00 line.byte 0x00 "MPTESTR16,Manufacturing Protection Test Register" group.byte 0x391++0x00 line.byte 0x00 "MPMR17,Manufacturing Protection Message Register" rgroup.byte (0x391+0x40)++0x00 line.byte 0x00 "MPTESTR17,Manufacturing Protection Test Register" group.byte 0x392++0x00 line.byte 0x00 "MPMR18,Manufacturing Protection Message Register" rgroup.byte (0x392+0x40)++0x00 line.byte 0x00 "MPTESTR18,Manufacturing Protection Test Register" group.byte 0x393++0x00 line.byte 0x00 "MPMR19,Manufacturing Protection Message Register" rgroup.byte (0x393+0x40)++0x00 line.byte 0x00 "MPTESTR19,Manufacturing Protection Test Register" group.byte 0x394++0x00 line.byte 0x00 "MPMR20,Manufacturing Protection Message Register" rgroup.byte (0x394+0x40)++0x00 line.byte 0x00 "MPTESTR20,Manufacturing Protection Test Register" group.byte 0x395++0x00 line.byte 0x00 "MPMR21,Manufacturing Protection Message Register" rgroup.byte (0x395+0x40)++0x00 line.byte 0x00 "MPTESTR21,Manufacturing Protection Test Register" group.byte 0x396++0x00 line.byte 0x00 "MPMR22,Manufacturing Protection Message Register" rgroup.byte (0x396+0x40)++0x00 line.byte 0x00 "MPTESTR22,Manufacturing Protection Test Register" group.byte 0x397++0x00 line.byte 0x00 "MPMR23,Manufacturing Protection Message Register" rgroup.byte (0x397+0x40)++0x00 line.byte 0x00 "MPTESTR23,Manufacturing Protection Test Register" group.byte 0x398++0x00 line.byte 0x00 "MPMR24,Manufacturing Protection Message Register" rgroup.byte (0x398+0x40)++0x00 line.byte 0x00 "MPTESTR24,Manufacturing Protection Test Register" group.byte 0x399++0x00 line.byte 0x00 "MPMR25,Manufacturing Protection Message Register" rgroup.byte (0x399+0x40)++0x00 line.byte 0x00 "MPTESTR25,Manufacturing Protection Test Register" group.byte 0x39A++0x00 line.byte 0x00 "MPMR26,Manufacturing Protection Message Register" rgroup.byte (0x39A+0x40)++0x00 line.byte 0x00 "MPTESTR26,Manufacturing Protection Test Register" group.byte 0x39B++0x00 line.byte 0x00 "MPMR27,Manufacturing Protection Message Register" rgroup.byte (0x39B+0x40)++0x00 line.byte 0x00 "MPTESTR27,Manufacturing Protection Test Register" group.byte 0x39C++0x00 line.byte 0x00 "MPMR28,Manufacturing Protection Message Register" rgroup.byte (0x39C+0x40)++0x00 line.byte 0x00 "MPTESTR28,Manufacturing Protection Test Register" group.byte 0x39D++0x00 line.byte 0x00 "MPMR29,Manufacturing Protection Message Register" rgroup.byte (0x39D+0x40)++0x00 line.byte 0x00 "MPTESTR29,Manufacturing Protection Test Register" group.byte 0x39E++0x00 line.byte 0x00 "MPMR30,Manufacturing Protection Message Register" rgroup.byte (0x39E+0x40)++0x00 line.byte 0x00 "MPTESTR30,Manufacturing Protection Test Register" group.byte 0x39F++0x00 line.byte 0x00 "MPMR31,Manufacturing Protection Message Register" rgroup.byte (0x39F+0x40)++0x00 line.byte 0x00 "MPTESTR31,Manufacturing Protection Test Register" tree.end tree "Descriptor Key Encryption Key Registers" if (((per.l.be(ad:0x1700000+0xFD4))&0x300)==0x00) group.long 0x400++0x03 line.long 0x00 "JDKEKR0,Job Descriptor Key Encryption Key Register 0" group.long 0x404++0x03 line.long 0x00 "JDKEKR1,Job Descriptor Key Encryption Key Register 1" group.long 0x408++0x03 line.long 0x00 "JDKEKR2,Job Descriptor Key Encryption Key Register 2" group.long 0x40C++0x03 line.long 0x00 "JDKEKR3,Job Descriptor Key Encryption Key Register 3" group.long 0x410++0x03 line.long 0x00 "JDKEKR4,Job Descriptor Key Encryption Key Register 4" group.long 0x414++0x03 line.long 0x00 "JDKEKR5,Job Descriptor Key Encryption Key Register 5" group.long 0x418++0x03 line.long 0x00 "JDKEKR6,Job Descriptor Key Encryption Key Register 6" group.long 0x41C++0x03 line.long 0x00 "JDKEKR7,Job Descriptor Key Encryption Key Register 7" newline group.long 0x420++0x03 line.long 0x00 "TDKEKR00,Trusted Descriptor Key Encryption Key Register 0" group.long 0x424++0x03 line.long 0x00 "TDKEKR01,Trusted Descriptor Key Encryption Key Register 1" group.long 0x428++0x03 line.long 0x00 "TDKEKR02,Trusted Descriptor Key Encryption Key Register 2" group.long 0x42C++0x03 line.long 0x00 "TDKEKR03,Trusted Descriptor Key Encryption Key Register 3" group.long 0x430++0x03 line.long 0x00 "TDKEKR04,Trusted Descriptor Key Encryption Key Register 4" group.long 0x434++0x03 line.long 0x00 "TDKEKR05,Trusted Descriptor Key Encryption Key Register 5" group.long 0x438++0x03 line.long 0x00 "TDKEKR06,Trusted Descriptor Key Encryption Key Register 6" group.long 0x43C++0x03 line.long 0x00 "TDKEKR07,Trusted Descriptor Key Encryption Key Register 7" newline group.long 0x440++0x03 line.long 0x00 "TDSKR0,Trusted Descriptor Signing Key Register 0" group.long 0x444++0x03 line.long 0x00 "TDSKR1,Trusted Descriptor Signing Key Register 1" group.long 0x448++0x03 line.long 0x00 "TDSKR2,Trusted Descriptor Signing Key Register 2" group.long 0x44C++0x03 line.long 0x00 "TDSKR3,Trusted Descriptor Signing Key Register 3" group.long 0x450++0x03 line.long 0x00 "TDSKR4,Trusted Descriptor Signing Key Register 4" group.long 0x454++0x03 line.long 0x00 "TDSKR5,Trusted Descriptor Signing Key Register 5" group.long 0x458++0x03 line.long 0x00 "TDSKR6,Trusted Descriptor Signing Key Register 6" group.long 0x45C++0x03 line.long 0x00 "TDSKR7,Trusted Descriptor Signing Key Register 7" else hgroup.long 0x400++0x03 hide.long 0x00 "JDKEKR0,Job Descriptor Key Encryption Key Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "JDKEKR1,Job Descriptor Key Encryption Key Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "JDKEKR2,Job Descriptor Key Encryption Key Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "JDKEKR3,Job Descriptor Key Encryption Key Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "JDKEKR4,Job Descriptor Key Encryption Key Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "JDKEKR5,Job Descriptor Key Encryption Key Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "JDKEKR6,Job Descriptor Key Encryption Key Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "JDKEKR7,Job Descriptor Key Encryption Key Register 7" newline hgroup.long 0x420++0x03 hide.long 0x00 "TDKEKR00,Trusted Descriptor Key Encryption Key Register 0" hgroup.long 0x424++0x03 hide.long 0x00 "TDKEKR01,Trusted Descriptor Key Encryption Key Register 1" hgroup.long 0x428++0x03 hide.long 0x00 "TDKEKR02,Trusted Descriptor Key Encryption Key Register 2" hgroup.long 0x42C++0x03 hide.long 0x00 "TDKEKR03,Trusted Descriptor Key Encryption Key Register 3" hgroup.long 0x430++0x03 hide.long 0x00 "TDKEKR04,Trusted Descriptor Key Encryption Key Register 4" hgroup.long 0x434++0x03 hide.long 0x00 "TDKEKR05,Trusted Descriptor Key Encryption Key Register 5" hgroup.long 0x438++0x03 hide.long 0x00 "TDKEKR06,Trusted Descriptor Key Encryption Key Register 6" hgroup.long 0x43C++0x03 hide.long 0x00 "TDKEKR07,Trusted Descriptor Key Encryption Key Register 7" newline hgroup.long 0x440++0x03 hide.long 0x00 "TDSKR0,Trusted Descriptor Signing Key Register 0" hgroup.long 0x444++0x03 hide.long 0x00 "TDSKR1,Trusted Descriptor Signing Key Register 1" hgroup.long 0x448++0x03 hide.long 0x00 "TDSKR2,Trusted Descriptor Signing Key Register 2" hgroup.long 0x44C++0x03 hide.long 0x00 "TDSKR3,Trusted Descriptor Signing Key Register 3" hgroup.long 0x450++0x03 hide.long 0x00 "TDSKR4,Trusted Descriptor Signing Key Register 4" hgroup.long 0x454++0x03 hide.long 0x00 "TDSKR5,Trusted Descriptor Signing Key Register 5" hgroup.long 0x458++0x03 hide.long 0x00 "TDSKR6,Trusted Descriptor Signing Key Register 6" hgroup.long 0x45C++0x03 hide.long 0x00 "TDSKR7,Trusted Descriptor Signing Key Register 7" endif tree.end newline width 21. if (((per.l.be(ad:0x1700000+0xFD4))&0x300)==0x00) group.quad 0x4E0++0x07 line.quad 0x00 "SKNR,Secure Key Nonce Register" hexmask.quad.word 0x00 32.--44. 1. " SK_NONCE_MS ,Secure key nonce most significant" hexmask.quad.long 0x00 0.--31. 1. " SK_NONCE_LS ,Secure key nonce least significant" newline else hgroup.quad 0x4E0++0x07 hide.quad 0x00 "SKNR,Secure Key Nonce Register" newline endif rgroup.long 0x50C++0x13 line.long 0x00 "DMA_STA,DMA Status Register" bitfld.long 0x00 7. " DMA0_IDLE ,DMA0 is idle" "Busy,Idle" bitfld.long 0x00 0.--4. " DMA0_ETIF ,DMA0 external transactions in flight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DMA_X_AID_7_4_MAP,Mapping For DMA AXI IDs 7-4 Register" hexmask.long.byte 0x04 24.--31. 1. " AID7_BID ,SEC block ID using AXI ID 7" hexmask.long.byte 0x04 16.--23. 1. " AID6_BID ,SEC block ID using AXI ID 6" hexmask.long.byte 0x04 8.--15. 1. " AID5_BID ,SEC block ID using AXI ID 5" newline hexmask.long.byte 0x04 0.--7. 1. " AID4_BID ,SEC block ID using AXI ID 4" line.long 0x08 "DMA_X_AID_3_0_MAP,Mapping For DMA AXI IDs 3-0 Register" hexmask.long.byte 0x08 24.--31. 1. " AID3_BID ,SEC block ID using AXI ID 3" hexmask.long.byte 0x08 16.--23. 1. " AID2_BID ,SEC block ID using AXI ID 2" hexmask.long.byte 0x08 8.--15. 1. " AID1_BID ,SEC block ID using AXI ID 1" newline hexmask.long.byte 0x08 0.--7. 1. " AID0_BID ,SEC block ID using AXI ID 0" line.long 0x0C "DMA_X_AID_15_12_MAP,Mapping For DMA AXI IDs 15-12 Register" hexmask.long.byte 0x0C 24.--31. 1. " AID15_BID ,SEC block ID using AXI ID 15" hexmask.long.byte 0x0C 16.--23. 1. " AID14_BID ,SEC block ID using AXI ID 14" hexmask.long.byte 0x0C 8.--15. 1. " AID13_BID ,SEC block ID using AXI ID 13" newline hexmask.long.byte 0x0C 0.--7. 1. " AID12_BID ,SEC block ID using AXI ID 12" line.long 0x10 "DMA_X_AID_11_8_MAP,Mapping For DMA AXI IDs 11-8 Register" hexmask.long.byte 0x10 24.--31. 1. " AID11_BID ,SEC block ID using AXI ID 11" hexmask.long.byte 0x10 16.--23. 1. " AID10_BID ,SEC block ID using AXI ID 10" hexmask.long.byte 0x10 8.--15. 1. " AID9_BID ,SEC block ID using AXI ID 9" newline hexmask.long.byte 0x10 0.--7. 1. " AID8_BID ,SEC block ID using AXI ID 8" rgroup.long 0x524++0x03 line.long 0x00 "DMA_X_AID_15_0_EN,DMA_X AXI ID Map Enable Register" bitfld.long 0x00 15. " AID15E ,DMA engine 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " AID14E ,DMA engine 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " AID13E ,DMA engine 13 enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " AID12E ,DMA engine 12 enable" "Disabled,Enabled" bitfld.long 0x00 11. " AID11E ,DMA engine 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " AID10E ,DMA engine 10 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " AID9E ,DMA engine 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " AID8E ,DMA engine 8 enable" "Disabled,Enabled" bitfld.long 0x00 7. " AID7E ,DMA engine 7 enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " AID6E ,DMA engine 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " AID5E ,DMA engine 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " AID4E ,DMA engine 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " AID3E ,DMA engine 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " AID2E ,DMA engine 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " AID1E ,DMA engine 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " AID0E ,DMA engine 0 enable" "Disabled,Enabled" wgroup.long 0x530++0x03 line.long 0x00 "DMA_X_ARTC_CTL,DMA_X AXI Read Timing Check Control Register" bitfld.long 0x00 31. " ARTCE ,AXI read timing check enable" "Disabled,Enabled" bitfld.long 0x00 30. " ARCT ,AXI read counter test" "No test,Test" bitfld.long 0x00 29. " ARTT ,AXI read timer test" "No test,Test" newline bitfld.long 0x00 28. " ARTL ,AXI read timer last" "First,Last" hexmask.long.word 0x00 16.--27. 1. " ARL ,AXI read limit" hexmask.long.word 0x00 0.--11. 1. " ART ,AXI read timer" if (((per.l.be(ad:0x1700000+0x530))&0x80000000)==0x00) group.long 0x534++0x03 line.long 0x00 "DMA_X_ARTC_LC,DMA_X AXI Read Timing Check Late Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " ARLC ,AXI read late count" wgroup.long 0x538++0x03 line.long 0x00 "DMA_X_ARTC_SC,DMA_X AXI Read Timing Check Sample Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " ARSC ,AXI read sample count" group.long 0x53C++0x03 line.long 0x00 "DMA_X_ARTC_LAT,DMA_X Read Timing Check Latency Register" else rgroup.long 0x534++0x0B line.long 0x00 "DMA_X_ARTC_LC,DMA_X AXI Read Timing Check Late Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " ARLC ,AXI read late count" line.long 0x04 "DMA_X_ARTC_SC,DMA_X AXI Read Timing Check Sample Count Register" hexmask.long.tbyte 0x04 0.--19. 1. " ARSC ,AXI read sample count" line.long 0x08 "DMA_X_ARTC_LAT,DMA_X Read Timing Check Latency Register" endif group.long 0x540++0x03 line.long 0x00 "DMA_X_AWTC_CTL,DMA_X AXI Write Timing Check Control Register" bitfld.long 0x00 31. " AWTCE ,AXI write timing check enable" "Disabled,Enabled" bitfld.long 0x00 30. " AWCT ,AXI write counter test" "No test,Test" bitfld.long 0x00 29. " AWTT ,AXI write timer test" "No test,Test" newline hexmask.long.word 0x00 16.--27. 1. " AWL ,AXI write limit" hexmask.long.word 0x00 0.--11. 1. " AWT ,AXI write timer" if (((per.l.be(ad:0x1700000+0x540))&0x80000000)==0x00) group.long 0x544++0x03 line.long 0x00 "DMA_X_AWTC_LC,DMA_X AXI Write Timing Check Late Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " AWLC ,AXI write late count" wgroup.long 0x548++0x03 line.long 0x00 "DMA_X_AWTC_SC,DMA_X AXI Write Timing Check Sample Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " AWSC ,AXI write sample count" group.long 0x54C++0x03 line.long 0x00 "DMA_X_AWTC_LAT,DMA_X Write Timing Check Latency Register" else rgroup.long 0x544++0x0B line.long 0x00 "DMA_X_AWTC_LC,DMA_X AXI Write Timing Check Late Count Register" hexmask.long.tbyte 0x00 0.--19. 1. " AWLC ,AXI write late count" line.long 0x04 "DMA_X_AWTC_SC,DMA_X AXI Write Timing Check Sample Count Register" hexmask.long.tbyte 0x04 0.--19. 1. " AWSC ,AXI write sample count" line.long 0x08 "DMA_X_AWTC_LAT,DMA_X Write Timing Check Latency Register" endif tree "RNG (Random-Number Generator) Registers" if ((per.l.be(ad:0x1700000+0x600)&0x10000)==0x10000) group.long 0x600++0x0F line.long 0x00 "RTMCTL,RNG TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,TRNG ring oscillator stopped" "Running,Stopped" eventfld.long 0x00 12. " ERR ,Error status" "Not detected,Detected" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" bitfld.long 0x00 7. " FORCE_SYSCLK ,Force system clock" "Ring oscillator,TRNG" bitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No reset,Reset" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "Not set,Set" bitfld.long 0x00 4. " CLK_OUT_EN ,Clock output enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "No divide,/2,/4,/8" newline bitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode" "Von Neumann/Von Neumann,Raw/Von Neumann,Von Neumann/Raw,?..." line.long 0x04 "RTSCMISC,RNG TRNG Statistical Check Miscellaneous Register" bitfld.long 0x04 16.--19. " RTY_CNT ,RETRY count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 0.--7. 1. " LRUN_MAX ,LONG RUN MAX LIMIT" line.long 0x08 "RTPKRRNG,RNG TRNG Poker Range Register" hexmask.long.word 0x08 0.--15. 1. " PKR_RNG ,Poker range" line.long 0x0C "RTPKRMAX,RNG TRNG Poker Maximum Limit Register" hexmask.long.tbyte 0x0C 0.--23. 1. " PKR_RNG ,Poker maximum limit" else group.long 0x600++0x03 line.long 0x00 "RTMCTL,RNG TRNG Miscellaneous Control Register" bitfld.long 0x00 16. " PRGM ,Programming mode select" "Run mode,Program mode" rbitfld.long 0x00 13. " TSTOP_OK ,TRNG ring oscillator stopped" "Running,Stopped" eventfld.long 0x00 12. " ERR ,Error status" "Not detected,Detected" newline rbitfld.long 0x00 11. " TST_OUT ,Test point inside ring oscillator" "0,1" rbitfld.long 0x00 10. " ENT_VAL ,Entropy valid" "Not valid,Valid" rbitfld.long 0x00 9. " FCT_VAL ,Frequency count valid" "Not valid,Valid" newline rbitfld.long 0x00 8. " FCT_FAIL ,Frequency count fail" "Not failed,Failed" rbitfld.long 0x00 7. " FORCE_SYSCLK ,Force system clock" "Ring oscillator,TRNG" rbitfld.long 0x00 6. " RST_DEF ,Reset defaults" "No reset,Reset" newline bitfld.long 0x00 5. " TRNG_ACC ,TRNG access mode" "Not set,Set" bitfld.long 0x00 4. " CLK_OUT_EN ,Clock output enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " OSC_DIV ,Oscillator divide" "No divide,/2,/4,/8" newline rbitfld.long 0x00 0.--1. " SAMP_MODE ,Sample mode" "Von Neumann/Von Neumann,Raw/Von Neumann,Von Neumann/Raw,?..." hgroup.long 0x604++0x03 hide.long 0x00 "RTSCMISC,RNG TRNG Statistical Check Miscellaneous Register" rgroup.long 0x608++0x07 line.long 0x00 "RTPKRRNG,RNG TRNG Poker Range Register" hexmask.long.word 0x00 0.--15. 1. " PKR_RNG ,Poker range" line.long 0x04 "RTPKRSQ,RNG TRNG Poker Square Calculation Result Register" hexmask.long.tbyte 0x04 0.--23. 1. " PKR_SQ ,Poker square calculation result" endif group.long 0x610++0x03 line.long 0x00 "RTSDCTL,RNG TRNG Seed Control Register" hexmask.long.word 0x00 16.--31. 1. " ENT_DLY ,Entropy delay" hexmask.long.word 0x00 0.--15. 1. " SAMP_SIZE ,Sample size" if ((per.l.be(ad:0x1700000+0x600)&0x10000)==0x10000) group.long 0x614++0x03 line.long 0x00 "RTSBLIM,RNG TRNG Sparse Bit Limit Register" hexmask.long.word 0x00 0.--9. 1. " SB_LIM ,Sparse bit limit" else rgroup.long 0x614++0x03 line.long 0x00 "RTTOTSAM,RNG TRNG Total Samples Register" hexmask.long.tbyte 0x00 0.--19. 1. " TOT_SAM ,Total samples" endif if ((per.l.be(ad:0x1700000+0x600)&0x10000)==0x10000) group.long 0x618++0x23 line.long 0x00 "RTFRQMIN,RNG TRNG Frequency Count Minimum Limit Register" hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_MIN ,Frequency count minimum limit" line.long 0x04 "RTFRQMAX,RNG TRNG Frequency Count Maximum Limit Register" hexmask.long.tbyte 0x04 0.--21. 1. " FRQ_MAX ,Frequency counter maximum limit" line.long 0x08 "RTSCML,RNG TRNG Statistical Check Monobit Limit Register" hexmask.long.word 0x08 16.--31. 1. " MONO_RNG ,Monobit range" hexmask.long.word 0x08 0.--15. 1. " MONO_MAX ,Monobit maximum limit" line.long 0x0C "RTSCR1L,RNG TRNG Statistical Check Run Length 1 Limit Register" hexmask.long.word 0x0C 16.--30. 1. " RUN1_RNG ,Run length 1 range" hexmask.long.word 0x0C 0.--14. 1. " RUN1_MAX ,Run length 1 maximum limit" line.long 0x10 "RTSCR2L,RNG TRNG Statistical Check Run Length 2 Limit Register" hexmask.long.word 0x10 16.--29. 1. " RUN2_RNG ,Run length 2 range" hexmask.long.word 0x10 0.--13. 1. " RUN2_MAX ,Run length 2 maximum limit" line.long 0x14 "RTSCR3L,RNG TRNG Statistical Check Run Length 3 Limit Register" hexmask.long.word 0x14 16.--28. 1. " RUN3_RNG ,Run length 3 range" hexmask.long.word 0x14 0.--12. 1. " RUN3_MAX ,Run length 3 maximum limit" line.long 0x18 "RTSCR4L,RNG TRNG Statistical Check Run Length 4 Limit Register" hexmask.long.word 0x18 16.--27. 1. " RUN4_RNG ,Run length 4 range" hexmask.long.word 0x18 0.--11. 1. " RUN4_MAX ,Run length 4 maximum limit" line.long 0x1C "RTSCR5L,RNG TRNG Statistical Check Run Length 5 Limit Register" hexmask.long.word 0x1C 16.--26. 1. " RUN5_RNG ,Run length 5 range" hexmask.long.word 0x1C 0.--10. 1. " RUN5_MAX ,Run length 5 maximum limit" line.long 0x20 "RTSCR6PL,RNG TRNG Statistical Check Run Length 6+ Limit Register" hexmask.long.word 0x20 16.--26. 1. " RUN6P_RNG ,Run length 6+ range" hexmask.long.word 0x20 0.--10. 1. " RUN6P_MAX ,Run length 6+ maximum limit" else rgroup.long 0x618++0x23 line.long 0x00 "RTFRQMIN,RNG TRNG Frequency Count Minimum Limit Register" hexmask.long.tbyte 0x00 0.--21. 1. " FRQ_MIN ,Frequency count minimum limit" line.long 0x04 "RTFRQCNT,RNG TRNG Frequency Count Register" hexmask.long.tbyte 0x04 0.--21. 1. " FRQ_CNT ,Frequency count" line.long 0x08 "RTSCMC,RNG TRNG Statistical Check Monobit Count Register" hexmask.long.word 0x08 0.--15. 1. " MONO_CNT ,Monobit count" line.long 0x0C "RTSCR1C,RNG TRNG Statistical Check Run Length 1 Count Register" hexmask.long.word 0x0C 16.--30. 1. " R1_1_COUNT ,Runs of one length 1 count" hexmask.long.word 0x0C 0.--14. 1. " R1_0_COUNT ,Runs of zero length 1 count" line.long 0x10 "RTSCR2C,RNG TRNG Statistical Check Run Length 2 Count Register" hexmask.long.word 0x10 16.--29. 1. " R2_1_COUNT ,Runs of one length 2 count" hexmask.long.word 0x10 0.--13. 1. " R2_0_COUNT ,Runs of zero length 2 count" line.long 0x14 "RTSCR3C,RNG TRNG Statistical Check Run Length 3 Count Register" hexmask.long.word 0x14 16.--28. 1. " R3_1_COUNT ,Runs of one length 3 count" hexmask.long.word 0x14 0.--12. 1. " R3_0_COUNT ,Runs of zero length 3 count" line.long 0x18 "RTSCR4C,RNG TRNG Statistical Check Run Length 4 Count Register" hexmask.long.word 0x18 16.--27. 1. " R4_1_COUNT ,Runs of one length 4 count" hexmask.long.word 0x18 0.--11. 1. " R4_0_COUNT ,Runs of zero length 4 count" line.long 0x1C "RTSCR5C,RNG TRNG Statistical Check Run Length 5 Count Register" hexmask.long.word 0x1C 16.--26. 1. " R5_1_COUNT ,Runs of one length 5 count" hexmask.long.word 0x1C 0.--10. 1. " R5_0_COUNT ,Runs of zero length 5 count" line.long 0x20 "RTSCR6PC,RNG TRNG Statistical Check Run Length 6+ Count Register" hexmask.long.word 0x20 16.--26. 1. " R6P_1_COUNT ,Runs of one length 6+ count" hexmask.long.word 0x20 0.--10. 1. " R6P_0_COUNT ,Runs of zero length 6+ count" endif rgroup.long 0x63C++0x03 line.long 0x00 "RTSTATUS,RNG TRNG Status Register" bitfld.long 0x00 16.--19. " RETRY_COUNT ,Retry count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " FMBTF ,Mono bit test fail" "Not failed,Failed" bitfld.long 0x00 14. " FPTF ,Poker test fail" "Not failed,Failed" newline bitfld.long 0x00 13. " FLRTF ,Long run test fail" "Not failed,Failed" bitfld.long 0x00 12. " FSBTF ,Sparse bit test fail" "Not failed,Failed" bitfld.long 0x00 11. " F6PBR1TF ,6 plus bit run sampling 1s test fail" "Not failed,Failed" newline bitfld.long 0x00 10. " F6PBR0TF ,6 plus bit run sampling 0s test fail" "Not failed,Failed" bitfld.long 0x00 9. " F5BR1TF ,5-Bit run sampling 1s test fail" "Not failed,Failed" bitfld.long 0x00 8. " F5BR0TF ,5-Bit run sampling 0s test fail" "Not failed,Failed" newline bitfld.long 0x00 7. " F4BR1TF ,4-Bit run sampling 1s test fail" "Not failed,Failed" bitfld.long 0x00 6. " F4BR0TF ,4-Bit run sampling 0s test fail" "Not failed,Failed" bitfld.long 0x00 5. " F3BR1TF ,3-Bit run sampling 1s test fail" "Not failed,Failed" newline bitfld.long 0x00 4. " F3BR01TF ,3-Bit run sampling 0s test fail" "Not failed,Failed" bitfld.long 0x00 3. " F2BR1TF ,2-Bit run sampling 1s test fail" "Not failed,Failed" bitfld.long 0x00 2. " F2BR0TF ,2-Bit run sampling 0s test fail" "Not failed,Failed" newline bitfld.long 0x00 1. " F1BR1TF ,1-Bit run sampling 1s test fail" "Not failed,Failed" bitfld.long 0x00 0. " F1BR0TF ,1-Bit run sampling 0s test fail" "Not failed,Failed" rgroup.long 0x640++0x03 line.long 0x00 "RTENT0,RNG TRNG Entropy Read Register 0" rgroup.long 0x644++0x03 line.long 0x00 "RTENT1,RNG TRNG Entropy Read Register 1" rgroup.long 0x648++0x03 line.long 0x00 "RTENT2,RNG TRNG Entropy Read Register 2" rgroup.long 0x64C++0x03 line.long 0x00 "RTENT3,RNG TRNG Entropy Read Register 3" rgroup.long 0x650++0x03 line.long 0x00 "RTENT4,RNG TRNG Entropy Read Register 4" rgroup.long 0x654++0x03 line.long 0x00 "RTENT5,RNG TRNG Entropy Read Register 5" rgroup.long 0x658++0x03 line.long 0x00 "RTENT6,RNG TRNG Entropy Read Register 6" rgroup.long 0x65C++0x03 line.long 0x00 "RTENT7,RNG TRNG Entropy Read Register 7" rgroup.long 0x660++0x03 line.long 0x00 "RTENT8,RNG TRNG Entropy Read Register 8" rgroup.long 0x664++0x03 line.long 0x00 "RTENT9,RNG TRNG Entropy Read Register 9" rgroup.long 0x668++0x03 line.long 0x00 "RTENT10,RNG TRNG Entropy Read Register 10" rgroup.long 0x66C++0x03 line.long 0x00 "RTENT11,RNG TRNG Entropy Read Register 11" rgroup.long 0x670++0x03 line.long 0x00 "RTENT12,RNG TRNG Entropy Read Register 12" rgroup.long 0x674++0x03 line.long 0x00 "RTENT13,RNG TRNG Entropy Read Register 13" rgroup.long 0x678++0x03 line.long 0x00 "RTENT14,RNG TRNG Entropy Read Register 14" hgroup.long 0x67C++0x03 hide.long 0x00 "RTENT15,RNG TRNG Entropy Read Register 15" in if (((per.l.be(ad:0x1700000+0x600))&0x10000)==0x00) rgroup.long 0x680++0x1F line.long 0x00 "RTPKRCNT10,RNG TRNG Statistical Check Poker Count 1 And 0 Register" hexmask.long.word 0x00 16.--31. 1. " PKR_1_CNT ,Poker 1h count" hexmask.long.word 0x00 0.--15. 1. " PKR_0_CNT ,Poker 0h count" line.long 0x04 "RTPKRCNT32,RNG TRNG Statistical Check Poker Count 3 And 2 Register" hexmask.long.word 0x04 16.--31. 1. " PKR_3_CNT ,Poker 3h count" hexmask.long.word 0x04 0.--15. 1. " PKR_2_CNT ,Poker 2h count" line.long 0x08 "RTPKRCNT54,RNG TRNG Statistical Check Poker Count 5 And 4 Register" hexmask.long.word 0x08 16.--31. 1. " PKR_5_CNT ,Poker 5h count" hexmask.long.word 0x08 0.--15. 1. " PKR_4_CNT ,Poker 4h count" line.long 0x0C "RTPKRCNT76,RNG TRNG Statistical Check Poker Count 7 And 6 Register" hexmask.long.word 0x0C 16.--31. 1. " PKR_7_CNT ,Poker 7h count" hexmask.long.word 0x0C 0.--15. 1. " PKR_6_CNT ,Poker 6h count" line.long 0x10 "RTPKRCNT98,RNG TRNG Statistical Check Poker Count 9 And 8 Register" hexmask.long.word 0x10 16.--31. 1. " PKR_9_CNT ,Poker 9h count" hexmask.long.word 0x10 0.--15. 1. " PKR_8_CNT ,Poker 8h count" line.long 0x14 "RTPKRCNTBA,RNG TRNG Statistical Check Poker Count B And A Register" hexmask.long.word 0x14 16.--31. 1. " PKR_B_CNT ,Poker bh count" hexmask.long.word 0x14 0.--15. 1. " PKR_A_CNT ,Poker ah count" line.long 0x18 "RTPKRCNTDC,RNG TRNG Statistical Check Poker Count D And C Register" hexmask.long.word 0x18 16.--31. 1. " PKR_D_CNT ,Poker dh count" hexmask.long.word 0x18 0.--15. 1. " PKR_C_CNT ,Poker ch count" line.long 0x1C "RTPKRCNTFE,RNG TRNG Statistical Check Poker Count F And E Register" hexmask.long.word 0x1C 16.--31. 1. " PKR_F_CNT ,Poker fh count" hexmask.long.word 0x1C 0.--15. 1. " PKR_E_CNT ,Poker eh count" rgroup.long 0x6C0++0x03 line.long 0x00 "RDSTA,RNG DRNG Status Register" bitfld.long 0x00 31. " SKVT ,Secure key valid test" "Not generated,Generated" bitfld.long 0x00 30. " SKVN ,Secure key valid non-test" "Not generated,Generated" bitfld.long 0x00 20. " CE ,Catastrophic error" "No error,Error" newline bitfld.long 0x00 16.--19. " ERRCODE ,Error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " TF1 ,Test flag state handle 1." "No test,Test" bitfld.long 0x00 8. " TF0 ,Test flag state handle 0" "No test,Test" newline bitfld.long 0x00 5. " PR1 ,Prediction resistance flag state handle 1" "Not occurred,Occurred" bitfld.long 0x00 4. " PR0 ,Prediction resistance flag state handle 0" "Not occurred,Occurred" bitfld.long 0x00 1. " IF1 ,Instantiated flag state handle 1" "Not instantiated,Instantiated" newline bitfld.long 0x00 0. " IF0 ,Instantiated flag state handle 0" "Not instantiated,Instantiated" else hgroup.long 0x680++0x03 hide.long 0x00 "RTPKRCNT10,RNG TRNG Statistical Check Poker Count 1 And 0 Register" hgroup.long 0x684++0x03 hide.long 0x00 "RTPKRCNT32,RNG TRNG Statistical Check Poker Count 3 And 2 Register" hgroup.long 0x688++0x03 hide.long 0x00 "RTPKRCNT54,RNG TRNG Statistical Check Poker Count 5 And 4 Register" hgroup.long 0x68C++0x03 hide.long 0x00 "RTPKRCNT76,RNG TRNG Statistical Check Poker Count 7 And 6 Register" hgroup.long 0x690++0x03 hide.long 0x00 "RTPKRCNT98,RNG TRNG Statistical Check Poker Count 9 And 8 Register" hgroup.long 0x694++0x03 hide.long 0x00 "RTPKRCNTBA,RNG TRNG Statistical Check Poker Count B And A Register" hgroup.long 0x698++0x03 hide.long 0x00 "RTPKRCNTDC,RNG TRNG Statistical Check Poker Count D And C Register" hgroup.long 0x69C++0x03 hide.long 0x00 "RTPKRCNTFE,RNG TRNG Statistical Check Poker Count F And E Register" hgroup.long 0x6C0++0x03 hide.long 0x00 "RDSTA,RNG DRNG Status Register" endif rgroup.long 0x6D0++0x07 line.long 0x00 "RDINT0,RNG DRNG State Handle 0 Reseed Interval Register" line.long 0x04 "RDINT1,RNG DRNG State Handle 1 Reseed Interval Register" group.long 0x6E0++0x03 line.long 0x00 "RDHCNTL,RNG DRNG Hash Control Register" bitfld.long 0x00 4. " HTC ,Hashing test mode clear" "No effect,Clear" bitfld.long 0x00 3. " HTM ,Hashing test mode" "Disabled,Enabled" bitfld.long 0x00 2. " HI ,Hashing initialize" "No effect,Initialize" newline bitfld.long 0x00 1. " HB ,Hashing begin" "No effect,Begin" rbitfld.long 0x00 0. " HD ,Hashing done" "Not done,Done" hgroup.long 0x6E4++0x03 hide.long 0x00 "RDHDIG,RNG DRNG Hash Digest Register" in if (((per.l.be(ad:0x1700000+0x6E0))&0x08)==0x08) wgroup.long 0x6E8++0x03 line.long 0x00 "RDHBUF,RNG DRNG Hash Buffer Register" else hgroup.long 0x6E8++0x03 hide.long 0x00 "RDHBUF,RNG DRNG Hash Buffer Register" endif tree.end newline group.long 0xB00++0x03 line.long 0x00 "REIS,Recoverable Error Interrupt Status" eventfld.long 0x00 27. " JBAE3 ,Job ring 3 bus access error" "No error,Error" eventfld.long 0x00 26. " JBAE2 ,Job ring 2 bus access error" "No error,Error" eventfld.long 0x00 25. " JBAE1 ,Job ring 1 bus access error" "No error,Error" newline eventfld.long 0x00 24. " JBAE0 ,Job ring 0 bus access error" "No error,Error" eventfld.long 0x00 16. " RBAE ,SEC RTIC bus access error" "No error,Error" newline eventfld.long 0x00 9. " QBAE ,SEC's queue manager interface bus access error" "No error,Error" eventfld.long 0x00 8. " QHLT ,SEC's queue manager interface halted due to stop or stop on error" "Not halted,Halted" newline eventfld.long 0x00 0. " CWDE ,The SEC watchdog timer expired" "Not expired,Expired" group.long 0xB0C++0x03 line.long 0x00 "REIH,Recoverable Error Interrupt Halt" bitfld.long 0x00 27. " JBAE3 ,Halt SEC if JR3-initiated job execution caused bus access error" "No halt,Halt" bitfld.long 0x00 26. " JBAE2 ,Halt SEC if JR2-initiated job execution caused bus access error" "No halt,Halt" bitfld.long 0x00 25. " JBAE1 ,Halt SEC if JR1-initiated job execution caused bus access error" "No halt,Halt" newline bitfld.long 0x00 24. " JBAE0 ,Halt SEC if JR0-initiated job execution caused bus access error" "No halt,Halt" bitfld.long 0x00 16. " RBAE ,Halt SEC if RTIC-initiated job execution caused bus access error" "No halt,Halt" rbitfld.long 0x00 11. " QFDD ,Halt SEC if QI frame descriptor dropped" "No halt,Halt" newline bitfld.long 0x00 10. " QIVE ,Halt SEC if QI isolation violation error" "No halt,Halt" bitfld.long 0x00 9. " QBAE ,Halt SEC if QI-initiated job execution caused bus access error" "No halt,Halt" bitfld.long 0x00 8. " QHLT ,Halt SEC if QI halted" "No halt,Halt" newline bitfld.long 0x00 0. " CWDE ,Halt SEC if SEC watchdog timer expires" "No halt,Halt" rgroup.long 0xBF8++0x07 line.long 0x00 "SECVID_MS,SEC Version ID Register Most Significant Half" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,ID for SEC" hexmask.long.byte 0x00 8.--15. 1. " MAJ_REV ,Major revision number for SEC" hexmask.long.byte 0x00 0.--7. 1. " MIN_REV ,Minor revision number for SEC" line.long 0x04 "SECVID_LS,SEC Version ID Register Least Significant Half" hexmask.long.byte 0x04 24.--31. 1. " COMPILE_OPT ,Compile options for SEC" hexmask.long.byte 0x04 16.--23. 1. " INTG_OPT ,Integration options for SEC" hexmask.long.byte 0x04 8.--15. 1. " ECO_REV ,ECO revision for SEC" newline hexmask.long.byte 0x04 0.--7. 1. " CONFIG_OPT ,Configuration options for SEC" newline hgroup.quad 0xC00++0x07 hide.quad 0x00 "HT0_JD_ADDR,Holding Tank 0 Job Descriptor Address" in rgroup.quad 0xC08++0x07 line.quad 0x00 "HT0_SD_ADDR,Holding Tank 0 Shared Descriptor Address" hexmask.quad 0x00 0.--48. 0x01 " SD_ADDR ,Shared descriptor address" newline rgroup.long 0xC10++0x07 line.long 0x00 "HT0_JQ_CTRL_MS,Holding Tank 0 Job Queue Control Most Significant Half Register" bitfld.long 0x00 29. " WHL ,Whole descriptor" "0,1" bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" newline bitfld.long 0x00 22.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 19. " DWORD_SWAP ,Double word swap" "MS-LS,LS-MS" bitfld.long 0x00 17.--18. " HT_ERROR ,Holding tank error" "None,Job/Shared Desc. length,Job Ring/QI Shared/Job ring Job Desc.,AXI error on QI/AI in. frame" newline bitfld.long 0x00 16. " SOB ,Shared or burst" "0,1" bitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" bitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,QI,AI,?..." newline bitfld.long 0x00 0.--4. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HT0_JQ_CTRL_LS,Holding Tank 0 Job Queue Control Least Significant Half Register" bitfld.long 0x04 31. " CTL_PL ,Control privilege level" "Low,High" hexmask.long.byte 0x04 16.--22. 1. " CTL_ICID ,Control ICID" bitfld.long 0x04 15. " OUT_PL ,Output privilege level" "Low,High" newline hexmask.long.byte 0x04 0.--6. 1. " OUT_ICID ,Output ICID value" hgroup.long 0xC1C++0x03 hide.long 0x00 "HT0_STATUS,Holding Tank Status" in group.long 0xC24++0x03 line.long 0x00 "JQ_DEBUG_SEL,Job Queue Debug Select Register" rbitfld.long 0x00 16.--20. " JOB_ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--2. " HT_SEL ,Holding tank select" "0,1,2,3,4,5,6,7" rgroup.long 0xDBC++0x0B line.long 0x00 "JRJIDU_LS,Job Ring Job IDs In Use Register Least Significant Half" bitfld.long 0x00 15. " JID15 ,Job ID 15 is currently in use" "Not in use,In use" bitfld.long 0x00 14. " JID14 ,Job ID 14 is currently in use" "Not in use,In use" bitfld.long 0x00 13. " JID13 ,Job ID 13 is currently in use" "Not in use,In use" newline bitfld.long 0x00 12. " JID12 ,Job ID 12 is currently in use" "Not in use,In use" bitfld.long 0x00 11. " JID11 ,Job ID 11 is currently in use" "Not in use,In use" bitfld.long 0x00 10. " JID10 ,Job ID 10 is currently in use" "Not in use,In use" newline bitfld.long 0x00 9. " JID9 ,Job ID 9 is currently in use" "Not in use,In use" bitfld.long 0x00 8. " JID8 ,Job ID 8 is currently in use" "Not in use,In use" bitfld.long 0x00 7. " JID7 ,Job ID 7 is currently in use" "Not in use,In use" newline bitfld.long 0x00 6. " JID6 ,Job ID 6 is currently in use" "Not in use,In use" bitfld.long 0x00 5. " JID5 ,Job ID 5 is currently in use" "Not in use,In use" bitfld.long 0x00 4. " JID4 ,Job ID 4 is currently in use" "Not in use,In use" newline bitfld.long 0x00 3. " JID3 ,Job ID 3 is currently in use" "Not in use,In use" bitfld.long 0x00 2. " JID2 ,Job ID 2 is currently in use" "Not in use,In use" bitfld.long 0x00 1. " JID1 ,Job ID 1 is currently in use" "Not in use,In use" newline bitfld.long 0x00 0. " JID0 ,Job ID 0 is currently in use" "Not in use,In use" line.long 0x04 "JRJDJIFBC,Job Ring Job-Done Job ID FIFO BC" bitfld.long 0x04 31. " BC ,Been changed" "Not changed,Changed" line.long 0x08 "JRJDJIF,Job Ring Job-Done Job ID FIFO" bitfld.long 0x08 0.--4. " JOB_ID_ENTRY ,Job ID entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xDE4++0x03 line.long 0x00 "JRJDS1,Job Ring Job-Done Source 1" bitfld.long 0x00 31. " VALID ,JQ_DEBUG_SEL.JOB_ID-specified job completion-status" "Not valid,Valid" bitfld.long 0x00 0.--1. " SRC ,Number of the job ring being the source of a job with completion status waiting to be written to an output ring" "0,1,2,3" newline group.quad 0xF00++0x37 line.quad 0x00 "PC_REQ_DEQ,Performance Counter Number Of Requests Dequeued" hexmask.quad 0x00 0.--47. 1. " PC_REQ_DEQ ,Performance counter requests dequeued" line.quad 0x08 "PC_OB_ENC_REQ,Performance Counter Number Of Outbound Encrypt Requests" hexmask.quad 0x08 0.--47. 1. " PC_OB_ENC_REQ ,Performance counter outbound encryption requests" line.quad 0x10 "PC_IB_DEC_REQ,Performance Counter Number Of Inbound Decrypt Requests" hexmask.quad 0x10 0.--47. 1. " PC_IB_DEC_REQ ,Performance counter inbound decryptions requested" line.quad 0x18 "PC_OB_ENCRYPT,Performance Counter Number Of Outbound Bytes Encrypted" hexmask.quad 0x18 0.--47. 1. " PC_OB_ENCRYPT ,Performance counter outbound bytes encrypted" line.quad 0x20 "PC_OB_PROTECT,Performance Counter Number Of Outbound Bytes Protected" hexmask.quad 0x20 0.--47. 1. " PC_OB_PROTECT ,Performance counter outbound bytes encrypted" line.quad 0x28 "PC_IB_DECRYPT,Performance Counter Number Of Inbound Bytes Decrypted" hexmask.quad 0x28 0.--47. 1. " PC_IB_DECRYPT ,Performance counter inbound bytes decrypted" line.quad 0x30 "PC_IB_VALIDATED,Performance Counter Number Of Inbound Bytes Validated" hexmask.quad 0x30 0.--47. 1. " PC_IB_VALIDATED ,Performance counter inbound bytes validated" newline rgroup.long 0xFA0++0x0F line.long 0x00 "CRNR_MS,CHA Revision Number Register Most Significant Half" hexmask.long.byte 0x00 28.--31. 1. " JRRN ,Job ring revision number" hexmask.long.byte 0x00 24.--27. 1. " DECORN ,DECO revision number" bitfld.long 0x00 12.--15. " ZARN ,ZUC authentication hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " ZERN ,ZUC encryption hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SNW9RN ,SNOW-f9 hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CRCRN ,CRC hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CRNR_LS,CHA Revision Number Register Least Significant Half" bitfld.long 0x04 28.--31. " PKRN ,Public key hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " KASRN ,Kasumi f8/f9 hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " SNW8RN ,SNOW-f8 hardware accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. " RNGRN ,Random number generator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " MDRN ,Message digest hardware accelerator module revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DESRN ,DES accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " AESRN ,AES accelerator revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CTPR_MS,Compile Time Parameters Register Most Significant Half" bitfld.long 0x08 28.--31. " AXI_PIPE_DEPTH ,AXI pipeline depth" "Maximum,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 27. " AXI_LIODN ,LIODN logic included" "Not implemented,Implemented" bitfld.long 0x08 26. " AXI_PRI ,AXI master priority implemented" "Not implemented,Implemented" newline bitfld.long 0x08 25. " QI ,Queue manager interface (QI)" "Not implemented,Implemented" bitfld.long 0x08 24. " ACC_CTL ,ICID-based access control" "Not implemented,Implemented" bitfld.long 0x08 23. " C1C2 ,Separate C1 and C2 registers" "Shared,Separated" newline bitfld.long 0x08 21. " PC ,Performance counter registers implemented" "Not implemented,Implemented" bitfld.long 0x08 20. " DECO_WD ,DECO watchdog counter implemented" "Not implemented,Implemented" bitfld.long 0x08 19. " PM_EVT_BUS ,Performance monitor event bus implemented" "Not implemented,Implemented" newline bitfld.long 0x08 18. " SG8 ,Eight scatter-gather tables implemented" "1 table,8 tables" bitfld.long 0x08 17. " MCFG_PS ,Pointer size field implemented" "Not implemented,Implemented" bitfld.long 0x08 16. " MCFG_BURST ,Support for large AXI bursts" "Not implemented,Implemented" newline bitfld.long 0x08 14. " IP_CLK ,IP bus slave clock to SEC's AXI bus clock ratio" "1:1,1:2" bitfld.long 0x08 13. " DPAA2 ,DPAA2 architecture supported" "Not supported,Supported" bitfld.long 0x08 11. " AI_INCL ,AIOP interface implemented" "Not implemented,Implemented" newline bitfld.long 0x08 8.--10. " RNG_I ,RNG instantiations" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. " REG_PG_SIZE ,SEC register page size" "4Kbyte,64Kbyte" bitfld.long 0x08 1. " VIRT_EN_POR_VALUE ,Job ring virtualization POR state" "Disabled,Enabled" newline bitfld.long 0x08 0. " VIRT_EN_INCL ,Job ring virtualization programmable" "Not included,Included" line.long 0x0C "CTPR_LS,Compile Time Parameters Register Least Significant Half" bitfld.long 0x0C 14. " SPLIT_KEY ,Split key protocol" "Not implemented,Implemented" bitfld.long 0x0C 13. " MAN_PROT ,Manufacturing protection protocol" "Not implemented,Implemented" bitfld.long 0x0C 12. " DBL_CRC ,Double CRC protocol" "Not implemented,Implemented" newline bitfld.long 0x0C 11. " P3G_LTE ,3GPP/LTE protocol" "Not implemented,Implemented" bitfld.long 0x0C 10. " RSA ,RSA protocol" "Not implemented,Implemented" bitfld.long 0x0C 9. " MACSEC ,MACSEC protocol" "Not implemented,Implemented" newline bitfld.long 0x0C 8. " TLS_PRF ,TLS PRF protocol" "Not implemented,Implemented" bitfld.long 0x0C 7. " SSL_TLS ,SSL/TLS protocol" "Not implemented,Implemented" bitfld.long 0x0C 6. " IKE ,IKE protocols" "Not implemented,Implemented" newline bitfld.long 0x0C 5. " IPSEC ,IPSEC protocols" "Not implemented,Implemented" bitfld.long 0x0C 4. " SRTP ,SRTP protocol" "Not implemented,Implemented" bitfld.long 0x0C 3. " WIMAX ,WiMax protocol" "Not implemented,Implemented" newline bitfld.long 0x0C 2. " WIFI ,WiFi protocol" "Not implemented,Implemented" bitfld.long 0x0C 1. " BLOB ,Blob protocol" "Not implemented,Implemented" bitfld.long 0x0C 0. " KG_DS ,PK generation and digital signature protocols" "Not implemented,Implemented" newline hgroup.quad 0xFC0++0x07 hide.quad 0x00 "FAR,Fault Address Register" in newline hgroup.long 0xFC8++0x03 hide.long 0x00 "FAICID,Fault Address ICID Register" in hgroup.long 0xFCC++0x03 hide.long 0x00 "FADR,Fault Address Detail Register" in rgroup.long 0xFD4++0x03 line.long 0x00 "SSTA,SEC Status Register" bitfld.long 0x00 10. " PLEND ,Platform endianness" "Little,Big" bitfld.long 0x00 8.--9. " MOO ,Mode of operation" "Non secure,Secure,Trusted,Fail" bitfld.long 0x00 2. " TRNG_IDLE ,TRNG idle" "Not idle,Idle" newline bitfld.long 0x00 1. " IDLE ,SEC is idle" "Not idle,Idle" bitfld.long 0x00 0. " BSY ,SEC busy" "Not busy,Busy" rgroup.long 0xFE0++0x17 line.long 0x00 "RVID,RTIC Version ID Register" bitfld.long 0x00 27. " MD ,Memory block D available" "Not available,Available" bitfld.long 0x00 26. " MC ,Memory block C available" "Not available,Available" bitfld.long 0x00 25. " MB ,Memory block B available" "Not available,Available" newline bitfld.long 0x00 24. " MA ,Memory block A available" "Not available,Available" bitfld.long 0x00 19. " SHA_512 ,SHA-512" "Not usable,Usable" bitfld.long 0x00 17. " SHA_256 ,SHA-256" "Not usable,Usable" newline hexmask.long.byte 0x00 8.--15. 1. " RMJV ,RTIC major version" hexmask.long.byte 0x00 0.--7. 1. " RMNV ,RTIC minor version" line.long 0x04 "CCBVID,CHA Cluster Block Version ID Register" hexmask.long.byte 0x04 24.--31. 1. " SEC_ERA ,SEC era" hexmask.long.byte 0x04 8.--15. 1. " AMJV ,Accelerator major revision number" hexmask.long.byte 0x04 0.--7. 1. " AMNV ,Accelerator minor revision number" line.long 0x08 "CHAVID_MS,CHA Version ID Register Most Significant Half" bitfld.long 0x08 28.--31. " JRVID ,Job ring version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " DECOVID ,DECO version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " ZAVID ,ZUC authentication hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--11. " ZEVID ,ZUC encryption hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " SNW9VID ,SNOW-f9 hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " CRCVID ,CRC hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CHAVID_LS,CHA Version ID Register Least Significant Half" bitfld.long 0x0C 28.--31. " PKVID ,Public key hardware accelerator version ID" "PKHA-XT 32-bit,PKHA-SD 32-bit,PKHA-SD 64-bit,PKHA-SD 128-bit,?..." newline bitfld.long 0x0C 24.--27. " KASVID ,Kasumi f8/f9 hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 20.--23. " SNW8VID ,SNOW-f8 hardware accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 16.--19. " RNGVID ,Random number generator version ID" ",,RNGB,,RNG4,?..." newline bitfld.long 0x0C 12.--15. " MDVID ,Message digest hardware accelerator version ID" "Low-power,Low-power (+ SHA-512/SHA-512/224/SHA-512/256/SHA-384),Medium-performance,High-performance,?..." newline bitfld.long 0x0C 4.--7. " DESVID ,DES accelerator version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " AESVID ,AES accelerator version ID" ",,,Low-power,High-performance,?..." line.long 0x10 "CHANUM_MS,CHA Number Register Most Significant Half" bitfld.long 0x10 28.--31. " JRNUM ,Job ring number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " DECONUM ,DECO number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. " ZANUM ,ZUC authentication hardware accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 8.--11. " ZENUM ,ZUC encryption hardware accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. " SNW9NUM ,SNOW-f9 hardware accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " CRCNUM ,CRC hardware accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "CHANUM_LS,CHA Number Register Least Significant Half" bitfld.long 0x14 28.--31. " PKNUM ,Public key number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. " KASNUM ,Kasumi f8/f9 number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 20.--23. " SNW8NUM ,SNOW-f8 number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 16.--19. " RNGNUM ,Random number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 12.--15. " MDNUM ,Message digest number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 8.--11. " ARC4NUM ,DES accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 4.--7. " DESNUM ,DES accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. " AESNUM ,AES accelerator number of copies implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 15. tree "Job ring Registers" tree "Job ring 0" group.quad 0x10000++0x07 line.quad 0x00 "IRBAR_JR0,Input Ring Base Address Register For Job Ring 0" hexmask.quad 0x00 0.--39. 0x01 " IRBA ,Input ring base address" newline group.long (0x10000+0x0C)++0x03 line.long 0x00 "IRSR_JR0,Input Ring Size Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " IRS ,Input ring size" group.long (0x10000+0x14)++0x03 line.long 0x00 "IRSAR_JR0,Input Ring Slots Available Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " IRSA ,Input ring slots available" group.long (0x10000+0x1C)++0x03 line.long 0x00 "IRJAR_JR0,Input Ring Jobs Added Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " IRJA ,Input ring jobs added" newline group.quad (0x10000+0x20)++0x07 line.quad 0x00 "ORBAR_JR0,Output Ring Base Address Register For Job Ring 0" hexmask.quad 0x00 0.--39. 0x01 " ORBA ,Output ring base address" newline group.long (0x10000+0x2C)++0x03 line.long 0x00 "ORSR_JR0,Output Ring Size Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " ORS ,Output ring size" group.long (0x10000+0x34)++0x03 line.long 0x00 "ORJRR_JR0,Output Ring Jobs Removed Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " ORJR ,Output ring jobs removed" group.long (0x10000+0x3C)++0x03 line.long 0x00 "ORSFR_JR0,Output Ring Slots Full Register For Job Ring 0" hexmask.long.word 0x00 0.--9. 1. " ORSF ,Output ring slots full" if (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x00) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR0,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x10000000)||(((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x50000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR01,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x20000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR02,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" bitfld.long 0x00 4.--7. " CHAID ,Algorithm that generated the error" "CCB,AESA,DESA,,MDHA,RNG,SNOWf8,KFHA f8/9,PKHA,CRCA,SNOWf9,ZUCE,ZUCA,?..." bitfld.long 0x00 0.--3. " ERRID ,Descriptor error ID" "None,Mode,Data size,Key size/Instantiate,Not instantiated/A size,Test instantiate/B size,Prediction resistance/Data out of sequence /ECC F2M,Prediction resistance and test request/Divide by 0,Modulus even,Key parity/Secure Key generation,ICV check failed,Hardware,CCM AAD size/Continuous check/Invalid key write,Class 1 or class 2 CHA is not reset,Invalid CHA combination selected,Invalid CHA" elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x30000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR03,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " LOCAL_OFFSET ,User defined value" elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x40000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR04,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x60000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR06,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 8.--11. " NADDR ,Number of descriptor addresses requested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x10000+0x44))&0xF0000000)==0x70000000) rgroup.long (0x10000+0x44)++0x03 line.long 0x00 "JRSTAR_JR07,Job Ring Output Status Register For Job Ring 0" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " COND ,PKHA/Math condition codes field from JUMP HALT command" endif group.long (0x10000+0x4C)++0x0B line.long 0x00 "JRINTR_JR0,Job Ring Interrupt Status Register For Job Ring 0" hexmask.long.word 0x00 16.--29. 1. " ERR_ORWI ,Output ring write index with error" rbitfld.long 0x00 8.--12. " ERR_TYPE ,Error type" ",Error writing status to Output Ring,,Bad input ring base address,Bad output ring base address,Invalid write to IRBAR_JR or IRSR_JR,Invalid write to ORBAR_JR or ORSR_JR,Job ring reset released before halted,ORJRR > ORSFR,IRJAR > IRSAR,Writing ORSF > ORS,Writing IRSA > IRS,Writing ORWI > ORS in bytes,Writing IRRI > IRS in bytes,Writing IRSA when ring is active,Writing IRRI when ring is active,Writing ORSF when ring is active,Writing ORWI when ring is active,?..." newline eventfld.long 0x00 5. " EXIT_FAIL ,Exit secmon fail state" "Not exited,Exited" eventfld.long 0x00 4. " ENTER_FAIL ,Enter secmon fail state" "Not entered,Entered" newline eventfld.long 0x00 3. " HALT[1] ,Halt the job ring 1" ",Requested" eventfld.long 0x00 2. " [0] ,Halt the job ring 0" ",Flushed-Halted/Clear" newline eventfld.long 0x00 1. " JRE ,Job ring error" "No error,Error" eventfld.long 0x00 0. " JRI ,Job ring interrupt" "No interrupt,Interrupt" line.long 0x04 "JRCFGR_JR0_MS,Job Ring Configuration Register For Job Ring 0 Most Significant Half" bitfld.long 0x04 31. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x04 30. " INCL_SEQ_OUT ,Include sequence out length" "Not included,Included" newline bitfld.long 0x04 29. " FAIL_MODE ,Fail mode control" "Halt,Continue" bitfld.long 0x04 18. " DWSO ,Double word swap override" "Not swapped,Swapped" newline bitfld.long 0x04 17. " PEO ,Platform endian override" "No Override,Override" bitfld.long 0x04 16. " DMBS ,Descriptor message data byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 15. " CDWSO ,Control data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 14. " CWSO ,Control data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 13. " CHWSO ,Control data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 12. " CBSO ,Control data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 11. " MDWSO ,Message data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 10. " MWSO ,Message data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 9. " MHWSO ,Message data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 8. " MBSO ,Message data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 7. " CDWSI ,Control data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 6. " CWSI ,Control data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 5. " CHWSI ,Control data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 4. " CBSI ,Control data read byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 3. " MDWSI ,Message data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 2. " MWSI ,Message data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 1. " MHWSI ,Message data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 0. " MBSI ,Message data read byte swap" "Not swapped,Swapped" line.long 0x08 "JRCFGR_JR0_LS,Job Ring Configuration Register For Job Ring 0 Least Significant Half" hexmask.long.word 0x08 16.--31. 1. " ICTT ,Interrupt coalescing timer threshold" hexmask.long.byte 0x08 8.--15. 1. " ICDCT ,Interrupt coalescing descriptor count threshold" newline bitfld.long 0x08 1. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x08 0. " IMSK ,Interrupt mask" "Not masked,Masked" group.long (0x10000+0x5C)++0x03 line.long 0x00 "IRRIR_JR0,Input Ring Read Index Register For Job Ring 0" hexmask.long.word 0x00 0.--12. 1. " IRRI ,Input ring read index" group.long (0x10000+0x64)++0x03 line.long 0x00 "ORWIR_JR0,Output Ring Write Index Register For Job Ring 0" hexmask.long.word 0x00 0.--13. 1. " ORWI ,Output ring write index" wgroup.long (0x10000+0x6C)++0x03 line.long 0x00 "JRCR_JR0,Job Ring Command Register For Job Ring 0" bitfld.long 0x00 1. " PARK ,Park" "No effect,Park" bitfld.long 0x00 0. " RESET ,Reset" "No effect,Reset" hgroup.long (0x10000+0x704)++0x03 hide.long 0x00 "JR0AAV,Job Ring 0 Address-Array Valid Register" in newline hgroup.quad (0x10000+0x800)++0x07 hide.quad 0x00 "JR0AAAV0,Job Ring 0 Address-Array Address 0 Register" in rgroup.quad (0x10000+0x808)++0x37 line.quad 0x00 "JR0AAAV1,Job Ring 0 Address-Array Address 1 Register" hexmask.quad 0x00 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x08 "JR0AAAV2,Job Ring 0 Address-Array Address 2 Register" hexmask.quad 0x08 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x10 "JR0AAAV3,Job Ring 0 Address-Array Address 3 Register" hexmask.quad 0x10 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x18 "JR0AAAV4,Job Ring 0 Address-Array Address 4 Register" hexmask.quad 0x18 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x20 "JR0AAAV5,Job Ring 0 Address-Array Address 5 Register" hexmask.quad 0x20 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x28 "JR0AAAV6,Job Ring 0 Address-Array Address 6 Register" hexmask.quad 0x28 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x30 "JR0AAAV7,Job Ring 0 Address-Array Address 7 Register" hexmask.quad 0x30 0.--48. 0x01 " JD_ADDR ,Job descriptor address" rgroup.long (0x10000+0xE00)++0x03 line.long 0x00 "REIR0JR0,Recoverable Error Interrupt Record 0 For Job Ring 0" bitfld.long 0x00 31. " MISS ,Miss" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,Type of the recoverable error" ",Memory access,?..." rgroup.quad (0x10000+0xE08)++0x07 line.quad 0x00 "REIR2JR0,Recoverable Error Interrupt Record 2 For Job Ring 0" rgroup.long (0x10000+0xE10)++0x07 line.long 0x00 "REIR4JR0,Recoverable Error Interrupt Record 4 For Job Ring 0" bitfld.long 0x00 30.--31. " MIX ,Memory interface index" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response" "0,1,2,3" newline bitfld.long 0x00 23. " RWB ,Read or write" "0,1" bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. " ICID ,ICID" line.long 0x04 "REIR5JR0,Recoverable Error Interrupt Record 5 For Job Ring 0" bitfld.long 0x04 24. " SAFE ,Safe" "0,1" bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction" "General registers,Job ring registers,Job ring registers,Job ring registers,Job ring registers,AIOP interface registers,Real-time integrity check registers,Queue interface registers,DECO 0/CHA CCB 0,DECO 1/CHA CCB 1,DECO 2/CHA CCB 2,DECO 3/CHA CCB 3,DECO 4/CHA CCB 4,DECO 5/CHA CCB 5,?..." tree.end tree "Job ring 1" group.quad 0x20000++0x07 line.quad 0x00 "IRBAR_JR1,Input Ring Base Address Register For Job Ring 1" hexmask.quad 0x00 0.--39. 0x01 " IRBA ,Input ring base address" newline group.long (0x20000+0x0C)++0x03 line.long 0x00 "IRSR_JR1,Input Ring Size Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " IRS ,Input ring size" group.long (0x20000+0x14)++0x03 line.long 0x00 "IRSAR_JR1,Input Ring Slots Available Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " IRSA ,Input ring slots available" group.long (0x20000+0x1C)++0x03 line.long 0x00 "IRJAR_JR1,Input Ring Jobs Added Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " IRJA ,Input ring jobs added" newline group.quad (0x20000+0x20)++0x07 line.quad 0x00 "ORBAR_JR1,Output Ring Base Address Register For Job Ring 1" hexmask.quad 0x00 0.--39. 0x01 " ORBA ,Output ring base address" newline group.long (0x20000+0x2C)++0x03 line.long 0x00 "ORSR_JR1,Output Ring Size Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " ORS ,Output ring size" group.long (0x20000+0x34)++0x03 line.long 0x00 "ORJRR_JR1,Output Ring Jobs Removed Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " ORJR ,Output ring jobs removed" group.long (0x20000+0x3C)++0x03 line.long 0x00 "ORSFR_JR1,Output Ring Slots Full Register For Job Ring 1" hexmask.long.word 0x00 0.--9. 1. " ORSF ,Output ring slots full" if (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x00) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR1,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x10000000)||(((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x50000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR11,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x20000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR12,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" bitfld.long 0x00 4.--7. " CHAID ,Algorithm that generated the error" "CCB,AESA,DESA,,MDHA,RNG,SNOWf8,KFHA f8/9,PKHA,CRCA,SNOWf9,ZUCE,ZUCA,?..." bitfld.long 0x00 0.--3. " ERRID ,Descriptor error ID" "None,Mode,Data size,Key size/Instantiate,Not instantiated/A size,Test instantiate/B size,Prediction resistance/Data out of sequence /ECC F2M,Prediction resistance and test request/Divide by 0,Modulus even,Key parity/Secure Key generation,ICV check failed,Hardware,CCM AAD size/Continuous check/Invalid key write,Class 1 or class 2 CHA is not reset,Invalid CHA combination selected,Invalid CHA" elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x30000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR13,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " LOCAL_OFFSET ,User defined value" elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x40000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR14,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x60000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR16,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 8.--11. " NADDR ,Number of descriptor addresses requested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x20000+0x44))&0xF0000000)==0x70000000) rgroup.long (0x20000+0x44)++0x03 line.long 0x00 "JRSTAR_JR17,Job Ring Output Status Register For Job Ring 1" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " COND ,PKHA/Math condition codes field from JUMP HALT command" endif group.long (0x20000+0x4C)++0x0B line.long 0x00 "JRINTR_JR1,Job Ring Interrupt Status Register For Job Ring 1" hexmask.long.word 0x00 16.--29. 1. " ERR_ORWI ,Output ring write index with error" rbitfld.long 0x00 8.--12. " ERR_TYPE ,Error type" ",Error writing status to Output Ring,,Bad input ring base address,Bad output ring base address,Invalid write to IRBAR_JR or IRSR_JR,Invalid write to ORBAR_JR or ORSR_JR,Job ring reset released before halted,ORJRR > ORSFR,IRJAR > IRSAR,Writing ORSF > ORS,Writing IRSA > IRS,Writing ORWI > ORS in bytes,Writing IRRI > IRS in bytes,Writing IRSA when ring is active,Writing IRRI when ring is active,Writing ORSF when ring is active,Writing ORWI when ring is active,?..." newline eventfld.long 0x00 5. " EXIT_FAIL ,Exit secmon fail state" "Not exited,Exited" eventfld.long 0x00 4. " ENTER_FAIL ,Enter secmon fail state" "Not entered,Entered" newline eventfld.long 0x00 3. " HALT[1] ,Halt the job ring 1" ",Requested" eventfld.long 0x00 2. " [0] ,Halt the job ring 0" ",Flushed-Halted/Clear" newline eventfld.long 0x00 1. " JRE ,Job ring error" "No error,Error" eventfld.long 0x00 0. " JRI ,Job ring interrupt" "No interrupt,Interrupt" line.long 0x04 "JRCFGR_JR1_MS,Job Ring Configuration Register For Job Ring 1 Most Significant Half" bitfld.long 0x04 31. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x04 30. " INCL_SEQ_OUT ,Include sequence out length" "Not included,Included" newline bitfld.long 0x04 29. " FAIL_MODE ,Fail mode control" "Halt,Continue" bitfld.long 0x04 18. " DWSO ,Double word swap override" "Not swapped,Swapped" newline bitfld.long 0x04 17. " PEO ,Platform endian override" "No Override,Override" bitfld.long 0x04 16. " DMBS ,Descriptor message data byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 15. " CDWSO ,Control data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 14. " CWSO ,Control data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 13. " CHWSO ,Control data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 12. " CBSO ,Control data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 11. " MDWSO ,Message data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 10. " MWSO ,Message data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 9. " MHWSO ,Message data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 8. " MBSO ,Message data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 7. " CDWSI ,Control data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 6. " CWSI ,Control data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 5. " CHWSI ,Control data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 4. " CBSI ,Control data read byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 3. " MDWSI ,Message data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 2. " MWSI ,Message data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 1. " MHWSI ,Message data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 0. " MBSI ,Message data read byte swap" "Not swapped,Swapped" line.long 0x08 "JRCFGR_JR1_LS,Job Ring Configuration Register For Job Ring 1 Least Significant Half" hexmask.long.word 0x08 16.--31. 1. " ICTT ,Interrupt coalescing timer threshold" hexmask.long.byte 0x08 8.--15. 1. " ICDCT ,Interrupt coalescing descriptor count threshold" newline bitfld.long 0x08 1. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x08 0. " IMSK ,Interrupt mask" "Not masked,Masked" group.long (0x20000+0x5C)++0x03 line.long 0x00 "IRRIR_JR1,Input Ring Read Index Register For Job Ring 1" hexmask.long.word 0x00 0.--12. 1. " IRRI ,Input ring read index" group.long (0x20000+0x64)++0x03 line.long 0x00 "ORWIR_JR1,Output Ring Write Index Register For Job Ring 1" hexmask.long.word 0x00 0.--13. 1. " ORWI ,Output ring write index" wgroup.long (0x20000+0x6C)++0x03 line.long 0x00 "JRCR_JR1,Job Ring Command Register For Job Ring 1" bitfld.long 0x00 1. " PARK ,Park" "No effect,Park" bitfld.long 0x00 0. " RESET ,Reset" "No effect,Reset" hgroup.long (0x20000+0x704)++0x03 hide.long 0x00 "JR1AAV,Job Ring 1 Address-Array Valid Register" in newline hgroup.quad (0x20000+0x800)++0x07 hide.quad 0x00 "JR1AAAV0,Job Ring 1 Address-Array Address 0 Register" in rgroup.quad (0x20000+0x808)++0x37 line.quad 0x00 "JR1AAAV1,Job Ring 1 Address-Array Address 1 Register" hexmask.quad 0x00 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x08 "JR1AAAV2,Job Ring 1 Address-Array Address 2 Register" hexmask.quad 0x08 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x10 "JR1AAAV3,Job Ring 1 Address-Array Address 3 Register" hexmask.quad 0x10 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x18 "JR1AAAV4,Job Ring 1 Address-Array Address 4 Register" hexmask.quad 0x18 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x20 "JR1AAAV5,Job Ring 1 Address-Array Address 5 Register" hexmask.quad 0x20 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x28 "JR1AAAV6,Job Ring 1 Address-Array Address 6 Register" hexmask.quad 0x28 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x30 "JR1AAAV7,Job Ring 1 Address-Array Address 7 Register" hexmask.quad 0x30 0.--48. 0x01 " JD_ADDR ,Job descriptor address" rgroup.long (0x20000+0xE00)++0x03 line.long 0x00 "REIR0JR1,Recoverable Error Interrupt Record 0 For Job Ring 1" bitfld.long 0x00 31. " MISS ,Miss" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,Type of the recoverable error" ",Memory access,?..." rgroup.quad (0x20000+0xE08)++0x07 line.quad 0x00 "REIR2JR1,Recoverable Error Interrupt Record 2 For Job Ring 1" rgroup.long (0x20000+0xE10)++0x07 line.long 0x00 "REIR4JR1,Recoverable Error Interrupt Record 4 For Job Ring 1" bitfld.long 0x00 30.--31. " MIX ,Memory interface index" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response" "0,1,2,3" newline bitfld.long 0x00 23. " RWB ,Read or write" "0,1" bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. " ICID ,ICID" line.long 0x04 "REIR5JR1,Recoverable Error Interrupt Record 5 For Job Ring 1" bitfld.long 0x04 24. " SAFE ,Safe" "0,1" bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction" "General registers,Job ring registers,Job ring registers,Job ring registers,Job ring registers,AIOP interface registers,Real-time integrity check registers,Queue interface registers,DECO 0/CHA CCB 0,DECO 1/CHA CCB 1,DECO 2/CHA CCB 2,DECO 3/CHA CCB 3,DECO 4/CHA CCB 4,DECO 5/CHA CCB 5,?..." tree.end tree "Job ring 2" group.quad 0x30000++0x07 line.quad 0x00 "IRBAR_JR2,Input Ring Base Address Register For Job Ring 2" hexmask.quad 0x00 0.--39. 0x01 " IRBA ,Input ring base address" newline group.long (0x30000+0x0C)++0x03 line.long 0x00 "IRSR_JR2,Input Ring Size Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " IRS ,Input ring size" group.long (0x30000+0x14)++0x03 line.long 0x00 "IRSAR_JR2,Input Ring Slots Available Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " IRSA ,Input ring slots available" group.long (0x30000+0x1C)++0x03 line.long 0x00 "IRJAR_JR2,Input Ring Jobs Added Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " IRJA ,Input ring jobs added" newline group.quad (0x30000+0x20)++0x07 line.quad 0x00 "ORBAR_JR2,Output Ring Base Address Register For Job Ring 2" hexmask.quad 0x00 0.--39. 0x01 " ORBA ,Output ring base address" newline group.long (0x30000+0x2C)++0x03 line.long 0x00 "ORSR_JR2,Output Ring Size Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " ORS ,Output ring size" group.long (0x30000+0x34)++0x03 line.long 0x00 "ORJRR_JR2,Output Ring Jobs Removed Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " ORJR ,Output ring jobs removed" group.long (0x30000+0x3C)++0x03 line.long 0x00 "ORSFR_JR2,Output Ring Slots Full Register For Job Ring 2" hexmask.long.word 0x00 0.--9. 1. " ORSF ,Output ring slots full" if (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x00) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR2,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x10000000)||(((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x50000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR21,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x20000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR22,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" bitfld.long 0x00 4.--7. " CHAID ,Algorithm that generated the error" "CCB,AESA,DESA,,MDHA,RNG,SNOWf8,KFHA f8/9,PKHA,CRCA,SNOWf9,ZUCE,ZUCA,?..." bitfld.long 0x00 0.--3. " ERRID ,Descriptor error ID" "None,Mode,Data size,Key size/Instantiate,Not instantiated/A size,Test instantiate/B size,Prediction resistance/Data out of sequence /ECC F2M,Prediction resistance and test request/Divide by 0,Modulus even,Key parity/Secure Key generation,ICV check failed,Hardware,CCM AAD size/Continuous check/Invalid key write,Class 1 or class 2 CHA is not reset,Invalid CHA combination selected,Invalid CHA" elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x30000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR23,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " LOCAL_OFFSET ,User defined value" elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x40000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR24,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x60000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR26,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 8.--11. " NADDR ,Number of descriptor addresses requested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x30000+0x44))&0xF0000000)==0x70000000) rgroup.long (0x30000+0x44)++0x03 line.long 0x00 "JRSTAR_JR27,Job Ring Output Status Register For Job Ring 2" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " COND ,PKHA/Math condition codes field from JUMP HALT command" endif group.long (0x30000+0x4C)++0x0B line.long 0x00 "JRINTR_JR2,Job Ring Interrupt Status Register For Job Ring 2" hexmask.long.word 0x00 16.--29. 1. " ERR_ORWI ,Output ring write index with error" rbitfld.long 0x00 8.--12. " ERR_TYPE ,Error type" ",Error writing status to Output Ring,,Bad input ring base address,Bad output ring base address,Invalid write to IRBAR_JR or IRSR_JR,Invalid write to ORBAR_JR or ORSR_JR,Job ring reset released before halted,ORJRR > ORSFR,IRJAR > IRSAR,Writing ORSF > ORS,Writing IRSA > IRS,Writing ORWI > ORS in bytes,Writing IRRI > IRS in bytes,Writing IRSA when ring is active,Writing IRRI when ring is active,Writing ORSF when ring is active,Writing ORWI when ring is active,?..." newline eventfld.long 0x00 5. " EXIT_FAIL ,Exit secmon fail state" "Not exited,Exited" eventfld.long 0x00 4. " ENTER_FAIL ,Enter secmon fail state" "Not entered,Entered" newline eventfld.long 0x00 3. " HALT[1] ,Halt the job ring 1" ",Requested" eventfld.long 0x00 2. " [0] ,Halt the job ring 0" ",Flushed-Halted/Clear" newline eventfld.long 0x00 1. " JRE ,Job ring error" "No error,Error" eventfld.long 0x00 0. " JRI ,Job ring interrupt" "No interrupt,Interrupt" line.long 0x04 "JRCFGR_JR2_MS,Job Ring Configuration Register For Job Ring 2 Most Significant Half" bitfld.long 0x04 31. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x04 30. " INCL_SEQ_OUT ,Include sequence out length" "Not included,Included" newline bitfld.long 0x04 29. " FAIL_MODE ,Fail mode control" "Halt,Continue" bitfld.long 0x04 18. " DWSO ,Double word swap override" "Not swapped,Swapped" newline bitfld.long 0x04 17. " PEO ,Platform endian override" "No Override,Override" bitfld.long 0x04 16. " DMBS ,Descriptor message data byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 15. " CDWSO ,Control data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 14. " CWSO ,Control data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 13. " CHWSO ,Control data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 12. " CBSO ,Control data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 11. " MDWSO ,Message data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 10. " MWSO ,Message data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 9. " MHWSO ,Message data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 8. " MBSO ,Message data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 7. " CDWSI ,Control data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 6. " CWSI ,Control data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 5. " CHWSI ,Control data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 4. " CBSI ,Control data read byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 3. " MDWSI ,Message data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 2. " MWSI ,Message data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 1. " MHWSI ,Message data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 0. " MBSI ,Message data read byte swap" "Not swapped,Swapped" line.long 0x08 "JRCFGR_JR2_LS,Job Ring Configuration Register For Job Ring 2 Least Significant Half" hexmask.long.word 0x08 16.--31. 1. " ICTT ,Interrupt coalescing timer threshold" hexmask.long.byte 0x08 8.--15. 1. " ICDCT ,Interrupt coalescing descriptor count threshold" newline bitfld.long 0x08 1. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x08 0. " IMSK ,Interrupt mask" "Not masked,Masked" group.long (0x30000+0x5C)++0x03 line.long 0x00 "IRRIR_JR2,Input Ring Read Index Register For Job Ring 2" hexmask.long.word 0x00 0.--12. 1. " IRRI ,Input ring read index" group.long (0x30000+0x64)++0x03 line.long 0x00 "ORWIR_JR2,Output Ring Write Index Register For Job Ring 2" hexmask.long.word 0x00 0.--13. 1. " ORWI ,Output ring write index" wgroup.long (0x30000+0x6C)++0x03 line.long 0x00 "JRCR_JR2,Job Ring Command Register For Job Ring 2" bitfld.long 0x00 1. " PARK ,Park" "No effect,Park" bitfld.long 0x00 0. " RESET ,Reset" "No effect,Reset" hgroup.long (0x30000+0x704)++0x03 hide.long 0x00 "JR2AAV,Job Ring 2 Address-Array Valid Register" in newline hgroup.quad (0x30000+0x800)++0x07 hide.quad 0x00 "JR2AAAV0,Job Ring 2 Address-Array Address 0 Register" in rgroup.quad (0x30000+0x808)++0x37 line.quad 0x00 "JR2AAAV1,Job Ring 2 Address-Array Address 1 Register" hexmask.quad 0x00 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x08 "JR2AAAV2,Job Ring 2 Address-Array Address 2 Register" hexmask.quad 0x08 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x10 "JR2AAAV3,Job Ring 2 Address-Array Address 3 Register" hexmask.quad 0x10 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x18 "JR2AAAV4,Job Ring 2 Address-Array Address 4 Register" hexmask.quad 0x18 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x20 "JR2AAAV5,Job Ring 2 Address-Array Address 5 Register" hexmask.quad 0x20 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x28 "JR2AAAV6,Job Ring 2 Address-Array Address 6 Register" hexmask.quad 0x28 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x30 "JR2AAAV7,Job Ring 2 Address-Array Address 7 Register" hexmask.quad 0x30 0.--48. 0x01 " JD_ADDR ,Job descriptor address" rgroup.long (0x30000+0xE00)++0x03 line.long 0x00 "REIR0JR2,Recoverable Error Interrupt Record 0 For Job Ring 2" bitfld.long 0x00 31. " MISS ,Miss" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,Type of the recoverable error" ",Memory access,?..." rgroup.quad (0x30000+0xE08)++0x07 line.quad 0x00 "REIR2JR2,Recoverable Error Interrupt Record 2 For Job Ring 2" rgroup.long (0x30000+0xE10)++0x07 line.long 0x00 "REIR4JR2,Recoverable Error Interrupt Record 4 For Job Ring 2" bitfld.long 0x00 30.--31. " MIX ,Memory interface index" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response" "0,1,2,3" newline bitfld.long 0x00 23. " RWB ,Read or write" "0,1" bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. " ICID ,ICID" line.long 0x04 "REIR5JR2,Recoverable Error Interrupt Record 5 For Job Ring 2" bitfld.long 0x04 24. " SAFE ,Safe" "0,1" bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction" "General registers,Job ring registers,Job ring registers,Job ring registers,Job ring registers,AIOP interface registers,Real-time integrity check registers,Queue interface registers,DECO 0/CHA CCB 0,DECO 1/CHA CCB 1,DECO 2/CHA CCB 2,DECO 3/CHA CCB 3,DECO 4/CHA CCB 4,DECO 5/CHA CCB 5,?..." tree.end tree "Job ring 3" group.quad 0x40000++0x07 line.quad 0x00 "IRBAR_JR3,Input Ring Base Address Register For Job Ring 3" hexmask.quad 0x00 0.--39. 0x01 " IRBA ,Input ring base address" newline group.long (0x40000+0x0C)++0x03 line.long 0x00 "IRSR_JR3,Input Ring Size Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " IRS ,Input ring size" group.long (0x40000+0x14)++0x03 line.long 0x00 "IRSAR_JR3,Input Ring Slots Available Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " IRSA ,Input ring slots available" group.long (0x40000+0x1C)++0x03 line.long 0x00 "IRJAR_JR3,Input Ring Jobs Added Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " IRJA ,Input ring jobs added" newline group.quad (0x40000+0x20)++0x07 line.quad 0x00 "ORBAR_JR3,Output Ring Base Address Register For Job Ring 3" hexmask.quad 0x00 0.--39. 0x01 " ORBA ,Output ring base address" newline group.long (0x40000+0x2C)++0x03 line.long 0x00 "ORSR_JR3,Output Ring Size Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " ORS ,Output ring size" group.long (0x40000+0x34)++0x03 line.long 0x00 "ORJRR_JR3,Output Ring Jobs Removed Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " ORJR ,Output ring jobs removed" group.long (0x40000+0x3C)++0x03 line.long 0x00 "ORSFR_JR3,Output Ring Slots Full Register For Job Ring 3" hexmask.long.word 0x00 0.--9. 1. " ORSF ,Output ring slots full" if (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x00) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR3,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x10000000)||(((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x50000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR31,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x20000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR32,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" bitfld.long 0x00 4.--7. " CHAID ,Algorithm that generated the error" "CCB,AESA,DESA,,MDHA,RNG,SNOWf8,KFHA f8/9,PKHA,CRCA,SNOWf9,ZUCE,ZUCA,?..." bitfld.long 0x00 0.--3. " ERRID ,Descriptor error ID" "None,Mode,Data size,Key size/Instantiate,Not instantiated/A size,Test instantiate/B size,Prediction resistance/Data out of sequence /ECC F2M,Prediction resistance and test request/Divide by 0,Modulus even,Key parity/Secure Key generation,ICV check failed,Hardware,CCM AAD size/Continuous check/Invalid key write,Class 1 or class 2 CHA is not reset,Invalid CHA combination selected,Invalid CHA" elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x30000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR33,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " LOCAL_OFFSET ,User defined value" elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x40000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR34,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to an error within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x60000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR36,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 8.--11. " NADDR ,Number of descriptor addresses requested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ERROR ,Error code" elif (((per.l.be(ad:0x1700000+0x40000+0x44))&0xF0000000)==0x70000000) rgroup.long (0x40000+0x44)++0x03 line.long 0x00 "JRSTAR_JR37,Job Ring Output Status Register For Job Ring 3" bitfld.long 0x00 28.--31. " SSRC ,Status source" "None,AI,CCB,Jump Halt User,DECO,QI,Job Ring,Jump Halt Condition Codes,?..." bitfld.long 0x00 27. " JMP ,Jump to another descriptor" "Not occurred,Occurred" bitfld.long 0x00 26. " MLK ,Memory leak" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--15. 1. " DESCINDEX ,Index to JUMP HALT command within the descriptor (number of words)" hexmask.long.byte 0x00 0.--7. 1. " COND ,PKHA/Math condition codes field from JUMP HALT command" endif group.long (0x40000+0x4C)++0x0B line.long 0x00 "JRINTR_JR3,Job Ring Interrupt Status Register For Job Ring 3" hexmask.long.word 0x00 16.--29. 1. " ERR_ORWI ,Output ring write index with error" rbitfld.long 0x00 8.--12. " ERR_TYPE ,Error type" ",Error writing status to Output Ring,,Bad input ring base address,Bad output ring base address,Invalid write to IRBAR_JR or IRSR_JR,Invalid write to ORBAR_JR or ORSR_JR,Job ring reset released before halted,ORJRR > ORSFR,IRJAR > IRSAR,Writing ORSF > ORS,Writing IRSA > IRS,Writing ORWI > ORS in bytes,Writing IRRI > IRS in bytes,Writing IRSA when ring is active,Writing IRRI when ring is active,Writing ORSF when ring is active,Writing ORWI when ring is active,?..." newline eventfld.long 0x00 5. " EXIT_FAIL ,Exit secmon fail state" "Not exited,Exited" eventfld.long 0x00 4. " ENTER_FAIL ,Enter secmon fail state" "Not entered,Entered" newline eventfld.long 0x00 3. " HALT[1] ,Halt the job ring 1" ",Requested" eventfld.long 0x00 2. " [0] ,Halt the job ring 0" ",Flushed-Halted/Clear" newline eventfld.long 0x00 1. " JRE ,Job ring error" "No error,Error" eventfld.long 0x00 0. " JRI ,Job ring interrupt" "No interrupt,Interrupt" line.long 0x04 "JRCFGR_JR3_MS,Job Ring Configuration Register For Job Ring 3 Most Significant Half" bitfld.long 0x04 31. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x04 30. " INCL_SEQ_OUT ,Include sequence out length" "Not included,Included" newline bitfld.long 0x04 29. " FAIL_MODE ,Fail mode control" "Halt,Continue" bitfld.long 0x04 18. " DWSO ,Double word swap override" "Not swapped,Swapped" newline bitfld.long 0x04 17. " PEO ,Platform endian override" "No Override,Override" bitfld.long 0x04 16. " DMBS ,Descriptor message data byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 15. " CDWSO ,Control data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 14. " CWSO ,Control data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 13. " CHWSO ,Control data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 12. " CBSO ,Control data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 11. " MDWSO ,Message data write double word swap" "Not swapped,Swapped" bitfld.long 0x04 10. " MWSO ,Message data write fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 9. " MHWSO ,Message data write halfword swap" "Not swapped,Swapped" bitfld.long 0x04 8. " MBSO ,Message data write byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 7. " CDWSI ,Control data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 6. " CWSI ,Control data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 5. " CHWSI ,Control data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 4. " CBSI ,Control data read byte swap" "Not swapped,Swapped" newline bitfld.long 0x04 3. " MDWSI ,Message data read double word swap" "Not swapped,Swapped" bitfld.long 0x04 2. " MWSI ,Message data read fullword swap" "Not swapped,Swapped" newline bitfld.long 0x04 1. " MHWSI ,Message data read halfword swap" "Not swapped,Swapped" bitfld.long 0x04 0. " MBSI ,Message data read byte swap" "Not swapped,Swapped" line.long 0x08 "JRCFGR_JR3_LS,Job Ring Configuration Register For Job Ring 3 Least Significant Half" hexmask.long.word 0x08 16.--31. 1. " ICTT ,Interrupt coalescing timer threshold" hexmask.long.byte 0x08 8.--15. 1. " ICDCT ,Interrupt coalescing descriptor count threshold" newline bitfld.long 0x08 1. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x08 0. " IMSK ,Interrupt mask" "Not masked,Masked" group.long (0x40000+0x5C)++0x03 line.long 0x00 "IRRIR_JR3,Input Ring Read Index Register For Job Ring 3" hexmask.long.word 0x00 0.--12. 1. " IRRI ,Input ring read index" group.long (0x40000+0x64)++0x03 line.long 0x00 "ORWIR_JR3,Output Ring Write Index Register For Job Ring 3" hexmask.long.word 0x00 0.--13. 1. " ORWI ,Output ring write index" wgroup.long (0x40000+0x6C)++0x03 line.long 0x00 "JRCR_JR3,Job Ring Command Register For Job Ring 3" bitfld.long 0x00 1. " PARK ,Park" "No effect,Park" bitfld.long 0x00 0. " RESET ,Reset" "No effect,Reset" hgroup.long (0x40000+0x704)++0x03 hide.long 0x00 "JR3AAV,Job Ring 3 Address-Array Valid Register" in newline hgroup.quad (0x40000+0x800)++0x07 hide.quad 0x00 "JR3AAAV0,Job Ring 3 Address-Array Address 0 Register" in rgroup.quad (0x40000+0x808)++0x37 line.quad 0x00 "JR3AAAV1,Job Ring 3 Address-Array Address 1 Register" hexmask.quad 0x00 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x08 "JR3AAAV2,Job Ring 3 Address-Array Address 2 Register" hexmask.quad 0x08 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x10 "JR3AAAV3,Job Ring 3 Address-Array Address 3 Register" hexmask.quad 0x10 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x18 "JR3AAAV4,Job Ring 3 Address-Array Address 4 Register" hexmask.quad 0x18 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x20 "JR3AAAV5,Job Ring 3 Address-Array Address 5 Register" hexmask.quad 0x20 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x28 "JR3AAAV6,Job Ring 3 Address-Array Address 6 Register" hexmask.quad 0x28 0.--48. 0x01 " JD_ADDR ,Job descriptor address" line.quad 0x30 "JR3AAAV7,Job Ring 3 Address-Array Address 7 Register" hexmask.quad 0x30 0.--48. 0x01 " JD_ADDR ,Job descriptor address" rgroup.long (0x40000+0xE00)++0x03 line.long 0x00 "REIR0JR3,Recoverable Error Interrupt Record 0 For Job Ring 3" bitfld.long 0x00 31. " MISS ,Miss" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,Type of the recoverable error" ",Memory access,?..." rgroup.quad (0x40000+0xE08)++0x07 line.quad 0x00 "REIR2JR3,Recoverable Error Interrupt Record 2 For Job Ring 3" rgroup.long (0x40000+0xE10)++0x07 line.long 0x00 "REIR4JR3,Recoverable Error Interrupt Record 4 For Job Ring 3" bitfld.long 0x00 30.--31. " MIX ,Memory interface index" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response" "0,1,2,3" newline bitfld.long 0x00 23. " RWB ,Read or write" "0,1" bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. " ICID ,ICID" line.long 0x04 "REIR5JR3,Recoverable Error Interrupt Record 5 For Job Ring 3" bitfld.long 0x04 24. " SAFE ,Safe" "0,1" bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction" "General registers,Job ring registers,Job ring registers,Job ring registers,Job ring registers,AIOP interface registers,Real-time integrity check registers,Queue interface registers,DECO 0/CHA CCB 0,DECO 1/CHA CCB 1,DECO 2/CHA CCB 2,DECO 3/CHA CCB 3,DECO 4/CHA CCB 4,DECO 5/CHA CCB 5,?..." tree.end tree.end width 15. tree "RTIC (Run-Time Integrity Checker) Registers" hgroup.long 0x60004++0x03 hide.long 0x00 "RSTA,RTIC Status Register" in newline group.long 0x6000C++0x03 line.long 0x00 "RCMD,RTIC Command Register" bitfld.long 0x00 3. " RTD ,Run time disable" "No,Yes" bitfld.long 0x00 2. " RTC ,Run time check" "Disabled,Enabled" newline bitfld.long 0x00 1. " HO ,Hash once" "Disabled,Enabled" bitfld.long 0x00 0. " CINT ,Clear interrupt" "No clear,Clear" group.long 0x60014++0x03 line.long 0x00 "RCTL,RTIC Control Register" bitfld.long 0x00 31. " DSV ,DECOSEL valid" "Not valid,Valid" bitfld.long 0x00 24.--25. " DECOSEL ,DECO select" "DECO 0,DECO 1,DECO 2,?..." newline bitfld.long 0x00 20. " RIDLE ,RTIC setting for the IPG_IDLE signal" "Neg when hashing,Neg when in Run-Time" bitfld.long 0x00 19. " RALG[3] ,RTIC algorithm select for memory block D" "SHA-256,SHA-512" newline bitfld.long 0x00 18. " [2] ,RTIC algorithm select for memory block C" "SHA-256,SHA-512" bitfld.long 0x00 17. " [1] ,RTIC algorithm select for memory block B" "SHA-256,SHA-512" newline bitfld.long 0x00 16. " [0] ,RTIC algorithm select for memory block A" "SHA-256,SHA-512" bitfld.long 0x00 15. " RTMU[3] ,Run time unlock memory block D" "Not unlocked,Unlocked" newline bitfld.long 0x00 14. " [2] ,Run time unlock memory block C" "Not unlocked,Unlocked" bitfld.long 0x00 13. " [1] ,Run time unlock memory block B" "Not unlocked,Unlocked" newline bitfld.long 0x00 12. " [0] ,Run time unlock memory block A" "Not unlocked,Unlocked" bitfld.long 0x00 11. " RTME[3] ,Run time enable memory block D" "Disabled,Enabled" newline bitfld.long 0x00 10. " [2] ,Run time enable memory block C" "Disabled,Enabled" bitfld.long 0x00 9. " [1] ,Run time enable memory block B" "Disabled,Enabled" newline bitfld.long 0x00 8. " [0] ,Run time enable memory block A" "Disabled,Enabled" bitfld.long 0x00 7. " HOME[3] ,Hash once enable memory block D" "Disabled,Enabled" newline bitfld.long 0x00 6. " [2] ,Hash once enable memory block C" "Disabled,Enabled" bitfld.long 0x00 5. " [1] ,Hash once enable memory block B" "Disabled,Enabled" newline bitfld.long 0x00 4. " [0] ,Hash once enable memory block A" "Disabled,Enabled" bitfld.long 0x00 1.--3. " RREQS ,RTIC request size" "1 block,1 block,2 blocks,3 blocks,4 blocks,5 blocks,6 blocks,7 blocks" newline bitfld.long 0x00 0. " IE ,Interrupt enable" "Disabled,Enabled" group.long 0x6001C++0x03 line.long 0x00 "RTHR,RTIC Throttle Register" newline group.quad 0x60028++0x07 line.quad 0x00 "RWDOG,RTIC Watchdog Timer" hexmask.quad 0x00 0.--47. 1. " RWDOG ,Run time watchdog time-out value" newline group.long 0x60014++0x03 line.long 0x00 "RCTL,RTIC Control Register" bitfld.long 0x00 19. " RDWS[3] ,RTIC double word swap for memory block D" "Not swapped,Swapped" newline bitfld.long 0x00 18. " [2] ,RTIC double word swap for memory block C" "Not swapped,Swapped" bitfld.long 0x00 17. " [1] ,RTIC double word swap for memory block B" "Not swapped,Swapped" newline bitfld.long 0x00 16. " [0] ,RTIC double word swap for memory block A" "Not swapped,Swapped" bitfld.long 0x00 15. " RWS[3] ,RTIC word swap memory block D" "Not swapped,Swapped" newline bitfld.long 0x00 14. " [2] ,RTIC word swap memory block C" "Not swapped,Swapped" bitfld.long 0x00 13. " [1] ,RTIC word swap memory block B" "Not swapped,Swapped" newline bitfld.long 0x00 12. " [0] ,RTIC word swap memory block A" "Not swapped,Swapped" bitfld.long 0x00 11. " RHWS[3] ,RTIC half-word swap memory block D" "Not swapped,Swapped" newline bitfld.long 0x00 10. " [2] ,RTIC half-word swap memory block C" "Not swapped,Swapped" bitfld.long 0x00 9. " [1] ,RTIC half-word swap memory block B" "Not swapped,Swapped" newline bitfld.long 0x00 8. " [0] ,RTIC half-word swap memory block A" "Not swapped,Swapped" bitfld.long 0x00 7. " RBS[3] ,RTIC byte swap for memory block D" "Not swapped,Swapped" newline bitfld.long 0x00 6. " [2] ,RTIC byte swap for memory block C" "Not swapped,Swapped" bitfld.long 0x00 5. " [1] ,RTIC byte swap for memory block B" "Not swapped,Swapped" newline bitfld.long 0x00 4. " [0] ,RTIC byte swap for memory block A" "Not swapped,Swapped" bitfld.long 0x00 3. " REPO[3] ,RTIC endian platform override for memory block D" "Not swapped,Swapped" newline bitfld.long 0x00 2. " [2] ,RTIC endian platform override for memory block C" "Not swapped,Swapped" bitfld.long 0x00 1. " [1] ,RTIC endian platform override for memory block B" "Not swapped,Swapped" newline bitfld.long 0x00 0. " [0] ,RTIC endian platform override for memory block A" "Not swapped,Swapped" tree "RTIC Memory block Registers" group.quad 0x60100++0x07 line.quad 0x00 "RMAA0,RTIC Memory Block A Address 0 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60100+0x0C)++0x03 line.long 0x00 "RMAL0,RTIC Memory Block A Length 0 Register" group.quad 0x60110++0x07 line.quad 0x00 "RMAA1,RTIC Memory Block A Address 1 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60110+0x0C)++0x03 line.long 0x00 "RMAL1,RTIC Memory Block A Length 1 Register" group.quad 0x60120++0x07 line.quad 0x00 "RMBA0,RTIC Memory Block B Address 0 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60120+0x0C)++0x03 line.long 0x00 "RMBL0,RTIC Memory Block B Length 0 Register" group.quad 0x60130++0x07 line.quad 0x00 "RMBA1,RTIC Memory Block B Address 1 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60130+0x0C)++0x03 line.long 0x00 "RMBL1,RTIC Memory Block B Length 1 Register" group.quad 0x60140++0x07 line.quad 0x00 "RMCA0,RTIC Memory Block C Address 0 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60140+0x0C)++0x03 line.long 0x00 "RMCL0,RTIC Memory Block C Length 0 Register" group.quad 0x60150++0x07 line.quad 0x00 "RMCA1,RTIC Memory Block C Address 1 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60150+0x0C)++0x03 line.long 0x00 "RMCL1,RTIC Memory Block C Length 1 Register" group.quad 0x60160++0x07 line.quad 0x00 "RMDA0,RTIC Memory Block D Address 0 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60160+0x0C)++0x03 line.long 0x00 "RMDL0,RTIC Memory Block D Length 0 Register" group.quad 0x60170++0x07 line.quad 0x00 "RMDA1,RTIC Memory Block D Address 1 Register" hexmask.quad 0x00 0.--39. 0x01 " MEMBLKADDR ,Memory block address" group.long (0x60170+0x0C)++0x03 line.long 0x00 "RMDL1,RTIC Memory Block D Length 1 Register" tree.end tree "Endian Format Registers" tree "Big Endian Format" group.long 0x60200++0x03 line.long 0x00 "RAMDB_0,RTIC Memory Block A Hash Result Big Endian Format Register 0" group.long 0x60204++0x03 line.long 0x00 "RAMDB_1,RTIC Memory Block A Hash Result Big Endian Format Register 1" group.long 0x60208++0x03 line.long 0x00 "RAMDB_2,RTIC Memory Block A Hash Result Big Endian Format Register 2" group.long 0x6020C++0x03 line.long 0x00 "RAMDB_3,RTIC Memory Block A Hash Result Big Endian Format Register 3" group.long 0x60210++0x03 line.long 0x00 "RAMDB_4,RTIC Memory Block A Hash Result Big Endian Format Register 4" group.long 0x60214++0x03 line.long 0x00 "RAMDB_5,RTIC Memory Block A Hash Result Big Endian Format Register 5" group.long 0x60218++0x03 line.long 0x00 "RAMDB_6,RTIC Memory Block A Hash Result Big Endian Format Register 6" group.long 0x6021C++0x03 line.long 0x00 "RAMDB_7,RTIC Memory Block A Hash Result Big Endian Format Register 7" group.long 0x60220++0x03 line.long 0x00 "RAMDB_8,RTIC Memory Block A Hash Result Big Endian Format Register 8" group.long 0x60224++0x03 line.long 0x00 "RAMDB_9,RTIC Memory Block A Hash Result Big Endian Format Register 9" group.long 0x60228++0x03 line.long 0x00 "RAMDB_10,RTIC Memory Block A Hash Result Big Endian Format Register 10" group.long 0x6022C++0x03 line.long 0x00 "RAMDB_11,RTIC Memory Block A Hash Result Big Endian Format Register 11" group.long 0x60230++0x03 line.long 0x00 "RAMDB_12,RTIC Memory Block A Hash Result Big Endian Format Register 12" group.long 0x60234++0x03 line.long 0x00 "RAMDB_13,RTIC Memory Block A Hash Result Big Endian Format Register 13" group.long 0x60238++0x03 line.long 0x00 "RAMDB_14,RTIC Memory Block A Hash Result Big Endian Format Register 14" group.long 0x6023C++0x03 line.long 0x00 "RAMDB_15,RTIC Memory Block A Hash Result Big Endian Format Register 15" group.long 0x60240++0x03 line.long 0x00 "RAMDB_16,RTIC Memory Block A Hash Result Big Endian Format Register 16" group.long 0x60244++0x03 line.long 0x00 "RAMDB_17,RTIC Memory Block A Hash Result Big Endian Format Register 17" group.long 0x60248++0x03 line.long 0x00 "RAMDB_18,RTIC Memory Block A Hash Result Big Endian Format Register 18" group.long 0x6024C++0x03 line.long 0x00 "RAMDB_19,RTIC Memory Block A Hash Result Big Endian Format Register 19" group.long 0x60250++0x03 line.long 0x00 "RAMDB_20,RTIC Memory Block A Hash Result Big Endian Format Register 20" group.long 0x60254++0x03 line.long 0x00 "RAMDB_21,RTIC Memory Block A Hash Result Big Endian Format Register 21" group.long 0x60258++0x03 line.long 0x00 "RAMDB_22,RTIC Memory Block A Hash Result Big Endian Format Register 22" group.long 0x6025C++0x03 line.long 0x00 "RAMDB_23,RTIC Memory Block A Hash Result Big Endian Format Register 23" group.long 0x60260++0x03 line.long 0x00 "RAMDB_24,RTIC Memory Block A Hash Result Big Endian Format Register 24" group.long 0x60264++0x03 line.long 0x00 "RAMDB_25,RTIC Memory Block A Hash Result Big Endian Format Register 25" group.long 0x60268++0x03 line.long 0x00 "RAMDB_26,RTIC Memory Block A Hash Result Big Endian Format Register 26" group.long 0x6026C++0x03 line.long 0x00 "RAMDB_27,RTIC Memory Block A Hash Result Big Endian Format Register 27" group.long 0x60270++0x03 line.long 0x00 "RAMDB_28,RTIC Memory Block A Hash Result Big Endian Format Register 28" group.long 0x60274++0x03 line.long 0x00 "RAMDB_29,RTIC Memory Block A Hash Result Big Endian Format Register 29" group.long 0x60278++0x03 line.long 0x00 "RAMDB_30,RTIC Memory Block A Hash Result Big Endian Format Register 30" group.long 0x6027C++0x03 line.long 0x00 "RAMDB_31,RTIC Memory Block A Hash Result Big Endian Format Register 31" group.long 0x60300++0x03 line.long 0x00 "RBMDB_0,RTIC Memory Block B Hash Result Big Endian Format Register 0" group.long 0x60304++0x03 line.long 0x00 "RBMDB_1,RTIC Memory Block B Hash Result Big Endian Format Register 1" group.long 0x60308++0x03 line.long 0x00 "RBMDB_2,RTIC Memory Block B Hash Result Big Endian Format Register 2" group.long 0x6030C++0x03 line.long 0x00 "RBMDB_3,RTIC Memory Block B Hash Result Big Endian Format Register 3" group.long 0x60310++0x03 line.long 0x00 "RBMDB_4,RTIC Memory Block B Hash Result Big Endian Format Register 4" group.long 0x60314++0x03 line.long 0x00 "RBMDB_5,RTIC Memory Block B Hash Result Big Endian Format Register 5" group.long 0x60318++0x03 line.long 0x00 "RBMDB_6,RTIC Memory Block B Hash Result Big Endian Format Register 6" group.long 0x6031C++0x03 line.long 0x00 "RBMDB_7,RTIC Memory Block B Hash Result Big Endian Format Register 7" group.long 0x60320++0x03 line.long 0x00 "RBMDB_8,RTIC Memory Block B Hash Result Big Endian Format Register 8" group.long 0x60324++0x03 line.long 0x00 "RBMDB_9,RTIC Memory Block B Hash Result Big Endian Format Register 9" group.long 0x60328++0x03 line.long 0x00 "RBMDB_10,RTIC Memory Block B Hash Result Big Endian Format Register 10" group.long 0x6032C++0x03 line.long 0x00 "RBMDB_11,RTIC Memory Block B Hash Result Big Endian Format Register 11" group.long 0x60330++0x03 line.long 0x00 "RBMDB_12,RTIC Memory Block B Hash Result Big Endian Format Register 12" group.long 0x60334++0x03 line.long 0x00 "RBMDB_13,RTIC Memory Block B Hash Result Big Endian Format Register 13" group.long 0x60338++0x03 line.long 0x00 "RBMDB_14,RTIC Memory Block B Hash Result Big Endian Format Register 14" group.long 0x6033C++0x03 line.long 0x00 "RBMDB_15,RTIC Memory Block B Hash Result Big Endian Format Register 15" group.long 0x60340++0x03 line.long 0x00 "RBMDB_16,RTIC Memory Block B Hash Result Big Endian Format Register 16" group.long 0x60344++0x03 line.long 0x00 "RBMDB_17,RTIC Memory Block B Hash Result Big Endian Format Register 17" group.long 0x60348++0x03 line.long 0x00 "RBMDB_18,RTIC Memory Block B Hash Result Big Endian Format Register 18" group.long 0x6034C++0x03 line.long 0x00 "RBMDB_19,RTIC Memory Block B Hash Result Big Endian Format Register 19" group.long 0x60350++0x03 line.long 0x00 "RBMDB_20,RTIC Memory Block B Hash Result Big Endian Format Register 20" group.long 0x60354++0x03 line.long 0x00 "RBMDB_21,RTIC Memory Block B Hash Result Big Endian Format Register 21" group.long 0x60358++0x03 line.long 0x00 "RBMDB_22,RTIC Memory Block B Hash Result Big Endian Format Register 22" group.long 0x6035C++0x03 line.long 0x00 "RBMDB_23,RTIC Memory Block B Hash Result Big Endian Format Register 23" group.long 0x60360++0x03 line.long 0x00 "RBMDB_24,RTIC Memory Block B Hash Result Big Endian Format Register 24" group.long 0x60364++0x03 line.long 0x00 "RBMDB_25,RTIC Memory Block B Hash Result Big Endian Format Register 25" group.long 0x60368++0x03 line.long 0x00 "RBMDB_26,RTIC Memory Block B Hash Result Big Endian Format Register 26" group.long 0x6036C++0x03 line.long 0x00 "RBMDB_27,RTIC Memory Block B Hash Result Big Endian Format Register 27" group.long 0x60370++0x03 line.long 0x00 "RBMDB_28,RTIC Memory Block B Hash Result Big Endian Format Register 28" group.long 0x60374++0x03 line.long 0x00 "RBMDB_29,RTIC Memory Block B Hash Result Big Endian Format Register 29" group.long 0x60378++0x03 line.long 0x00 "RBMDB_30,RTIC Memory Block B Hash Result Big Endian Format Register 30" group.long 0x6037C++0x03 line.long 0x00 "RBMDB_31,RTIC Memory Block B Hash Result Big Endian Format Register 31" group.long 0x60400++0x03 line.long 0x00 "RCMDB_0,RTIC Memory Block C Hash Result Big Endian Format Register 0" group.long 0x60404++0x03 line.long 0x00 "RCMDB_1,RTIC Memory Block C Hash Result Big Endian Format Register 1" group.long 0x60408++0x03 line.long 0x00 "RCMDB_2,RTIC Memory Block C Hash Result Big Endian Format Register 2" group.long 0x6040C++0x03 line.long 0x00 "RCMDB_3,RTIC Memory Block C Hash Result Big Endian Format Register 3" group.long 0x60410++0x03 line.long 0x00 "RCMDB_4,RTIC Memory Block C Hash Result Big Endian Format Register 4" group.long 0x60414++0x03 line.long 0x00 "RCMDB_5,RTIC Memory Block C Hash Result Big Endian Format Register 5" group.long 0x60418++0x03 line.long 0x00 "RCMDB_6,RTIC Memory Block C Hash Result Big Endian Format Register 6" group.long 0x6041C++0x03 line.long 0x00 "RCMDB_7,RTIC Memory Block C Hash Result Big Endian Format Register 7" group.long 0x60420++0x03 line.long 0x00 "RCMDB_8,RTIC Memory Block C Hash Result Big Endian Format Register 8" group.long 0x60424++0x03 line.long 0x00 "RCMDB_9,RTIC Memory Block C Hash Result Big Endian Format Register 9" group.long 0x60428++0x03 line.long 0x00 "RCMDB_10,RTIC Memory Block C Hash Result Big Endian Format Register 10" group.long 0x6042C++0x03 line.long 0x00 "RCMDB_11,RTIC Memory Block C Hash Result Big Endian Format Register 11" group.long 0x60430++0x03 line.long 0x00 "RCMDB_12,RTIC Memory Block C Hash Result Big Endian Format Register 12" group.long 0x60434++0x03 line.long 0x00 "RCMDB_13,RTIC Memory Block C Hash Result Big Endian Format Register 13" group.long 0x60438++0x03 line.long 0x00 "RCMDB_14,RTIC Memory Block C Hash Result Big Endian Format Register 14" group.long 0x6043C++0x03 line.long 0x00 "RCMDB_15,RTIC Memory Block C Hash Result Big Endian Format Register 15" group.long 0x60440++0x03 line.long 0x00 "RCMDB_16,RTIC Memory Block C Hash Result Big Endian Format Register 16" group.long 0x60444++0x03 line.long 0x00 "RCMDB_17,RTIC Memory Block C Hash Result Big Endian Format Register 17" group.long 0x60448++0x03 line.long 0x00 "RCMDB_18,RTIC Memory Block C Hash Result Big Endian Format Register 18" group.long 0x6044C++0x03 line.long 0x00 "RCMDB_19,RTIC Memory Block C Hash Result Big Endian Format Register 19" group.long 0x60450++0x03 line.long 0x00 "RCMDB_20,RTIC Memory Block C Hash Result Big Endian Format Register 20" group.long 0x60454++0x03 line.long 0x00 "RCMDB_21,RTIC Memory Block C Hash Result Big Endian Format Register 21" group.long 0x60458++0x03 line.long 0x00 "RCMDB_22,RTIC Memory Block C Hash Result Big Endian Format Register 22" group.long 0x6045C++0x03 line.long 0x00 "RCMDB_23,RTIC Memory Block C Hash Result Big Endian Format Register 23" group.long 0x60460++0x03 line.long 0x00 "RCMDB_24,RTIC Memory Block C Hash Result Big Endian Format Register 24" group.long 0x60464++0x03 line.long 0x00 "RCMDB_25,RTIC Memory Block C Hash Result Big Endian Format Register 25" group.long 0x60468++0x03 line.long 0x00 "RCMDB_26,RTIC Memory Block C Hash Result Big Endian Format Register 26" group.long 0x6046C++0x03 line.long 0x00 "RCMDB_27,RTIC Memory Block C Hash Result Big Endian Format Register 27" group.long 0x60470++0x03 line.long 0x00 "RCMDB_28,RTIC Memory Block C Hash Result Big Endian Format Register 28" group.long 0x60474++0x03 line.long 0x00 "RCMDB_29,RTIC Memory Block C Hash Result Big Endian Format Register 29" group.long 0x60478++0x03 line.long 0x00 "RCMDB_30,RTIC Memory Block C Hash Result Big Endian Format Register 30" group.long 0x6047C++0x03 line.long 0x00 "RCMDB_31,RTIC Memory Block C Hash Result Big Endian Format Register 31" group.long 0x60500++0x03 line.long 0x00 "RDMDB_0,RTIC Memory Block D Hash Result Big Endian Format Register 0" group.long 0x60504++0x03 line.long 0x00 "RDMDB_1,RTIC Memory Block D Hash Result Big Endian Format Register 1" group.long 0x60508++0x03 line.long 0x00 "RDMDB_2,RTIC Memory Block D Hash Result Big Endian Format Register 2" group.long 0x6050C++0x03 line.long 0x00 "RDMDB_3,RTIC Memory Block D Hash Result Big Endian Format Register 3" group.long 0x60510++0x03 line.long 0x00 "RDMDB_4,RTIC Memory Block D Hash Result Big Endian Format Register 4" group.long 0x60514++0x03 line.long 0x00 "RDMDB_5,RTIC Memory Block D Hash Result Big Endian Format Register 5" group.long 0x60518++0x03 line.long 0x00 "RDMDB_6,RTIC Memory Block D Hash Result Big Endian Format Register 6" group.long 0x6051C++0x03 line.long 0x00 "RDMDB_7,RTIC Memory Block D Hash Result Big Endian Format Register 7" group.long 0x60520++0x03 line.long 0x00 "RDMDB_8,RTIC Memory Block D Hash Result Big Endian Format Register 8" group.long 0x60524++0x03 line.long 0x00 "RDMDB_9,RTIC Memory Block D Hash Result Big Endian Format Register 9" group.long 0x60528++0x03 line.long 0x00 "RDMDB_10,RTIC Memory Block D Hash Result Big Endian Format Register 10" group.long 0x6052C++0x03 line.long 0x00 "RDMDB_11,RTIC Memory Block D Hash Result Big Endian Format Register 11" group.long 0x60530++0x03 line.long 0x00 "RDMDB_12,RTIC Memory Block D Hash Result Big Endian Format Register 12" group.long 0x60534++0x03 line.long 0x00 "RDMDB_13,RTIC Memory Block D Hash Result Big Endian Format Register 13" group.long 0x60538++0x03 line.long 0x00 "RDMDB_14,RTIC Memory Block D Hash Result Big Endian Format Register 14" group.long 0x6053C++0x03 line.long 0x00 "RDMDB_15,RTIC Memory Block D Hash Result Big Endian Format Register 15" group.long 0x60540++0x03 line.long 0x00 "RDMDB_16,RTIC Memory Block D Hash Result Big Endian Format Register 16" group.long 0x60544++0x03 line.long 0x00 "RDMDB_17,RTIC Memory Block D Hash Result Big Endian Format Register 17" group.long 0x60548++0x03 line.long 0x00 "RDMDB_18,RTIC Memory Block D Hash Result Big Endian Format Register 18" group.long 0x6054C++0x03 line.long 0x00 "RDMDB_19,RTIC Memory Block D Hash Result Big Endian Format Register 19" group.long 0x60550++0x03 line.long 0x00 "RDMDB_20,RTIC Memory Block D Hash Result Big Endian Format Register 20" group.long 0x60554++0x03 line.long 0x00 "RDMDB_21,RTIC Memory Block D Hash Result Big Endian Format Register 21" group.long 0x60558++0x03 line.long 0x00 "RDMDB_22,RTIC Memory Block D Hash Result Big Endian Format Register 22" group.long 0x6055C++0x03 line.long 0x00 "RDMDB_23,RTIC Memory Block D Hash Result Big Endian Format Register 23" group.long 0x60560++0x03 line.long 0x00 "RDMDB_24,RTIC Memory Block D Hash Result Big Endian Format Register 24" group.long 0x60564++0x03 line.long 0x00 "RDMDB_25,RTIC Memory Block D Hash Result Big Endian Format Register 25" group.long 0x60568++0x03 line.long 0x00 "RDMDB_26,RTIC Memory Block D Hash Result Big Endian Format Register 26" group.long 0x6056C++0x03 line.long 0x00 "RDMDB_27,RTIC Memory Block D Hash Result Big Endian Format Register 27" group.long 0x60570++0x03 line.long 0x00 "RDMDB_28,RTIC Memory Block D Hash Result Big Endian Format Register 28" group.long 0x60574++0x03 line.long 0x00 "RDMDB_29,RTIC Memory Block D Hash Result Big Endian Format Register 29" group.long 0x60578++0x03 line.long 0x00 "RDMDB_30,RTIC Memory Block D Hash Result Big Endian Format Register 30" group.long 0x6057C++0x03 line.long 0x00 "RDMDB_31,RTIC Memory Block D Hash Result Big Endian Format Register 31" tree.end tree "Little Endian Format" group.long 0x60280++0x03 line.long 0x00 "RAMDL_0,RTIC Memory Block A Hash Result Little Endian Format Register 0" group.long 0x60284++0x03 line.long 0x00 "RAMDL_1,RTIC Memory Block A Hash Result Little Endian Format Register 1" group.long 0x60288++0x03 line.long 0x00 "RAMDL_2,RTIC Memory Block A Hash Result Little Endian Format Register 2" group.long 0x6028C++0x03 line.long 0x00 "RAMDL_3,RTIC Memory Block A Hash Result Little Endian Format Register 3" group.long 0x60290++0x03 line.long 0x00 "RAMDL_4,RTIC Memory Block A Hash Result Little Endian Format Register 4" group.long 0x60294++0x03 line.long 0x00 "RAMDL_5,RTIC Memory Block A Hash Result Little Endian Format Register 5" group.long 0x60298++0x03 line.long 0x00 "RAMDL_6,RTIC Memory Block A Hash Result Little Endian Format Register 6" group.long 0x6029C++0x03 line.long 0x00 "RAMDL_7,RTIC Memory Block A Hash Result Little Endian Format Register 7" group.long 0x602A0++0x03 line.long 0x00 "RAMDL_8,RTIC Memory Block A Hash Result Little Endian Format Register 8" group.long 0x602A4++0x03 line.long 0x00 "RAMDL_9,RTIC Memory Block A Hash Result Little Endian Format Register 9" group.long 0x602A8++0x03 line.long 0x00 "RAMDL_10,RTIC Memory Block A Hash Result Little Endian Format Register 10" group.long 0x602AC++0x03 line.long 0x00 "RAMDL_11,RTIC Memory Block A Hash Result Little Endian Format Register 11" group.long 0x602B0++0x03 line.long 0x00 "RAMDL_12,RTIC Memory Block A Hash Result Little Endian Format Register 12" group.long 0x602B4++0x03 line.long 0x00 "RAMDL_13,RTIC Memory Block A Hash Result Little Endian Format Register 13" group.long 0x602B8++0x03 line.long 0x00 "RAMDL_14,RTIC Memory Block A Hash Result Little Endian Format Register 14" group.long 0x602BC++0x03 line.long 0x00 "RAMDL_15,RTIC Memory Block A Hash Result Little Endian Format Register 15" group.long 0x602C0++0x03 line.long 0x00 "RAMDL_16,RTIC Memory Block A Hash Result Little Endian Format Register 16" group.long 0x602C4++0x03 line.long 0x00 "RAMDL_17,RTIC Memory Block A Hash Result Little Endian Format Register 17" group.long 0x602C8++0x03 line.long 0x00 "RAMDL_18,RTIC Memory Block A Hash Result Little Endian Format Register 18" group.long 0x602CC++0x03 line.long 0x00 "RAMDL_19,RTIC Memory Block A Hash Result Little Endian Format Register 19" group.long 0x602D0++0x03 line.long 0x00 "RAMDL_20,RTIC Memory Block A Hash Result Little Endian Format Register 20" group.long 0x602D4++0x03 line.long 0x00 "RAMDL_21,RTIC Memory Block A Hash Result Little Endian Format Register 21" group.long 0x602D8++0x03 line.long 0x00 "RAMDL_22,RTIC Memory Block A Hash Result Little Endian Format Register 22" group.long 0x602DC++0x03 line.long 0x00 "RAMDL_23,RTIC Memory Block A Hash Result Little Endian Format Register 23" group.long 0x602E0++0x03 line.long 0x00 "RAMDL_24,RTIC Memory Block A Hash Result Little Endian Format Register 24" group.long 0x602E4++0x03 line.long 0x00 "RAMDL_25,RTIC Memory Block A Hash Result Little Endian Format Register 25" group.long 0x602E8++0x03 line.long 0x00 "RAMDL_26,RTIC Memory Block A Hash Result Little Endian Format Register 26" group.long 0x602EC++0x03 line.long 0x00 "RAMDL_27,RTIC Memory Block A Hash Result Little Endian Format Register 27" group.long 0x602F0++0x03 line.long 0x00 "RAMDL_28,RTIC Memory Block A Hash Result Little Endian Format Register 28" group.long 0x602F4++0x03 line.long 0x00 "RAMDL_29,RTIC Memory Block A Hash Result Little Endian Format Register 29" group.long 0x602F8++0x03 line.long 0x00 "RAMDL_30,RTIC Memory Block A Hash Result Little Endian Format Register 30" group.long 0x602FC++0x03 line.long 0x00 "RAMDL_31,RTIC Memory Block A Hash Result Little Endian Format Register 31" group.long 0x60380++0x03 line.long 0x00 "RBMDL_0,RTIC Memory Block B Hash Result Little Endian Format Register 0" group.long 0x60384++0x03 line.long 0x00 "RBMDL_1,RTIC Memory Block B Hash Result Little Endian Format Register 1" group.long 0x60388++0x03 line.long 0x00 "RBMDL_2,RTIC Memory Block B Hash Result Little Endian Format Register 2" group.long 0x6038C++0x03 line.long 0x00 "RBMDL_3,RTIC Memory Block B Hash Result Little Endian Format Register 3" group.long 0x60390++0x03 line.long 0x00 "RBMDL_4,RTIC Memory Block B Hash Result Little Endian Format Register 4" group.long 0x60394++0x03 line.long 0x00 "RBMDL_5,RTIC Memory Block B Hash Result Little Endian Format Register 5" group.long 0x60398++0x03 line.long 0x00 "RBMDL_6,RTIC Memory Block B Hash Result Little Endian Format Register 6" group.long 0x6039C++0x03 line.long 0x00 "RBMDL_7,RTIC Memory Block B Hash Result Little Endian Format Register 7" group.long 0x603A0++0x03 line.long 0x00 "RBMDL_8,RTIC Memory Block B Hash Result Little Endian Format Register 8" group.long 0x603A4++0x03 line.long 0x00 "RBMDL_9,RTIC Memory Block B Hash Result Little Endian Format Register 9" group.long 0x603A8++0x03 line.long 0x00 "RBMDL_10,RTIC Memory Block B Hash Result Little Endian Format Register 10" group.long 0x603AC++0x03 line.long 0x00 "RBMDL_11,RTIC Memory Block B Hash Result Little Endian Format Register 11" group.long 0x603B0++0x03 line.long 0x00 "RBMDL_12,RTIC Memory Block B Hash Result Little Endian Format Register 12" group.long 0x603B4++0x03 line.long 0x00 "RBMDL_13,RTIC Memory Block B Hash Result Little Endian Format Register 13" group.long 0x603B8++0x03 line.long 0x00 "RBMDL_14,RTIC Memory Block B Hash Result Little Endian Format Register 14" group.long 0x603BC++0x03 line.long 0x00 "RBMDL_15,RTIC Memory Block B Hash Result Little Endian Format Register 15" group.long 0x603C0++0x03 line.long 0x00 "RBMDL_16,RTIC Memory Block B Hash Result Little Endian Format Register 16" group.long 0x603C4++0x03 line.long 0x00 "RBMDL_17,RTIC Memory Block B Hash Result Little Endian Format Register 17" group.long 0x603C8++0x03 line.long 0x00 "RBMDL_18,RTIC Memory Block B Hash Result Little Endian Format Register 18" group.long 0x603CC++0x03 line.long 0x00 "RBMDL_19,RTIC Memory Block B Hash Result Little Endian Format Register 19" group.long 0x603D0++0x03 line.long 0x00 "RBMDL_20,RTIC Memory Block B Hash Result Little Endian Format Register 20" group.long 0x603D4++0x03 line.long 0x00 "RBMDL_21,RTIC Memory Block B Hash Result Little Endian Format Register 21" group.long 0x603D8++0x03 line.long 0x00 "RBMDL_22,RTIC Memory Block B Hash Result Little Endian Format Register 22" group.long 0x603DC++0x03 line.long 0x00 "RBMDL_23,RTIC Memory Block B Hash Result Little Endian Format Register 23" group.long 0x603E0++0x03 line.long 0x00 "RBMDL_24,RTIC Memory Block B Hash Result Little Endian Format Register 24" group.long 0x603E4++0x03 line.long 0x00 "RBMDL_25,RTIC Memory Block B Hash Result Little Endian Format Register 25" group.long 0x603E8++0x03 line.long 0x00 "RBMDL_26,RTIC Memory Block B Hash Result Little Endian Format Register 26" group.long 0x603EC++0x03 line.long 0x00 "RBMDL_27,RTIC Memory Block B Hash Result Little Endian Format Register 27" group.long 0x603F0++0x03 line.long 0x00 "RBMDL_28,RTIC Memory Block B Hash Result Little Endian Format Register 28" group.long 0x603F4++0x03 line.long 0x00 "RBMDL_29,RTIC Memory Block B Hash Result Little Endian Format Register 29" group.long 0x603F8++0x03 line.long 0x00 "RBMDL_30,RTIC Memory Block B Hash Result Little Endian Format Register 30" group.long 0x603FC++0x03 line.long 0x00 "RBMDL_31,RTIC Memory Block B Hash Result Little Endian Format Register 31" group.long 0x60480++0x03 line.long 0x00 "RCMDL_0,RTIC Memory Block C Hash Result Little Endian Format Register 0" group.long 0x60484++0x03 line.long 0x00 "RCMDL_1,RTIC Memory Block C Hash Result Little Endian Format Register 1" group.long 0x60488++0x03 line.long 0x00 "RCMDL_2,RTIC Memory Block C Hash Result Little Endian Format Register 2" group.long 0x6048C++0x03 line.long 0x00 "RCMDL_3,RTIC Memory Block C Hash Result Little Endian Format Register 3" group.long 0x60490++0x03 line.long 0x00 "RCMDL_4,RTIC Memory Block C Hash Result Little Endian Format Register 4" group.long 0x60494++0x03 line.long 0x00 "RCMDL_5,RTIC Memory Block C Hash Result Little Endian Format Register 5" group.long 0x60498++0x03 line.long 0x00 "RCMDL_6,RTIC Memory Block C Hash Result Little Endian Format Register 6" group.long 0x6049C++0x03 line.long 0x00 "RCMDL_7,RTIC Memory Block C Hash Result Little Endian Format Register 7" group.long 0x604A0++0x03 line.long 0x00 "RCMDL_8,RTIC Memory Block C Hash Result Little Endian Format Register 8" group.long 0x604A4++0x03 line.long 0x00 "RCMDL_9,RTIC Memory Block C Hash Result Little Endian Format Register 9" group.long 0x604A8++0x03 line.long 0x00 "RCMDL_10,RTIC Memory Block C Hash Result Little Endian Format Register 10" group.long 0x604AC++0x03 line.long 0x00 "RCMDL_11,RTIC Memory Block C Hash Result Little Endian Format Register 11" group.long 0x604B0++0x03 line.long 0x00 "RCMDL_12,RTIC Memory Block C Hash Result Little Endian Format Register 12" group.long 0x604B4++0x03 line.long 0x00 "RCMDL_13,RTIC Memory Block C Hash Result Little Endian Format Register 13" group.long 0x604B8++0x03 line.long 0x00 "RCMDL_14,RTIC Memory Block C Hash Result Little Endian Format Register 14" group.long 0x604BC++0x03 line.long 0x00 "RCMDL_15,RTIC Memory Block C Hash Result Little Endian Format Register 15" group.long 0x604C0++0x03 line.long 0x00 "RCMDL_16,RTIC Memory Block C Hash Result Little Endian Format Register 16" group.long 0x604C4++0x03 line.long 0x00 "RCMDL_17,RTIC Memory Block C Hash Result Little Endian Format Register 17" group.long 0x604C8++0x03 line.long 0x00 "RCMDL_18,RTIC Memory Block C Hash Result Little Endian Format Register 18" group.long 0x604CC++0x03 line.long 0x00 "RCMDL_19,RTIC Memory Block C Hash Result Little Endian Format Register 19" group.long 0x604D0++0x03 line.long 0x00 "RCMDL_20,RTIC Memory Block C Hash Result Little Endian Format Register 20" group.long 0x604D4++0x03 line.long 0x00 "RCMDL_21,RTIC Memory Block C Hash Result Little Endian Format Register 21" group.long 0x604D8++0x03 line.long 0x00 "RCMDL_22,RTIC Memory Block C Hash Result Little Endian Format Register 22" group.long 0x604DC++0x03 line.long 0x00 "RCMDL_23,RTIC Memory Block C Hash Result Little Endian Format Register 23" group.long 0x604E0++0x03 line.long 0x00 "RCMDL_24,RTIC Memory Block C Hash Result Little Endian Format Register 24" group.long 0x604E4++0x03 line.long 0x00 "RCMDL_25,RTIC Memory Block C Hash Result Little Endian Format Register 25" group.long 0x604E8++0x03 line.long 0x00 "RCMDL_26,RTIC Memory Block C Hash Result Little Endian Format Register 26" group.long 0x604EC++0x03 line.long 0x00 "RCMDL_27,RTIC Memory Block C Hash Result Little Endian Format Register 27" group.long 0x604F0++0x03 line.long 0x00 "RCMDL_28,RTIC Memory Block C Hash Result Little Endian Format Register 28" group.long 0x604F4++0x03 line.long 0x00 "RCMDL_29,RTIC Memory Block C Hash Result Little Endian Format Register 29" group.long 0x604F8++0x03 line.long 0x00 "RCMDL_30,RTIC Memory Block C Hash Result Little Endian Format Register 30" group.long 0x604FC++0x03 line.long 0x00 "RCMDL_31,RTIC Memory Block C Hash Result Little Endian Format Register 31" group.long 0x60580++0x03 line.long 0x00 "RDMDL_0,RTIC Memory Block D Hash Result Little Endian Format Register 0" group.long 0x60584++0x03 line.long 0x00 "RDMDL_1,RTIC Memory Block D Hash Result Little Endian Format Register 1" group.long 0x60588++0x03 line.long 0x00 "RDMDL_2,RTIC Memory Block D Hash Result Little Endian Format Register 2" group.long 0x6058C++0x03 line.long 0x00 "RDMDL_3,RTIC Memory Block D Hash Result Little Endian Format Register 3" group.long 0x60590++0x03 line.long 0x00 "RDMDL_4,RTIC Memory Block D Hash Result Little Endian Format Register 4" group.long 0x60594++0x03 line.long 0x00 "RDMDL_5,RTIC Memory Block D Hash Result Little Endian Format Register 5" group.long 0x60598++0x03 line.long 0x00 "RDMDL_6,RTIC Memory Block D Hash Result Little Endian Format Register 6" group.long 0x6059C++0x03 line.long 0x00 "RDMDL_7,RTIC Memory Block D Hash Result Little Endian Format Register 7" group.long 0x605A0++0x03 line.long 0x00 "RDMDL_8,RTIC Memory Block D Hash Result Little Endian Format Register 8" group.long 0x605A4++0x03 line.long 0x00 "RDMDL_9,RTIC Memory Block D Hash Result Little Endian Format Register 9" group.long 0x605A8++0x03 line.long 0x00 "RDMDL_10,RTIC Memory Block D Hash Result Little Endian Format Register 10" group.long 0x605AC++0x03 line.long 0x00 "RDMDL_11,RTIC Memory Block D Hash Result Little Endian Format Register 11" group.long 0x605B0++0x03 line.long 0x00 "RDMDL_12,RTIC Memory Block D Hash Result Little Endian Format Register 12" group.long 0x605B4++0x03 line.long 0x00 "RDMDL_13,RTIC Memory Block D Hash Result Little Endian Format Register 13" group.long 0x605B8++0x03 line.long 0x00 "RDMDL_14,RTIC Memory Block D Hash Result Little Endian Format Register 14" group.long 0x605BC++0x03 line.long 0x00 "RDMDL_15,RTIC Memory Block D Hash Result Little Endian Format Register 15" group.long 0x605C0++0x03 line.long 0x00 "RDMDL_16,RTIC Memory Block D Hash Result Little Endian Format Register 16" group.long 0x605C4++0x03 line.long 0x00 "RDMDL_17,RTIC Memory Block D Hash Result Little Endian Format Register 17" group.long 0x605C8++0x03 line.long 0x00 "RDMDL_18,RTIC Memory Block D Hash Result Little Endian Format Register 18" group.long 0x605CC++0x03 line.long 0x00 "RDMDL_19,RTIC Memory Block D Hash Result Little Endian Format Register 19" group.long 0x605D0++0x03 line.long 0x00 "RDMDL_20,RTIC Memory Block D Hash Result Little Endian Format Register 20" group.long 0x605D4++0x03 line.long 0x00 "RDMDL_21,RTIC Memory Block D Hash Result Little Endian Format Register 21" group.long 0x605D8++0x03 line.long 0x00 "RDMDL_22,RTIC Memory Block D Hash Result Little Endian Format Register 22" group.long 0x605DC++0x03 line.long 0x00 "RDMDL_23,RTIC Memory Block D Hash Result Little Endian Format Register 23" group.long 0x605E0++0x03 line.long 0x00 "RDMDL_24,RTIC Memory Block D Hash Result Little Endian Format Register 24" group.long 0x605E4++0x03 line.long 0x00 "RDMDL_25,RTIC Memory Block D Hash Result Little Endian Format Register 25" group.long 0x605E8++0x03 line.long 0x00 "RDMDL_26,RTIC Memory Block D Hash Result Little Endian Format Register 26" group.long 0x605EC++0x03 line.long 0x00 "RDMDL_27,RTIC Memory Block D Hash Result Little Endian Format Register 27" group.long 0x605F0++0x03 line.long 0x00 "RDMDL_28,RTIC Memory Block D Hash Result Little Endian Format Register 28" group.long 0x605F4++0x03 line.long 0x00 "RDMDL_29,RTIC Memory Block D Hash Result Little Endian Format Register 29" group.long 0x605F8++0x03 line.long 0x00 "RDMDL_30,RTIC Memory Block D Hash Result Little Endian Format Register 30" group.long 0x605FC++0x03 line.long 0x00 "RDMDL_31,RTIC Memory Block D Hash Result Little Endian Format Register 31" tree.end tree.end newline rgroup.long 0x60E00++0x03 line.long 0x00 "REIR0RTIC,Recoverable Error Interrupt Record 0 For RTIC" bitfld.long 0x00 31. " MISS ,Second RTIC recoverable error occurrence" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,This field indicates the type of the recoverable error" ",Memory access,?..." rgroup.quad 0x60E08++0x07 line.quad 0x00 "REIR2RTIC,Recoverable Error Interrupt Record 2 For RTIC" rgroup.long 0x60E10++0x07 line.long 0x00 "REIR4RTIC,Recoverable Error Interrupt Record 4 For RTIC" bitfld.long 0x00 30.--31. " MIX ,Memory interface index associated" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response associated" "0,1,2,3" newline bitfld.long 0x00 23. " RWB ,Read or write" "0,1" bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--6. 1. " ICID ,ICID transaction attribute associated" line.long 0x04 "REIR5RTIC,Recoverable Error Interrupt Record 5 For RTIC" bitfld.long 0x04 24. " SAFE ,AXI transaction associated being a safe transaction" "0,1" bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction associated" "General,Job ring 0,Job ring 1,Job ring 2,Job ring 3,AIOP,Real-time,Queue,DECO0/CCB0,DECO1/CCB1,DECO2/CCB2,DECO3/CCB3,DECO4/CCB4,DECO5/CCB5,?..." newline tree.end newline width 12. tree "QI (queue manager interface) Registers" group.long 0x70000++0x07 line.long 0x00 "QICTL_MS,Queue Interface Control Register (Most Significant)" bitfld.long 0x00 18. " DWSO ,Double word swap override" "No override,Override" bitfld.long 0x00 17. " PEO ,Platform endianness override" "No override,Override" bitfld.long 0x00 16. " DMBS ,Descriptor message data byte swap" "Not swapped,Swapped" newline bitfld.long 0x00 15. " CDWSO ,Control data doubleword swap on output" "Not swapped,Swapped" bitfld.long 0x00 14. " CWSO ,Control data word swap on output" "Not swapped,Swapped" bitfld.long 0x00 13. " CHWSO ,Control data halfword swap on output" "Not swapped,Swapped" bitfld.long 0x00 12. " CBSO ,Control data byte swap on output" "Not swapped,Swapped" newline bitfld.long 0x00 11. " MDWSO ,Message double word swap for output data" "Not swapped,Swapped" bitfld.long 0x00 10. " MWSO ,Message word swap for output data" "Not swapped,Swapped" bitfld.long 0x00 9. " MHWSO ,Message half word swap for output data" "Not swapped,Swapped" bitfld.long 0x00 8. " MBSO ,Message byte swap for output data" "Not swapped,Swapped" newline bitfld.long 0x00 7. " CDWSI ,Control data doubleword swap on input" "Not swapped,Swapped" bitfld.long 0x00 6. " CWSI ,Control data word swap on input" "Not swapped,Swapped" bitfld.long 0x00 5. " CHWSI ,Control data halfword swap on input" "Not swapped,Swapped" bitfld.long 0x00 4. " CBSI ,Control data byte swap on input" "Not swapped,Swapped" newline bitfld.long 0x00 3. " MDWSI ,Message data double word swap on input" "Not swapped,Swapped" bitfld.long 0x00 2. " MWSI ,Message data word swap on input" "Not swapped,Swapped" bitfld.long 0x00 1. " MHWSI ,Message data half-word swap on input" "Not swapped,Swapped" bitfld.long 0x00 0. " MBSI ,Message data byte swap on input (PLEND XOR PEO==0/PLEND XOR PEO==1)" "Not swapped/Swapped,Swapped/Not swapped" line.long 0x04 "QICTL_LS,Queue Interface Control Register (Least-significant)" bitfld.long 0x04 16. " CROV ,Critical resource override" "No override,Override" bitfld.long 0x04 2. " SOE ,Stop on error" "Not stopped,Stopped" bitfld.long 0x04 1. " STOP ,Gracefully stop all operations" "Not stopped,Stopped" bitfld.long 0x04 0. " DQEN ,Dequeue enable" "Disabled,Enabled" group.long 0x7000C++0x1B line.long 0x00 "QISTA,Queue Interface Status Register" rbitfld.long 0x00 31. " STOPD ,Frame dequeue and enqueue operations and transfer of jobs stopped" "Not stopped,Stopped" newline eventfld.long 0x00 8. " TBTSERR ,Table buffer too small error" "No error,Error" eventfld.long 0x00 7. " TBPDERR ,Table buffer pool depletion error" "No error,Error" eventfld.long 0x00 6. " OFTLERR ,Output frame too large error" "No error,Error" newline eventfld.long 0x00 5. " CFWRERR ,Compound frame write error" "No error,Error" eventfld.long 0x00 4. " BTSERR ,Buffer too small error" "No error,Error" eventfld.long 0x00 3. " BPDERR ,Buffer pool depletion error" "No error,Error" newline eventfld.long 0x00 2. " OFWRERR ,Output frame write error" "No error,Error" eventfld.long 0x00 1. " CFRDERR ,Compound frame read error" "No error,Error" eventfld.long 0x00 0. " PHRDERR ,PreHeader read error" "No error,Error" line.long 0x04 "QIDQC_MS,Queue Interface Dequeue Configuration Register (Most Significant)" bitfld.long 0x04 24.--26. " SPFCNT ,Subportal frame count threshold" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. " BCNT ,Dequeue command byte count" line.long 0x08 "QIDQC_LS,Queue Interface Dequeue Configuration Register (Least Significant)" hexmask.long.tbyte 0x08 8.--31. 1. " SRC ,Dequeue command source" bitfld.long 0x08 4. " FCNT ,Dequeue command frame count" "1,Up to 3" bitfld.long 0x08 0.--3. " VERB ,Dequeue command verb" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "QIEQC_MS,Queue Interface Enqueue Configuration Register (Most Significant)" bitfld.long 0x0C 0.--1. " FC ,Enqueue command frame color" "0,1,2,3" line.long 0x10 "QIEQC_LS,Queue Interface Enqueue Configuration Register (Least Significant)" line.long 0x14 "QIIC_MS,Queue Interface ICID Configuration Register (Most Significant)" hexmask.long.word 0x14 16.--25. 1. " QNSIOM ,QI non-SEQ ICID mask" line.long 0x18 "QIIC_LS,Queue Interface ICID Configuration Register (Least Significant)" hexmask.long.word 0x18 16.--27. 1. " QNSICIDB ,QI non-SEQ ICID base" hexmask.long.word 0x18 0.--11. 1. " QSICIDB ,QI SEQ ICID base" rgroup.long 0x70100++0x03 line.long 0x00 "QIDESC0,Queue Interface Descriptor Word 0 Register" rgroup.long 0x70104++0x03 line.long 0x00 "QIDESC1,Queue Interface Descriptor Word 1 Register" rgroup.long 0x70108++0x03 line.long 0x00 "QIDESC2,Queue Interface Descriptor Word 2 Register" rgroup.long 0x7010C++0x03 line.long 0x00 "QIDESC3,Queue Interface Descriptor Word 3 Register" rgroup.long 0x70110++0x03 line.long 0x00 "QIDESC4,Queue Interface Descriptor Word 4 Register" rgroup.long 0x70114++0x03 line.long 0x00 "QIDESC5,Queue Interface Descriptor Word 5 Register" rgroup.long 0x70118++0x03 line.long 0x00 "QIDESC6,Queue Interface Descriptor Word 6 Register" rgroup.long 0x7011C++0x03 line.long 0x00 "QIDESC7,Queue Interface Descriptor Word 7 Register" rgroup.long 0x70120++0x03 line.long 0x00 "QIDESC8,Queue Interface Descriptor Word 8 Register" rgroup.long 0x70124++0x03 line.long 0x00 "QIDESC9,Queue Interface Descriptor Word 9 Register" rgroup.long 0x70128++0x03 line.long 0x00 "QIDESC10,Queue Interface Descriptor Word 10 Register" rgroup.long 0x7012C++0x03 line.long 0x00 "QIDESC11,Queue Interface Descriptor Word 11 Register" rgroup.long 0x70130++0x03 line.long 0x00 "QIDESC12,Queue Interface Descriptor Word 12 Register" rgroup.long 0x70210++0x1F line.long 0x00 "QICFOFH_MS,Output Frame High (Most Significant)" line.long 0x04 "QICFOFH_LS,Output Frame High (Least Significant)" line.long 0x08 "QICFOFL_MS,Output Frame Low (Most Significant)" line.long 0x0C "QICFOFL_LS,Output Frame Low (Least Significant)" line.long 0x10 "QICFIFH_MS,Input Frame High (Most Significant)" line.long 0x14 "QICFIFH_LS,Input Frame High (Least Significant)" line.long 0x18 "QICFIFL_MS,Input Frame Low (Most Significant)" line.long 0x1C "QICFIFL_LS,Input Frame Low (Least Significant)" newline rgroup.quad 0x70300++0x0F line.quad 0x00 "QIJIDVALID,Queue Interface Job ID Valid Register" bitfld.quad 0x00 15. " JID[15] ,Job ID 15 valid" "Not used,Used" bitfld.quad 0x00 14. " JID[14] ,Job ID 14 valid" "Not used,Used" bitfld.quad 0x00 13. " JID[13] ,Job ID 13 valid" "Not used,Used" bitfld.quad 0x00 12. " JID[12] ,Job ID 12 valid" "Not used,Used" newline bitfld.quad 0x00 11. " JID[11] ,Job ID 11 valid" "Not used,Used" bitfld.quad 0x00 10. " JID[10] ,Job ID 10 valid" "Not used,Used" bitfld.quad 0x00 9. " JID[9] ,Job ID 9 valid" "Not used,Used" bitfld.quad 0x00 8. " JID[8] ,Job ID 8 valid" "Not used,Used" newline bitfld.quad 0x00 7. " JID[7] ,Job ID 7 valid" "Not used,Used" bitfld.quad 0x00 6. " JID[6] ,Job ID 6 valid" "Not used,Used" bitfld.quad 0x00 5. " JID[5] ,Job ID 5 valid" "Not used,Used" bitfld.quad 0x00 4. " JID[4] ,Job ID 4 valid" "Not used,Used" newline bitfld.quad 0x00 3. " JID[3] ,Job ID 3 valid" "Not used,Used" bitfld.quad 0x00 2. " JID[2] ,Job ID 2 valid" "Not used,Used" bitfld.quad 0x00 1. " JID[1] ,Job ID 1 valid" "Not used,Used" line.quad 0x08 "QIJIDRDY,Queue Interface Job ID Job Ready Register" bitfld.quad 0x08 15. " JID[15] ,Job ID 15 valid" "Not ready,Ready" bitfld.quad 0x08 14. " JID[14] ,Job ID 14 valid" "Not ready,Ready" bitfld.quad 0x08 13. " JID[13] ,Job ID 13 valid" "Not ready,Ready" bitfld.quad 0x08 12. " JID[12] ,Job ID 12 valid" "Not ready,Ready" newline bitfld.quad 0x08 11. " JID[11] ,Job ID 11 valid" "Not ready,Ready" bitfld.quad 0x08 10. " JID[10] ,Job ID 10 valid" "Not ready,Ready" bitfld.quad 0x08 9. " JID[9] ,Job ID 9 valid" "Not ready,Ready" bitfld.quad 0x08 8. " JID[8] ,Job ID 8 valid" "Not ready,Ready" newline bitfld.quad 0x08 7. " JID[7] ,Job ID 7 valid" "Not ready,Ready" bitfld.quad 0x08 6. " JID[6] ,Job ID 6 valid" "Not ready,Ready" bitfld.quad 0x08 5. " JID[5] ,Job ID 5 valid" "Not ready,Ready" bitfld.quad 0x08 4. " JID[4] ,Job ID 4 valid" "Not ready,Ready" newline bitfld.quad 0x08 3. " JID[3] ,Job ID 3 valid" "Not ready,Ready" bitfld.quad 0x08 2. " JID[2] ,Job ID 2 valid" "Not ready,Ready" bitfld.quad 0x08 1. " JID[1] ,Job ID 1 valid" "Not ready,Ready" newline rgroup.long 0x70700++0x07 line.long 0x00 "REIR0QI,Recoverable Error Indication Record 0 For The QI" bitfld.long 0x00 31. " MISS ,Missed error status" "Not occurred,Occurred" bitfld.long 0x00 24.--25. " TYPE ,Type of the recoverable error" ",Memory access,?..." line.long 0x04 "REIR1QI,Recoverable Error Interrupt Record 1 For The QI" bitfld.long 0x04 15. " BDI ,BDI" "0,1" hexmask.long.word 0x04 0.--11. 1. " NONSEQ_ICID ,Non-SEquence ICID" newline rgroup.quad 0x70708++0x07 line.quad 0x00 "REIR2QI,Recoverable Error Interrupt Record 2 For The QI" newline rgroup.long 0x70710++0x07 line.long 0x00 "REIR4QI,Recoverable Error Interrupt Record 4 For The QI" bitfld.long 0x00 30.--31. " MIX ,Memory interface index" "0,1,2,3" bitfld.long 0x00 28.--29. " ERR ,AXI error response" "0,1,2,3" bitfld.long 0x00 23. " RWB ,Memory access read or write" "0,1" newline bitfld.long 0x00 20.--22. " AXPROT ,AXI protection transaction attribute" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. " AXCACHE ,AXI cache control transaction attribute" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ICID ,ICID transaction attribute associated" line.long 0x04 "REIR5QI,Recoverable Error Interrupt Record 5 For The QI" bitfld.long 0x04 24. " SAFE ,AXI transaction associated (either read-safe or write-safe)" "0,1" newline bitfld.long 0x04 16.--19. " BID ,Block identifier of the source of the AXI transaction associated" ",Job ring 0,,,Burst buffer,,,Queue interface,DECO0,DECO1,DECO2,?..." tree.end tree "CCB Mode Control And Status Registers" if (((per.l.be(ad:0x1700000+(0x80004+0x44)))&0xF000)==0x5000) group.long 0x80004++0x03 line.long 0x00 "C0C1MR_RNG,CCB 0 Class 1 Mode Register Format For RNG4" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" bitfld.long 0x00 12. " SK ,Secure key" "Disabled,Enabled" bitfld.long 0x00 11. " AI ,Additional input" "Not included,Included" newline bitfld.long 0x00 10. " PS ,Personalization string" "Not included,Included" bitfld.long 0x00 9. " OBP ,Odd byte parity" "Disabled,Enabled" bitfld.long 0x00 8. " NZB ,Non-zero bytes" "Disabled,Enabled" bitfld.long 0x00 4.--5. " SH ,State handle" "0,1,?..." newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Generate,Instantiate,Reseed,Uninstantiate" bitfld.long 0x00 1. " PR ,Prediction resistance" "0,1" bitfld.long 0x00 0. " TST ,Test mode request" "Not requested,Requested" elif (((per.l.be(ad:0x1700000+(0x80004+0x44)))&0xF000)==0x8000) if (((per.l.be(ad:0x1700000+0x80004))&0x3F)==0x01) group.long 0x80004++0x03 line.long 0x00 "C0C1MR_PK,CCB 0 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " ARAM ,A RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 18. " BRAM ,B RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 17. " ERAM ,E RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 16. " NRAM ,N RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 9. " QUADRANT_3 ,Quadrant 3" "Not selected,Selected" bitfld.long 0x00 8. " QUADRANT_2 ,Quadrant 2" "Not selected,Selected" newline bitfld.long 0x00 7. " QUADRANT_1 ,Quadrant 1" "Not selected,Selected" bitfld.long 0x00 6. " QUADRANT_0 ,Quadrant 0" "Not selected,Selected" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x80004))&0x3F)==(0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x0C||0x0E||0x0F||0x16||0x17||0x18||0x19||0x1A||0x1B||0x1D||0x1E||0x1F)) group.long 0x80004++0x03 line.long 0x00 "C0C1MR_PK,CCB 0 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " INM ,Inputs in montgomery form" "Normal,Montgomery" bitfld.long 0x00 18. " OUTM ,Outputs in montgomery form" "Normal,Montgomery" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" newline bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x80004))&0x3F)==(0x09||0x0A||0x0B||0x1C)) group.long 0x80004++0x03 line.long 0x00 "C0C1MR_PK,CCB 0 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 16. " R2 ,R2 mod N supplied as an input or calculated by routine" "Calculated,Input" newline bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x80004))&0x3F)==(0x10||0x11)) group.long 0x80004++0x03 line.long 0x00 "C0C1MR_PK,CCB 0 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17.--19. " SOURCE_REGISTER ,Source register" "A,B,,N,?..." bitfld.long 0x00 10.--11. 16. " DESTINATION_REGISTER ,Destination register" "A,B,E,N,?..." newline bitfld.long 0x00 8.--9. " SOURCE_SEGMENT ,Source segment" "0,1,2,3" newline bitfld.long 0x00 6.--7. " DESTINATION_SEGMENT ,Destination segment" "0,1,2,3" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." else group.long 0x80004++0x03 line.long 0x00 "C0C1MR_PK,CCB 0 Class 1 Mode Register Format For Public Key Algorithms" newline newline newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." endif else group.long 0x80004++0x03 line.long 0x00 "C0C1MR_NPK,CCB 0 Class 1 Mode Register Format For Non-Public Key Algorithms" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" newline hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" newline bitfld.long 0x00 1. " ICV_TEST ,ICV checking/test AES fault detection" "No,Yes" bitfld.long 0x00 0. " ENC ,Encryption or decryption" "Decrypt,Encrypt" endif group.long (0x80004+0x08)++0x03 line.long 0x00 "C0C1KSR,CCB 0 Class 1 Key Size Register" hexmask.long.byte 0x00 0.--6. 1. " C1KS ,Class 1 key size in bytes" newline group.quad (0x80004+0x0C)++0x07 line.quad 0x00 "C0C1DSR,CCB 0 Class 1 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 1 data size number of bits" "0,1,2,3,4,5,6,7" rbitfld.quad 0x00 32. " C1CY ,Class 1 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C1DS ,Class 1 data size" newline group.long (0x80004+0x18)++0x03 line.long 0x00 "C0C1ICVSR,CCB 0 Class 1 ICV Size Register" bitfld.long 0x00 0.--4. " C1ICVS ,Class 1 ICV size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long (0x80004+0x30)++0x03 line.long 0x00 "C0CCTRL,CCB 0 CHA Control Register" bitfld.long 0x00 27. " UB ,Unload the PKHA B memory" "No effect,Unload" bitfld.long 0x00 26. " UA ,Unload the PKHA A memory" "No effect,Unload" newline bitfld.long 0x00 24. " UN ,Unload the PKHA N memory" "No effect,Unload" bitfld.long 0x00 23. " UB3 ,Unload the public key B3 memory" "No effect,Unload" newline bitfld.long 0x00 22. " UB2 ,Unload the PKHA B2 memory" "No effect,Unload" bitfld.long 0x00 21. " UB1 ,Unload the PKHA B1 memory" "No effect,Unload" newline bitfld.long 0x00 20. " UB0 ,Unload the PKHA B0 memory" "No effect,Unload" bitfld.long 0x00 19. " UA3 ,Unload the PKHA A3 memory" "No effect,Unload" newline bitfld.long 0x00 18. " UA2 ,Unload the PKHA A2 memory" "No effect,Unload" bitfld.long 0x00 17. " UA1 ,Unload the PKHA A1 memory" "No effect,Unload" newline bitfld.long 0x00 16. " UA0 ,Unload the PKHA A0 memory" "No effect,Unload" bitfld.long 0x00 13. " AES_C2 ,Reset AES class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 12. " ZUCA ,Reset ZUCA authentication accelerator" "No effect,Reset" bitfld.long 0x00 11. " ZUCE ,Reset ZUCE encryption accelerator" "No effect,Reset" newline bitfld.long 0x00 10. " SNF9 ,Reset SNOW f9 block" "No effect,Reset" bitfld.long 0x00 9. " RNG ,Reset random number generator" "No effect,Reset" newline bitfld.long 0x00 8. " CRC ,Reset CRCA block" "No effect,Reset" bitfld.long 0x00 7. " MD ,Reset MDHA hashing block" "No effect,Reset" newline bitfld.long 0x00 6. " PK ,Reset PKHA block" "No effect,Reset" bitfld.long 0x00 5. " SNF8 ,Reset SNOW f8 block" "No effect,Reset" newline bitfld.long 0x00 4. " KAS ,Reset KFHA kasumi" "No effect,Reset" bitfld.long 0x00 2. " DES ,Reset DESA" "No effect,Reset" newline bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset" bitfld.long 0x00 0. " ALL ,Reset all internal CHAs" "No effect,Reset" group.long (0x80004+0x38)++0x03 line.long 0x00 "C0ICTL,CCB 0 Interrupt Control Register" eventfld.long 0x00 28. " ZAEI ,ZUCA error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 27. " ZEEI ,ZUCE error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 26. " S9EI ,SNOW-f9 error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 25. " RNEI ,RNG error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 24. " CEI ,CRC error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 23. " MEI ,Hashing error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 22. " PEI ,Public key error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 21. " S8EI ,SNOW-f8 error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 20. " KEI ,Kasumi error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 18. " DEI ,DES error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 17. " AEI ,AES error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 12. " ZADI ,ZUCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 11. " ZEDI ,ZUCE done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 10. " S9DI ,SNOW-f9 done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 9. " RNDI ,RNG done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 8. " CDI ,CRCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 7. " MDI ,MDHA hashing done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 6. " PDI ,PKHA public key done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 5. " S8DI ,SNOW-f8 done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 4. " KDI ,KFHA kasumi done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 2. " DDI ,DESA done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 1. " ADI ,AESA done interrupt occurrence" "Not occurred,Occurred" wgroup.long (0x80004+0x40)++0x03 line.long 0x00 "C0CWR,CCB 0 Clear Written Register" bitfld.long 0x00 31. " CIF ,Clear input FIFO (and NFIFO)" "No effect,Reset" bitfld.long 0x00 30. " COF ,Clear output FIFO" "No effect,Reset" newline bitfld.long 0x00 29. " C1RST ,Reset class 1 CHA" "No effect,Reset" bitfld.long 0x00 28. " C2RST ,Reset class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 27. " C1D ,Clear class 1 done interrupt" "No effect,Reset" bitfld.long 0x00 26. " C2D ,Clear class 2 done interrupt" "No effect,Reset" newline bitfld.long 0x00 25. " CDS ,Clear descriptor sharing signal" "No effect,Reset" bitfld.long 0x00 22. " C2K ,Clear the class 2 key register" "No effect,Reset" newline bitfld.long 0x00 21. " C2C ,Clear the class 2 context register" "No effect,Reset" bitfld.long 0x00 18. " C2DS ,Clear the class 2 data size registers" "No effect,Reset" newline bitfld.long 0x00 16. " C2M ,Clear the class 2 mode register" "No effect,Reset" bitfld.long 0x00 15. " CPKE ,Clear the PKHA A size register" "No effect,Reset" newline bitfld.long 0x00 14. " CPKN ,Clear the PKHA N size register" "No effect,Reset" bitfld.long 0x00 13. " CPKB ,Clear the PKHA B size register" "No effect,Reset" newline bitfld.long 0x00 12. " CPKA ,Clear the PKHA E size register" "No effect,Reset" bitfld.long 0x00 6. " C1K ,Clear the class 1 key register" "No effect,Reset" newline bitfld.long 0x00 5. " C1C ,Clear the class 1 context register" "No effect,Reset" bitfld.long 0x00 3. " C1ICV ,Clear the class 1 ICV size register" "No effect,Reset" newline bitfld.long 0x00 2. " C1DS ,Clear the class 1 data size register" "No effect,Reset" bitfld.long 0x00 0. " C1M ,Clear the class 1 mode register" "No effect,Reset" newline rgroup.long (0x80004+0x44)++0x07 line.long 0x00 "C0CSTA_MS,CCB 0 Status And Error Register (Most Significant)" bitfld.long 0x00 28.--31. " CL2 ,Class 2 algorithms" ",,,,MD5/SHA-[1/224/256/384/512[(/224)/(/256)]],,,,,CRC,SNOW f9,,ZUC authentication,?..." newline bitfld.long 0x00 16.--19. " ERRID2 ,Error ID 2" ",Mode,Data size,Key size,,,Data arrived out of sequence,,,,ICV check failed,Internal hardware failure,,,Invalid CHA combination,Invalid CHA" newline bitfld.long 0x00 12.--15. " CL1 ,Class 1 algorithms" ",AES,DES,,,RNG,SNOW,Kasumi,Public key,,,ZUC encryption,?..." newline bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,PKHA A memory size,PKHA B memory size,Data arrived out of sequence,PKHA divide by zero,PKHA modulus even,DES key parity,ICV check failed,Internal hardware failure,CCM AAD size,Class 1 CHA not reset,Invalid CHA combination,Invalid CHA" newline line.long 0x04 "C0CSTA_LS,CCB 0 Status And Error Register (Least-Significant)" bitfld.long 0x04 30. " PIZ ,Public key operation is zero" "No,Yes" bitfld.long 0x04 29. " GCD ,Greates common divisor is one" "No,Yes" newline bitfld.long 0x04 28. " PRM ,Public key is prime" "No,Yes" bitfld.long 0x04 21. " SEI ,Class 2 error interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 20. " PEI ,Class 1 error interrupt" "Not occurred,Occurred" bitfld.long 0x04 17. " SDI ,Class 2 done interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 16. " PDI ,Class 1 done interrupt" "Not occurred,Occurred" bitfld.long 0x04 12. " ZAB ,ZUCA block busy" "Idle,Busy" newline bitfld.long 0x04 11. " ZEB ,ZUCE block busy" "Idle,Busy" bitfld.long 0x04 10. " S9B ,SNOW f9 busy" "Idle,Busy" newline bitfld.long 0x04 9. " RNB ,RNG block busy" "Idle,Busy" bitfld.long 0x04 8. " CB ,CRC block busy" "Idle,Busy" newline bitfld.long 0x04 7. " MB ,MDHA busy" "Idle,Busy" bitfld.long 0x04 6. " PB ,PKHA busy" "Idle,Busy" newline bitfld.long 0x04 5. " S8B ,SNOW f8" "Idle,Busy" bitfld.long 0x04 4. " KB ,KFHA busy" "Idle,Busy" newline bitfld.long 0x04 2. " DB ,DESA busy" "Idle,Busy" bitfld.long 0x04 1. " AB ,AESA busy" "Idle,Busy" group.long (0x80004+0x58)++0x03 line.long 0x00 "C0AADSZR,CCB 0 AAD Size Register 0" bitfld.long 0x00 0.--3. " AASZ ,AAD size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x80004+0x60)++0x03 line.long 0x00 "C0C1IVSZR,Class 1 IV Size Register 0" bitfld.long 0x00 0.--3. " IVSZ ,IV size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x80004+0x80)++0x03 line.long 0x00 "C0PKASZR,PKHA A Size Register 0" hexmask.long.word 0x00 0.--9. 1. " PKASZ ,PKHA A memory key size in bytes" group.long (0x80004+0x88)++0x03 line.long 0x00 "C0PKBSZR,PKHA B Size Register 0" hexmask.long.word 0x00 0.--9. 1. " PKBSZ ,PKHA B memory key size in bytes" group.long (0x80004+0x90)++0x03 line.long 0x00 "C0PKNSZR,PKHA N Size Register 0" hexmask.long.word 0x00 0.--9. 1. " PKNSZ ,PKHA N memory key size in bytes" group.long (0x80004+0x98)++0x03 line.long 0x00 "C0PKESZR,PKHA E Size Register 0" hexmask.long.word 0x00 0.--9. 1. " PKESZ ,PKHA E memory key size in bytes" newline if (((per.l.be(ad:0x1700000+(0x90004+0x44)))&0xF000)==0x5000) group.long 0x90004++0x03 line.long 0x00 "C1C1MR_RNG,CCB 1 Class 1 Mode Register Format For RNG4" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" bitfld.long 0x00 12. " SK ,Secure key" "Disabled,Enabled" bitfld.long 0x00 11. " AI ,Additional input" "Not included,Included" newline bitfld.long 0x00 10. " PS ,Personalization string" "Not included,Included" bitfld.long 0x00 9. " OBP ,Odd byte parity" "Disabled,Enabled" bitfld.long 0x00 8. " NZB ,Non-zero bytes" "Disabled,Enabled" bitfld.long 0x00 4.--5. " SH ,State handle" "0,1,?..." newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Generate,Instantiate,Reseed,Uninstantiate" bitfld.long 0x00 1. " PR ,Prediction resistance" "0,1" bitfld.long 0x00 0. " TST ,Test mode request" "Not requested,Requested" elif (((per.l.be(ad:0x1700000+(0x90004+0x44)))&0xF000)==0x8000) if (((per.l.be(ad:0x1700000+0x90004))&0x3F)==0x01) group.long 0x90004++0x03 line.long 0x00 "C1C1MR_PK,CCB 1 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " ARAM ,A RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 18. " BRAM ,B RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 17. " ERAM ,E RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 16. " NRAM ,N RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 9. " QUADRANT_3 ,Quadrant 3" "Not selected,Selected" bitfld.long 0x00 8. " QUADRANT_2 ,Quadrant 2" "Not selected,Selected" newline bitfld.long 0x00 7. " QUADRANT_1 ,Quadrant 1" "Not selected,Selected" bitfld.long 0x00 6. " QUADRANT_0 ,Quadrant 0" "Not selected,Selected" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x90004))&0x3F)==(0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x0C||0x0E||0x0F||0x16||0x17||0x18||0x19||0x1A||0x1B||0x1D||0x1E||0x1F)) group.long 0x90004++0x03 line.long 0x00 "C1C1MR_PK,CCB 1 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " INM ,Inputs in montgomery form" "Normal,Montgomery" bitfld.long 0x00 18. " OUTM ,Outputs in montgomery form" "Normal,Montgomery" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" newline bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x90004))&0x3F)==(0x09||0x0A||0x0B||0x1C)) group.long 0x90004++0x03 line.long 0x00 "C1C1MR_PK,CCB 1 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 16. " R2 ,R2 mod N supplied as an input or calculated by routine" "Calculated,Input" newline bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0x90004))&0x3F)==(0x10||0x11)) group.long 0x90004++0x03 line.long 0x00 "C1C1MR_PK,CCB 1 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17.--19. " SOURCE_REGISTER ,Source register" "A,B,,N,?..." bitfld.long 0x00 10.--11. 16. " DESTINATION_REGISTER ,Destination register" "A,B,E,N,?..." newline bitfld.long 0x00 8.--9. " SOURCE_SEGMENT ,Source segment" "0,1,2,3" newline bitfld.long 0x00 6.--7. " DESTINATION_SEGMENT ,Destination segment" "0,1,2,3" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." else group.long 0x90004++0x03 line.long 0x00 "C1C1MR_PK,CCB 1 Class 1 Mode Register Format For Public Key Algorithms" newline newline newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." endif else group.long 0x90004++0x03 line.long 0x00 "C1C1MR_NPK,CCB 1 Class 1 Mode Register Format For Non-Public Key Algorithms" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" newline hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" newline bitfld.long 0x00 1. " ICV_TEST ,ICV checking/test AES fault detection" "No,Yes" bitfld.long 0x00 0. " ENC ,Encryption or decryption" "Decrypt,Encrypt" endif group.long (0x90004+0x08)++0x03 line.long 0x00 "C1C1KSR,CCB 1 Class 1 Key Size Register" hexmask.long.byte 0x00 0.--6. 1. " C1KS ,Class 1 key size in bytes" newline group.quad (0x90004+0x0C)++0x07 line.quad 0x00 "C1C1DSR,CCB 1 Class 1 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 1 data size number of bits" "0,1,2,3,4,5,6,7" rbitfld.quad 0x00 32. " C1CY ,Class 1 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C1DS ,Class 1 data size" newline group.long (0x90004+0x18)++0x03 line.long 0x00 "C1C1ICVSR,CCB 1 Class 1 ICV Size Register" bitfld.long 0x00 0.--4. " C1ICVS ,Class 1 ICV size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long (0x90004+0x30)++0x03 line.long 0x00 "C1CCTRL,CCB 1 CHA Control Register" bitfld.long 0x00 27. " UB ,Unload the PKHA B memory" "No effect,Unload" bitfld.long 0x00 26. " UA ,Unload the PKHA A memory" "No effect,Unload" newline bitfld.long 0x00 24. " UN ,Unload the PKHA N memory" "No effect,Unload" bitfld.long 0x00 23. " UB3 ,Unload the public key B3 memory" "No effect,Unload" newline bitfld.long 0x00 22. " UB2 ,Unload the PKHA B2 memory" "No effect,Unload" bitfld.long 0x00 21. " UB1 ,Unload the PKHA B1 memory" "No effect,Unload" newline bitfld.long 0x00 20. " UB0 ,Unload the PKHA B0 memory" "No effect,Unload" bitfld.long 0x00 19. " UA3 ,Unload the PKHA A3 memory" "No effect,Unload" newline bitfld.long 0x00 18. " UA2 ,Unload the PKHA A2 memory" "No effect,Unload" bitfld.long 0x00 17. " UA1 ,Unload the PKHA A1 memory" "No effect,Unload" newline bitfld.long 0x00 16. " UA0 ,Unload the PKHA A0 memory" "No effect,Unload" bitfld.long 0x00 13. " AES_C2 ,Reset AES class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 12. " ZUCA ,Reset ZUCA authentication accelerator" "No effect,Reset" bitfld.long 0x00 11. " ZUCE ,Reset ZUCE encryption accelerator" "No effect,Reset" newline bitfld.long 0x00 10. " SNF9 ,Reset SNOW f9 block" "No effect,Reset" bitfld.long 0x00 9. " RNG ,Reset random number generator" "No effect,Reset" newline bitfld.long 0x00 8. " CRC ,Reset CRCA block" "No effect,Reset" bitfld.long 0x00 7. " MD ,Reset MDHA hashing block" "No effect,Reset" newline bitfld.long 0x00 6. " PK ,Reset PKHA block" "No effect,Reset" bitfld.long 0x00 5. " SNF8 ,Reset SNOW f8 block" "No effect,Reset" newline bitfld.long 0x00 4. " KAS ,Reset KFHA kasumi" "No effect,Reset" bitfld.long 0x00 2. " DES ,Reset DESA" "No effect,Reset" newline bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset" bitfld.long 0x00 0. " ALL ,Reset all internal CHAs" "No effect,Reset" group.long (0x90004+0x38)++0x03 line.long 0x00 "C1ICTL,CCB 1 Interrupt Control Register" eventfld.long 0x00 28. " ZAEI ,ZUCA error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 27. " ZEEI ,ZUCE error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 26. " S9EI ,SNOW-f9 error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 25. " RNEI ,RNG error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 24. " CEI ,CRC error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 23. " MEI ,Hashing error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 22. " PEI ,Public key error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 21. " S8EI ,SNOW-f8 error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 20. " KEI ,Kasumi error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 18. " DEI ,DES error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 17. " AEI ,AES error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 12. " ZADI ,ZUCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 11. " ZEDI ,ZUCE done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 10. " S9DI ,SNOW-f9 done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 9. " RNDI ,RNG done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 8. " CDI ,CRCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 7. " MDI ,MDHA hashing done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 6. " PDI ,PKHA public key done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 5. " S8DI ,SNOW-f8 done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 4. " KDI ,KFHA kasumi done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 2. " DDI ,DESA done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 1. " ADI ,AESA done interrupt occurrence" "Not occurred,Occurred" wgroup.long (0x90004+0x40)++0x03 line.long 0x00 "C1CWR,CCB 1 Clear Written Register" bitfld.long 0x00 31. " CIF ,Clear input FIFO (and NFIFO)" "No effect,Reset" bitfld.long 0x00 30. " COF ,Clear output FIFO" "No effect,Reset" newline bitfld.long 0x00 29. " C1RST ,Reset class 1 CHA" "No effect,Reset" bitfld.long 0x00 28. " C2RST ,Reset class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 27. " C1D ,Clear class 1 done interrupt" "No effect,Reset" bitfld.long 0x00 26. " C2D ,Clear class 2 done interrupt" "No effect,Reset" newline bitfld.long 0x00 25. " CDS ,Clear descriptor sharing signal" "No effect,Reset" bitfld.long 0x00 22. " C2K ,Clear the class 2 key register" "No effect,Reset" newline bitfld.long 0x00 21. " C2C ,Clear the class 2 context register" "No effect,Reset" bitfld.long 0x00 18. " C2DS ,Clear the class 2 data size registers" "No effect,Reset" newline bitfld.long 0x00 16. " C2M ,Clear the class 2 mode register" "No effect,Reset" bitfld.long 0x00 15. " CPKE ,Clear the PKHA A size register" "No effect,Reset" newline bitfld.long 0x00 14. " CPKN ,Clear the PKHA N size register" "No effect,Reset" bitfld.long 0x00 13. " CPKB ,Clear the PKHA B size register" "No effect,Reset" newline bitfld.long 0x00 12. " CPKA ,Clear the PKHA E size register" "No effect,Reset" bitfld.long 0x00 6. " C1K ,Clear the class 1 key register" "No effect,Reset" newline bitfld.long 0x00 5. " C1C ,Clear the class 1 context register" "No effect,Reset" bitfld.long 0x00 3. " C1ICV ,Clear the class 1 ICV size register" "No effect,Reset" newline bitfld.long 0x00 2. " C1DS ,Clear the class 1 data size register" "No effect,Reset" bitfld.long 0x00 0. " C1M ,Clear the class 1 mode register" "No effect,Reset" newline rgroup.long (0x90004+0x44)++0x07 line.long 0x00 "C1CSTA_MS,CCB 1 Status And Error Register (Most Significant)" bitfld.long 0x00 28.--31. " CL2 ,Class 2 algorithms" ",,,,MD5/SHA-[1/224/256/384/512[(/224)/(/256)]],,,,,CRC,SNOW f9,,ZUC authentication,?..." newline bitfld.long 0x00 16.--19. " ERRID2 ,Error ID 2" ",Mode,Data size,Key size,,,Data arrived out of sequence,,,,ICV check failed,Internal hardware failure,,,Invalid CHA combination,Invalid CHA" newline bitfld.long 0x00 12.--15. " CL1 ,Class 1 algorithms" ",AES,DES,,,RNG,SNOW,Kasumi,Public key,,,ZUC encryption,?..." newline bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,PKHA A memory size,PKHA B memory size,Data arrived out of sequence,PKHA divide by zero,PKHA modulus even,DES key parity,ICV check failed,Internal hardware failure,CCM AAD size,Class 1 CHA not reset,Invalid CHA combination,Invalid CHA" newline line.long 0x04 "C1CSTA_LS,CCB 1 Status And Error Register (Least-Significant)" bitfld.long 0x04 30. " PIZ ,Public key operation is zero" "No,Yes" bitfld.long 0x04 29. " GCD ,Greates common divisor is one" "No,Yes" newline bitfld.long 0x04 28. " PRM ,Public key is prime" "No,Yes" bitfld.long 0x04 21. " SEI ,Class 2 error interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 20. " PEI ,Class 1 error interrupt" "Not occurred,Occurred" bitfld.long 0x04 17. " SDI ,Class 2 done interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 16. " PDI ,Class 1 done interrupt" "Not occurred,Occurred" bitfld.long 0x04 12. " ZAB ,ZUCA block busy" "Idle,Busy" newline bitfld.long 0x04 11. " ZEB ,ZUCE block busy" "Idle,Busy" bitfld.long 0x04 10. " S9B ,SNOW f9 busy" "Idle,Busy" newline bitfld.long 0x04 9. " RNB ,RNG block busy" "Idle,Busy" bitfld.long 0x04 8. " CB ,CRC block busy" "Idle,Busy" newline bitfld.long 0x04 7. " MB ,MDHA busy" "Idle,Busy" bitfld.long 0x04 6. " PB ,PKHA busy" "Idle,Busy" newline bitfld.long 0x04 5. " S8B ,SNOW f8" "Idle,Busy" bitfld.long 0x04 4. " KB ,KFHA busy" "Idle,Busy" newline bitfld.long 0x04 2. " DB ,DESA busy" "Idle,Busy" bitfld.long 0x04 1. " AB ,AESA busy" "Idle,Busy" group.long (0x90004+0x58)++0x03 line.long 0x00 "C1AADSZR,CCB 1 AAD Size Register 1" bitfld.long 0x00 0.--3. " AASZ ,AAD size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90004+0x60)++0x03 line.long 0x00 "C1C1IVSZR,Class 1 IV Size Register 1" bitfld.long 0x00 0.--3. " IVSZ ,IV size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90004+0x80)++0x03 line.long 0x00 "C1PKASZR,PKHA A Size Register 1" hexmask.long.word 0x00 0.--9. 1. " PKASZ ,PKHA A memory key size in bytes" group.long (0x90004+0x88)++0x03 line.long 0x00 "C1PKBSZR,PKHA B Size Register 1" hexmask.long.word 0x00 0.--9. 1. " PKBSZ ,PKHA B memory key size in bytes" group.long (0x90004+0x90)++0x03 line.long 0x00 "C1PKNSZR,PKHA N Size Register 1" hexmask.long.word 0x00 0.--9. 1. " PKNSZ ,PKHA N memory key size in bytes" group.long (0x90004+0x98)++0x03 line.long 0x00 "C1PKESZR,PKHA E Size Register 1" hexmask.long.word 0x00 0.--9. 1. " PKESZ ,PKHA E memory key size in bytes" newline if (((per.l.be(ad:0x1700000+(0xA0004+0x44)))&0xF000)==0x5000) group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_RNG,CCB 2 Class 1 Mode Register Format For RNG4" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" bitfld.long 0x00 12. " SK ,Secure key" "Disabled,Enabled" bitfld.long 0x00 11. " AI ,Additional input" "Not included,Included" newline bitfld.long 0x00 10. " PS ,Personalization string" "Not included,Included" bitfld.long 0x00 9. " OBP ,Odd byte parity" "Disabled,Enabled" bitfld.long 0x00 8. " NZB ,Non-zero bytes" "Disabled,Enabled" bitfld.long 0x00 4.--5. " SH ,State handle" "0,1,?..." newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Generate,Instantiate,Reseed,Uninstantiate" bitfld.long 0x00 1. " PR ,Prediction resistance" "0,1" bitfld.long 0x00 0. " TST ,Test mode request" "Not requested,Requested" elif (((per.l.be(ad:0x1700000+(0xA0004+0x44)))&0xF000)==0x8000) if (((per.l.be(ad:0x1700000+0xA0004))&0x3F)==0x01) group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_PK,CCB 2 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " ARAM ,A RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 18. " BRAM ,B RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 17. " ERAM ,E RAM for zeroization" "Not selected,Selected" bitfld.long 0x00 16. " NRAM ,N RAM for zeroization" "Not selected,Selected" newline bitfld.long 0x00 9. " QUADRANT_3 ,Quadrant 3" "Not selected,Selected" bitfld.long 0x00 8. " QUADRANT_2 ,Quadrant 2" "Not selected,Selected" newline bitfld.long 0x00 7. " QUADRANT_1 ,Quadrant 1" "Not selected,Selected" bitfld.long 0x00 6. " QUADRANT_0 ,Quadrant 0" "Not selected,Selected" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0xA0004))&0x3F)==(0x02||0x03||0x04||0x05||0x06||0x07||0x08||0x0C||0x0E||0x0F||0x16||0x17||0x18||0x19||0x1A||0x1B||0x1D||0x1E||0x1F)) group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_PK,CCB 2 Class 1 Mode Register Format For Public Key Algorithms" bitfld.long 0x00 19. " INM ,Inputs in montgomery form" "Normal,Montgomery" bitfld.long 0x00 18. " OUTM ,Outputs in montgomery form" "Normal,Montgomery" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" newline bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0xA0004))&0x3F)==(0x09||0x0A||0x0B||0x1C)) group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_PK,CCB 2 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17. " F2M ,Integer or binary polynomial arithmetic" "Integer,Binary" bitfld.long 0x00 16. " R2 ,R2 mod N supplied as an input or calculated by routine" "Calculated,Input" newline bitfld.long 0x00 10. " TEQ ,Timing equalized" "Not selected,Selected" bitfld.long 0x00 8.--9. " OUTSEL ,Output destination select" "B,A,?..." newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." elif (((per.l.be(ad:0x1700000+0xA0004))&0x3F)==(0x10||0x11)) group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_PK,CCB 2 Class 1 Mode Register Format For Public Key Algorithms" newline bitfld.long 0x00 17.--19. " SOURCE_REGISTER ,Source register" "A,B,,N,?..." bitfld.long 0x00 10.--11. 16. " DESTINATION_REGISTER ,Destination register" "A,B,E,N,?..." newline bitfld.long 0x00 8.--9. " SOURCE_SEGMENT ,Source segment" "0,1,2,3" newline bitfld.long 0x00 6.--7. " DESTINATION_SEGMENT ,Destination segment" "0,1,2,3" newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." else group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_PK,CCB 2 Class 1 Mode Register Format For Public Key Algorithms" newline newline newline newline bitfld.long 0x00 0.--5. " FUNCTION ,Function" ",CLEAR_MEMORY,ADD,SUB 1,SUB 2,MUL,EXP,AMODN,INV,ECC_MOD_ADD,ECC_MOD_DBL,ECC_MOD_MUL,R2,,GCD,PRIME_TEST,CM_NSIZE,CM_SRC_SIZE,,,,,SML_EXP,SQRT,DBL_A,DBL_B,SQR,CUBE,ECC_MOD_CHECK_POINT,SHIFT_RIGHT,COMPARE,EVALUATE,?..." endif else group.long 0xA0004++0x03 line.long 0x00 "C2C1MR_NPK,CCB 2 Class 1 Mode Register Format For Non-Public Key Algorithms" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm selection" bitfld.long 0x00 13. " C2K ,Class 2 key" "Class 1,Class 2" newline hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" newline bitfld.long 0x00 1. " ICV_TEST ,ICV checking/test AES fault detection" "No,Yes" bitfld.long 0x00 0. " ENC ,Encryption or decryption" "Decrypt,Encrypt" endif group.long (0xA0004+0x08)++0x03 line.long 0x00 "C2C1KSR,CCB 2 Class 1 Key Size Register" hexmask.long.byte 0x00 0.--6. 1. " C1KS ,Class 1 key size in bytes" newline group.quad (0xA0004+0x0C)++0x07 line.quad 0x00 "C2C1DSR,CCB 2 Class 1 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 1 data size number of bits" "0,1,2,3,4,5,6,7" rbitfld.quad 0x00 32. " C1CY ,Class 1 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C1DS ,Class 1 data size" newline group.long (0xA0004+0x18)++0x03 line.long 0x00 "C2C1ICVSR,CCB 2 Class 1 ICV Size Register" bitfld.long 0x00 0.--4. " C1ICVS ,Class 1 ICV size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.long (0xA0004+0x30)++0x03 line.long 0x00 "C2CCTRL,CCB 2 CHA Control Register" bitfld.long 0x00 27. " UB ,Unload the PKHA B memory" "No effect,Unload" bitfld.long 0x00 26. " UA ,Unload the PKHA A memory" "No effect,Unload" newline bitfld.long 0x00 24. " UN ,Unload the PKHA N memory" "No effect,Unload" bitfld.long 0x00 23. " UB3 ,Unload the public key B3 memory" "No effect,Unload" newline bitfld.long 0x00 22. " UB2 ,Unload the PKHA B2 memory" "No effect,Unload" bitfld.long 0x00 21. " UB1 ,Unload the PKHA B1 memory" "No effect,Unload" newline bitfld.long 0x00 20. " UB0 ,Unload the PKHA B0 memory" "No effect,Unload" bitfld.long 0x00 19. " UA3 ,Unload the PKHA A3 memory" "No effect,Unload" newline bitfld.long 0x00 18. " UA2 ,Unload the PKHA A2 memory" "No effect,Unload" bitfld.long 0x00 17. " UA1 ,Unload the PKHA A1 memory" "No effect,Unload" newline bitfld.long 0x00 16. " UA0 ,Unload the PKHA A0 memory" "No effect,Unload" bitfld.long 0x00 13. " AES_C2 ,Reset AES class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 12. " ZUCA ,Reset ZUCA authentication accelerator" "No effect,Reset" bitfld.long 0x00 11. " ZUCE ,Reset ZUCE encryption accelerator" "No effect,Reset" newline bitfld.long 0x00 10. " SNF9 ,Reset SNOW f9 block" "No effect,Reset" bitfld.long 0x00 9. " RNG ,Reset random number generator" "No effect,Reset" newline bitfld.long 0x00 8. " CRC ,Reset CRCA block" "No effect,Reset" bitfld.long 0x00 7. " MD ,Reset MDHA hashing block" "No effect,Reset" newline bitfld.long 0x00 6. " PK ,Reset PKHA block" "No effect,Reset" bitfld.long 0x00 5. " SNF8 ,Reset SNOW f8 block" "No effect,Reset" newline bitfld.long 0x00 4. " KAS ,Reset KFHA kasumi" "No effect,Reset" bitfld.long 0x00 2. " DES ,Reset DESA" "No effect,Reset" newline bitfld.long 0x00 1. " AES ,Reset AESA" "No effect,Reset" bitfld.long 0x00 0. " ALL ,Reset all internal CHAs" "No effect,Reset" group.long (0xA0004+0x38)++0x03 line.long 0x00 "C2ICTL,CCB 2 Interrupt Control Register" eventfld.long 0x00 28. " ZAEI ,ZUCA error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 27. " ZEEI ,ZUCE error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 26. " S9EI ,SNOW-f9 error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 25. " RNEI ,RNG error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 24. " CEI ,CRC error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 23. " MEI ,Hashing error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 22. " PEI ,Public key error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 21. " S8EI ,SNOW-f8 error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 20. " KEI ,Kasumi error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 18. " DEI ,DES error interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 17. " AEI ,AES error interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 12. " ZADI ,ZUCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 11. " ZEDI ,ZUCE done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 10. " S9DI ,SNOW-f9 done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 9. " RNDI ,RNG done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 8. " CDI ,CRCA done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 7. " MDI ,MDHA hashing done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 6. " PDI ,PKHA public key done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 5. " S8DI ,SNOW-f8 done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 4. " KDI ,KFHA kasumi done interrupt occurrence" "Not occurred,Occurred" newline eventfld.long 0x00 2. " DDI ,DESA done interrupt occurrence" "Not occurred,Occurred" eventfld.long 0x00 1. " ADI ,AESA done interrupt occurrence" "Not occurred,Occurred" wgroup.long (0xA0004+0x40)++0x03 line.long 0x00 "C2CWR,CCB 2 Clear Written Register" bitfld.long 0x00 31. " CIF ,Clear input FIFO (and NFIFO)" "No effect,Reset" bitfld.long 0x00 30. " COF ,Clear output FIFO" "No effect,Reset" newline bitfld.long 0x00 29. " C1RST ,Reset class 1 CHA" "No effect,Reset" bitfld.long 0x00 28. " C2RST ,Reset class 2 CHA" "No effect,Reset" newline bitfld.long 0x00 27. " C1D ,Clear class 1 done interrupt" "No effect,Reset" bitfld.long 0x00 26. " C2D ,Clear class 2 done interrupt" "No effect,Reset" newline bitfld.long 0x00 25. " CDS ,Clear descriptor sharing signal" "No effect,Reset" bitfld.long 0x00 22. " C2K ,Clear the class 2 key register" "No effect,Reset" newline bitfld.long 0x00 21. " C2C ,Clear the class 2 context register" "No effect,Reset" bitfld.long 0x00 18. " C2DS ,Clear the class 2 data size registers" "No effect,Reset" newline bitfld.long 0x00 16. " C2M ,Clear the class 2 mode register" "No effect,Reset" bitfld.long 0x00 15. " CPKE ,Clear the PKHA A size register" "No effect,Reset" newline bitfld.long 0x00 14. " CPKN ,Clear the PKHA N size register" "No effect,Reset" bitfld.long 0x00 13. " CPKB ,Clear the PKHA B size register" "No effect,Reset" newline bitfld.long 0x00 12. " CPKA ,Clear the PKHA E size register" "No effect,Reset" bitfld.long 0x00 6. " C1K ,Clear the class 1 key register" "No effect,Reset" newline bitfld.long 0x00 5. " C1C ,Clear the class 1 context register" "No effect,Reset" bitfld.long 0x00 3. " C1ICV ,Clear the class 1 ICV size register" "No effect,Reset" newline bitfld.long 0x00 2. " C1DS ,Clear the class 1 data size register" "No effect,Reset" bitfld.long 0x00 0. " C1M ,Clear the class 1 mode register" "No effect,Reset" newline rgroup.long (0xA0004+0x44)++0x07 line.long 0x00 "C2CSTA_MS,CCB 2 Status And Error Register (Most Significant)" bitfld.long 0x00 28.--31. " CL2 ,Class 2 algorithms" ",,,,MD5/SHA-[1/224/256/384/512[(/224)/(/256)]],,,,,CRC,SNOW f9,,ZUC authentication,?..." newline bitfld.long 0x00 16.--19. " ERRID2 ,Error ID 2" ",Mode,Data size,Key size,,,Data arrived out of sequence,,,,ICV check failed,Internal hardware failure,,,Invalid CHA combination,Invalid CHA" newline bitfld.long 0x00 12.--15. " CL1 ,Class 1 algorithms" ",AES,DES,,,RNG,SNOW,Kasumi,Public key,,,ZUC encryption,?..." newline bitfld.long 0x00 0.--3. " ERRID1 ,Error ID 1" ",Mode,Data size,Key size,PKHA A memory size,PKHA B memory size,Data arrived out of sequence,PKHA divide by zero,PKHA modulus even,DES key parity,ICV check failed,Internal hardware failure,CCM AAD size,Class 1 CHA not reset,Invalid CHA combination,Invalid CHA" newline line.long 0x04 "C2CSTA_LS,CCB 2 Status And Error Register (Least-Significant)" bitfld.long 0x04 30. " PIZ ,Public key operation is zero" "No,Yes" bitfld.long 0x04 29. " GCD ,Greates common divisor is one" "No,Yes" newline bitfld.long 0x04 28. " PRM ,Public key is prime" "No,Yes" bitfld.long 0x04 21. " SEI ,Class 2 error interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 20. " PEI ,Class 1 error interrupt" "Not occurred,Occurred" bitfld.long 0x04 17. " SDI ,Class 2 done interrupt" "Not occurred,Occurred" newline bitfld.long 0x04 16. " PDI ,Class 1 done interrupt" "Not occurred,Occurred" bitfld.long 0x04 12. " ZAB ,ZUCA block busy" "Idle,Busy" newline bitfld.long 0x04 11. " ZEB ,ZUCE block busy" "Idle,Busy" bitfld.long 0x04 10. " S9B ,SNOW f9 busy" "Idle,Busy" newline bitfld.long 0x04 9. " RNB ,RNG block busy" "Idle,Busy" bitfld.long 0x04 8. " CB ,CRC block busy" "Idle,Busy" newline bitfld.long 0x04 7. " MB ,MDHA busy" "Idle,Busy" bitfld.long 0x04 6. " PB ,PKHA busy" "Idle,Busy" newline bitfld.long 0x04 5. " S8B ,SNOW f8" "Idle,Busy" bitfld.long 0x04 4. " KB ,KFHA busy" "Idle,Busy" newline bitfld.long 0x04 2. " DB ,DESA busy" "Idle,Busy" bitfld.long 0x04 1. " AB ,AESA busy" "Idle,Busy" group.long (0xA0004+0x58)++0x03 line.long 0x00 "C2AADSZR,CCB 2 AAD Size Register 2" bitfld.long 0x00 0.--3. " AASZ ,AAD size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA0004+0x60)++0x03 line.long 0x00 "C2C1IVSZR,Class 1 IV Size Register 2" bitfld.long 0x00 0.--3. " IVSZ ,IV size in bytes mod 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xA0004+0x80)++0x03 line.long 0x00 "C2PKASZR,PKHA A Size Register 2" hexmask.long.word 0x00 0.--9. 1. " PKASZ ,PKHA A memory key size in bytes" group.long (0xA0004+0x88)++0x03 line.long 0x00 "C2PKBSZR,PKHA B Size Register 2" hexmask.long.word 0x00 0.--9. 1. " PKBSZ ,PKHA B memory key size in bytes" group.long (0xA0004+0x90)++0x03 line.long 0x00 "C2PKNSZR,PKHA N Size Register 2" hexmask.long.word 0x00 0.--9. 1. " PKNSZ ,PKHA N memory key size in bytes" group.long (0xA0004+0x98)++0x03 line.long 0x00 "C2PKESZR,PKHA E Size Register 2" hexmask.long.word 0x00 0.--9. 1. " PKESZ ,PKHA E memory key size in bytes" newline tree.end tree "CCB Class 1 Context Registers" group.long 0x80100++0x3F line.long 0x00 "C0C1CTXR0,CCB 0 Class 1 Context Register Word 0" line.long 0x04 "C0C1CTXR1,CCB 0 Class 1 Context Register Word 1" line.long 0x08 "C0C1CTXR2,CCB 0 Class 1 Context Register Word 2" line.long 0x0C "C0C1CTXR3,CCB 0 Class 1 Context Register Word 3" line.long 0x10 "C0C1CTXR4,CCB 0 Class 1 Context Register Word 4" line.long 0x14 "C0C1CTXR5,CCB 0 Class 1 Context Register Word 5" line.long 0x18 "C0C1CTXR6,CCB 0 Class 1 Context Register Word 6" line.long 0x1C "C0C1CTXR7,CCB 0 Class 1 Context Register Word 7" line.long 0x20 "C0C1CTXR8,CCB 0 Class 1 Context Register Word 8" line.long 0x24 "C0C1CTXR9,CCB 0 Class 1 Context Register Word 9" line.long 0x28 "C0C1CTXR10,CCB 0 Class 1 Context Register Word 10" line.long 0x2C "C0C1CTXR11,CCB 0 Class 1 Context Register Word 11" line.long 0x30 "C0C1CTXR12,CCB 0 Class 1 Context Register Word 12" line.long 0x34 "C0C1CTXR13,CCB 0 Class 1 Context Register Word 13" line.long 0x38 "C0C1CTXR14,CCB 0 Class 1 Context Register Word 14" line.long 0x3C "C0C1CTXR15,CCB 0 Class 1 Context Register Word 15" group.long 0x90100++0x3F line.long 0x00 "C1C1CTXR0,CCB 1 Class 1 Context Register Word 0" line.long 0x04 "C1C1CTXR1,CCB 1 Class 1 Context Register Word 1" line.long 0x08 "C1C1CTXR2,CCB 1 Class 1 Context Register Word 2" line.long 0x0C "C1C1CTXR3,CCB 1 Class 1 Context Register Word 3" line.long 0x10 "C1C1CTXR4,CCB 1 Class 1 Context Register Word 4" line.long 0x14 "C1C1CTXR5,CCB 1 Class 1 Context Register Word 5" line.long 0x18 "C1C1CTXR6,CCB 1 Class 1 Context Register Word 6" line.long 0x1C "C1C1CTXR7,CCB 1 Class 1 Context Register Word 7" line.long 0x20 "C1C1CTXR8,CCB 1 Class 1 Context Register Word 8" line.long 0x24 "C1C1CTXR9,CCB 1 Class 1 Context Register Word 9" line.long 0x28 "C1C1CTXR10,CCB 1 Class 1 Context Register Word 10" line.long 0x2C "C1C1CTXR11,CCB 1 Class 1 Context Register Word 11" line.long 0x30 "C1C1CTXR12,CCB 1 Class 1 Context Register Word 12" line.long 0x34 "C1C1CTXR13,CCB 1 Class 1 Context Register Word 13" line.long 0x38 "C1C1CTXR14,CCB 1 Class 1 Context Register Word 14" line.long 0x3C "C1C1CTXR15,CCB 1 Class 1 Context Register Word 15" group.long 0xA0100++0x3F line.long 0x00 "C2C1CTXR0,CCB 2 Class 1 Context Register Word 0" line.long 0x04 "C2C1CTXR1,CCB 2 Class 1 Context Register Word 1" line.long 0x08 "C2C1CTXR2,CCB 2 Class 1 Context Register Word 2" line.long 0x0C "C2C1CTXR3,CCB 2 Class 1 Context Register Word 3" line.long 0x10 "C2C1CTXR4,CCB 2 Class 1 Context Register Word 4" line.long 0x14 "C2C1CTXR5,CCB 2 Class 1 Context Register Word 5" line.long 0x18 "C2C1CTXR6,CCB 2 Class 1 Context Register Word 6" line.long 0x1C "C2C1CTXR7,CCB 2 Class 1 Context Register Word 7" line.long 0x20 "C2C1CTXR8,CCB 2 Class 1 Context Register Word 8" line.long 0x24 "C2C1CTXR9,CCB 2 Class 1 Context Register Word 9" line.long 0x28 "C2C1CTXR10,CCB 2 Class 1 Context Register Word 10" line.long 0x2C "C2C1CTXR11,CCB 2 Class 1 Context Register Word 11" line.long 0x30 "C2C1CTXR12,CCB 2 Class 1 Context Register Word 12" line.long 0x34 "C2C1CTXR13,CCB 2 Class 1 Context Register Word 13" line.long 0x38 "C2C1CTXR14,CCB 2 Class 1 Context Register Word 14" line.long 0x3C "C2C1CTXR15,CCB 2 Class 1 Context Register Word 15" tree.end tree "CCB Class 1 Key Registers" group.long 0x80200++0x1F line.long 0x00 "C0C1KR0,CCB 0 Class 1 Key Register Word 0" line.long 0x04 "C0C1KR1,CCB 0 Class 1 Key Register Word 1" line.long 0x08 "C0C1KR2,CCB 0 Class 1 Key Register Word 2" line.long 0x0C "C0C1KR3,CCB 0 Class 1 Key Register Word 3" line.long 0x10 "C0C1KR4,CCB 0 Class 1 Key Register Word 4" line.long 0x14 "C0C1KR5,CCB 0 Class 1 Key Register Word 5" line.long 0x18 "C0C1KR6,CCB 0 Class 1 Key Register Word 6" line.long 0x1C "C0C1KR7,CCB 0 Class 1 Key Register Word 7" group.long 0x90200++0x1F line.long 0x00 "C1C1KR0,CCB 1 Class 1 Key Register Word 0" line.long 0x04 "C1C1KR1,CCB 1 Class 1 Key Register Word 1" line.long 0x08 "C1C1KR2,CCB 1 Class 1 Key Register Word 2" line.long 0x0C "C1C1KR3,CCB 1 Class 1 Key Register Word 3" line.long 0x10 "C1C1KR4,CCB 1 Class 1 Key Register Word 4" line.long 0x14 "C1C1KR5,CCB 1 Class 1 Key Register Word 5" line.long 0x18 "C1C1KR6,CCB 1 Class 1 Key Register Word 6" line.long 0x1C "C1C1KR7,CCB 1 Class 1 Key Register Word 7" group.long 0xA0200++0x1F line.long 0x00 "C2C1KR0,CCB 2 Class 1 Key Register Word 0" line.long 0x04 "C2C1KR1,CCB 2 Class 1 Key Register Word 1" line.long 0x08 "C2C1KR2,CCB 2 Class 1 Key Register Word 2" line.long 0x0C "C2C1KR3,CCB 2 Class 1 Key Register Word 3" line.long 0x10 "C2C1KR4,CCB 2 Class 1 Key Register Word 4" line.long 0x14 "C2C1KR5,CCB 2 Class 1 Key Register Word 5" line.long 0x18 "C2C1KR6,CCB 2 Class 1 Key Register Word 6" line.long 0x1C "C2C1KR7,CCB 2 Class 1 Key Register Word 7" tree.end tree "CCB Class 2 Mode And Size Registers" group.long 0x80404++0x03 line.long 0x00 "C0C2MR,CCB 0 Class 2 Mode Register" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm" hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" bitfld.long 0x00 1. " ICV ,ICV checking" "Not compared,Compared" newline bitfld.long 0x00 0. " AP ,Authenticate or protect" "Authenticated,Protected" group.long (0x80404+0x08)++0x03 line.long 0x00 "C0C2KSR,CCB 0 Class 2 Key Size Register" hexmask.long.byte 0x00 0.--7. 1. " C2KS ,Class 2 key size in bytes" group.quad (0x80404+0x0C)++0x07 line.quad 0x00 "C0C2DSR,CCB 0 Class 2 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 2 data size number of bits" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 32. " C2CY ,Class 2 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C2DS ,Class 2 data size" group.long (0x80404+0x18)++0x03 line.long 0x00 "C0C2ICVSZR,CCB 0 Class 2 ICV Size (mod 8) In Bytes" bitfld.long 0x00 0.--3. " ICVSZ ,Class 2 ICV size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90404++0x03 line.long 0x00 "C1C2MR,CCB 1 Class 2 Mode Register" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm" hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" bitfld.long 0x00 1. " ICV ,ICV checking" "Not compared,Compared" newline bitfld.long 0x00 0. " AP ,Authenticate or protect" "Authenticated,Protected" group.long (0x90404+0x08)++0x03 line.long 0x00 "C1C2KSR,CCB 1 Class 2 Key Size Register" hexmask.long.byte 0x00 0.--7. 1. " C2KS ,Class 2 key size in bytes" group.quad (0x90404+0x0C)++0x07 line.quad 0x00 "C1C2DSR,CCB 1 Class 2 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 2 data size number of bits" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 32. " C2CY ,Class 2 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C2DS ,Class 2 data size" group.long (0x90404+0x18)++0x03 line.long 0x00 "C1C2ICVSZR,CCB 1 Class 2 ICV Size (mod 8) In Bytes" bitfld.long 0x00 0.--3. " ICVSZ ,Class 2 ICV size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0404++0x03 line.long 0x00 "C2C2MR,CCB 2 Class 2 Mode Register" hexmask.long.byte 0x00 16.--23. 1. " ALG ,Algorithm" hexmask.long.word 0x00 4.--12. 1. " AAI ,Additional algorithm information" newline bitfld.long 0x00 2.--3. " AS ,Algorithm state" "Updated,Initialized,Finalized,Initialized/Finalized" bitfld.long 0x00 1. " ICV ,ICV checking" "Not compared,Compared" newline bitfld.long 0x00 0. " AP ,Authenticate or protect" "Authenticated,Protected" group.long (0xA0404+0x08)++0x03 line.long 0x00 "C2C2KSR,CCB 2 Class 2 Key Size Register" hexmask.long.byte 0x00 0.--7. 1. " C2KS ,Class 2 key size in bytes" group.quad (0xA0404+0x0C)++0x07 line.quad 0x00 "C2C2DSR,CCB 2 Class 2 Data Size Register" rbitfld.quad 0x00 61.--63. " NUMBITS ,Class 2 data size number of bits" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 32. " C2CY ,Class 2 data size carry" "No carry,Carry" newline hexmask.quad.long 0x00 0.--31. 1. " C2DS ,Class 2 data size" group.long (0xA0404+0x18)++0x03 line.long 0x00 "C2C2ICVSZR,CCB 2 Class 2 ICV Size (mod 8) In Bytes" bitfld.long 0x00 0.--3. " ICVSZ ,Class 2 ICV size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CCB Class 2 Context Registers" group.long 0x80500++0x47 line.long 0x00 "C0C2CTXR0,CCB 0 Class 2 Context Register Word 0" line.long 0x04 "C0C2CTXR1,CCB 0 Class 2 Context Register Word 1" line.long 0x08 "C0C2CTXR2,CCB 0 Class 2 Context Register Word 2" line.long 0x0C "C0C2CTXR3,CCB 0 Class 2 Context Register Word 3" line.long 0x10 "C0C2CTXR4,CCB 0 Class 2 Context Register Word 4" line.long 0x14 "C0C2CTXR5,CCB 0 Class 2 Context Register Word 5" line.long 0x18 "C0C2CTXR6,CCB 0 Class 2 Context Register Word 6" line.long 0x1C "C0C2CTXR7,CCB 0 Class 2 Context Register Word 7" line.long 0x20 "C0C2CTXR8,CCB 0 Class 2 Context Register Word 8" line.long 0x24 "C0C2CTXR9,CCB 0 Class 2 Context Register Word 9" line.long 0x28 "C0C2CTXR10,CCB 0 Class 2 Context Register Word 10" line.long 0x2C "C0C2CTXR11,CCB 0 Class 2 Context Register Word 11" line.long 0x30 "C0C2CTXR12,CCB 0 Class 2 Context Register Word 12" line.long 0x34 "C0C2CTXR13,CCB 0 Class 2 Context Register Word 13" line.long 0x38 "C0C2CTXR14,CCB 0 Class 2 Context Register Word 14" line.long 0x3C "C0C2CTXR15,CCB 0 Class 2 Context Register Word 15" line.long 0x40 "C0C2CTXR16,CCB 0 Class 2 Context Register Word 16" line.long 0x44 "C0C2CTXR17,CCB 0 Class 2 Context Register Word 17" group.long 0x90500++0x47 line.long 0x00 "C1C2CTXR0,CCB 1 Class 2 Context Register Word 0" line.long 0x04 "C1C2CTXR1,CCB 1 Class 2 Context Register Word 1" line.long 0x08 "C1C2CTXR2,CCB 1 Class 2 Context Register Word 2" line.long 0x0C "C1C2CTXR3,CCB 1 Class 2 Context Register Word 3" line.long 0x10 "C1C2CTXR4,CCB 1 Class 2 Context Register Word 4" line.long 0x14 "C1C2CTXR5,CCB 1 Class 2 Context Register Word 5" line.long 0x18 "C1C2CTXR6,CCB 1 Class 2 Context Register Word 6" line.long 0x1C "C1C2CTXR7,CCB 1 Class 2 Context Register Word 7" line.long 0x20 "C1C2CTXR8,CCB 1 Class 2 Context Register Word 8" line.long 0x24 "C1C2CTXR9,CCB 1 Class 2 Context Register Word 9" line.long 0x28 "C1C2CTXR10,CCB 1 Class 2 Context Register Word 10" line.long 0x2C "C1C2CTXR11,CCB 1 Class 2 Context Register Word 11" line.long 0x30 "C1C2CTXR12,CCB 1 Class 2 Context Register Word 12" line.long 0x34 "C1C2CTXR13,CCB 1 Class 2 Context Register Word 13" line.long 0x38 "C1C2CTXR14,CCB 1 Class 2 Context Register Word 14" line.long 0x3C "C1C2CTXR15,CCB 1 Class 2 Context Register Word 15" line.long 0x40 "C1C2CTXR16,CCB 1 Class 2 Context Register Word 16" line.long 0x44 "C1C2CTXR17,CCB 1 Class 2 Context Register Word 17" group.long 0xA0500++0x47 line.long 0x00 "C2C2CTXR0,CCB 2 Class 2 Context Register Word 0" line.long 0x04 "C2C2CTXR1,CCB 2 Class 2 Context Register Word 1" line.long 0x08 "C2C2CTXR2,CCB 2 Class 2 Context Register Word 2" line.long 0x0C "C2C2CTXR3,CCB 2 Class 2 Context Register Word 3" line.long 0x10 "C2C2CTXR4,CCB 2 Class 2 Context Register Word 4" line.long 0x14 "C2C2CTXR5,CCB 2 Class 2 Context Register Word 5" line.long 0x18 "C2C2CTXR6,CCB 2 Class 2 Context Register Word 6" line.long 0x1C "C2C2CTXR7,CCB 2 Class 2 Context Register Word 7" line.long 0x20 "C2C2CTXR8,CCB 2 Class 2 Context Register Word 8" line.long 0x24 "C2C2CTXR9,CCB 2 Class 2 Context Register Word 9" line.long 0x28 "C2C2CTXR10,CCB 2 Class 2 Context Register Word 10" line.long 0x2C "C2C2CTXR11,CCB 2 Class 2 Context Register Word 11" line.long 0x30 "C2C2CTXR12,CCB 2 Class 2 Context Register Word 12" line.long 0x34 "C2C2CTXR13,CCB 2 Class 2 Context Register Word 13" line.long 0x38 "C2C2CTXR14,CCB 2 Class 2 Context Register Word 14" line.long 0x3C "C2C2CTXR15,CCB 2 Class 2 Context Register Word 15" line.long 0x40 "C2C2CTXR16,CCB 2 Class 2 Context Register Word 16" line.long 0x44 "C2C2CTXR17,CCB 2 Class 2 Context Register Word 17" tree.end tree "CCB Class 2 Key Registers" group.long 0x80600++0x7F line.long 0x00 "C0C2KEYR0,CCB 0 Class 2 Key Register Word 0" line.long 0x04 "C0C2KEYR1,CCB 0 Class 2 Key Register Word 1" line.long 0x08 "C0C2KEYR2,CCB 0 Class 2 Key Register Word 2" line.long 0x0C "C0C2KEYR3,CCB 0 Class 2 Key Register Word 3" line.long 0x10 "C0C2KEYR4,CCB 0 Class 2 Key Register Word 4" line.long 0x14 "C0C2KEYR5,CCB 0 Class 2 Key Register Word 5" line.long 0x18 "C0C2KEYR6,CCB 0 Class 2 Key Register Word 6" line.long 0x1C "C0C2KEYR7,CCB 0 Class 2 Key Register Word 7" line.long 0x20 "C0C2KEYR8,CCB 0 Class 2 Key Register Word 8" line.long 0x24 "C0C2KEYR9,CCB 0 Class 2 Key Register Word 9" line.long 0x28 "C0C2KEYR10,CCB 0 Class 2 Key Register Word 10" line.long 0x2C "C0C2KEYR11,CCB 0 Class 2 Key Register Word 11" line.long 0x30 "C0C2KEYR12,CCB 0 Class 2 Key Register Word 12" line.long 0x34 "C0C2KEYR13,CCB 0 Class 2 Key Register Word 13" line.long 0x38 "C0C2KEYR14,CCB 0 Class 2 Key Register Word 14" line.long 0x3C "C0C2KEYR15,CCB 0 Class 2 Key Register Word 15" line.long 0x40 "C0C2KEYR16,CCB 0 Class 2 Key Register Word 16" line.long 0x44 "C0C2KEYR17,CCB 0 Class 2 Key Register Word 17" line.long 0x48 "C0C2KEYR18,CCB 0 Class 2 Key Register Word 18" line.long 0x4C "C0C2KEYR19,CCB 0 Class 2 Key Register Word 19" line.long 0x50 "C0C2KEYR20,CCB 0 Class 2 Key Register Word 20" line.long 0x54 "C0C2KEYR21,CCB 0 Class 2 Key Register Word 21" line.long 0x58 "C0C2KEYR22,CCB 0 Class 2 Key Register Word 22" line.long 0x5C "C0C2KEYR23,CCB 0 Class 2 Key Register Word 23" line.long 0x60 "C0C2KEYR24,CCB 0 Class 2 Key Register Word 24" line.long 0x64 "C0C2KEYR25,CCB 0 Class 2 Key Register Word 25" line.long 0x68 "C0C2KEYR26,CCB 0 Class 2 Key Register Word 26" line.long 0x6C "C0C2KEYR27,CCB 0 Class 2 Key Register Word 27" line.long 0x70 "C0C2KEYR28,CCB 0 Class 2 Key Register Word 28" line.long 0x74 "C0C2KEYR29,CCB 0 Class 2 Key Register Word 29" line.long 0x78 "C0C2KEYR30,CCB 0 Class 2 Key Register Word 30" line.long 0x7C "C0C2KEYR31,CCB 0 Class 2 Key Register Word 31" group.long 0x90600++0x7F line.long 0x00 "C1C2KEYR0,CCB 1 Class 2 Key Register Word 0" line.long 0x04 "C1C2KEYR1,CCB 1 Class 2 Key Register Word 1" line.long 0x08 "C1C2KEYR2,CCB 1 Class 2 Key Register Word 2" line.long 0x0C "C1C2KEYR3,CCB 1 Class 2 Key Register Word 3" line.long 0x10 "C1C2KEYR4,CCB 1 Class 2 Key Register Word 4" line.long 0x14 "C1C2KEYR5,CCB 1 Class 2 Key Register Word 5" line.long 0x18 "C1C2KEYR6,CCB 1 Class 2 Key Register Word 6" line.long 0x1C "C1C2KEYR7,CCB 1 Class 2 Key Register Word 7" line.long 0x20 "C1C2KEYR8,CCB 1 Class 2 Key Register Word 8" line.long 0x24 "C1C2KEYR9,CCB 1 Class 2 Key Register Word 9" line.long 0x28 "C1C2KEYR10,CCB 1 Class 2 Key Register Word 10" line.long 0x2C "C1C2KEYR11,CCB 1 Class 2 Key Register Word 11" line.long 0x30 "C1C2KEYR12,CCB 1 Class 2 Key Register Word 12" line.long 0x34 "C1C2KEYR13,CCB 1 Class 2 Key Register Word 13" line.long 0x38 "C1C2KEYR14,CCB 1 Class 2 Key Register Word 14" line.long 0x3C "C1C2KEYR15,CCB 1 Class 2 Key Register Word 15" line.long 0x40 "C1C2KEYR16,CCB 1 Class 2 Key Register Word 16" line.long 0x44 "C1C2KEYR17,CCB 1 Class 2 Key Register Word 17" line.long 0x48 "C1C2KEYR18,CCB 1 Class 2 Key Register Word 18" line.long 0x4C "C1C2KEYR19,CCB 1 Class 2 Key Register Word 19" line.long 0x50 "C1C2KEYR20,CCB 1 Class 2 Key Register Word 20" line.long 0x54 "C1C2KEYR21,CCB 1 Class 2 Key Register Word 21" line.long 0x58 "C1C2KEYR22,CCB 1 Class 2 Key Register Word 22" line.long 0x5C "C1C2KEYR23,CCB 1 Class 2 Key Register Word 23" line.long 0x60 "C1C2KEYR24,CCB 1 Class 2 Key Register Word 24" line.long 0x64 "C1C2KEYR25,CCB 1 Class 2 Key Register Word 25" line.long 0x68 "C1C2KEYR26,CCB 1 Class 2 Key Register Word 26" line.long 0x6C "C1C2KEYR27,CCB 1 Class 2 Key Register Word 27" line.long 0x70 "C1C2KEYR28,CCB 1 Class 2 Key Register Word 28" line.long 0x74 "C1C2KEYR29,CCB 1 Class 2 Key Register Word 29" line.long 0x78 "C1C2KEYR30,CCB 1 Class 2 Key Register Word 30" line.long 0x7C "C1C2KEYR31,CCB 1 Class 2 Key Register Word 31" group.long 0xA0600++0x7F line.long 0x00 "C2C2KEYR0,CCB 2 Class 2 Key Register Word 0" line.long 0x04 "C2C2KEYR1,CCB 2 Class 2 Key Register Word 1" line.long 0x08 "C2C2KEYR2,CCB 2 Class 2 Key Register Word 2" line.long 0x0C "C2C2KEYR3,CCB 2 Class 2 Key Register Word 3" line.long 0x10 "C2C2KEYR4,CCB 2 Class 2 Key Register Word 4" line.long 0x14 "C2C2KEYR5,CCB 2 Class 2 Key Register Word 5" line.long 0x18 "C2C2KEYR6,CCB 2 Class 2 Key Register Word 6" line.long 0x1C "C2C2KEYR7,CCB 2 Class 2 Key Register Word 7" line.long 0x20 "C2C2KEYR8,CCB 2 Class 2 Key Register Word 8" line.long 0x24 "C2C2KEYR9,CCB 2 Class 2 Key Register Word 9" line.long 0x28 "C2C2KEYR10,CCB 2 Class 2 Key Register Word 10" line.long 0x2C "C2C2KEYR11,CCB 2 Class 2 Key Register Word 11" line.long 0x30 "C2C2KEYR12,CCB 2 Class 2 Key Register Word 12" line.long 0x34 "C2C2KEYR13,CCB 2 Class 2 Key Register Word 13" line.long 0x38 "C2C2KEYR14,CCB 2 Class 2 Key Register Word 14" line.long 0x3C "C2C2KEYR15,CCB 2 Class 2 Key Register Word 15" line.long 0x40 "C2C2KEYR16,CCB 2 Class 2 Key Register Word 16" line.long 0x44 "C2C2KEYR17,CCB 2 Class 2 Key Register Word 17" line.long 0x48 "C2C2KEYR18,CCB 2 Class 2 Key Register Word 18" line.long 0x4C "C2C2KEYR19,CCB 2 Class 2 Key Register Word 19" line.long 0x50 "C2C2KEYR20,CCB 2 Class 2 Key Register Word 20" line.long 0x54 "C2C2KEYR21,CCB 2 Class 2 Key Register Word 21" line.long 0x58 "C2C2KEYR22,CCB 2 Class 2 Key Register Word 22" line.long 0x5C "C2C2KEYR23,CCB 2 Class 2 Key Register Word 23" line.long 0x60 "C2C2KEYR24,CCB 2 Class 2 Key Register Word 24" line.long 0x64 "C2C2KEYR25,CCB 2 Class 2 Key Register Word 25" line.long 0x68 "C2C2KEYR26,CCB 2 Class 2 Key Register Word 26" line.long 0x6C "C2C2KEYR27,CCB 2 Class 2 Key Register Word 27" line.long 0x70 "C2C2KEYR28,CCB 2 Class 2 Key Register Word 28" line.long 0x74 "C2C2KEYR29,CCB 2 Class 2 Key Register Word 29" line.long 0x78 "C2C2KEYR30,CCB 2 Class 2 Key Register Word 30" line.long 0x7C "C2C2KEYR31,CCB 2 Class 2 Key Register Word 31" tree.end tree "FIFO/DECO Registers" group.long 0x807C0++0x03 line.long 0x00 "C0FIFOSTA,CCB 0 FIFO Status" hexmask.long.byte 0x00 24.--31. 1. " C1IQHEAD ,Current head of the class 1 alignment block queue located within the input data FIFO" hexmask.long.byte 0x00 16.--23. 1. " C2IQHEAD ,Current head of the class 2 alignment block queue located within the input data FIFO" newline hexmask.long.byte 0x00 8.--15. 1. " DMAOQHEAD ,Current head of the DMA queue located within the output data FIFO" hexmask.long.byte 0x00 0.--7. 1. " DECOOQHEAD ,Current head of the DECO alignment block queue located within the output data FIFO" if (((per.l.be(ad:0x1700000+0x807C0+0x10))&0x3000000)==0x2000000) wgroup.long (0x807C0+0x10)++0x03 line.long 0x00 "C0NFIFO_2,CCB 0 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " PR ,Prediction resistance" "Disabled,Enabled" newline bitfld.long 0x00 11. " BM ,Boundary minus 1" "Disabled,Enabled" bitfld.long 0x00 10. " PS ,Pad snoop" "Disabled,Enabled" newline hexmask.long.byte 0x00 0.--6. 1. " PL ,Pad length" else wgroup.long (0x807C0+0x10)++0x03 line.long 0x00 "C0NFIFO,CCB 0 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both Classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " OC ,OFIFO continuation" "Disabled,Enabled" newline bitfld.long 0x00 14. " AST ,Additional source types" "0,1" hexmask.long.word 0x00 0.--11. 1. " DL ,Data length" endif wgroup.long (0x807C0+0x20)++0x03 line.long 0x00 "C0IFIFO,CCB 0 Input Data FIFO" newline hgroup.quad (0x807C0+0x30)++0x07 hide.quad 0x00 "C0OFIFO,CCB 0 Output Data FIFO" in newline group.long (0x807C0+0x40)++0x03 line.long 0x00 "D0JQCR_MS,DECO0 Job Queue Control Register (Most Significant)" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" newline bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" newline bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " SOB ,Shared descriptor or input frame burst" "Not passed,Passed" newline rbitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Not selected,Selected" newline rbitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,Queue interface,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x807C0+0x44)++0x03 line.long 0x00 "D0JQCR_LS,DECO0 Job Queue Control Register (Least Significant)" rgroup.quad (0x807C0+0x48)++0x07 line.quad 0x00 "D0DAR,DECO0 Descriptor Address Register" hexmask.quad 0x00 0.--39. 0x01 " DPTR ,Descriptor pointer" rgroup.long (0x807C0+0x50)++0x07 line.long 0x00 "D0OPSTA_MS,DECO0 Operation Status Register (Most Significant)" bitfld.long 0x00 28.--31. " STATUS_TYPE ,Status type" "No error,DMA error,CCB error,Jump halt user status,DECO error,,,Jump halt condition code,?..." bitfld.long 0x00 27. " NLJ ,Non-Local jump" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--14. 1. " COMMAND_INDEX ,Command index" hexmask.long.byte 0x00 0.--7. 1. " STATUS ,Error status" line.long 0x04 "D0OPSTA_LS,DECO0 Operation Status Register (Least Significant)" hexmask.long 0x04 0.--28. 1. " OUT_CT ,Output count" group.long (0x807C0+0x58)++0x03 line.long 0x00 "D0CKSUMR,DECO0 Checksum Register" hexmask.long.word 0x00 0.--15. 1. " CKSUM ,Checksum" group.long (0x807C0+0x60)++0x03 line.long 0x00 "D0SDIDSR,DECO0 SDID / Trusted ICID Status Register" rbitfld.long 0x00 31. " TZ ,TrustZone" "0,1" hexmask.long.word 0x00 16.--27. 1. " SDID ,Security domain identifier" newline hexmask.long.word 0x00 0.--11. 1. " DTICID ,DECO trusted ICID" group.long (0x807C0+0x60)++0x03 line.long 0x00 "D0ISR,DECO0 ICID Status Register" hexmask.long.word 0x00 16.--27. 1. " DNSICID ,DECO non-SEQ ICID" newline hexmask.long.word 0x00 0.--11. 1. " DSICID ,DECO SEQ ICID" group.long 0x907C0++0x03 line.long 0x00 "C1FIFOSTA,CCB 1 FIFO Status" hexmask.long.byte 0x00 24.--31. 1. " C1IQHEAD ,Current head of the class 1 alignment block queue located within the input data FIFO" hexmask.long.byte 0x00 16.--23. 1. " C2IQHEAD ,Current head of the class 2 alignment block queue located within the input data FIFO" newline hexmask.long.byte 0x00 8.--15. 1. " DMAOQHEAD ,Current head of the DMA queue located within the output data FIFO" hexmask.long.byte 0x00 0.--7. 1. " DECOOQHEAD ,Current head of the DECO alignment block queue located within the output data FIFO" if (((per.l.be(ad:0x1700000+0x907C0+0x10))&0x3000000)==0x2000000) wgroup.long (0x907C0+0x10)++0x03 line.long 0x00 "C1NFIFO_2,CCB 1 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " PR ,Prediction resistance" "Disabled,Enabled" newline bitfld.long 0x00 11. " BM ,Boundary minus 1" "Disabled,Enabled" bitfld.long 0x00 10. " PS ,Pad snoop" "Disabled,Enabled" newline hexmask.long.byte 0x00 0.--6. 1. " PL ,Pad length" else wgroup.long (0x907C0+0x10)++0x03 line.long 0x00 "C1NFIFO,CCB 1 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both Classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " OC ,OFIFO continuation" "Disabled,Enabled" newline bitfld.long 0x00 14. " AST ,Additional source types" "0,1" hexmask.long.word 0x00 0.--11. 1. " DL ,Data length" endif wgroup.long (0x907C0+0x20)++0x03 line.long 0x00 "C1IFIFO,CCB 1 Input Data FIFO" newline hgroup.quad (0x907C0+0x30)++0x07 hide.quad 0x00 "C1OFIFO,CCB 1 Output Data FIFO" in newline group.long (0x907C0+0x40)++0x03 line.long 0x00 "D1JQCR_MS,DECO1 Job Queue Control Register (Most Significant)" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" newline bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" newline bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " SOB ,Shared descriptor or input frame burst" "Not passed,Passed" newline rbitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Not selected,Selected" newline rbitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,Queue interface,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0x907C0+0x44)++0x03 line.long 0x00 "D1JQCR_LS,DECO1 Job Queue Control Register (Least Significant)" rgroup.quad (0x907C0+0x48)++0x07 line.quad 0x00 "D1DAR,DECO1 Descriptor Address Register" hexmask.quad 0x00 0.--39. 0x01 " DPTR ,Descriptor pointer" rgroup.long (0x907C0+0x50)++0x07 line.long 0x00 "D1OPSTA_MS,DECO1 Operation Status Register (Most Significant)" bitfld.long 0x00 28.--31. " STATUS_TYPE ,Status type" "No error,DMA error,CCB error,Jump halt user status,DECO error,,,Jump halt condition code,?..." bitfld.long 0x00 27. " NLJ ,Non-Local jump" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--14. 1. " COMMAND_INDEX ,Command index" hexmask.long.byte 0x00 0.--7. 1. " STATUS ,Error status" line.long 0x04 "D1OPSTA_LS,DECO1 Operation Status Register (Least Significant)" hexmask.long 0x04 0.--28. 1. " OUT_CT ,Output count" group.long (0x907C0+0x58)++0x03 line.long 0x00 "D1CKSUMR,DECO1 Checksum Register" hexmask.long.word 0x00 0.--15. 1. " CKSUM ,Checksum" group.long (0x907C0+0x60)++0x03 line.long 0x00 "D1SDIDSR,DECO1 SDID / Trusted ICID Status Register" rbitfld.long 0x00 31. " TZ ,TrustZone" "0,1" hexmask.long.word 0x00 16.--27. 1. " SDID ,Security domain identifier" newline hexmask.long.word 0x00 0.--11. 1. " DTICID ,DECO trusted ICID" group.long (0x907C0+0x60)++0x03 line.long 0x00 "D1ISR,DECO1 ICID Status Register" hexmask.long.word 0x00 16.--27. 1. " DNSICID ,DECO non-SEQ ICID" newline hexmask.long.word 0x00 0.--11. 1. " DSICID ,DECO SEQ ICID" group.long 0xA07C0++0x03 line.long 0x00 "C2FIFOSTA,CCB 2 FIFO Status" hexmask.long.byte 0x00 24.--31. 1. " C1IQHEAD ,Current head of the class 1 alignment block queue located within the input data FIFO" hexmask.long.byte 0x00 16.--23. 1. " C2IQHEAD ,Current head of the class 2 alignment block queue located within the input data FIFO" newline hexmask.long.byte 0x00 8.--15. 1. " DMAOQHEAD ,Current head of the DMA queue located within the output data FIFO" hexmask.long.byte 0x00 0.--7. 1. " DECOOQHEAD ,Current head of the DECO alignment block queue located within the output data FIFO" if (((per.l.be(ad:0x1700000+0xA07C0+0x10))&0x3000000)==0x2000000) wgroup.long (0xA07C0+0x10)++0x03 line.long 0x00 "C2NFIFO_2,CCB 2 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " PR ,Prediction resistance" "Disabled,Enabled" newline bitfld.long 0x00 11. " BM ,Boundary minus 1" "Disabled,Enabled" bitfld.long 0x00 10. " PS ,Pad snoop" "Disabled,Enabled" newline hexmask.long.byte 0x00 0.--6. 1. " PL ,Pad length" else wgroup.long (0xA07C0+0x10)++0x03 line.long 0x00 "C2NFIFO,CCB 2 INformation FIFO" bitfld.long 0x00 30.--31. " DEST ,Destination" "DECO alignment block,Class 1,Class 2,Both Classes" bitfld.long 0x00 29. " LC2 ,Last class 2" "Not last,Last" newline bitfld.long 0x00 28. " LC1 ,Last class 1" "Not last,Last" bitfld.long 0x00 27. " FC2 ,Flush class 2" "No flush,Flush" newline bitfld.long 0x00 26. " FC1 ,Flush class 1" "No flush,Flush" bitfld.long 0x00 24.--25. " STYPE ,Source type of the data for the alignment block (AST=0/AST=1)" "Input/Aux,Output/-,Padding block,Outsnooping" newline bitfld.long 0x00 20.--23. " DTYPE ,Data type [PKHA/Other CHAs]" "PKHA A0/-,PKHA A1/ADD,PKHA A2/IV,PKHA A3/SAD,PKHA B0/-,PKHA B1/-,PKHA B2/-,PKHA B3/-,PKHA N/-,PKHA E/-,-/ICV,,PKHA A/-,PKHA B/-,-/DECO ignore,-/Message data" bitfld.long 0x00 19. " BND ,Boundary padding" "Disabled,Enabled" newline bitfld.long 0x00 16.--18. " PTYPE ,Pad type" "All 0,Random non-0,Incremented,Random,All 0 + num,Random non-0 + 0,N-1,Random non-0 + N" bitfld.long 0x00 15. " OC ,OFIFO continuation" "Disabled,Enabled" newline bitfld.long 0x00 14. " AST ,Additional source types" "0,1" hexmask.long.word 0x00 0.--11. 1. " DL ,Data length" endif wgroup.long (0xA07C0+0x20)++0x03 line.long 0x00 "C2IFIFO,CCB 2 Input Data FIFO" newline hgroup.quad (0xA07C0+0x30)++0x07 hide.quad 0x00 "C2OFIFO,CCB 2 Output Data FIFO" in newline group.long (0xA07C0+0x40)++0x03 line.long 0x00 "D2JQCR_MS,DECO2 Job Queue Control Register (Most Significant)" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" newline bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" newline bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " SOB ,Shared descriptor or input frame burst" "Not passed,Passed" newline rbitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Not selected,Selected" newline rbitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,Queue interface,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long (0xA07C0+0x44)++0x03 line.long 0x00 "D2JQCR_LS,DECO2 Job Queue Control Register (Least Significant)" rgroup.quad (0xA07C0+0x48)++0x07 line.quad 0x00 "D2DAR,DECO2 Descriptor Address Register" hexmask.quad 0x00 0.--39. 0x01 " DPTR ,Descriptor pointer" rgroup.long (0xA07C0+0x50)++0x07 line.long 0x00 "D2OPSTA_MS,DECO2 Operation Status Register (Most Significant)" bitfld.long 0x00 28.--31. " STATUS_TYPE ,Status type" "No error,DMA error,CCB error,Jump halt user status,DECO error,,,Jump halt condition code,?..." bitfld.long 0x00 27. " NLJ ,Non-Local jump" "Not occurred,Occurred" newline hexmask.long.byte 0x00 8.--14. 1. " COMMAND_INDEX ,Command index" hexmask.long.byte 0x00 0.--7. 1. " STATUS ,Error status" line.long 0x04 "D2OPSTA_LS,DECO2 Operation Status Register (Least Significant)" hexmask.long 0x04 0.--28. 1. " OUT_CT ,Output count" group.long (0xA07C0+0x58)++0x03 line.long 0x00 "D2CKSUMR,DECO2 Checksum Register" hexmask.long.word 0x00 0.--15. 1. " CKSUM ,Checksum" group.long (0xA07C0+0x60)++0x03 line.long 0x00 "D2SDIDSR,DECO2 SDID / Trusted ICID Status Register" rbitfld.long 0x00 31. " TZ ,TrustZone" "0,1" hexmask.long.word 0x00 16.--27. 1. " SDID ,Security domain identifier" newline hexmask.long.word 0x00 0.--11. 1. " DTICID ,DECO trusted ICID" group.long (0xA07C0+0x60)++0x03 line.long 0x00 "D2ISR,DECO2 ICID Status Register" hexmask.long.word 0x00 16.--27. 1. " DNSICID ,DECO non-SEQ ICID" newline hexmask.long.word 0x00 0.--11. 1. " DSICID ,DECO SEQ ICID" tree.end tree "DECO Math Registers" tree "DECO0" group.long 0x80840++0x3F line.long 0x00 "D0MTH0_MS,DECO0 Math Register 0_MS" line.long 0x04 "D0MTH0_LS,DECO0 Math Register 0_LS" line.long 0x08 "D0MTH1_MS,DECO0 Math Register 1_MS" line.long 0x0C "D0MTH1_LS,DECO0 Math Register 1_LS" line.long 0x10 "D0MTH2_MS,DECO0 Math Register 2_MS" line.long 0x14 "D0MTH2_LS,DECO0 Math Register 2_LS" line.long 0x18 "D0MTH3_MS,DECO0 Math Register 3_MS" line.long 0x1C "D0MTH3_LS,DECO0 Math Register 3_LS" line.long 0x20 "D0MTH4_MS,DECO0 Math Register 4_MS" line.long 0x24 "D0MTH4_LS,DECO0 Math Register 4_LS" line.long 0x28 "D0MTH5_MS,DECO0 Math Register 5_MS" line.long 0x2C "D0MTH5_LS,DECO0 Math Register 5_LS" line.long 0x30 "D0MTH6_MS,DECO0 Math Register 6_MS" line.long 0x34 "D0MTH6_LS,DECO0 Math Register 6_LS" line.long 0x38 "D0MTH7_MS,DECO0 Math Register 7_MS" line.long 0x3C "D0MTH7_LS,DECO0 Math Register 7_LS" tree.end tree "DECO1" group.long 0x90840++0x3F line.long 0x00 "D1MTH0_MS,DECO1 Math Register 0_MS" line.long 0x04 "D1MTH0_LS,DECO1 Math Register 0_LS" line.long 0x08 "D1MTH1_MS,DECO1 Math Register 1_MS" line.long 0x0C "D1MTH1_LS,DECO1 Math Register 1_LS" line.long 0x10 "D1MTH2_MS,DECO1 Math Register 2_MS" line.long 0x14 "D1MTH2_LS,DECO1 Math Register 2_LS" line.long 0x18 "D1MTH3_MS,DECO1 Math Register 3_MS" line.long 0x1C "D1MTH3_LS,DECO1 Math Register 3_LS" line.long 0x20 "D1MTH4_MS,DECO1 Math Register 4_MS" line.long 0x24 "D1MTH4_LS,DECO1 Math Register 4_LS" line.long 0x28 "D1MTH5_MS,DECO1 Math Register 5_MS" line.long 0x2C "D1MTH5_LS,DECO1 Math Register 5_LS" line.long 0x30 "D1MTH6_MS,DECO1 Math Register 6_MS" line.long 0x34 "D1MTH6_LS,DECO1 Math Register 6_LS" line.long 0x38 "D1MTH7_MS,DECO1 Math Register 7_MS" line.long 0x3C "D1MTH7_LS,DECO1 Math Register 7_LS" tree.end tree "DECO2" group.long 0xA0840++0x3F line.long 0x00 "D2MTH0_MS,DECO2 Math Register 0_MS" line.long 0x04 "D2MTH0_LS,DECO2 Math Register 0_LS" line.long 0x08 "D2MTH1_MS,DECO2 Math Register 1_MS" line.long 0x0C "D2MTH1_LS,DECO2 Math Register 1_LS" line.long 0x10 "D2MTH2_MS,DECO2 Math Register 2_MS" line.long 0x14 "D2MTH2_LS,DECO2 Math Register 2_LS" line.long 0x18 "D2MTH3_MS,DECO2 Math Register 3_MS" line.long 0x1C "D2MTH3_LS,DECO2 Math Register 3_LS" line.long 0x20 "D2MTH4_MS,DECO2 Math Register 4_MS" line.long 0x24 "D2MTH4_LS,DECO2 Math Register 4_LS" line.long 0x28 "D2MTH5_MS,DECO2 Math Register 5_MS" line.long 0x2C "D2MTH5_LS,DECO2 Math Register 5_LS" line.long 0x30 "D2MTH6_MS,DECO2 Math Register 6_MS" line.long 0x34 "D2MTH6_LS,DECO2 Math Register 6_LS" line.long 0x38 "D2MTH7_MS,DECO2 Math Register 7_MS" line.long 0x3C "D2MTH7_LS,DECO2 Math Register 7_LS" tree.end tree.end tree "DECO Gather Table Registers" group.long 0x80880++0x3F line.long 0x00 "D0GTR0_0,DECO0 Gather Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D0GTR0_1,DECO0 Gather Table Register 0" line.long 0x08 "D0GTR0_2,DECO0 Gather Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x0C "D0GTR0_3,DECO0 Gather Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D0GTR1_0,DECO0 Gather Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D0GTR1_1,DECO0 Gather Table Register 1" line.long 0x18 "D0GTR1_2,DECO0 Gather Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x1C "D0GTR1_3,DECO0 Gather Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D0GTR2_0,DECO0 Gather Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D0GTR2_1,DECO0 Gather Table Register 2" line.long 0x28 "D0GTR2_2,DECO0 Gather Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x2C "D0GTR2_3,DECO0 Gather Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D0GTR3_0,DECO0 Gather Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D0GTR3_1,DECO0 Gather Table Register 3" line.long 0x38 "D0GTR3_2,DECO0 Gather Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x3C "D0GTR3_3,DECO0 Gather Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" group.long 0x90880++0x3F line.long 0x00 "D1GTR0_0,DECO1 Gather Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D1GTR0_1,DECO1 Gather Table Register 0" line.long 0x08 "D1GTR0_2,DECO1 Gather Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x0C "D1GTR0_3,DECO1 Gather Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D1GTR1_0,DECO1 Gather Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D1GTR1_1,DECO1 Gather Table Register 1" line.long 0x18 "D1GTR1_2,DECO1 Gather Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x1C "D1GTR1_3,DECO1 Gather Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D1GTR2_0,DECO1 Gather Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D1GTR2_1,DECO1 Gather Table Register 2" line.long 0x28 "D1GTR2_2,DECO1 Gather Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x2C "D1GTR2_3,DECO1 Gather Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D1GTR3_0,DECO1 Gather Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D1GTR3_1,DECO1 Gather Table Register 3" line.long 0x38 "D1GTR3_2,DECO1 Gather Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x3C "D1GTR3_3,DECO1 Gather Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" group.long 0xA0880++0x3F line.long 0x00 "D2GTR0_0,DECO2 Gather Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D2GTR0_1,DECO2 Gather Table Register 0" line.long 0x08 "D2GTR0_2,DECO2 Gather Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x0C "D2GTR0_3,DECO2 Gather Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D2GTR1_0,DECO2 Gather Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D2GTR1_1,DECO2 Gather Table Register 1" line.long 0x18 "D2GTR1_2,DECO2 Gather Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x1C "D2GTR1_3,DECO2 Gather Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D2GTR2_0,DECO2 Gather Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D2GTR2_1,DECO2 Gather Table Register 2" line.long 0x28 "D2GTR2_2,DECO2 Gather Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x2C "D2GTR2_3,DECO2 Gather Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D2GTR3_0,DECO2 Gather Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D2GTR3_1,DECO2 Gather Table Register 3" line.long 0x38 "D2GTR3_2,DECO2 Gather Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Bytes of data" line.long 0x3C "D2GTR3_3,DECO2 Gather Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" tree.end tree "DECO Scatter Table Registers" group.long 0x80900++0x3F line.long 0x00 "D0STR0_0,DECO0 Scatter Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D0STR0_1,DECO0 Scatter Table Register 0" line.long 0x08 "D0STR0_2,DECO0 Scatter Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Available space" line.long 0x0C "D0STR0_3,DECO0 Scatter Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D0STR1_0,DECO0 Scatter Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D0STR1_1,DECO0 Scatter Table Register 1" line.long 0x18 "D0STR1_2,DECO0 Scatter Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Available space" line.long 0x1C "D0STR1_3,DECO0 Scatter Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D0STR2_0,DECO0 Scatter Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D0STR2_1,DECO0 Scatter Table Register 2" line.long 0x28 "D0STR2_2,DECO0 Scatter Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Available space" line.long 0x2C "D0STR2_3,DECO0 Scatter Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D0STR3_0,DECO0 Scatter Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D0STR3_1,DECO0 Scatter Table Register 3" line.long 0x38 "D0STR3_2,DECO0 Scatter Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Available space" line.long 0x3C "D0STR3_3,DECO0 Scatter Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" group.long 0x90900++0x3F line.long 0x00 "D1STR0_0,DECO1 Scatter Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D1STR0_1,DECO1 Scatter Table Register 0" line.long 0x08 "D1STR0_2,DECO1 Scatter Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Available space" line.long 0x0C "D1STR0_3,DECO1 Scatter Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D1STR1_0,DECO1 Scatter Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D1STR1_1,DECO1 Scatter Table Register 1" line.long 0x18 "D1STR1_2,DECO1 Scatter Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Available space" line.long 0x1C "D1STR1_3,DECO1 Scatter Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D1STR2_0,DECO1 Scatter Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D1STR2_1,DECO1 Scatter Table Register 2" line.long 0x28 "D1STR2_2,DECO1 Scatter Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Available space" line.long 0x2C "D1STR2_3,DECO1 Scatter Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D1STR3_0,DECO1 Scatter Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D1STR3_1,DECO1 Scatter Table Register 3" line.long 0x38 "D1STR3_2,DECO1 Scatter Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Available space" line.long 0x3C "D1STR3_3,DECO1 Scatter Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" group.long 0xA0900++0x3F line.long 0x00 "D2STR0_0,DECO2 Scatter Table Register 0" hexmask.long.byte 0x00 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x04 "D2STR0_1,DECO2 Scatter Table Register 0" line.long 0x08 "D2STR0_2,DECO2 Scatter Table Register 0" bitfld.long 0x08 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x08 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x08 0.--29. 1. " LENGTH ,Available space" line.long 0x0C "D2STR0_3,DECO2 Scatter Table Register 0" hexmask.long.byte 0x0C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x0C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x10 "D2STR1_0,DECO2 Scatter Table Register 1" hexmask.long.byte 0x10 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x14 "D2STR1_1,DECO2 Scatter Table Register 1" line.long 0x18 "D2STR1_2,DECO2 Scatter Table Register 1" bitfld.long 0x18 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x18 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x18 0.--29. 1. " LENGTH ,Available space" line.long 0x1C "D2STR1_3,DECO2 Scatter Table Register 1" hexmask.long.byte 0x1C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x1C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x20 "D2STR2_0,DECO2 Scatter Table Register 2" hexmask.long.byte 0x20 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x24 "D2STR2_1,DECO2 Scatter Table Register 2" line.long 0x28 "D2STR2_2,DECO2 Scatter Table Register 2" bitfld.long 0x28 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x28 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x28 0.--29. 1. " LENGTH ,Available space" line.long 0x2C "D2STR2_3,DECO2 Scatter Table Register 2" hexmask.long.byte 0x2C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x2C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" line.long 0x30 "D2STR3_0,DECO2 Scatter Table Register 3" hexmask.long.byte 0x30 0.--7. 0x01 " ADDRESS_POINTER ,Most-significant 8 bits of the memory address" line.long 0x34 "D2STR3_1,DECO2 Scatter Table Register 3" line.long 0x38 "D2STR3_2,DECO2 Scatter Table Register 3" bitfld.long 0x38 31. " E ,Extension bit" "Not set,Set" bitfld.long 0x38 30. " F ,Final bit" "Not set,Set" newline hexmask.long 0x38 0.--29. 1. " LENGTH ,Available space" line.long 0x3C "D2STR3_3,DECO2 Scatter Table Register 3" hexmask.long.byte 0x3C 16.--23. 1. " BPID ,Buffer pool ID" hexmask.long.word 0x3C 0.--12. 0x01 " OFFSET ,Offset (measured in bytes)" tree.end tree "DECO Descriptor Buffer Word Registers" tree "DECO0" group.long 0x80A00++0xFF line.long 0x00 "D0DESB0,DECO0 Descriptor Buffer Word 0" line.long 0x04 "D0DESB1,DECO0 Descriptor Buffer Word 1" line.long 0x08 "D0DESB2,DECO0 Descriptor Buffer Word 2" line.long 0x0C "D0DESB3,DECO0 Descriptor Buffer Word 3" line.long 0x10 "D0DESB4,DECO0 Descriptor Buffer Word 4" line.long 0x14 "D0DESB5,DECO0 Descriptor Buffer Word 5" line.long 0x18 "D0DESB6,DECO0 Descriptor Buffer Word 6" line.long 0x1C "D0DESB7,DECO0 Descriptor Buffer Word 7" line.long 0x20 "D0DESB8,DECO0 Descriptor Buffer Word 8" line.long 0x24 "D0DESB9,DECO0 Descriptor Buffer Word 9" line.long 0x28 "D0DESB10,DECO0 Descriptor Buffer Word 10" line.long 0x2C "D0DESB11,DECO0 Descriptor Buffer Word 11" line.long 0x30 "D0DESB12,DECO0 Descriptor Buffer Word 12" line.long 0x34 "D0DESB13,DECO0 Descriptor Buffer Word 13" line.long 0x38 "D0DESB14,DECO0 Descriptor Buffer Word 14" line.long 0x3C "D0DESB15,DECO0 Descriptor Buffer Word 15" line.long 0x40 "D0DESB16,DECO0 Descriptor Buffer Word 16" line.long 0x44 "D0DESB17,DECO0 Descriptor Buffer Word 17" line.long 0x48 "D0DESB18,DECO0 Descriptor Buffer Word 18" line.long 0x4C "D0DESB19,DECO0 Descriptor Buffer Word 19" line.long 0x50 "D0DESB20,DECO0 Descriptor Buffer Word 20" line.long 0x54 "D0DESB21,DECO0 Descriptor Buffer Word 21" line.long 0x58 "D0DESB22,DECO0 Descriptor Buffer Word 22" line.long 0x5C "D0DESB23,DECO0 Descriptor Buffer Word 23" line.long 0x60 "D0DESB24,DECO0 Descriptor Buffer Word 24" line.long 0x64 "D0DESB25,DECO0 Descriptor Buffer Word 25" line.long 0x68 "D0DESB26,DECO0 Descriptor Buffer Word 26" line.long 0x6C "D0DESB27,DECO0 Descriptor Buffer Word 27" line.long 0x70 "D0DESB28,DECO0 Descriptor Buffer Word 28" line.long 0x74 "D0DESB29,DECO0 Descriptor Buffer Word 29" line.long 0x78 "D0DESB30,DECO0 Descriptor Buffer Word 30" line.long 0x7C "D0DESB31,DECO0 Descriptor Buffer Word 31" line.long 0x80 "D0DESB32,DECO0 Descriptor Buffer Word 32" line.long 0x84 "D0DESB33,DECO0 Descriptor Buffer Word 33" line.long 0x88 "D0DESB34,DECO0 Descriptor Buffer Word 34" line.long 0x8C "D0DESB35,DECO0 Descriptor Buffer Word 35" line.long 0x90 "D0DESB36,DECO0 Descriptor Buffer Word 36" line.long 0x94 "D0DESB37,DECO0 Descriptor Buffer Word 37" line.long 0x98 "D0DESB38,DECO0 Descriptor Buffer Word 38" line.long 0x9C "D0DESB39,DECO0 Descriptor Buffer Word 39" line.long 0xA0 "D0DESB40,DECO0 Descriptor Buffer Word 40" line.long 0xA4 "D0DESB41,DECO0 Descriptor Buffer Word 41" line.long 0xA8 "D0DESB42,DECO0 Descriptor Buffer Word 42" line.long 0xAC "D0DESB43,DECO0 Descriptor Buffer Word 43" line.long 0xB0 "D0DESB44,DECO0 Descriptor Buffer Word 44" line.long 0xB4 "D0DESB45,DECO0 Descriptor Buffer Word 45" line.long 0xB8 "D0DESB46,DECO0 Descriptor Buffer Word 46" line.long 0xBC "D0DESB47,DECO0 Descriptor Buffer Word 47" line.long 0xC0 "D0DESB48,DECO0 Descriptor Buffer Word 48" line.long 0xC4 "D0DESB49,DECO0 Descriptor Buffer Word 49" line.long 0xC8 "D0DESB50,DECO0 Descriptor Buffer Word 50" line.long 0xCC "D0DESB51,DECO0 Descriptor Buffer Word 51" line.long 0xD0 "D0DESB52,DECO0 Descriptor Buffer Word 52" line.long 0xD4 "D0DESB53,DECO0 Descriptor Buffer Word 53" line.long 0xD8 "D0DESB54,DECO0 Descriptor Buffer Word 54" line.long 0xDC "D0DESB55,DECO0 Descriptor Buffer Word 55" line.long 0xE0 "D0DESB56,DECO0 Descriptor Buffer Word 56" line.long 0xE4 "D0DESB57,DECO0 Descriptor Buffer Word 57" line.long 0xE8 "D0DESB58,DECO0 Descriptor Buffer Word 58" line.long 0xEC "D0DESB59,DECO0 Descriptor Buffer Word 59" line.long 0xF0 "D0DESB60,DECO0 Descriptor Buffer Word 60" line.long 0xF4 "D0DESB61,DECO0 Descriptor Buffer Word 61" line.long 0xF8 "D0DESB62,DECO0 Descriptor Buffer Word 62" line.long 0xFC "D0DESB63,DECO0 Descriptor Buffer Word 63" tree.end tree "DECO1" group.long 0x90A00++0xFF line.long 0x00 "D1DESB0,DECO1 Descriptor Buffer Word 0" line.long 0x04 "D1DESB1,DECO1 Descriptor Buffer Word 1" line.long 0x08 "D1DESB2,DECO1 Descriptor Buffer Word 2" line.long 0x0C "D1DESB3,DECO1 Descriptor Buffer Word 3" line.long 0x10 "D1DESB4,DECO1 Descriptor Buffer Word 4" line.long 0x14 "D1DESB5,DECO1 Descriptor Buffer Word 5" line.long 0x18 "D1DESB6,DECO1 Descriptor Buffer Word 6" line.long 0x1C "D1DESB7,DECO1 Descriptor Buffer Word 7" line.long 0x20 "D1DESB8,DECO1 Descriptor Buffer Word 8" line.long 0x24 "D1DESB9,DECO1 Descriptor Buffer Word 9" line.long 0x28 "D1DESB10,DECO1 Descriptor Buffer Word 10" line.long 0x2C "D1DESB11,DECO1 Descriptor Buffer Word 11" line.long 0x30 "D1DESB12,DECO1 Descriptor Buffer Word 12" line.long 0x34 "D1DESB13,DECO1 Descriptor Buffer Word 13" line.long 0x38 "D1DESB14,DECO1 Descriptor Buffer Word 14" line.long 0x3C "D1DESB15,DECO1 Descriptor Buffer Word 15" line.long 0x40 "D1DESB16,DECO1 Descriptor Buffer Word 16" line.long 0x44 "D1DESB17,DECO1 Descriptor Buffer Word 17" line.long 0x48 "D1DESB18,DECO1 Descriptor Buffer Word 18" line.long 0x4C "D1DESB19,DECO1 Descriptor Buffer Word 19" line.long 0x50 "D1DESB20,DECO1 Descriptor Buffer Word 20" line.long 0x54 "D1DESB21,DECO1 Descriptor Buffer Word 21" line.long 0x58 "D1DESB22,DECO1 Descriptor Buffer Word 22" line.long 0x5C "D1DESB23,DECO1 Descriptor Buffer Word 23" line.long 0x60 "D1DESB24,DECO1 Descriptor Buffer Word 24" line.long 0x64 "D1DESB25,DECO1 Descriptor Buffer Word 25" line.long 0x68 "D1DESB26,DECO1 Descriptor Buffer Word 26" line.long 0x6C "D1DESB27,DECO1 Descriptor Buffer Word 27" line.long 0x70 "D1DESB28,DECO1 Descriptor Buffer Word 28" line.long 0x74 "D1DESB29,DECO1 Descriptor Buffer Word 29" line.long 0x78 "D1DESB30,DECO1 Descriptor Buffer Word 30" line.long 0x7C "D1DESB31,DECO1 Descriptor Buffer Word 31" line.long 0x80 "D1DESB32,DECO1 Descriptor Buffer Word 32" line.long 0x84 "D1DESB33,DECO1 Descriptor Buffer Word 33" line.long 0x88 "D1DESB34,DECO1 Descriptor Buffer Word 34" line.long 0x8C "D1DESB35,DECO1 Descriptor Buffer Word 35" line.long 0x90 "D1DESB36,DECO1 Descriptor Buffer Word 36" line.long 0x94 "D1DESB37,DECO1 Descriptor Buffer Word 37" line.long 0x98 "D1DESB38,DECO1 Descriptor Buffer Word 38" line.long 0x9C "D1DESB39,DECO1 Descriptor Buffer Word 39" line.long 0xA0 "D1DESB40,DECO1 Descriptor Buffer Word 40" line.long 0xA4 "D1DESB41,DECO1 Descriptor Buffer Word 41" line.long 0xA8 "D1DESB42,DECO1 Descriptor Buffer Word 42" line.long 0xAC "D1DESB43,DECO1 Descriptor Buffer Word 43" line.long 0xB0 "D1DESB44,DECO1 Descriptor Buffer Word 44" line.long 0xB4 "D1DESB45,DECO1 Descriptor Buffer Word 45" line.long 0xB8 "D1DESB46,DECO1 Descriptor Buffer Word 46" line.long 0xBC "D1DESB47,DECO1 Descriptor Buffer Word 47" line.long 0xC0 "D1DESB48,DECO1 Descriptor Buffer Word 48" line.long 0xC4 "D1DESB49,DECO1 Descriptor Buffer Word 49" line.long 0xC8 "D1DESB50,DECO1 Descriptor Buffer Word 50" line.long 0xCC "D1DESB51,DECO1 Descriptor Buffer Word 51" line.long 0xD0 "D1DESB52,DECO1 Descriptor Buffer Word 52" line.long 0xD4 "D1DESB53,DECO1 Descriptor Buffer Word 53" line.long 0xD8 "D1DESB54,DECO1 Descriptor Buffer Word 54" line.long 0xDC "D1DESB55,DECO1 Descriptor Buffer Word 55" line.long 0xE0 "D1DESB56,DECO1 Descriptor Buffer Word 56" line.long 0xE4 "D1DESB57,DECO1 Descriptor Buffer Word 57" line.long 0xE8 "D1DESB58,DECO1 Descriptor Buffer Word 58" line.long 0xEC "D1DESB59,DECO1 Descriptor Buffer Word 59" line.long 0xF0 "D1DESB60,DECO1 Descriptor Buffer Word 60" line.long 0xF4 "D1DESB61,DECO1 Descriptor Buffer Word 61" line.long 0xF8 "D1DESB62,DECO1 Descriptor Buffer Word 62" line.long 0xFC "D1DESB63,DECO1 Descriptor Buffer Word 63" tree.end tree "DECO2" group.long 0xA0A00++0xFF line.long 0x00 "D2DESB0,DECO2 Descriptor Buffer Word 0" line.long 0x04 "D2DESB1,DECO2 Descriptor Buffer Word 1" line.long 0x08 "D2DESB2,DECO2 Descriptor Buffer Word 2" line.long 0x0C "D2DESB3,DECO2 Descriptor Buffer Word 3" line.long 0x10 "D2DESB4,DECO2 Descriptor Buffer Word 4" line.long 0x14 "D2DESB5,DECO2 Descriptor Buffer Word 5" line.long 0x18 "D2DESB6,DECO2 Descriptor Buffer Word 6" line.long 0x1C "D2DESB7,DECO2 Descriptor Buffer Word 7" line.long 0x20 "D2DESB8,DECO2 Descriptor Buffer Word 8" line.long 0x24 "D2DESB9,DECO2 Descriptor Buffer Word 9" line.long 0x28 "D2DESB10,DECO2 Descriptor Buffer Word 10" line.long 0x2C "D2DESB11,DECO2 Descriptor Buffer Word 11" line.long 0x30 "D2DESB12,DECO2 Descriptor Buffer Word 12" line.long 0x34 "D2DESB13,DECO2 Descriptor Buffer Word 13" line.long 0x38 "D2DESB14,DECO2 Descriptor Buffer Word 14" line.long 0x3C "D2DESB15,DECO2 Descriptor Buffer Word 15" line.long 0x40 "D2DESB16,DECO2 Descriptor Buffer Word 16" line.long 0x44 "D2DESB17,DECO2 Descriptor Buffer Word 17" line.long 0x48 "D2DESB18,DECO2 Descriptor Buffer Word 18" line.long 0x4C "D2DESB19,DECO2 Descriptor Buffer Word 19" line.long 0x50 "D2DESB20,DECO2 Descriptor Buffer Word 20" line.long 0x54 "D2DESB21,DECO2 Descriptor Buffer Word 21" line.long 0x58 "D2DESB22,DECO2 Descriptor Buffer Word 22" line.long 0x5C "D2DESB23,DECO2 Descriptor Buffer Word 23" line.long 0x60 "D2DESB24,DECO2 Descriptor Buffer Word 24" line.long 0x64 "D2DESB25,DECO2 Descriptor Buffer Word 25" line.long 0x68 "D2DESB26,DECO2 Descriptor Buffer Word 26" line.long 0x6C "D2DESB27,DECO2 Descriptor Buffer Word 27" line.long 0x70 "D2DESB28,DECO2 Descriptor Buffer Word 28" line.long 0x74 "D2DESB29,DECO2 Descriptor Buffer Word 29" line.long 0x78 "D2DESB30,DECO2 Descriptor Buffer Word 30" line.long 0x7C "D2DESB31,DECO2 Descriptor Buffer Word 31" line.long 0x80 "D2DESB32,DECO2 Descriptor Buffer Word 32" line.long 0x84 "D2DESB33,DECO2 Descriptor Buffer Word 33" line.long 0x88 "D2DESB34,DECO2 Descriptor Buffer Word 34" line.long 0x8C "D2DESB35,DECO2 Descriptor Buffer Word 35" line.long 0x90 "D2DESB36,DECO2 Descriptor Buffer Word 36" line.long 0x94 "D2DESB37,DECO2 Descriptor Buffer Word 37" line.long 0x98 "D2DESB38,DECO2 Descriptor Buffer Word 38" line.long 0x9C "D2DESB39,DECO2 Descriptor Buffer Word 39" line.long 0xA0 "D2DESB40,DECO2 Descriptor Buffer Word 40" line.long 0xA4 "D2DESB41,DECO2 Descriptor Buffer Word 41" line.long 0xA8 "D2DESB42,DECO2 Descriptor Buffer Word 42" line.long 0xAC "D2DESB43,DECO2 Descriptor Buffer Word 43" line.long 0xB0 "D2DESB44,DECO2 Descriptor Buffer Word 44" line.long 0xB4 "D2DESB45,DECO2 Descriptor Buffer Word 45" line.long 0xB8 "D2DESB46,DECO2 Descriptor Buffer Word 46" line.long 0xBC "D2DESB47,DECO2 Descriptor Buffer Word 47" line.long 0xC0 "D2DESB48,DECO2 Descriptor Buffer Word 48" line.long 0xC4 "D2DESB49,DECO2 Descriptor Buffer Word 49" line.long 0xC8 "D2DESB50,DECO2 Descriptor Buffer Word 50" line.long 0xCC "D2DESB51,DECO2 Descriptor Buffer Word 51" line.long 0xD0 "D2DESB52,DECO2 Descriptor Buffer Word 52" line.long 0xD4 "D2DESB53,DECO2 Descriptor Buffer Word 53" line.long 0xD8 "D2DESB54,DECO2 Descriptor Buffer Word 54" line.long 0xDC "D2DESB55,DECO2 Descriptor Buffer Word 55" line.long 0xE0 "D2DESB56,DECO2 Descriptor Buffer Word 56" line.long 0xE4 "D2DESB57,DECO2 Descriptor Buffer Word 57" line.long 0xE8 "D2DESB58,DECO2 Descriptor Buffer Word 58" line.long 0xEC "D2DESB59,DECO2 Descriptor Buffer Word 59" line.long 0xF0 "D2DESB60,DECO2 Descriptor Buffer Word 60" line.long 0xF4 "D2DESB61,DECO2 Descriptor Buffer Word 61" line.long 0xF8 "D2DESB62,DECO2 Descriptor Buffer Word 62" line.long 0xFC "D2DESB63,DECO2 Descriptor Buffer Word 63" tree.end tree.end newline rgroup.long 0x80E00++0x07 line.long 0x00 "D0DJR,DECO0 Debug Job" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" newline bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " GSD ,Got shared descriptor" "No,Yes" bitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,QI,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "D0DDR,DECO0 Debug DECO" bitfld.long 0x04 31. " VALID ,Valid" "Not valid,Valid" bitfld.long 0x04 30. " SD ,Shared descriptor" "Not received,Received" bitfld.long 0x04 28.--29. " TRCT ,DMA transaction count" "0,1,2,3" newline bitfld.long 0x04 26.--27. " SEQLSEL ,SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" bitfld.long 0x04 24.--25. " NSEQLSEL ,Non-SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" newline bitfld.long 0x04 20.--23. " DECO_STATE ,DECO state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 18.--19. " PDB_WB_ST ,PDB writeback state" "0,1,2,3" bitfld.long 0x04 16.--17. " PDB_STALL ,PDB stall state" "0,1,2,3" newline bitfld.long 0x04 15. " PTCL_RUN ,Protocol running" "Not running,Running" bitfld.long 0x04 14. " NLJ ,Took non-local JUMP" "Not occurred,Occurred" bitfld.long 0x04 8.--13. " CMD_INDEDX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 5.--7. " CMD_STAGE ,Command stage" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. " CSA ,Command stage aux" "0,1" bitfld.long 0x04 3. " NC ,No command" "No,Yes" newline bitfld.long 0x04 2. " BWB ,Burster write busy" "Idle,Busy" bitfld.long 0x04 1. " BRB ,Burster read busy" "Idle,Busy" bitfld.long 0x04 0. " CT ,Checking trusted" "Not checked,Checked" newline rgroup.quad (0x80E00+0x08)++0x0F line.quad 0x00 "D0DJP,DECO0 Debug Job Pointer" hexmask.quad 0x00 0.--39. 0x01 " JDPTR ,Job descriptor pointer" line.quad 0x08 "D0SDP,DECO0 Debug Shared Pointer" hexmask.quad 0x08 0.--39. 0x01 " SDPTR ,Shared descriptor pointer" newline rgroup.long (0x80E00+0x18)++0x03 line.long 0x00 "D0DIR_MS,DECO0 Debug_ICID (Most Significant)" hexmask.long.word 0x00 16.--27. 1. " NON_SEQICID ,DECO non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQICID ,DECO SEQ ICID" group.long (0x80E00+0x20)++0x1B line.long 0x00 "SOL0,Sequence Output Length Register 0" line.long 0x04 "VSOL0,Variable Sequence Output Length Register 0" line.long 0x08 "SIL0,Sequence Input Length Register 0" line.long 0x0C "VSIL0,Variable Sequence Input Length Register 0" line.long 0x10 "D0POVRD,Protocol Override Register 0" line.long 0x14 "UVSOL0,Variable Sequence Output Length Register 0; Upper 32 Bits" line.long 0x18 "UVSIL0,Variable Sequence Input Length Register 0; Upper 32 Bits" newline rgroup.long 0x90E00++0x07 line.long 0x00 "D1DJR,DECO1 Debug Job" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" newline bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " GSD ,Got shared descriptor" "No,Yes" bitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,QI,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "D1DDR,DECO1 Debug DECO" bitfld.long 0x04 31. " VALID ,Valid" "Not valid,Valid" bitfld.long 0x04 30. " SD ,Shared descriptor" "Not received,Received" bitfld.long 0x04 28.--29. " TRCT ,DMA transaction count" "0,1,2,3" newline bitfld.long 0x04 26.--27. " SEQLSEL ,SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" bitfld.long 0x04 24.--25. " NSEQLSEL ,Non-SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" newline bitfld.long 0x04 20.--23. " DECO_STATE ,DECO state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 18.--19. " PDB_WB_ST ,PDB writeback state" "0,1,2,3" bitfld.long 0x04 16.--17. " PDB_STALL ,PDB stall state" "0,1,2,3" newline bitfld.long 0x04 15. " PTCL_RUN ,Protocol running" "Not running,Running" bitfld.long 0x04 14. " NLJ ,Took non-local JUMP" "Not occurred,Occurred" bitfld.long 0x04 8.--13. " CMD_INDEDX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 5.--7. " CMD_STAGE ,Command stage" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. " CSA ,Command stage aux" "0,1" bitfld.long 0x04 3. " NC ,No command" "No,Yes" newline bitfld.long 0x04 2. " BWB ,Burster write busy" "Idle,Busy" bitfld.long 0x04 1. " BRB ,Burster read busy" "Idle,Busy" bitfld.long 0x04 0. " CT ,Checking trusted" "Not checked,Checked" newline rgroup.quad (0x90E00+0x08)++0x0F line.quad 0x00 "D1DJP,DECO1 Debug Job Pointer" hexmask.quad 0x00 0.--39. 0x01 " JDPTR ,Job descriptor pointer" line.quad 0x08 "D1SDP,DECO1 Debug Shared Pointer" hexmask.quad 0x08 0.--39. 0x01 " SDPTR ,Shared descriptor pointer" newline rgroup.long (0x90E00+0x18)++0x03 line.long 0x00 "D1DIR_MS,DECO1 Debug_ICID (Most Significant)" hexmask.long.word 0x00 16.--27. 1. " NON_SEQICID ,DECO non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQICID ,DECO SEQ ICID" group.long (0x90E00+0x20)++0x1B line.long 0x00 "SOL1,Sequence Output Length Register 1" line.long 0x04 "VSOL1,Variable Sequence Output Length Register 1" line.long 0x08 "SIL1,Sequence Input Length Register 1" line.long 0x0C "VSIL1,Variable Sequence Input Length Register 1" line.long 0x10 "D1POVRD,Protocol Override Register 1" line.long 0x14 "UVSOL1,Variable Sequence Output Length Register 1; Upper 32 Bits" line.long 0x18 "UVSIL1,Variable Sequence Input Length Register 1; Upper 32 Bits" newline rgroup.long 0xA0E00++0x07 line.long 0x00 "D2DJR,DECO2 Debug Job" bitfld.long 0x00 31. " STEP ,Step" "No effect,Step" bitfld.long 0x00 30. " SING ,Single step mode" "Disabled,Enabled" bitfld.long 0x00 29. " WHL ,Whole descriptor" "Not occurred,Occurred" newline bitfld.long 0x00 28. " FOUR ,Four words" "Less,At least" bitfld.long 0x00 27. " ILE ,Immediate little endian" "Not swapped,Swapped" bitfld.long 0x00 24.--26. " SHR_FROM ,Share from" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " DWS ,Double word swap" "Not swapped,Swapped" bitfld.long 0x00 16. " GSD ,Got shared descriptor" "No,Yes" bitfld.long 0x00 15. " AMTD ,Allow make trusted descriptor" "Not allowed,Allowed" newline bitfld.long 0x00 14. " JDIS ,Job descriptor ICID select" "Non-SEQ ICID,SEQ ICID" bitfld.long 0x00 8.--10. " SRC ,Job source" "Job ring 0,Job ring 1,Job ring 2,Job ring 3,RTIC,QI,?..." bitfld.long 0x00 0.--3. " ID ,Job ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "D2DDR,DECO2 Debug DECO" bitfld.long 0x04 31. " VALID ,Valid" "Not valid,Valid" bitfld.long 0x04 30. " SD ,Shared descriptor" "Not received,Received" bitfld.long 0x04 28.--29. " TRCT ,DMA transaction count" "0,1,2,3" newline bitfld.long 0x04 26.--27. " SEQLSEL ,SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" bitfld.long 0x04 24.--25. " NSEQLSEL ,Non-SEQ ICID select" ",SEQ ICID,Non-SEQ ICID,Trusted ICID" newline bitfld.long 0x04 20.--23. " DECO_STATE ,DECO state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 18.--19. " PDB_WB_ST ,PDB writeback state" "0,1,2,3" bitfld.long 0x04 16.--17. " PDB_STALL ,PDB stall state" "0,1,2,3" newline bitfld.long 0x04 15. " PTCL_RUN ,Protocol running" "Not running,Running" bitfld.long 0x04 14. " NLJ ,Took non-local JUMP" "Not occurred,Occurred" bitfld.long 0x04 8.--13. " CMD_INDEDX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 5.--7. " CMD_STAGE ,Command stage" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4. " CSA ,Command stage aux" "0,1" bitfld.long 0x04 3. " NC ,No command" "No,Yes" newline bitfld.long 0x04 2. " BWB ,Burster write busy" "Idle,Busy" bitfld.long 0x04 1. " BRB ,Burster read busy" "Idle,Busy" bitfld.long 0x04 0. " CT ,Checking trusted" "Not checked,Checked" newline rgroup.quad (0xA0E00+0x08)++0x0F line.quad 0x00 "D2DJP,DECO2 Debug Job Pointer" hexmask.quad 0x00 0.--39. 0x01 " JDPTR ,Job descriptor pointer" line.quad 0x08 "D2SDP,DECO2 Debug Shared Pointer" hexmask.quad 0x08 0.--39. 0x01 " SDPTR ,Shared descriptor pointer" newline rgroup.long (0xA0E00+0x18)++0x03 line.long 0x00 "D2DIR_MS,DECO2 Debug_ICID (Most Significant)" hexmask.long.word 0x00 16.--27. 1. " NON_SEQICID ,DECO non-SEQ ICID" hexmask.long.word 0x00 0.--11. 1. " SEQICID ,DECO SEQ ICID" group.long (0xA0E00+0x20)++0x1B line.long 0x00 "SOL2,Sequence Output Length Register 2" line.long 0x04 "VSOL2,Variable Sequence Output Length Register 2" line.long 0x08 "SIL2,Sequence Input Length Register 2" line.long 0x0C "VSIL2,Variable Sequence Input Length Register 2" line.long 0x10 "D2POVRD,Protocol Override Register 2" line.long 0x14 "UVSOL2,Variable Sequence Output Length Register 2; Upper 32 Bits" line.long 0x18 "UVSIL2,Variable Sequence Input Length Register 2; Upper 32 Bits" newline endian.le width 0x0B tree.end endif sif !cpuis("LS1012*") sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "DDR (DDR Memory Controller)" base ad:0x01080000 width 26. group.long 0x0++0x03 line.long 0x00 "DDR_CS0_BNDS,Chip Select 0 Memory Bounds" hexmask.long.word 0x00 16.--31. 0x01 " SA ,Starting address for chip select (bank) 0" hexmask.long.word 0x00 0.--15. 0x01 " EA ,Ending address for chip select (bank) 0" group.long 0x8++0x03 line.long 0x00 "DDR_CS1_BNDS,Chip Select 1 Memory Bounds" hexmask.long.word 0x00 16.--31. 0x01 " SA ,Starting address for chip select (bank) 1" hexmask.long.word 0x00 0.--15. 0x01 " EA ,Ending address for chip select (bank) 1" group.long 0x10++0x03 line.long 0x00 "DDR_CS2_BNDS,Chip Select 2 Memory Bounds" hexmask.long.word 0x00 16.--31. 0x01 " SA ,Starting address for chip select (bank) 2" hexmask.long.word 0x00 0.--15. 0x01 " EA ,Ending address for chip select (bank) 2" group.long 0x18++0x03 line.long 0x00 "DDR_CS3_BNDS,Chip Select 3 Memory Bounds" hexmask.long.word 0x00 16.--31. 0x01 " SA ,Starting address for chip select (bank) 3" hexmask.long.word 0x00 0.--15. 0x01 " EA ,Ending address for chip select (bank) 3" group.long 0x80++0x03 line.long 0x00 "DDR_CS0_CONFIG,Chip Select 0 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 0 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 0 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS0,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS0,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 0" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 0" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 0" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 0" "8 bits,9 bits,10 bits,11 bits,?..." group.long 0x84++0x03 line.long 0x00 "DDR_CS1_CONFIG,Chip Select 1 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 1 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 1 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS1,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS1,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 1" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 1" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 1" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 1" "8 bits,9 bits,10 bits,11 bits,?..." group.long 0x88++0x03 line.long 0x00 "DDR_CS2_CONFIG,Chip Select 2 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 2 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 2 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS2,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS2,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 2" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 2" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 2" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 2" "8 bits,9 bits,10 bits,11 bits,?..." group.long 0x8C++0x03 line.long 0x00 "DDR_CS3_CONFIG,Chip Select 3 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 3 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 3 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS3,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS3,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 3" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 3" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 3" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 3" "8 bits,9 bits,10 bits,11 bits,?..." group.long 0xC0++0x03 line.long 0x00 "DDR_CS0_CONFIG2,Chip Select 0 Configuration 2" bitfld.long 0x00 31. " PASR_DEC ,Partial array decoding" "Normal,Partial" group.long 0xC4++0x03 line.long 0x00 "DDR_CS1_CONFIG2,Chip Select 1 Configuration 2" bitfld.long 0x00 31. " PASR_DEC ,Partial array decoding" "Normal,Partial" group.long 0xC8++0x03 line.long 0x00 "DDR_CS2_CONFIG2,Chip Select 2 Configuration 2" bitfld.long 0x00 31. " PASR_DEC ,Partial array decoding" "Normal,Partial" group.long 0xCC++0x03 line.long 0x00 "DDR_CS3_CONFIG2,Chip Select 3 Configuration 2" bitfld.long 0x00 31. " PASR_DEC ,Partial array decoding" "Normal,Partial" group.long 0x100++0x0F line.long 0x00 "DDR_TIMING_CFG_3,DDR SDRAM Timing Configuration 3" bitfld.long 0x00 28. " EXT_PRETOACT ,Extended precharge-to-activate interval (t_RP)" "0 clocks,16 clocks" bitfld.long 0x00 24.--25. " EXT_ACTTOPRE ,Extended activate to precharge interval (t_RAS)" "0 clocks,16 clocks,32 clocks,48 clocks" bitfld.long 0x00 22. " EXT_ACTTORW ,Extended activate to read/write interval for SDRAM (t_RCD)" "0,1" newline bitfld.long 0x00 16.--21. " EXT_REFREC ,Extended refresh recovery time (t_RFC)" "0 clocks,16 clocks,32 clocks,48 clocks,64 clocks,80 clocks,96 clocks,112 clocks,128 clocks,144 clocks,160 clocks,176 clocks,192 clocks,208 clocks,224 clocks,240 clocks,256 clocks,272 clocks,288 clocks,304 clocks,320 clocks,336 clocks,352 clocks,368 clocks,384 clocks,400 clocks,416 clocks,432 clocks,448 clocks,464 clocks,480 clocks,496 clocks,512 clocks,528 clocks,544 clocks,560 clocks,576 clocks,592 clocks,608 clocks,624 clocks,640 clocks,656 clocks,672 clocks,688 clocks,704 clocks,720 clocks,751 clocks,752 clocks,?..." bitfld.long 0x00 12.--13. " EXT_CASLAT ,Extended MCAS_B latency from READ command" "0 clocks,8 clocks,16 clocks,?..." bitfld.long 0x00 10. " EXT_ADD_LAT ,Extended additive latency" "0 clocks,16 clocks" newline bitfld.long 0x00 8. " EXT_WRREC ,Extended last data to precharge minimum interval (t_WR)" "0 clocks,16 clocks" bitfld.long 0x00 0.--2. " CNTL_ADJ ,Control adjust. affects modtn mcsn_B and mcken" "Aligned,1/2 cycle,1 cycle,3/2 cycles,2 cycles,5/2 cycles,?..." line.long 0x04 "DDR_TIMING_CFG_0,DDR SDRAM Timing Configuration 0" bitfld.long 0x04 30.--31. " RWT ,Read-to-write turnaround. how many extra cycles will be added between a read to write turnaround" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 28.--29. " WRT ,Write-to-read turnaround. how many extra cycles will be added between a write to read turnaround" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 26.--27. " RRT ,Read-to-read turnaround. how many extra cycles will be added between reads to different chip selects" "0 clocks,1 clock,2 clocks,3 clocks" newline bitfld.long 0x04 24.--25. " WWT ,Write-to-write turnaround. how many extra cycles will be added between writes to different chip selects" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 20.--23. " ACT_PD_EXIT ,Active powerdown exit timing (t_XP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x04 16.--19. " PRE_PD_EXIT ,Precharge powerdown exit timing (t_XP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x04 14.--15. " EXT_PRE_PD_EXIT ,Extended precharge powerdown exit timing (t_XP)" "0 clocks,16 clocks,32 clocks,48 clocks" bitfld.long 0x04 0.--4. " MRS_CYC ,Mode register set cycle time (t_MRD t_MOD)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" line.long 0x08 "DDR_TIMING_CFG_1,DDR SDRAM Timing Configuration 1" bitfld.long 0x08 28.--31. " PRETOACT ,Precharge-to-activate interval (t_RP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 24.--27. " ACTTOPRE ,Activate to precharge interval (t_RAS)" "16 clocks,17 clocks,18 clocks,19 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 20.--23. " ACTTORW ,Activate to read/write interval for SDRAM (t_RCD)" ",1 clocks,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x08 17.--19. " CASLAT ,MCAS_B latency from READ command" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x08 12.--15. " REFREC ,Refresh recovery time (t_RFC)" "8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks" bitfld.long 0x08 8.--11. " WRREC ,Last data to precharge minimum interval (t_WR)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x08 4.--7. " ACTTOACT ,Activate-to-activate interval (t_RRD)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 0.--3. " WRTORD ,Last write data pair to read command issue interval (t_WTR)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" line.long 0x0C "DDR_TIMING_CFG_2,DDR SDRAM Timing Configuration 2" bitfld.long 0x0C 28.--31. " ADD_LAT ,Additive latency" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,?..." bitfld.long 0x0C 19.--22. " WR_LAT ,Write latency" ",,,,,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x0C 18. " EXT_WR_LAT ,Extended write latency" "0 clocks,16 clocks" newline bitfld.long 0x0C 13.--16. " RD_TO_PRE ,Read to precharge (t_RTP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x0C 9.--12. " WR_DATA_DELAY ,Write command to write data strobe timing adjustment" "0 clock delay,2 clock delay,1/4 clock delay,9/4 clock delay,1/2 clock delay,5/2 clock delay,3/4 clock delay,,1 clock delay,,5/4 clock delay,,3/2 clock delay,,7/4 clock delay,?..." bitfld.long 0x0C 6.--8. " CKE_PLS ,Minimum CKE pulse width (t_CKE)" "8 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" newline bitfld.long 0x0C 0.--5. " FOUR_ACT ,Window for four activates (t_FAW)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks" if (((per.l(ad:0x01080000+0x110))&0x1C0000)==(0x80000||0x100000)) if (((per.l(ad:0x01080000+0x114))&0x40)==0x40) group.long 0x110++0x03 line.long 0x00 "DDR_DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." bitfld.long 0x00 18. " 8_BE ,8-beat burst enable" "4-beat,8-beat" bitfld.long 0x00 16. " 3T_EN ,Enable 3T timing" "Disabled,Enabled" newline bitfld.long 0x00 15. " 2T_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" bitfld.long 0x00 3. " HSE ,Global half-strength overrides" "Full,Half" newline bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" else group.long 0x110++0x03 line.long 0x00 "DDR_DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." bitfld.long 0x00 18. " 8_BE ,8-beat burst enable" "4-beat,8-beat" bitfld.long 0x00 15. " 2T_EN ,Enable 2T timing" "Disabled,Enabled" newline hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" bitfld.long 0x00 3. " HSE ,Global half-strength overrides" "Full,Half" bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" endif else group.long 0x110++0x03 line.long 0x00 "DDR_DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." bitfld.long 0x00 18. " 8_BE ,8-beat burst enable" "4-beat,8-beat" bitfld.long 0x00 16. " 3T_EN ,Enable 3T timing" "Disabled,Enabled" newline bitfld.long 0x00 15. " 2T_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" bitfld.long 0x00 3. " HSE ,Global half-strength overrides" "Full,Half" newline bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" endif group.long 0x114++0x17 line.long 0x00 "DDR_DDR_SDRAM_CFG_2,DDR SDRAM Control Configuration 2" bitfld.long 0x00 31. " FRC_SR ,Force self refresh" "Normal,Self-refresh" bitfld.long 0x00 21.--22. " ODT_CFG ,ODT configuration" "Never,,On DRAM reads,?..." bitfld.long 0x00 12.--15. " NUM_PR ,Number of posted refreshes" ",1,2,3,4,5,6,7,8,?..." newline bitfld.long 0x00 11. " DDR_SLOW ,DDR slow frequency" "1250 MT/s or higher,Less than 1250 MT/s" bitfld.long 0x00 9. " QD_EN ,Quad-rank enable" "Disabled,Enabled" bitfld.long 0x00 8. " UNQ_MRS_EN ,Unique MRS enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " OBC_CFG ,On-The-Fly burst chop configuration" "Disabled,Enabled" bitfld.long 0x00 5. " AP_EN ,Address parity enable" "Disabled,Enabled" bitfld.long 0x00 4. " D_INIT ,DRAM data initialization" "Disabled,Enabled" newline bitfld.long 0x00 2. " RCW_EN ,Register control word enable" "Disabled,Enabled" bitfld.long 0x00 1. " CD_DIS ,Corrupted data disable" "Enabled,Disabled" bitfld.long 0x00 0. " MD_EN ,Mirrored DIMM enable" "Disabled,Enabled" line.long 0x04 "DDR_DDR_SDRAM_MODE,DDR SDRAM Mode Configuration" hexmask.long.word 0x04 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x04 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x08 "DDR_DDR_SDRAM_MODE2,DDR SDRAM Mode Configuration 2" hexmask.long.word 0x08 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x08 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x0C "DDR_DDR_SDRAM_MD_CNTL,DDR SDRAM Mode Control" bitfld.long 0x0C 31. " MD_EN ,Mode enable. specifies that valid data in MD_VALUE is ready to be written to DRAM" "Not ready,Ready" bitfld.long 0x0C 28.--30. " CS_SEL ,Select chip select" "0,1,2,3,0 and 1,2 and 3,?..." bitfld.long 0x0C 24.--27. " MD_SEL ,Mode register select" "MR,EMR,EMR2,EMR3,?..." newline bitfld.long 0x0C 23. " SET_REF ,Set refresh" "No refresh,Refresh" bitfld.long 0x0C 22. " SET_PRE ,Set precharge" "No precharge,Precharge" bitfld.long 0x0C 20.--21. " CKE_CNTL ,Clock enable control" "Not forced,Forced to low value,Forced to high value,?..." newline hexmask.long.tbyte 0x0C 0.--17. 1. " MD_VALUE ,Mode register value" line.long 0x10 "DDR_DDR_SDRAM_INTERVAL,DDR SDRAM Interval Configuration" hexmask.long.word 0x10 16.--31. 1. " REFINT ,Refresh interval" hexmask.long.word 0x10 0.--13. 1. " BSTOPRE ,Precharge interval" line.long 0x14 "DDR_DDR_DATA_INIT,DDR SDRAM Data Initialization" group.long 0x130++0x03 line.long 0x00 "DDR_DDR_SDRAM_CLK_CNTL,DDR SDRAM Clock Control" bitfld.long 0x00 22.--26. " CLK_ADJUST ,Clock adjust. launch after address/command delay in cycles" "No delay,1/16,1/8,3/16,1/4,5/16,3/8,7/16,1/2,9/16,5/8,11/16,3/4,13/16,7/8,15/16,1,?..." group.long 0x148++0x07 line.long 0x00 "DDR_DDR_INIT_ADDR,DDR Training Initialization Address" line.long 0x04 "DDR_DDR_INIT_EXT_ADDRESS,DDR Training Initialization Extended Address" bitfld.long 0x04 31. " UIA ,Use initialization address" "Default,Initialization" hexmask.long.byte 0x04 0.--7. 0x01 " INIT_EXT_ADDR ,Initialization extended address" group.long 0x160++0x07 line.long 0x00 "DDR_TIMING_CFG_4,DDR SDRAM Timing Configuration 4" bitfld.long 0x00 28.--31. " RWT ,Read-to-write turnaround for same chip select" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT ,Write-to-read turnaround for same chip select" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT ,Read-to-read turnaround for same chip select" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT ,Write-to-write turnaround for same chip select" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 14.--15. " EXT_RWT ,Extended read-to-write turnaround (t_RTW)" "0 clocks,1 clocks,2 clocks,3 clocks" bitfld.long 0x00 12. " EXT_WRT ,Extended write-to-read turnaround" "0 clocks,4 clocks" newline bitfld.long 0x00 10. " EXT_RRT ,Extended read-to-read turnaround" "0 clocks,4 clocks" bitfld.long 0x00 8. " EXT_WWT ,Extended write-to-write turnaround" "0 clocks,4 clocks" bitfld.long 0x00 4. " EXT_REFINT ,Refresh interval" "0 clocks,65536 clocks" newline bitfld.long 0x00 0.--1. " DLL_LOCK ,DDR SDRAM DLL lock time" "200 clocks,512 clocks,?..." line.long 0x04 "DDR_TIMING_CFG_5,DDR SDRAM Timing Configuration 5" bitfld.long 0x04 24.--28. " RODT_ON ,Read to ODT on" "CASLAT-WR_LAT,0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,?..." bitfld.long 0x04 20.--22. " RODT_OFF ,Read to ODT off" "4 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" bitfld.long 0x04 12.--16. " WODT_ON ,Write to ODT on" "0 clocks,0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,?..." newline bitfld.long 0x04 8.--10. " WODT_OFF ,Write to ODT off" "4 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" group.long 0x16C++0x0F line.long 0x00 "DDR_TIMING_CFG_7,DDR SDRAM Timing Configuration 7" bitfld.long 0x00 28.--29. " CKE_RST ,CKE reset time (t_XPR)" "200 clocks,256 clocks,512 clocks,1024 clocks" bitfld.long 0x00 24.--27. " CKSRE ,Valid clock after self refresh entry (t_CKSRE)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,32 clocks" bitfld.long 0x00 20.--23. " CKSRX ,Valid clock after self refresh exit (t_CKSRX)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,27 clocks" newline bitfld.long 0x00 16.--19. " PAR_LAT ,Chip select to command latency" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,?..." bitfld.long 0x00 4.--7. " CS_TO_CMD ,Parity latency" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,?..." line.long 0x04 "DDR_DDR_ZQ_CNTL,DDR ZQ Calibration Control" bitfld.long 0x04 31. " ZQ_EN ,ZQ calibration enable" "Disabled,Enabled" bitfld.long 0x04 24.--27. " ZQINIT ,POR ZQ calibration time (t_zqinit)" ",,,,,,,128,256,512,1024,?..." bitfld.long 0x04 16.--19. " ZQOPER ,Normal operation full calibration time (t_zqoper)" ",,,,,,,128,256,512,1024,?..." newline bitfld.long 0x04 8.--11. " ZQCS ,Normal operation short calibration time (t_ZQCS)" "1,2,4,8,16,32,64,128,256,512,?..." bitfld.long 0x04 0.--3. " ZQCS_INT ,ZQCS interval. determines the number of refresh sequences that will pass between each ZQCS calibration" "32,64,128,256,512,1024,2048,4096,8192,16384,32768,,,,,Disabled" line.long 0x08 "DDR_DDR_WRLVL_CNTL,DDR Write Leveling Control" bitfld.long 0x08 31. " WRLVL_EN ,Write leveling enable" "Disabled,Enabled" bitfld.long 0x08 30. " WRLVL_DONE ,Write leveling done" "Not completed,Completed" bitfld.long 0x08 24.--26. " WRLVL_MRD ,First DQS pulse rising edge after margining mode is programmed (t_WL_MRD)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" newline bitfld.long 0x08 20.--22. " WRLVL_ODTEN ,ODT delay after margining mode is programmed (t_WL_ODTEN)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x08 16.--18. " WRLVL_DQSEN ,DQS/DQS_B delay after margining mode is programmed (t_WL_DQSEN)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x08 12.--15. " WRLVL_SMPL ,Write leveling sample time" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8.--10. " WRLVL_WLR ,Write leveling repetition time" "1,2,4,8,16,32,64,128" bitfld.long 0x08 0.--4. " WRLVL_START ,Write leveling start time (delay) for DQS[0]" "0,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" line.long 0x0C "DDR_DDR_SR_CNTR,DDR Self Refresh Counter" bitfld.long 0x0C 16.--19. " SR_IT ,Self refresh idle threshold number of DRAM cycles" "Disabled,2^10,2^12,2^14,2^16,2^18,2^20,2^22,2^24,2^26,2^28,2^30,?..." group.long 0x180++0x07 line.long 0x00 "DDR_DDR_SDRAM_RCW_1,DDR Register Control Words 1" bitfld.long 0x00 28.--31. " RCW0 ,Register control word 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " RCW1 ,Register control word 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " RCW2 ,Register control word 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. " RCW3 ,Register control word 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " RCW4 ,Register control word 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RCW5 ,Register control word 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " RCW6 ,Register control word 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RCW7 ,Register control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DDR_DDR_SDRAM_RCW_2,DDR Register Control Words 2" bitfld.long 0x04 28.--31. " RCW8 ,Register control word 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " RCW9 ,Register control word 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " RCW10 ,Register control word 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. " RCW11 ,Register control word 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RCW12 ,Register control word 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RCW13 ,Register control word 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " RCW14 ,Register control word 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " RCW15 ,Register control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x190++0x07 line.long 0x00 "DDR_DDR_WRLVL_CNTL_2,DDR Write Leveling Control 2" bitfld.long 0x00 24.--28. " WRLVL_START_1 ,Write leveling start time for DQS[1]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x00 16.--20. " WRLVL_START_2 ,Write leveling start time for DQS[2]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x00 8.--12. " WRLVL_START_3 ,Write leveling start time for DQS[3]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" newline bitfld.long 0x00 0.--4. " WRLVL_START_4 ,Write leveling start time for DQS[4]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" line.long 0x04 "DDR_DDR_WRLVL_CNTL_3,DDR Write Leveling Control 3" bitfld.long 0x04 24.--28. " WRLVL_START_5 ,Write leveling start time for DQS[5]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x04 16.--20. " WRLVL_START_6 ,Write leveling start time for DQS[6]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x04 8.--12. " WRLVL_START_7 ,Write leveling start time for DQS[7]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" newline bitfld.long 0x04 0.--4. " WRLVL_START_8 ,Write leveling start time for DQS[8]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" group.long 0x1A0++0x0F line.long 0x00 "DDR_DDR_SDRAM_RCW_3,DDR Register Control Words 3" hexmask.long.byte 0x00 24.--31. 1. " RCW1X ,Register control word 1X" hexmask.long.byte 0x00 16.--23. 1. " RCW2X ,Register control word 2X" hexmask.long.byte 0x00 8.--15. 1. " RCW3X ,Register control word 3X" newline hexmask.long.byte 0x00 0.--7. 1. " RCW4X ,Register control word 4X" line.long 0x04 "DDR_DDR_SDRAM_RCW_4,DDR Register Control Words 4" hexmask.long.byte 0x04 24.--31. 1. " RCW5X ,Register control word 5X" hexmask.long.byte 0x04 16.--23. 1. " RCW6X ,Register control word 6X" hexmask.long.byte 0x04 8.--15. 1. " RCW7X ,Register control word 7X" newline hexmask.long.byte 0x04 0.--7. 1. " RCW8X ,Register control word 8X" line.long 0x08 "DDR_DDR_SDRAM_RCW_5,DDR Register Control Words 5" hexmask.long.byte 0x08 24.--31. 1. " RCW9X ,Register control word 9X" hexmask.long.byte 0x08 16.--23. 1. " RCW10X ,Register control word 10X" hexmask.long.byte 0x08 8.--15. 1. " RCW11X ,Register control word 11X" newline hexmask.long.byte 0x08 0.--7. 1. " RCW12X ,Register control word 12X" line.long 0x0C "DDR_DDR_SDRAM_RCW_6,DDR Register Control Words 6" hexmask.long.byte 0x0C 24.--31. 1. " RCW13X ,Register control word 13X" hexmask.long.byte 0x0C 16.--23. 1. " RCW14X ,Register control word 14X" hexmask.long.byte 0x0C 8.--15. 1. " RCW15X ,Register control word 15X" group.long 0x200++0x17 line.long 0x00 "DDR_DDR_SDRAM_MODE_3,DDR SDRAM Mode Configuration 3" hexmask.long.word 0x00 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x00 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x04 "DDR_DDR_SDRAM_MODE_4,DDR SDRAM Mode Configuration 4" hexmask.long.word 0x04 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x04 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x08 "DDR_DDR_SDRAM_MODE_5,DDR SDRAM Mode Configuration 5" hexmask.long.word 0x08 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x08 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x0C "DDR_DDR_SDRAM_MODE_6,DDR SDRAM Mode Configuration 6" hexmask.long.word 0x0C 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x0C 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x10 "DDR_DDR_SDRAM_MODE_7,DDR SDRAM Mode Configuration 7" hexmask.long.word 0x10 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x10 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x14 "DDR_DDR_SDRAM_MODE_8,DDR SDRAM Mode Configuration 8" hexmask.long.word 0x14 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x14 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" group.long 0x220++0x1F line.long 0x00 "DDR_DDR_SDRAM_MODE_9,DDR SDRAM Mode Configuration 9" hexmask.long.word 0x00 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x00 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x04 "DDR_DDR_SDRAM_MODE_10,DDR SDRAM Mode Configuration 10" hexmask.long.word 0x04 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x04 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x08 "DDR_DDR_SDRAM_MODE_11,DDR SDRAM Mode Configuration 11" hexmask.long.word 0x08 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x08 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x0C "DDR_DDR_SDRAM_MODE_12,DDR SDRAM Mode Configuration 12" hexmask.long.word 0x0C 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x0C 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x10 "DDR_DDR_SDRAM_MODE_13,DDR SDRAM Mode Configuration 13" hexmask.long.word 0x10 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x10 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x14 "DDR_DDR_SDRAM_MODE_14,DDR SDRAM Mode Configuration 14" hexmask.long.word 0x14 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x14 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x18 "DDR_DDR_SDRAM_MODE_15,DDR SDRAM Mode Configuration 15" hexmask.long.word 0x18 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x18 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x1C "DDR_DDR_SDRAM_MODE_16,DDR SDRAM Mode Configuration 16" hexmask.long.word 0x1C 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x1C 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" group.long 0x250++0x03 line.long 0x00 "DDR_TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 28.--31. " RWT_BG ,Read-to-write turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT_BG ,Write-to-read turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT_BG ,Read-to-read turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT_BG ,Write-to-write turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 12.--15. " ACTTOACT_BG ,Activate-to-activate interval for the same bank group(t_RRD_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 8.--11. " WRTORD_BG ,Last write data pair to read command issue interval for the same bank group(t_WTR_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x00 7. " EXT_WRTORD_BG ,Extended write-to-read same bank group" "Disabled,16 clocks" bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. when 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" group.long 0x260++0x03 line.long 0x00 "DDR_DDR_SDRAM_CFG_3,DDR SDRAM Control Configuration 3" bitfld.long 0x00 31. " DDRC_RST ,DDR controller reset" "No reset,Reset" bitfld.long 0x00 30. " ECC_FIX_EN ,ECC fixing enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " ECC_SCRUB_INT ,ECC scrubbing interval" "Disabled,1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384" newline bitfld.long 0x00 17. " WR_PRE ,Write preamble" "1 t_ck,2 t_ck" bitfld.long 0x00 16. " RD_PRE ,Read preamble" "1 t_ck,2 t_ck" bitfld.long 0x00 12.--13. " DM_CFG ,Data mask config" "Normal data masks,,Data bus inversion,Not used" newline bitfld.long 0x00 8.--9. " REF_MODE ,Refresh mode" "Disabled,2x,4x,?..." bitfld.long 0x00 0. " DIS_MRS_PAR ,Disable MRS on parity error" "No,Yes" group.long 0x400++0x0F line.long 0x00 "DDR_DDR_DQ_MAP0,DQ Mapping Register 0" bitfld.long 0x00 26.--31. " DQ_0_3 ,DQ[0:3] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 20.--25. " DQ_4_7 ,DQ[4:7] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 14.--19. " DQ_8_11 ,DQ[8:11] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x00 8.--13. " DQ_12_15 ,DQ[12:15] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 2.--7. " DQ_16_19 ,DQ[16:19] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x04 "DDR_DDR_DQ_MAP1,DQ Mapping Register 1" bitfld.long 0x04 26.--31. " DQ_20_23 ,DQ[20:23] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 20.--25. " DQ_24_27 ,DQ[24:27] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 14.--19. " DQ_28_31 ,DQ[28:31] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x04 8.--13. " DQ_32_35 ,DQ[32:35] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 2.--7. " DQ_36_39 ,DQ[36:39] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x08 "DDR_DDR_DQ_MAP2,DQ Mapping Register 2" bitfld.long 0x08 26.--31. " DQ_40_43 ,DQ[40:43] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 20.--25. " DQ_44_47 ,DQ[44:47] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 14.--19. " DQ_48_51 ,DQ[48:51] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x08 8.--13. " DQ_52_55 ,DQ[52:55] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 2.--7. " DQ_56_59 ,DQ[56:59] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x0C "DDR_DDR_DQ_MAP3,DQ Mapping Register 3" bitfld.long 0x0C 26.--31. " DQ_60_63 ,DQ[60:63] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x0C 20.--25. " ECC_0_3 ,ECC[0:3] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x0C 14.--19. " ECC_4_7 ,ECC[4:7] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x0C 0. " ORS ,Odd rank swizzle" "Disabled,Enabled" rgroup.long 0xB20++0x03 line.long 0x00 "DDR_DDRDSR_1,DDR Debug Status Register 1" bitfld.long 0x00 15. " CZ ,Current setting of driver command impedance" "High,Low" bitfld.long 0x00 7. " DZ ,Current setting of driver data impedance" "High,Low" group.long 0xB24++0x0B line.long 0x00 "DDR_DDRDSR_2,DDR Debug Status Register 2" bitfld.long 0x00 31. " CLKZ ,Current setting of driver clock impedance" "High,Low" eventfld.long 0x00 1. " RPD_ST ,Rapid clear of memory start" "Not started,Started" eventfld.long 0x00 0. " RPD_END ,Rapid clear of memory end" "Not completed,Completed" line.long 0x04 "DDR_DDRCDR_1,DDR Control Driver Register 1" bitfld.long 0x04 31. " DHC_EN ,DDR driver hardware compensation enable" "Disabled,Enabled" bitfld.long 0x04 30. " V0PT9_EN ,Enable if using 0.9V vdd" "Disabled,Enabled" bitfld.long 0x04 18.--19. " ODT ,ODT termination value for IOs" "0,1,2,3" newline bitfld.long 0x04 17. " DSO_C_EN ,Driver software override enable for address/command" "Disabled,Enabled" bitfld.long 0x04 16. " DSO_D_EN ,Driver software override enable for data" "Disabled,Enabled" bitfld.long 0x04 15. " DSO_CZ ,DDR driver software command impedance override" "Highest,Lowest" newline bitfld.long 0x04 7. " DSO_DZ ,Driver software data impedance override" "Highest,Lowest" line.long 0x08 "DDR_DDRCDR_2,DDR Control Driver Register 2" bitfld.long 0x08 31. " DSO_CLK_EN ,Driver software override enable for clocks" "Disabled,Enabled" bitfld.long 0x08 27. " DSO_CLKZ ,Driver software clocks impedance override" "Highest,Lowest" bitfld.long 0x08 15. " VREF_OVRD_EN ,Internal vref generation override enable. when 0 if DDR4 mode an internal vref is generated an used for the data bus" "Not overridden,Overridden" newline bitfld.long 0x08 8.--13. " VREF_OVRD_VAL ,Defines the override value to use for the internal vref if VREF_OVRD_EN is set" "37%,38%,39%,40%,41%,42%,43%,44%,45%,46%,47%,48%,49%,50%,51%,52%,53%,54%,55%,56%,57%,58%,59%,60%,61%,62%,63%,64%,65%,66%,67%,68%,69%,70%,71%,72%,73%,74%,75%,76%,77%,78%,79%,80%,81%,82%,83%,84%,85%,86%,87%,88%,89%,90%,91%,92%,93%,94%,95%,96%,97%,98%,99%,100%" bitfld.long 0x08 7. " VREF_TRAIN_EN ,Enable DRAM vref training" "Disabled,Enabled" bitfld.long 0x08 6. " VREF_DRAM_RANGE ,The vref range during DRAM training" "Range1,Range2" newline bitfld.long 0x08 0. " ODT ,ODT termination value for IOs" "0,1" rgroup.long 0xBF8++0x07 line.long 0x00 "DDR_DDR_IP_REV1,DDR IP Block Revision 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "DDR_DDR_IP_REV2,DDR IP Block Revision 2" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,IP block integration options" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,IP block configuration options" group.long 0xD00++0x03 line.long 0x00 "DDR_DDR_MTCR,DDR Memory Test Control Register" bitfld.long 0x00 31. " MT_EN ,Memory test enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MT_TYP ,Memory test type" "Writes and reads,Writes only,Reads only,?..." bitfld.long 0x00 16.--19. " MT_TRNARND ,Memory test turnaround" "Entire mem write then read,1 transaction each,2 transaction each,4 transaction each,?..." newline bitfld.long 0x00 9. " MT_ADDR_EN ,Memory test address range enable" "Disabled,Enabled" bitfld.long 0x00 0. " MT_STAT ,Memory test status" "No fail,Fail" group.long 0xD1C++0x03 line.long 0x00 "DDR_DDR_MTP1 ,DDR Memory Test Pattern 1 Register" group.long 0xD20++0x03 line.long 0x00 "DDR_DDR_MTP2 ,DDR Memory Test Pattern 2 Register" group.long 0xD24++0x03 line.long 0x00 "DDR_DDR_MTP3 ,DDR Memory Test Pattern 3 Register" group.long 0xD28++0x03 line.long 0x00 "DDR_DDR_MTP4 ,DDR Memory Test Pattern 4 Register" group.long 0xD2C++0x03 line.long 0x00 "DDR_DDR_MTP5 ,DDR Memory Test Pattern 5 Register" group.long 0xD30++0x03 line.long 0x00 "DDR_DDR_MTP6 ,DDR Memory Test Pattern 6 Register" group.long 0xD34++0x03 line.long 0x00 "DDR_DDR_MTP7 ,DDR Memory Test Pattern 7 Register" group.long 0xD38++0x03 line.long 0x00 "DDR_DDR_MTP8 ,DDR Memory Test Pattern 8 Register" group.long 0xD3C++0x03 line.long 0x00 "DDR_DDR_MTP9 ,DDR Memory Test Pattern 9 Register" group.long 0xD40++0x03 line.long 0x00 "DDR_DDR_MTP10,DDR Memory Test Pattern 10 Register" group.long 0xD60++0x0F line.long 0x00 "DDR_DDR_MT_ST_EXT_ADDR,DDR Memory Test Start Extended Address" hexmask.long.byte 0x00 0.--7. 0x01 " MT_ST_EXT_ADDR ,This field represents the starting extended address" line.long 0x04 "DDR_DDR_MT_ST_ADDR,DDR Memory Test Start Address" line.long 0x08 "DDR_DDR_MT_END_EXT_ADDR,DDR Memory Test End Extended Address" hexmask.long.byte 0x08 0.--7. 0x01 " MT_END_EXT_ADDR ,This field represents the ending extended address" line.long 0x0C "DDR_DDR_MT_END_ADDR,DDR Memory Test End Address" group.long 0xE00++0x0B line.long 0x00 "DDR_DATA_ERR_INJECT_HI,Memory Data Path Error Injection Mask High" line.long 0x04 "DDR_DATA_ERR_INJECT_LO,Memory Data Path Error Injection Mask Low" line.long 0x08 "DDR_ECC_ERR_INJECT,Memory Data Path Error Injection Mask ECC" bitfld.long 0x08 16. " APIEN ,Address parity error injection enable" "Disabled,Enabled" bitfld.long 0x08 9. " EMB ,ECC mirror byte enable" "Disabled,Enabled" bitfld.long 0x08 8. " EIEN ,Error injection enable" "Disabled,Enabled" newline hexmask.long.byte 0x08 0.--7. 1. " EEIM ,ECC error injection mask" group.long 0xE20++0x0B line.long 0x00 "DDR_CAPTURE_DATA_HI,Memory Data Path Read Capture High" line.long 0x04 "DDR_CAPTURE_DATA_LO,Memory Data Path Read Capture Low" line.long 0x08 "DDR_CAPTURE_ECC,Memory Data Path Read Capture ECC" group.long 0xE40++0x1B line.long 0x00 "DDR_ERR_DETECT,Memory Error Detect" eventfld.long 0x00 31. " MME ,Multiple memory errors" "No error,Error" eventfld.long 0x00 12. " SSBE ,Scrubbed single-bit ECC error" "No error,Error" eventfld.long 0x00 8. " APE ,Address parity error" "No error,Error" newline eventfld.long 0x00 7. " ACE ,Automatic calibration error" "No error,Error" eventfld.long 0x00 4. " CDE ,Corrupted data error" "No error,Error" eventfld.long 0x00 3. " MBE ,Multiple-bit error" "No error,Error" newline eventfld.long 0x00 2. " SBE ,Single-bit ECC error" "No error,Error" eventfld.long 0x00 0. " MSE ,Memory select error" "No error,Error" line.long 0x04 "DDR_ERR_DISABLE,Memory Error Disable" bitfld.long 0x04 12. " SSBED ,Scrubbed single-bit ECC error disable" "No,Yes" bitfld.long 0x04 8. " APED ,Address parity error disable" "No,Yes" bitfld.long 0x04 7. " ACED ,Automatic calibration error disable" "No,Yes" newline bitfld.long 0x04 4. " CDED ,Corrupted data error disable" "No,Yes" bitfld.long 0x04 3. " MBED ,Multiple-bit ECC error disable" "No,Yes" bitfld.long 0x04 2. " SBED ,Single-bit ECC error disable" "No,Yes" newline bitfld.long 0x04 0. " MSED ,Memory select error disable" "No,Yes" line.long 0x08 "DDR_ERR_INT_EN,Memory Error Interrupt Enable" bitfld.long 0x08 12. " SSBEE ,Scrubbed single-bit ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " APEE ,Address parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " ACEE ,Automatic calibration error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CDEE ,Corrupted data error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 3. " MBEE ,Multiple-bit ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " SBEE ,Single-bit ECC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " MSEE ,Memory select error interrupt enable" "Disabled,Enabled" line.long 0x0C "DDR_CAPTURE_ATTRIBUTES,Memory Error Attributes Capture" bitfld.long 0x0C 28.--30. " BNUM ,Data beat number" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. " TSIZ ,Transaction size for the error in double words" "8 double words,1 double word,2 double words,3 double words,4 double words,5 double words,6 double words,7 double words" hexmask.long.byte 0x0C 16.--23. 1. " TSRC ,Transaction source for the error" newline bitfld.long 0x0C 12.--13. " TTYP ,Transaction type for the error" ",Write,Read,Read-modify-write" bitfld.long 0x0C 0. " VLD ,Valid" "Not valid,Valid" line.long 0x10 "DDR_CAPTURE_ADDRESS,Memory Error Address Capture" line.long 0x14 "DDR_CAPTURE_EXT_ADDRESS,Memory Error Extended Address Capture" hexmask.long.byte 0x14 0.--7. 0x01 " CEADDR ,Captured extended address" line.long 0x18 "DDR_ERR_SBE,Single-Bit ECC Memory Error Management" hexmask.long.byte 0x18 24.--31. 1. " SSBET ,Scrubbed single-bit error threshold" hexmask.long.byte 0x18 16.--23. 1. " SBET ,Single-bit error threshold" hexmask.long.byte 0x18 8.--15. 1. " SSBEC ,Scrubbed single-bit error counter" newline hexmask.long.byte 0x18 0.--7. 1. " SBEC ,Single-bit error counter" width 0x0B tree.end else tree "DDR (DDR Memory Controller)" base ad:0x01080000 width 22. endian.be group.long 0x0++0x03 line.long 0x00 "CS0_BNDS,Chip Select 0 Memory Bounds" hexmask.long.word 0x00 16.--31. 1. " SA ,Starting address for chip select (bank) 0" hexmask.long.word 0x00 0.--15. 1. " EA ,Ending address for chip select (bank) 0" group.long 0x8++0x03 line.long 0x00 "CS1_BNDS,Chip Select 1 Memory Bounds" hexmask.long.word 0x00 16.--31. 1. " SA ,Starting address for chip select (bank) 1" hexmask.long.word 0x00 0.--15. 1. " EA ,Ending address for chip select (bank) 1" group.long 0x10++0x03 line.long 0x00 "CS2_BNDS,Chip Select 2 Memory Bounds" hexmask.long.word 0x00 16.--31. 1. " SA ,Starting address for chip select (bank) 2" hexmask.long.word 0x00 0.--15. 1. " EA ,Ending address for chip select (bank) 2" group.long 0x18++0x03 line.long 0x00 "CS3_BNDS,Chip Select 3 Memory Bounds" hexmask.long.word 0x00 16.--31. 1. " SA ,Starting address for chip select (bank) 3" hexmask.long.word 0x00 0.--15. 1. " EA ,Ending address for chip select (bank) 3" if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x80++0x03 line.long 0x00 "CS0_CONFIG,Chip Select 0 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 0 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 0 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS0,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS0,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 0" "2 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 0" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 0" "0 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 0" "8 bits,9 bits,10 bits,11 bits,?..." else group.long 0x80++0x03 line.long 0x00 "CS0_CONFIG,Chip Select 0 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 0 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 0 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS0,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS0,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 0" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 0" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 0" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 0" "8 bits,9 bits,10 bits,11 bits,?..." endif if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x84++0x03 line.long 0x00 "CS1_CONFIG,Chip Select 1 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 1 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 1 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS1,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS1,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 1" "2 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 1" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 1" "0 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 1" "8 bits,9 bits,10 bits,11 bits,?..." else group.long 0x84++0x03 line.long 0x00 "CS1_CONFIG,Chip Select 1 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 1 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 1 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS1,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS1,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 1" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 1" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 1" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 1" "8 bits,9 bits,10 bits,11 bits,?..." endif if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x88++0x03 line.long 0x00 "CS2_CONFIG,Chip Select 2 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 2 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 2 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS2,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS2,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 2" "2 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 2" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 2" "0 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 2" "8 bits,9 bits,10 bits,11 bits,?..." else group.long 0x88++0x03 line.long 0x00 "CS2_CONFIG,Chip Select 2 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 2 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 2 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS2,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS2,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 2" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 2" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 2" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 2" "8 bits,9 bits,10 bits,11 bits,?..." endif if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x8C++0x03 line.long 0x00 "CS3_CONFIG,Chip Select 3 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 3 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 3 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS3,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS3,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 3" "2 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 3" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 3" "0 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 3" "8 bits,9 bits,10 bits,11 bits,?..." else group.long 0x8C++0x03 line.long 0x00 "CS3_CONFIG,Chip Select 3 Configuration" bitfld.long 0x00 31. " CS_EN ,Chip select 3 enable" "Disabled,Enabled" bitfld.long 0x00 23. " AP_EN ,Chip select 3 auto-precharge enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ODT_RD_CFG ,ODT for reads configuration" "Never,On reads to CS3,On reads to other chip selects,On reads to other DIMM,All reads,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" newline bitfld.long 0x00 16.--18. " ODT_WR_CFG ,ODT for writes configuration" "Never,On writes to CS3,On writes to other chip selects,On writes to other DIMM,All writes,On transactions to same DIMM,On transactions to own CS/other DIMM,On transactions to other CS/same DIMM" bitfld.long 0x00 14.--15. " BA_BITS_CS ,Number of bank bits for SDRAM on chip select 3" "2 bits,3 bits,?..." bitfld.long 0x00 8.--10. " ROW_BITS_CS ,Number of row bits for SDRAM on chip select 3" "12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,?..." newline bitfld.long 0x00 4.--5. " BG_BITS_CS ,Number of bank group bits for SDRAM on chip select 3" "0 bits,1 bit,2 bits,?..." bitfld.long 0x00 0.--2. " COL_BITS_CS ,Number of column bits for SDRAM on chip select 3" "8 bits,9 bits,10 bits,11 bits,?..." endif group.long 0x100++0x0B line.long 0x00 "TIMING_CFG_3,DDR SDRAM Timing Configuration 3" bitfld.long 0x00 28. " EXT_PRETOACT ,Extended precharge-to-activate interval (t_RP)" "0 clocks,16 clocks" bitfld.long 0x00 24.--25. " EXT_ACTTOPRE ,Extended activate to precharge interval (t_RAS)" "0 clocks,16 clocks,32 clocks,48 clocks" bitfld.long 0x00 22. " EXT_ACTTORW ,Extended activate to read/write interval for SDRAM (t_RCD)" "0,1" newline bitfld.long 0x00 16.--21. " EXT_REFREC ,Extended refresh recovery time (t_RFC)" "0 clocks,16 clocks,32 clocks,48 clocks,64 clocks,80 clocks,96 clocks,112 clocks,128 clocks,144 clocks,160 clocks,176 clocks,192 clocks,208 clocks,224 clocks,240 clocks,256 clocks,272 clocks,288 clocks,304 clocks,320 clocks,336 clocks,352 clocks,368 clocks,384 clocks,400 clocks,416 clocks,432 clocks,448 clocks,464 clocks,480 clocks,496 clocks,512 clocks,528 clocks,544 clocks,560 clocks,576 clocks,592 clocks,608 clocks,624 clocks,640 clocks,656 clocks,672 clocks,688 clocks,704 clocks,720 clocks,736 clocks,752 clocks,?..." bitfld.long 0x00 12.--13. " EXT_CASLAT ,Extended CAS latency" "0 clocks,8 clocks,16 clocks,?..." bitfld.long 0x00 10. " EXT_ADD_LAT ,Extended additive latency" "0 clocks,16 clocks" newline bitfld.long 0x00 8. " EXT_WRREC ,Extended last data to precharge minimum interval (t_WR)" "0 clocks,16 clocks" bitfld.long 0x00 0.--2. " CNTL_ADJ ,Control Adjust. Affects MODTn, MCSn_B, and MCKEn" "Aligned,1/4 cycle,1/2 cycle,3/4 cycles,1 cycles,5/4 cycles,?..." line.long 0x04 "TIMING_CFG_0,DDR SDRAM Timing Configuration 0" bitfld.long 0x04 30.--31. " RWT ,Read-to-write turnaround. How many extra cycles will be added between a read to write turnaround" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 28.--29. " WRT ,Write-to-read turnaround. How many extra cycles will be added between a write to read turnaround" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 26.--27. " RRT ,Read-to-read turnaround. How many extra cycles will be added between reads to different chip selects" "0 clocks,1 clock,2 clocks,3 clocks" newline bitfld.long 0x04 24.--25. " WWT ,Write-to-write turnaround. How many extra cycles will be added between writes to different chip selects" "0 clocks,1 clock,2 clocks,3 clocks" bitfld.long 0x04 20.--23. " ACT_PD_EXIT ,Active powerdown exit timing (t_XP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x04 16.--19. " PRE_PD_EXIT ,Precharge powerdown exit timing (t_XP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x04 14.--15. " EXT_PRE_PD_EXIT ,Extended precharge powerdown exit timing (t_XP)" "0 clocks,16 clocks,32 clocks,48 clocks" bitfld.long 0x04 0.--4. " MRS_CYC ,Mode register set cycle time (t_MRD, t_MOD)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" line.long 0x08 "TIMING_CFG_1,DDR SDRAM Timing Configuration 1" bitfld.long 0x08 28.--31. " PRETOACT ,Precharge-to-activate interval (t_RP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 24.--27. " ACTTOPRE ,Activate to precharge interval (t_RAS)" "16 clocks,17 clocks,18 clocks,19 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 20.--23. " ACTTORW ,Activate to read/write interval for SDRAM (t_RCD)" ",1 clocks,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x08 17.--19. " CASLAT ,CAS latency" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x08 12.--15. " REFREC ,Refresh recovery time (t_RFC)" "8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks" bitfld.long 0x08 8.--11. " WRREC ,Last data to precharge minimum interval (t_WR)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x08 4.--7. " ACTTOACT ,Activate-to-activate interval (t_RRD)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x08 0.--3. " WRTORD ,Last write data pair to read command issue interval (t_WTR)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" if (((per.l.be(ad:0x01080000+0x10C))&0x40000)==0x40000) group.long 0x10C++0x03 line.long 0x00 "TIMING_CFG_2,DDR SDRAM Timing Configuration 2" bitfld.long 0x00 28.--31. " ADD_LAT ,Additive latency" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,?..." bitfld.long 0x00 19.--22. " WR_LAT ,Write latency" "0 clocks,1 clocks,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 18. " EXT_WR_LAT ,Extended write latency" "0 clocks,16 clocks" newline bitfld.long 0x00 13.--16. " RD_TO_PRE ,Read to precharge (t_RTP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 9.--12. " WR_DATA_DELAY ,Write command to write data strobe timing adjustment" "0 clock delay,2 clock delay,1/4 clock delay,9/4 clock delay,1/2 clock delay,5/2 clock delay,3/4 clock delay,,1 clock delay,,5/4 clock delay,,3/2 clock delay,,7/4 clock delay,?..." bitfld.long 0x00 6.--8. " CKE_PLS ,Minimum CKE pulse width (t_CKE)" "8 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" newline bitfld.long 0x00 0.--5. " FOUR_ACT ,Window for four activates (t_FAW)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks" else group.long 0x10C++0x03 line.long 0x00 "TIMING_CFG_2,DDR SDRAM Timing Configuration 2" bitfld.long 0x00 28.--31. " ADD_LAT ,Additive latency" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,?..." bitfld.long 0x00 19.--22. " WR_LAT ,Write latency" ",,,,,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 18. " EXT_WR_LAT ,Extended write latency" "0 clocks,16 clocks" newline bitfld.long 0x00 13.--16. " RD_TO_PRE ,Read to precharge (t_RTP)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 9.--12. " WR_DATA_DELAY ,Write command to write data strobe timing adjustment" "0 clock delay,2 clock delay,1/4 clock delay,9/4 clock delay,1/2 clock delay,5/2 clock delay,3/4 clock delay,,1 clock delay,,5/4 clock delay,,3/2 clock delay,,7/4 clock delay,?..." bitfld.long 0x00 6.--8. " CKE_PLS ,Minimum CKE pulse width (t_CKE)" "8 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" newline bitfld.long 0x00 0.--5. " FOUR_ACT ,Window for four activates (t_FAW)" ",1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks,41 clocks,42 clocks,43 clocks,44 clocks,45 clocks,46 clocks,47 clocks,48 clocks,49 clocks,50 clocks,51 clocks,52 clocks,53 clocks,54 clocks,55 clocks,56 clocks,57 clocks,58 clocks,59 clocks,60 clocks,61 clocks,62 clocks,63 clocks" endif if (((per.l.be(ad:0x01080000+0x110))&0x40000)==0x00) if (((per.l.be(ad:0x01080000+0x110))&0x180000)!=0x80000) if (((per.l.be(ad:0x01080000+0x114))&0x40)==0x40) group.long 0x110++0x03 line.long 0x00 "DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" newline endif sif (cpuis("LS10?6*")) bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." newline else bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,,DDR3" newline endif bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." newline else bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" ",32-bit,16-bit,?..." newline endif bitfld.long 0x00 18. " BE_8 ,8-beat burst enable" "4-beat,8-beat" newline bitfld.long 0x00 16. " T3_EN ,Enable 3T timing" "Disabled,Enabled" bitfld.long 0x00 15. " T2_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" newline bitfld.long 0x00 3. " HSE ,Half-strength enable" "Full,Half" bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" newline bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" else group.long 0x110++0x03 line.long 0x00 "DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" newline endif sif (cpuis("LS10?6*")) bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." newline else bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,,DDR3" newline endif bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." newline else bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" ",32-bit,?..." newline endif bitfld.long 0x00 18. " BE_8 ,8-beat burst enable" "4-beat,8-beat" newline bitfld.long 0x00 15. " T2_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" bitfld.long 0x00 3. " HSE ,Half-strength enable" "Full,Half" newline bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" endif else group.long 0x110++0x03 line.long 0x00 "DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" newline endif sif (cpuis("LS10?6*")) bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." newline else bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,,DDR3" newline endif bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." newline else bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" ",32-bit,16-bit,?..." newline endif bitfld.long 0x00 18. " BE_8 ,8-beat burst enable" "4-beat,8-beat" newline bitfld.long 0x00 16. " T3_EN ,Enable 3T timing" "Disabled,Enabled" bitfld.long 0x00 15. " T2_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" newline bitfld.long 0x00 3. " HSE ,Half-strength enable" "Full,Half" bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" newline bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" endif else group.long 0x110++0x03 line.long 0x00 "DDR_SDRAM_CFG,DDR SDRAM Control Configuration" bitfld.long 0x00 31. " MEM_EN ,DDR SDRAM interface logic enable" "Disabled,Enabled" bitfld.long 0x00 30. " SREN ,Self refresh enable (during sleep)" "Disabled,Enabled" bitfld.long 0x00 29. " ECC_EN ,ECC enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 28. " RD_EN ,Registered DIMM enable" "Disabled,Enabled" newline endif sif (cpuis("LS10?6*")) bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,?..." newline else bitfld.long 0x00 24.--26. " SDRAM_TYPE ,Type of SDRAM device to be used" ",,,,,DDR4,,DDR3" newline endif bitfld.long 0x00 21. " DYN_PWR ,Dynamic power management mode enable" "Disabled,Enabled" newline sif (cpuis("LS10?6*")) bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" "64-bit,32-bit,?..." newline else bitfld.long 0x00 19.--20. " DBW ,DRAM data bus width" ",32-bit,16-bit,?..." newline endif bitfld.long 0x00 18. " BE_8 ,8-beat burst enable" "4-beat,8-beat" newline bitfld.long 0x00 16. " T3_EN ,Enable 3T timing" "Disabled,Enabled" bitfld.long 0x00 15. " T2_EN ,Enable 2T timing" "Disabled,Enabled" hexmask.long.byte 0x00 8.--14. 1. " BA_INTLV_CTL ,Bank (chip select) interleaving control" newline bitfld.long 0x00 3. " HSE ,Half-strength enable" "Full,Half" bitfld.long 0x00 2. " ACC_ECC_EN ,Accumulated ECC enable" "Disabled,Enabled" bitfld.long 0x00 1. " MEM_HALT ,DDR memory controller halt" "Not halted,Halted" newline bitfld.long 0x00 0. " BI ,Bypass initialization" "Not bypassed,Bypassed" endif group.long 0x114++0x17 line.long 0x00 "DDR_SDRAM_CFG_2,DDR SDRAM Control Configuration 2" bitfld.long 0x00 31. " FRC_SR ,Force self refresh" "Normal,Self-refresh" bitfld.long 0x00 21.--22. " ODT_CFG ,ODT configuration. Assert ODT to internal IOs" "Never,,On DRAM reads,?..." bitfld.long 0x00 12.--15. " NUM_PR ,Number of posted refreshes" ",1,2,3,4,5,6,7,8,?..." newline bitfld.long 0x00 11. " DDR_SLOW ,DDR slow frequency" "1250 MT/s or higher,Less than 1250 MT/s" bitfld.long 0x00 9. " QD_EN ,Quad-rank enable" "Disabled,Enabled" bitfld.long 0x00 8. " UNQ_MRS_EN ,Unique MRS enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " OBC_CFG ,On-the-fly burst chop configuration" "Disabled,Enabled" bitfld.long 0x00 5. " AP_EN ,Address parity enable" "Disabled,Enabled" bitfld.long 0x00 4. " D_INIT ,DRAM data initialization" "Disabled,Enabled" newline sif !cpuis("LS10?3*") bitfld.long 0x00 2. " RCW_EN ,Register control word enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " CD_DIS ,Corrupted data disable" "No,Yes" newline bitfld.long 0x00 0. " MD_EN ,Mirrored DIMM enable" "Disabled,Enabled" line.long 0x04 "DDR_SDRAM_MODE,DDR SDRAM Mode Configuration" hexmask.long.word 0x04 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x04 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x08 "DDR_SDRAM_MODE2,DDR SDRAM Mode Configuration 2" hexmask.long.word 0x08 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x08 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x0C "DDR_SDRAM_MD_CNTL,DDR SDRAM Mode Control" bitfld.long 0x0C 31. " MD_EN ,Mode enable. Specifies that valid data in MD_VALUE is ready to be written to DRAM" "Not ready,Ready" bitfld.long 0x0C 28.--30. " CS_SEL ,Select chip select" "0,1,2,3,0 and 1,2 and 3,?..." bitfld.long 0x0C 24.--27. " MD_SEL ,Mode register select" "MR,EMR,EMR2,EMR3,?..." newline bitfld.long 0x0C 23. " SET_REF ,Set refresh" "No refresh,Refresh" bitfld.long 0x0C 22. " SET_PRE ,Set precharge" "No precharge,Precharge" bitfld.long 0x0C 20.--21. " CKE_CNTL ,Clock enable control" "Not forced,Forced to low value,Forced to high value,?..." newline hexmask.long.tbyte 0x0C 0.--17. 1. " MD_VALUE ,Mode register value" line.long 0x10 "DDR_SDRAM_INTERVAL,DDR SDRAM Interval Configuration" hexmask.long.word 0x10 16.--31. 1. " REFINT ,Refresh interval" hexmask.long.word 0x10 0.--13. 1. " BSTOPRE ,Precharge interval" line.long 0x14 "DDR_DATA_INIT,DDR SDRAM Data Initialization" group.long 0x130++0x03 line.long 0x00 "DDR_SDRAM_CLK_CNTL,DDR SDRAM Clock Control" bitfld.long 0x00 22.--26. " CLK_ADJUST ,Clock adjust. Launch after address/command delay in cycles" "No delay,1/16,1/8,3/16,1/4,5/16,3/8,7/16,1/2,9/16,5/8,11/16,3/4,13/16,7/8,15/16,1,?..." group.long 0x148++0x07 line.long 0x00 "DDR_INIT_ADDR,DDR Training Initialization Address" line.long 0x04 "DDR_INIT_EXT_ADDRESS,DDR Training Initialization Extended Address" bitfld.long 0x04 31. " UIA ,Use initialization address" "Default,Initialization" hexmask.long.byte 0x04 0.--7. 0x01 " INIT_EXT_ADDR ,Initialization extended address" group.long 0x160++0x07 line.long 0x00 "TIMING_CFG_4,DDR SDRAM Timing Configuration 4" bitfld.long 0x00 28.--31. " RWT ,Read-to-write turnaround for same chip select" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT ,Write-to-read turnaround for same chip select" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT ,Read-to-read turnaround for same chip select" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT ,Write-to-write turnaround for same chip select" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 14.--15. " EXT_RWT ,Extended read-to-write turnaround (t_RTW)" "0 clocks,1 clocks,2 clocks,3 clocks" bitfld.long 0x00 12. " EXT_WRT ,Extended write-to-read turnaround" "0 clocks,4 clocks" newline bitfld.long 0x00 10. " EXT_RRT ,Extended read-to-read turnaround" "0 clocks,4 clocks" bitfld.long 0x00 8. " EXT_WWT ,Extended write-to-write turnaround" "0 clocks,4 clocks" bitfld.long 0x00 4. " EXT_REFINT ,Refresh interval" "0 clocks,65536 clocks" newline bitfld.long 0x00 0.--1. " DLL_LOCK ,DDR SDRAM DLL lock time" "200 clocks,512 clocks,1024 clocks,?..." line.long 0x04 "DDR_TIMING_CFG_5,DDR SDRAM Timing Configuration 5" bitfld.long 0x04 24.--28. " RODT_ON ,Read to ODT on" "CASLAT-WR_LAT,0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,?..." bitfld.long 0x04 20.--22. " RODT_OFF ,Read to ODT off" "4 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" bitfld.long 0x04 12.--16. " WODT_ON ,Write to ODT on" "0 clocks,0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,?..." newline bitfld.long 0x04 8.--10. " WODT_OFF ,Write to ODT off" "4 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks" sif !cpuis("LS10?6*") group.long 0x168++0x03 line.long 0x00 "DDR_TIMING_CFG_6,DDR SDRAM Timing Configuration 6" bitfld.long 0x00 24.--28. " HS_CASLAT ,MCAS_B latency from READ command while DDR controller is operating at half frequency" "Full speed value,,,,,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,?..." bitfld.long 0x00 19.--23. " HS_WRLAT ,Write latency while DDR controller is operating at half frequency" "Full speed value,16 clocks,,17 clocks,,18 clocks,,,,,5 clocks,,6 clocks,,7 clocks,?..." bitfld.long 0x00 12.--16. " HS_WRREC ,Last data to precharge minimum interval (t_WR) while DDR controller is operating at half frequency" "Full speed value,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" endif if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x16C++0x03 line.long 0x00 "DDR_TIMING_CFG_7,DDR SDRAM Timing Configuration 7" bitfld.long 0x00 28.--29. " CKE_RST ,CKE reset time (t_XPR)" "200 clocks,256 clocks,512 clocks,1024 clocks" bitfld.long 0x00 24.--27. " CKSRE ,Valid clock after self refresh entry (t_CKSRE)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,32 clocks" bitfld.long 0x00 20.--23. " CKSRX ,Valid clock after self refresh exit (t_CKSRX)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,27 clocks" newline bitfld.long 0x00 16.--19. " PAR_LAT ,Number of cycles to be used for the parity latency for DDR4 memories" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,?..." bitfld.long 0x00 4.--7. " CS_TO_CMD ,Number of cycles from a chip select until the command is launched" "Disabled,1 clock,2 clocks,,,,,7 clocks,8 clocks,?..." else group.long 0x16C++0x03 line.long 0x00 "DDR_TIMING_CFG_7,DDR SDRAM Timing Configuration 7" bitfld.long 0x00 28.--29. " CKE_RST ,CKE reset time (t_XPR)" "200 clocks,256 clocks,512 clocks,1024 clocks" bitfld.long 0x00 24.--27. " CKSRE ,Valid clock after self refresh entry (t_CKSRE)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,32 clocks" bitfld.long 0x00 20.--23. " CKSRX ,Valid clock after self refresh exit (t_CKSRX)" "15 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,27 clocks" endif group.long 0x170++0x03 line.long 0x00 "DDR_ZQ_CNTL,DDR ZQ Calibration Control" bitfld.long 0x00 31. " ZQ_EN ,ZQ calibration enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " ZQINIT ,POR ZQ calibration time (t_ZQinit)" ",,,,,,,128 clocks,256 clocks,512 clocks,1024 clocks,?..." bitfld.long 0x00 16.--19. " ZQOPER ,Normal operation full calibration time (t_ZQoper)" ",,,,,,,128 clocks,256 clocks,512 clocks,1024 clocks,?..." newline bitfld.long 0x00 8.--11. " ZQCS ,Normal operation short calibration time (t_ZQCS)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,512 clocks,?..." bitfld.long 0x00 0.--3. " ZQCS_INT ,ZQCS interval. Determines the number of refresh sequences that will pass between each ZQCS calibration" "32,64,128,256,512,1024,2048,4096,8192,16384,32768,,,,,Disabled" if (((per.l.be(ad:0x01080000+0x174))&0x80000000)==0x80000000) group.long 0x174++0x03 line.long 0x00 "DDR_WRLVL_CNTL,DDR Write Leveling Control" bitfld.long 0x00 31. " WRLVL_EN ,Write leveling enable" "Disabled,Enabled" rbitfld.long 0x00 30. " WRLVL_DONE ,Write leveling done" "Not completed,Completed" bitfld.long 0x00 24.--26. " WRLVL_MRD ,First DQS pulse rising edge after margining mode is programmed (t_WL_MRD)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" newline bitfld.long 0x00 20.--22. " WRLVL_ODTEN ,ODT delay after margining mode is programmed (t_WL_ODTEN)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x00 16.--18. " WRLVL_DQSEN ,DQS/DQS_B delay after margining mode is programmed (t_WL_DQSEN)" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x00 12.--15. " WRLVL_SMPL ,Write leveling sample time" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--10. " WRLVL_WLR ,Write leveling repetition time" "1,2,4,8,16,32,64,128" bitfld.long 0x00 0.--4. " WRLVL_START ,Write leveling start time (delay) for DQS[0]" "0,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" else group.long 0x174++0x03 line.long 0x00 "DDR_WRLVL_CNTL,DDR Write Leveling Control" bitfld.long 0x00 31. " WRLVL_EN ,Write leveling enable" "Disabled,Enabled" rbitfld.long 0x00 30. " WRLVL_DONE ,Write leveling done" "Not completed,Completed" bitfld.long 0x00 0.--4. " WRLVL_START ,Write leveling start time (delay) for DQS[0]" "0,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" endif group.long 0x17C++0x0B line.long 0x00 "DDR_SR_CNTR,DDR Self Refresh Counter" bitfld.long 0x00 16.--19. " SR_IT ,Self refresh idle threshold number of DRAM cycles" "Disabled,2^10,2^12,2^14,2^16,2^18,2^20,2^22,2^24,2^26,2^28,2^30,?..." line.long 0x04 "DDR_SDRAM_RCW_1,DDR Register Control Words 1" bitfld.long 0x04 28.--31. " RCW0 ,Register control word 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " RCW1 ,Register control word 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " RCW2 ,Register control word 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. " RCW3 ,Register control word 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. " RCW4 ,Register control word 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " RCW5 ,Register control word 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " RCW6 ,Register control word 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " RCW7 ,Register control word 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DDR_SDRAM_RCW_2,DDR Register Control Words 2" bitfld.long 0x08 28.--31. " RCW8 ,Register control word 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " RCW9 ,Register control word 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " RCW10 ,Register control word 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. " RCW11 ,Register control word 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " RCW12 ,Register control word 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " RCW13 ,Register control word 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 4.--7. " RCW14 ,Register control word 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " RCW15 ,Register control word 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x190++0x07 line.long 0x00 "DDR_WRLVL_CNTL_2,DDR Write Leveling Control 2" bitfld.long 0x00 24.--28. " WRLVL_START_1 ,Write leveling start time for DQS[1]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x00 16.--20. " WRLVL_START_2 ,Write leveling start time for DQS[2]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x00 8.--12. " WRLVL_START_3 ,Write leveling start time for DQS[3]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" newline bitfld.long 0x00 0.--4. " WRLVL_START_4 ,Write leveling start time for DQS[4]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" line.long 0x04 "DDR_WRLVL_CNTL_3,DDR Write Leveling Control 3" bitfld.long 0x04 24.--28. " WRLVL_START_5 ,Write leveling start time for DQS[5]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x04 16.--20. " WRLVL_START_6 ,Write leveling start time for DQS[6]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" bitfld.long 0x04 8.--12. " WRLVL_START_7 ,Write leveling start time for DQS[7]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" newline bitfld.long 0x04 0.--4. " WRLVL_START_8 ,Write leveling start time for DQS[8]" "WRLVL_START,1/8,1/4,3/8,1/2,5/8,3/4,7/8,1,9/8,5/4,11/8,3/2,13/8,7/4,15/8,2,17/8,9/4,19/8,5/2,21/8,16/4,23/8,3,25/8,13/4,27/8,7/2,29/8,15/4,31/8" group.long 0x1A0++0x0F line.long 0x00 "DDR_SDRAM_RCW_3,DDR Register Control Words 3" hexmask.long.byte 0x00 24.--31. 1. " RCW1X ,Register control word 1X" hexmask.long.byte 0x00 16.--23. 1. " RCW2X ,Register control word 2X" hexmask.long.byte 0x00 8.--15. 1. " RCW3X ,Register control word 3X" newline hexmask.long.byte 0x00 0.--7. 1. " RCW4X ,Register control word 4X" line.long 0x04 "DDR_SDRAM_RCW_4,DDR Register Control Words 4" hexmask.long.byte 0x04 24.--31. 1. " RCW5X ,Register control word 5X" hexmask.long.byte 0x04 16.--23. 1. " RCW6X ,Register control word 6X" hexmask.long.byte 0x04 8.--15. 1. " RCW7X ,Register control word 7X" newline hexmask.long.byte 0x04 0.--7. 1. " RCW8X ,Register control word 8X" line.long 0x08 "DDR_SDRAM_RCW_5,DDR Register Control Words 5" hexmask.long.byte 0x08 24.--31. 1. " RCW9X ,Register control word 9X" hexmask.long.byte 0x08 16.--23. 1. " RCW10X ,Register control word 10X" hexmask.long.byte 0x08 8.--15. 1. " RCW11X ,Register control word 11X" newline hexmask.long.byte 0x08 0.--7. 1. " RCW12X ,Register control word 12X" line.long 0x0C "DDR_SDRAM_RCW_6,DDR Register Control Words 6" hexmask.long.byte 0x0C 24.--31. 1. " RCW13X ,Register control word 13X" hexmask.long.byte 0x0C 16.--23. 1. " RCW14X ,Register control word 14X" hexmask.long.byte 0x0C 8.--15. 1. " RCW15X ,Register control word 15X" group.long 0x200++0x17 line.long 0x00 "DDR_SDRAM_MODE_3,DDR SDRAM Mode Configuration 3" hexmask.long.word 0x00 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x00 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x04 "DDR_SDRAM_MODE_4,DDR SDRAM Mode Configuration 4" hexmask.long.word 0x04 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x04 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x08 "DDR_SDRAM_MODE_5,DDR SDRAM Mode Configuration 5" hexmask.long.word 0x08 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x08 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x0C "DDR_SDRAM_MODE_6,DDR SDRAM Mode Configuration 6" hexmask.long.word 0x0C 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x0C 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" line.long 0x10 "DDR_SDRAM_MODE_7,DDR SDRAM Mode Configuration 7" hexmask.long.word 0x10 16.--31. 1. " ESDMODE ,Extended SDRAM mode" hexmask.long.word 0x10 0.--15. 1. " SDMODE ,SDRAM mode" line.long 0x14 "DDR_SDRAM_MODE_8,DDR SDRAM Mode Configuration 8" hexmask.long.word 0x14 16.--31. 1. " ESDMODE2 ,Extended SDRAM mode 2" hexmask.long.word 0x14 0.--15. 1. " ESDMODE3 ,Extended SDRAM mode 3" group.long 0x220++0x1F line.long 0x00 "DDR_SDRAM_MODE_9,DDR SDRAM Mode Configuration 9" hexmask.long.word 0x00 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x00 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x04 "DDR_SDRAM_MODE_10,DDR SDRAM Mode Configuration 10" hexmask.long.word 0x04 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x04 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x08 "DDR_SDRAM_MODE_11,DDR SDRAM Mode Configuration 11" hexmask.long.word 0x08 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x08 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x0C "DDR_SDRAM_MODE_12,DDR SDRAM Mode Configuration 12" hexmask.long.word 0x0C 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x0C 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x10 "DDR_SDRAM_MODE_13,DDR SDRAM Mode Configuration 13" hexmask.long.word 0x10 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x10 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x14 "DDR_SDRAM_MODE_14,DDR SDRAM Mode Configuration 14" hexmask.long.word 0x14 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x14 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" line.long 0x18 "DDR_SDRAM_MODE_15,DDR SDRAM Mode Configuration 15" hexmask.long.word 0x18 16.--31. 1. " ESDMODE4 ,Extended SDRAM mode 4" hexmask.long.word 0x18 0.--15. 1. " ESDMODE5 ,Extended SDRAM mode 5" line.long 0x1C "DDR_SDRAM_MODE_16,DDR SDRAM Mode Configuration 16" hexmask.long.word 0x1C 16.--31. 1. " ESDMODE6 ,Extended SDRAM mode 6" hexmask.long.word 0x1C 0.--15. 1. " ESDMODE7 ,Extended SDRAM mode 7" sif cpuis("LS10?6*") if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x250++0x03 line.long 0x00 "TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 28.--31. " RWT_BG ,Read-to-write turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT_BG ,Write-to-read turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT_BG ,Read-to-read turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT_BG ,Write-to-write turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 12.--15. " ACTTOACT_BG ,Activate-to-activate interval for the same bank group(t_RRD_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 8.--11. " WRTORD_BG ,Last write data pair to read command issue interval for the same bank group(t_WTR_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x00 7. " EXT_WRTORD_BG ,Extended write-to-read same bank group" "Disabled,16 clocks" bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. When 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" else group.long 0x250++0x03 line.long 0x00 "TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 28.--31. " RWT_BG ,Read-to-write turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT_BG ,Write-to-read turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT_BG ,Read-to-read turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT_BG ,Write-to-write turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 7. " EXT_WRTORD_BG ,Extended write-to-read same bank group" "Disabled,16 clocks" bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. When 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" endif else if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x7000000) group.long 0x250++0x03 line.long 0x00 "TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. When 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" elif (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x5000000) group.long 0x250++0x03 line.long 0x00 "TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 28.--31. " RWT_BG ,Read-to-write turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT_BG ,Write-to-read turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT_BG ,Read-to-read turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT_BG ,Write-to-write turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 12.--15. " ACTTOACT_BG ,Activate-to-activate interval for the same bank group(t_RRD_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 8.--11. " WRTORD_BG ,Last write data pair to read command issue interval for the same bank group(t_WTR_L)" "Disabled,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" newline bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. When 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" else group.long 0x250++0x03 line.long 0x00 "TIMING_CFG_8,DDR SDRAM Timing Configuration 8" bitfld.long 0x00 28.--31. " RWT_BG ,Read-to-write turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 24.--27. " WRT_BG ,Write-to-read turnaround for same chip select and same bank group" "Default,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks" bitfld.long 0x00 20.--23. " RRT_BG ,Read-to-read turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" newline bitfld.long 0x00 16.--19. " WWT_BG ,Write-to-write turnaround for same chip select and same bank group" "BL/2 clocks,BL/2+1 clock,BL/2+2 clocks,BL/2+3 clocks,BL/2+4 clocks,BL/2+5 clocks,BL/2+6 clocks,BL/2+7 clocks,BL/2+8 clocks,BL/2+9 clocks,BL/2+10 clocks,BL/2+11 clocks,BL/2+12 clocks,BL/2+13 clocks,BL/2+14 clocks,BL/2+15 clocks" bitfld.long 0x00 0.--4. " PRE_ALL_REC ,Precharge all-to-activate interval. When 0 external value from TIMING_CFG_1[PRETOACT] is used" "External,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks" endif endif group.long 0x260++0x03 line.long 0x00 "DDR_SDRAM_CFG_3,DDR SDRAM Control Configuration 3" bitfld.long 0x00 31. " DDRC_RST ,DDR controller reset" "No reset,Reset" bitfld.long 0x00 30. " ECC_FIX_EN ,ECC fixing enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " ECC_SCRUB_INT ,ECC scrubbing interval" "Disabled,1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384" newline sif cpuis("LS10?6*") bitfld.long 0x00 17. " WR_PRE ,Write preamble" "1 t_ck,2 t_ck" newline bitfld.long 0x00 16. " RD_PRE ,Read preamble" "1 t_ck,2 t_ck" newline endif bitfld.long 0x00 12.--13. " DM_CFG ,Data mask config" "Normal data masks,,Data bus inversion,Not used" bitfld.long 0x00 8.--9. " REF_MODE ,Refresh mode" "Disabled,2x,4x,?..." bitfld.long 0x00 0. " DIS_MRS_PAR ,Disable MRS on parity error" "No,Yes" group.long 0x400++0x0F line.long 0x00 "DDR_DQ_MAP0,DQ Mapping Register 0" bitfld.long 0x00 26.--31. " DQ_0_3 ,DQ[0:3] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 20.--25. " DQ_4_7 ,DQ[4:7] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 14.--19. " DQ_8_11 ,DQ[8:11] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x00 8.--13. " DQ_12_15 ,DQ[12:15] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x00 2.--7. " DQ_16_19 ,DQ[16:19] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x04 "DDR_DQ_MAP1,DQ Mapping Register 1" bitfld.long 0x04 26.--31. " DQ_20_23 ,DQ[20:23] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 20.--25. " DQ_24_27 ,DQ[24:27] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 14.--19. " DQ_28_31 ,DQ[28:31] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x04 8.--13. " DQ_32_35 ,DQ[32:35] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x04 2.--7. " DQ_36_39 ,DQ[36:39] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x08 "DDR_DQ_MAP2,DQ Mapping Register 2" bitfld.long 0x08 26.--31. " DQ_40_43 ,DQ[40:43] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 20.--25. " DQ_44_47 ,DQ[44:47] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 14.--19. " DQ_48_51 ,DQ[48:51] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x08 8.--13. " DQ_52_55 ,DQ[52:55] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x08 2.--7. " DQ_56_59 ,DQ[56:59] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." line.long 0x0C "DDR_DQ_MAP3,DQ Mapping Register 3" bitfld.long 0x0C 26.--31. " DQ_60_63 ,DQ[60:63] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x0C 20.--25. " ECC_0_3 ,ECC[0:3] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." bitfld.long 0x0C 14.--19. " ECC_4_7 ,ECC[4:7] mapping" "0-1-2-3,0-1-2-3,0-1-3-2,0-2-1-3,0-2-3-1,0-3-1-2,0-3-2-1,1-0-2-3,1-0-3-2,1-2-0-3,1-2-3-0,1-3-0-2,1-3-2-0,2-0-1-3,2-0-3-1,2-1-0-3,2-1-3-0,2-3-0-1,2-3-1-0,3-0-1-2,3-0-2-1,3-1-0-2,3-1-2-0,3-2-0-1,3-2-1-0,,,,,,,,,4-5-6-7,4-5-7-6,4-6-5-7,4-6-7-5,4-7-5-6,4-7-6-5,5-4-6-7,5-4-7-6,5-6-4-7,5-6-7-4,5-7-4-6,5-7-6-4,6-4-5-7,6-4-7-5,6-5-4-7,6-5-7-4,6-7-4-5,6-7-5-4,7-4-5-6,7-4-6-5,7-5-4-6,7-5-6-4,7-6-4-5,7-6-5-4,?..." newline bitfld.long 0x0C 0. " ORS ,Odd rank swizzle" "Disabled,Enabled" rgroup.long 0xB20++0x03 line.long 0x00 "DDRDSR_1,DDR Debug Status Register 1" bitfld.long 0x00 15. " CZ ,Current setting of driver command impedance" "High,Low" bitfld.long 0x00 7. " DZ ,Current setting of driver data impedance" "High,Low" group.long 0xB24++0x07 line.long 0x00 "DDRDSR_2,DDR Debug Status Register 2" bitfld.long 0x00 31. " CLKZ ,Current setting of driver clock impedance" "High,Low" eventfld.long 0x00 1. " RPD_ST ,Rapid clear of memory start" "Not started,Started" eventfld.long 0x00 0. " RPD_END ,Rapid clear of memory end" "Not completed,Completed" line.long 0x04 "DDRCDR_1,DDR Control Driver Register 1" bitfld.long 0x04 31. " DHC_EN ,DDR driver hardware compensation enable" "Disabled,Enabled" bitfld.long 0x04 18.--19. " ODT ,ODT termination value for IOs" "0,1,2,3" bitfld.long 0x04 17. " DSO_C_EN ,Driver software override enable for address/command" "Disabled,Enabled" newline bitfld.long 0x04 16. " DSO_D_EN ,Driver software override enable for data" "Disabled,Enabled" bitfld.long 0x04 15. " DSO_CZ ,DDR driver software command impedance override" "Highest,Lowest" bitfld.long 0x04 7. " DSO_DZ ,Driver software data impedance override" "Highest,Lowest" if (((per.l.be(ad:0x01080000+0x110))&0x7000000)==0x7000000) group.long 0xB2C++0x03 line.long 0x00 "DDRCDR_2,DDR Control Driver Register 2" bitfld.long 0x00 31. " DSO_CLK_EN ,Driver software override enable for clocks" "Disabled,Enabled" bitfld.long 0x00 27. " DSO_CLKZ ,Driver software clocks impedance override" "Highest,Lowest" bitfld.long 0x00 15. " VREF_OVRD_EN ,Internal VRef generation override enable. When 0 if DDR4 mode an internal VRef is generated an used for the data bus" "Not overridden,Overridden" newline bitfld.long 0x00 8.--13. " VREF_OVRD_VAL ,Defines the override value to use for the internal VRef if VREF_OVRD_EN is set" "37%,38%,39%,40%,41%,42%,43%,44%,45%,46%,47%,48%,49%,50%,51%,52%,53%,54%,55%,56%,57%,58%,59%,60%,61%,62%,63%,64%,65%,66%,67%,68%,69%,70%,71%,72%,73%,74%,75%,76%,77%,78%,79%,80%,81%,82%,83%,84%,85%,86%,87%,88%,89%,90%,91%,92%,93%,94%,95%,96%,97%,98%,99%,100%" sif cpuis("LS10?6*") bitfld.long 0x00 7. " VREF_TRAIN_EN ,Enable DRAM VRef training" "Disabled,Enabled" else bitfld.long 0x00 7. " VREF_TRAIN_EN ,Enable DRAM VRef training" "Disabled,?..." endif bitfld.long 0x00 6. " VREF_DRAM_RANGE ,The VRef range during DRAM training" "Range1,Range2" bitfld.long 0x00 0. " ODT ,ODT termination value for IOs" "0,1" else group.long 0xB2C++0x03 line.long 0x00 "DDRCDR_2,DDR Control Driver Register 2" bitfld.long 0x00 31. " DSO_CLK_EN ,Driver software override enable for clocks" "Disabled,Enabled" bitfld.long 0x00 27. " DSO_CLKZ ,Driver software clocks impedance override" "Highest,Lowest" bitfld.long 0x00 15. " VREF_OVRD_EN ,Internal VRef generation override enable. When 0 if DDR4 mode an internal VRef is generated an used for the data bus" "Not overridden,Overridden" newline bitfld.long 0x00 8.--13. " VREF_OVRD_VAL ,Defines the override value to use for the internal VRef if VREF_OVRD_EN is set" "37%,38%,39%,40%,41%,42%,43%,44%,45%,46%,47%,48%,49%,50%,51%,52%,53%,54%,55%,56%,57%,58%,59%,60%,61%,62%,63%,64%,65%,66%,67%,68%,69%,70%,71%,72%,73%,74%,75%,76%,77%,78%,79%,80%,81%,82%,83%,84%,85%,86%,87%,88%,89%,90%,91%,92%,93%,94%,95%,96%,97%,98%,99%,100%" bitfld.long 0x00 7. " VREF_TRAIN_EN ,Enable DRAM VRef training" "Disabled,Enabled" bitfld.long 0x00 6. " VREF_DRAM_RANGE ,The VRef range during DRAM training" "Range1,Range2" newline bitfld.long 0x00 0. " ODT ,ODT termination value for IOs" "0,1" endif rgroup.long 0xBF8++0x07 line.long 0x00 "DDR_IP_REV1,DDR IP Block Revision 1" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "DDR_IP_REV2,DDR IP Block Revision 2" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,IP block integration options" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,IP block configuration options" if (((per.l.be(ad:0x01080000+0xD00))&0x3000000)==0x00) group.long 0xD00++0x03 line.long 0x00 "DDR_MTCR,DDR Memory Test Control Register" bitfld.long 0x00 31. " MT_EN ,Memory test enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MT_TYP ,Memory test type" "Writes and reads,Writes only,Reads only,?..." bitfld.long 0x00 16.--19. " MT_TRNARND ,Memory test turnaround" "Entire mem write then read,1 transaction each,2 transaction each,4 transaction each,?..." newline bitfld.long 0x00 9. " MT_ADDR_EN ,Memory test address range enable" "Disabled,Enabled" bitfld.long 0x00 0. " MT_STAT ,Memory test status" "No fail,Fail" else group.long 0xD00++0x03 line.long 0x00 "DDR_MTCR,DDR Memory Test Control Register" bitfld.long 0x00 31. " MT_EN ,Memory test enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MT_TYP ,Memory test type" "Writes and reads,Writes only,Reads only,?..." bitfld.long 0x00 9. " MT_ADDR_EN ,Memory test address range enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " MT_STAT ,Memory test status" "No fail,Fail" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD20++0x03 line.long 0x00 "DDR_MTP0,DDR Memory Test Pattern 0 Register" else hgroup.long 0xD20++0x03 hide.long 0x00 "DDR_MTP0,DDR Memory Test Pattern 0 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD24++0x03 line.long 0x00 "DDR_MTP1,DDR Memory Test Pattern 1 Register" else hgroup.long 0xD24++0x03 hide.long 0x00 "DDR_MTP1,DDR Memory Test Pattern 1 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD28++0x03 line.long 0x00 "DDR_MTP2,DDR Memory Test Pattern 2 Register" else hgroup.long 0xD28++0x03 hide.long 0x00 "DDR_MTP2,DDR Memory Test Pattern 2 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD2C++0x03 line.long 0x00 "DDR_MTP3,DDR Memory Test Pattern 3 Register" else hgroup.long 0xD2C++0x03 hide.long 0x00 "DDR_MTP3,DDR Memory Test Pattern 3 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD30++0x03 line.long 0x00 "DDR_MTP4,DDR Memory Test Pattern 4 Register" else hgroup.long 0xD30++0x03 hide.long 0x00 "DDR_MTP4,DDR Memory Test Pattern 4 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD34++0x03 line.long 0x00 "DDR_MTP5,DDR Memory Test Pattern 5 Register" else hgroup.long 0xD34++0x03 hide.long 0x00 "DDR_MTP5,DDR Memory Test Pattern 5 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD38++0x03 line.long 0x00 "DDR_MTP6,DDR Memory Test Pattern 6 Register" else hgroup.long 0xD38++0x03 hide.long 0x00 "DDR_MTP6,DDR Memory Test Pattern 6 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD3C++0x03 line.long 0x00 "DDR_MTP7,DDR Memory Test Pattern 7 Register" else hgroup.long 0xD3C++0x03 hide.long 0x00 "DDR_MTP7,DDR Memory Test Pattern 7 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD40++0x03 line.long 0x00 "DDR_MTP8,DDR Memory Test Pattern 8 Register" else hgroup.long 0xD40++0x03 hide.long 0x00 "DDR_MTP8,DDR Memory Test Pattern 8 Register" endif if (((per.l.be(ad:0x01080000+0xD00))&0x80000000)==0x80000000) group.long 0xD44++0x03 line.long 0x00 "DDR_MTP9,DDR Memory Test Pattern 9 Register" else hgroup.long 0xD44++0x03 hide.long 0x00 "DDR_MTP9,DDR Memory Test Pattern 9 Register" endif group.long 0xD60++0x0F line.long 0x00 "DDR_MT_ST_EXT_ADDR,DDR Memory Test Start Extended Address" hexmask.long.byte 0x00 0.--7. 1. " MT_ST_EXT_ADDR ,This field represents the starting extended address" line.long 0x04 "DDR_MT_ST_ADDR,DDR Memory Test Start Address" line.long 0x08 "DDR_MT_END_EXT_ADDR,DDR Memory Test End Extended Address" hexmask.long.byte 0x08 0.--7. 1. " MT_END_EXT_ADDR ,This field represents the ending extended address" line.long 0x0C "DDR_MT_END_ADDR,DDR Memory Test End Address" group.long 0xE00++0x07 line.long 0x00 "DATA_ERR_INJECT_HI,Memory Data Path Error Injection Mask High" line.long 0x04 "DATA_ERR_INJECT_LO,Memory Data Path Error Injection Mask Low" group.long 0xE08++0x03 line.long 0x00 "ECC_ERR_INJECT,Memory Data Path Error Injection Mask ECC" bitfld.long 0x00 16. " APIEN ,Address parity error injection enable" "Disabled,Enabled" bitfld.long 0x00 9. " EMB ,ECC mirror byte enable" "Disabled,Enabled" bitfld.long 0x00 8. " EIEN ,Error injection enable" "Disabled,Enabled" newline hexmask.long.byte 0x00 0.--7. 1. " EEIM ,ECC error injection mask" group.long 0xE20++0x0B line.long 0x00 "CAPTURE_DATA_HI,Memory Data Path Read Capture High" line.long 0x04 "CAPTURE_DATA_LO,Memory Data Path Read Capture Low" line.long 0x08 "CAPTURE_ECC,Memory Data Path Read Capture ECC" group.long 0xE40++0x1B line.long 0x00 "ERR_DETECT,Memory Error Detect" eventfld.long 0x00 31. " MME ,Multiple memory errors" "No error,Error" eventfld.long 0x00 12. " SSBE ,Scrubbed single-bit ECC error" "No error,Error" eventfld.long 0x00 8. " APE ,Address parity error" "No error,Error" newline eventfld.long 0x00 7. " ACE ,Automatic calibration error" "No error,Error" eventfld.long 0x00 4. " CDE ,Corrupted data error" "No error,Error" eventfld.long 0x00 3. " MBE ,Multiple-bit error" "No error,Error" newline eventfld.long 0x00 2. " SBE ,Single-bit ECC error" "No error,Error" eventfld.long 0x00 0. " MSE ,Memory select error" "No error,Error" line.long 0x04 "ERR_DISABLE,Memory Error Disable" bitfld.long 0x04 12. " SSBED ,Scrubbed single-bit ECC error disable" "No,Yes" bitfld.long 0x04 8. " APED ,Address parity error disable" "No,Yes" bitfld.long 0x04 7. " ACED ,Automatic calibration error disable" "No,Yes" newline bitfld.long 0x04 4. " CDED ,Corrupted data error disable" "No,Yes" bitfld.long 0x04 3. " MBED ,Multiple-bit ECC error disable" "No,Yes" bitfld.long 0x04 2. " SBED ,Single-bit ECC error disable" "No,Yes" newline bitfld.long 0x04 0. " MSED ,Memory select error disable" "No,Yes" line.long 0x08 "ERR_INT_EN,Memory Error Interrupt Enable" bitfld.long 0x08 12. " SSBEE ,Scrubbed single-bit ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " APEE ,Address parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " ACEE ,Automatic calibration error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CDEE ,Corrupted data error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 3. " MBEE ,Multiple-bit ECC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " SBEE ,Single-bit ECC error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " MSEE ,Memory select error interrupt enable" "Disabled,Enabled" line.long 0x0C "CAPTURE_ATTRIBUTES,Memory Error Attributes Capture" bitfld.long 0x0C 28.--30. " BNUM ,Data beat number" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. " TSIZ ,Transaction size for the error in double words" "8 double words,1 double word,2 double words,3 double words,4 double words,5 double words,6 double words,7 double words" hexmask.long.byte 0x0C 16.--23. 1. " TSRC ,Transaction source for the error" newline bitfld.long 0x0C 12.--13. " TTYP ,Transaction type for the error" ",Write,Read,Read-modify-write" bitfld.long 0x0C 0. " VLD ,Valid" "Not valid,Valid" line.long 0x10 "CAPTURE_ADDRESS,Memory Error Address Capture" line.long 0x14 "CAPTURE_EXT_ADDRESS,Memory error extended address capture" hexmask.long.byte 0x14 0.--7. 1. " CEADDR ,Captured extended address" line.long 0x18 "ERR_SBE,Single-Bit ECC Memory Error Management" hexmask.long.byte 0x18 24.--31. 1. " SSBET ,Scrubbed single-bit error threshold" hexmask.long.byte 0x18 16.--23. 1. " SBET ,Single-bit error threshold" hexmask.long.byte 0x18 8.--15. 1. " SSBEC ,Scrubbed single-bit error counter" newline hexmask.long.byte 0x18 0.--7. 1. " SBEC ,Single-bit error counter" endian.le width 0x0B tree.end endif endif sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") tree.open "DMAMUX (Direct Memory Access Multiplexer)" tree "DMAMUX_1" base ad:0x02C10000 width 17. endian.be sif cpuis("LS1012*") group.byte 0x0++0x00 line.byte 0x00 "CHCFG3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x1++0x00 line.byte 0x00 "CHCFG2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x2++0x00 line.byte 0x00 "CHCFG1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x3++0x00 line.byte 0x00 "CHCFG0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x4++0x00 line.byte 0x00 "CHCFG7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x5++0x00 line.byte 0x00 "CHCFG6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x6++0x00 line.byte 0x00 "CHCFG5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x7++0x00 line.byte 0x00 "CHCFG4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x8++0x00 line.byte 0x00 "CHCFG11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0x9++0x00 line.byte 0x00 "CHCFG10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xA++0x00 line.byte 0x00 "CHCFG9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xB++0x00 line.byte 0x00 "CHCFG8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xC++0x00 line.byte 0x00 "CHCFG15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xD++0x00 line.byte 0x00 "CHCFG14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xE++0x00 line.byte 0x00 "CHCFG13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." group.byte 0xF++0x00 line.byte 0x00 "CHCFG12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",DMA req EPU,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],,,,,FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],,,,,,,,,,,,,,SPI1 RFDF,SPI1 CMD,SPI TF,?..." else group.byte 0x0++0x00 line.byte 0x00 "DMAMUX1_CHCFG0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x1++0x00 line.byte 0x00 "DMAMUX1_CHCFG1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x2++0x00 line.byte 0x00 "DMAMUX1_CHCFG2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x3++0x00 line.byte 0x00 "DMAMUX1_CHCFG3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x4++0x00 line.byte 0x00 "DMAMUX1_CHCFG4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x5++0x00 line.byte 0x00 "DMAMUX1_CHCFG5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x6++0x00 line.byte 0x00 "DMAMUX1_CHCFG6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x7++0x00 line.byte 0x00 "DMAMUX1_CHCFG7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x8++0x00 line.byte 0x00 "DMAMUX1_CHCFG8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0x9++0x00 line.byte 0x00 "DMAMUX1_CHCFG9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xA++0x00 line.byte 0x00 "DMAMUX1_CHCFG10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xB++0x00 line.byte 0x00 "DMAMUX1_CHCFG11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xC++0x00 line.byte 0x00 "DMAMUX1_CHCFG12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xD++0x00 line.byte 0x00 "DMAMUX1_CHCFG13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xE++0x00 line.byte 0x00 "DMAMUX1_CHCFG14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif group.byte 0xF++0x00 line.byte 0x00 "DMAMUX1_CHCFG15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,FlexTimer6[0],FlexTimer6[1],,,,,,,FlexTimer5[0],FlexTimer5[1],,,,,,,FlexTimer4[0],FlexTimer4[1],FlexTimer4[2],FlexTimer4[3],FlexTimer4[4],FlexTimer4[5],FlexTimer4[6],FlexTimer4[7],FlexTimer3[0],FlexTimer3[1],FlexTimer3[2],FlexTimer3[3],FlexTimer3[4],FlexTimer3[5],FlexTimer3[6],FlexTimer3[7],FlexTimer2[0],FlexTimer2[1],FlexTimer2[2],FlexTimer2[3],FlexTimer2[4],FlexTimer2[5],FlexTimer2[6],FlexTimer2[7],FlexTimer1[0],FlexTimer1[1],FlexTimer1[2],FlexTimer1[3],FlexTimer1[4],FlexTimer1[5],FlexTimer1[6],FlexTimer1[7],,,,,,,,,SPI1 DDIF,SPI1 RFDF,SPI1 CMD,SPI1 TF,Always enabled" endif endif endian.le width 0x0B tree.end tree "DMAMUX_2" base ad:0x02C20000 width 17. endian.be sif cpuis("LS1012*") group.byte 0x10++0x00 line.byte 0x00 "CHCFG19,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x11++0x00 line.byte 0x00 "CHCFG18,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x12++0x00 line.byte 0x00 "CHCFG17,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x13++0x00 line.byte 0x00 "CHCFG16,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x14++0x00 line.byte 0x00 "CHCFG23,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x15++0x00 line.byte 0x00 "CHCFG22,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x16++0x00 line.byte 0x00 "CHCFG21,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x17++0x00 line.byte 0x00 "CHCFG20,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x18++0x00 line.byte 0x00 "CHCFG27,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x19++0x00 line.byte 0x00 "CHCFG26,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1A++0x00 line.byte 0x00 "CHCFG25,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1B++0x00 line.byte 0x00 "CHCFG24,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1C++0x00 line.byte 0x00 "CHCFG31,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1D++0x00 line.byte 0x00 "CHCFG30,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1E++0x00 line.byte 0x00 "CHCFG29,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." group.byte 0x1F++0x00 line.byte 0x00 "CHCFG28,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA channel enable" "Disabled,Enabled" newline bitfld.byte 0x00 0.--5. " SOURCE ,DMA channel source (Slot)" ",,,,,,,,,,,,,,,,,,,QuadSPI RFDF,,,,,,,,,,,,,,,SAI5 RX,SAI5 TX,IIC2 RX,IIC TX,IIC1 RX,IIC1 TX,SAI4 RX,SAI4 TX,SAI3 RX,SAI3 TX,SAI2 RX,SAI2 TX,SAI1 RX,SAI1 TX,?..." else group.byte 0x0++0x00 line.byte 0x00 "DMAMUX2_CHCFG0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x1++0x00 line.byte 0x00 "DMAMUX2_CHCFG1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x2++0x00 line.byte 0x00 "DMAMUX2_CHCFG2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x3++0x00 line.byte 0x00 "DMAMUX2_CHCFG3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x4++0x00 line.byte 0x00 "DMAMUX2_CHCFG4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x5++0x00 line.byte 0x00 "DMAMUX2_CHCFG5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x6++0x00 line.byte 0x00 "DMAMUX2_CHCFG6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x7++0x00 line.byte 0x00 "DMAMUX2_CHCFG7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x8++0x00 line.byte 0x00 "DMAMUX2_CHCFG8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0x9++0x00 line.byte 0x00 "DMAMUX2_CHCFG9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xA++0x00 line.byte 0x00 "DMAMUX2_CHCFG10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xB++0x00 line.byte 0x00 "DMAMUX2_CHCFG11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xC++0x00 line.byte 0x00 "DMAMUX2_CHCFG12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xD++0x00 line.byte 0x00 "DMAMUX2_CHCFG13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xE++0x00 line.byte 0x00 "DMAMUX2_CHCFG14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif group.byte 0xF++0x00 line.byte 0x00 "DMAMUX2_CHCFG15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA Channel Enable" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],?..." else bitfld.byte 0x00 0.--5. " SOURCE ,DMA Channel Source (Slot)" ",,,,,,,,,,,,,,,,,,,QSPI rfdf,,,LPUART6 RX,LPUART6 TX,LPUART5 RX,LPUART5 TX,LPUART4 RX,LPUART4 TX,LPUART3 RX,LPUART3 TX,LPUART2 RX,LPUART2 TX,LPUART1 RX,LPUART1 TX,IIC3 RX,IIC3 TX,IIC2 RX,IIC2 TX,IIC1 RX,IIC1 TX,IIC4 RX,IIC4 TX,,,,,,,FlexTimer8[0],FlexTimer8[1],,,,,,,FlexTimer7[0],FlexTimer7[1],,,,,,Always enabled" endif endif endian.le width 0x0B tree.end tree.end endif tree.open "DUART (Dual Universal Asynchronous Receiver/Transmitters)" sif cpuis("LS108?*")||cpuis("LS104?*")||cpuis("LS10?6*") tree "DUART_1" tree "UART_1" base ad:0x021C0000 width 7. if (((per.b(ad:0x021C0000+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR1,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "UTHR1,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "UDMB1,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UIER1,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "UAFR1,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UFCR1,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR1,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR1,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "UTHR1,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UDMB1,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "UIER1,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UAFR1,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "UFCR1,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR1,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0000+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x10)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Mark" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif group.byte 0x504++0x00 line.byte 0x00 "UMCR1,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" newline bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" hgroup.byte 0x505++0x00 hide.byte 0x00 "ULSR1,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "UMSR1,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "USCR1,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "UDSR1,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" width 0x0B tree.end tree "UART_2" base ad:0x021C0100 width 7. if (((per.b(ad:0x021C0100+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR2,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "UTHR2,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "UDMB2,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UIER2,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "UAFR2,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UFCR2,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR2,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR2,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "UTHR2,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UDMB2,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "UIER2,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UAFR2,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "UFCR2,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR2,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0100+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x10)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Mark" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif group.byte 0x504++0x00 line.byte 0x00 "UMCR2,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" newline bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" hgroup.byte 0x505++0x00 hide.byte 0x00 "ULSR2,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "UMSR2,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "USCR2,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "UDSR2,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" width 0x0B tree.end tree.end tree "DUART_2" tree "UART_3" base ad:0x021D0000 width 7. if (((per.b(ad:0x021D0000+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "UDLB3,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR3,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "UTHR3,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "UDMB3,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UIER3,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "UAFR3,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UFCR3,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR3,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "UDLB3,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR3,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "UTHR3,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UDMB3,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "UIER3,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UAFR3,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "UFCR3,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR3,UART Interrupt ID Register" in endif if (((per.b(ad:0x021D0000+0x503))&0x08)==0x00)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x00)&&(((per.b(ad:0x021D0000+0x503))&0x10)==0x00)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Mark" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x20)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif group.byte 0x504++0x00 line.byte 0x00 "UMCR3,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" newline bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" hgroup.byte 0x505++0x00 hide.byte 0x00 "ULSR3,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "UMSR3,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "USCR3,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "UDSR3,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" width 0x0B tree.end tree "UART_4" base ad:0x021D0100 width 7. if (((per.b(ad:0x021D0100+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "UDLB4,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR4,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "UTHR4,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "UDMB4,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UIER4,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "UAFR4,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UFCR4,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR4,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "UDLB4,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "URBR4,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "UTHR4,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "UDMB4,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "UIER4,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UAFR4,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "UFCR4,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "UIIR4,UART Interrupt ID Register" in endif if (((per.b(ad:0x021D0100+0x503))&0x08)==0x00)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x00)&&(((per.b(ad:0x021D0100+0x503))&0x10)==0x00)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Mark" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x20)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" newline bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif group.byte 0x504++0x00 line.byte 0x00 "UMCR4,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" newline bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" hgroup.byte 0x505++0x00 hide.byte 0x00 "ULSR4,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "UMSR4,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "USCR4,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "UDSR4,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" width 0x0B tree.end tree.end elif cpuis("LS1012*") tree "DUART_1" tree "UART_1" base ad:0x021C0000 width 14. endian.be if (((per.b(ad:0x021C0000+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART1_UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR1,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UTHR1,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UDMB1,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UIER1,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART1_UAFR1,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UFCR1,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR1,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR1,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART1_UTHR1,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UDMB1,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UIER1,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UAFR1,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART1_UFCR1,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR1,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0000+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART1_UMCR1,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART1_ULSR1,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART1_UMSR1,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART1_USCR1,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART1_UDSR1,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree "UART_2" base ad:0x021C0100 width 14. endian.be if (((per.b(ad:0x021C0100+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART1_UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR2,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UTHR2,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UDMB2,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UIER2,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART1_UAFR2,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UFCR2,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR2,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR2,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART1_UTHR2,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UDMB2,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UIER2,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UAFR2,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART1_UFCR2,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR2,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0100+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART1_UMCR2,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART1_ULSR2,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART1_UMSR2,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART1_USCR2,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART1_UDSR2,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree.end else tree "DUART_1" tree "UART_1" base ad:0x021C0000 width 14. endian.be if (((per.b(ad:0x021C0000+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART1_UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR1,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UTHR1,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UDMB1,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UIER1,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART1_UAFR1,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UFCR1,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR1,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UDLB1,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR1,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART1_UTHR1,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UDMB1,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UIER1,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UAFR1,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART1_UFCR1,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR1,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0000+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0000+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR1,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART1_UMCR1,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART1_ULSR1,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART1_UMSR1,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART1_USCR1,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART1_UDSR1,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree "UART_2" base ad:0x021C0100 width 14. endian.be if (((per.b(ad:0x021C0100+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART1_UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR2,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UTHR2,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UDMB2,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UIER2,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART1_UAFR2,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UFCR2,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR2,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_UDLB2,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART1_URBR2,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART1_UTHR2,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART1_UDMB2,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART1_UIER2,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UAFR2,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART1_UFCR2,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART1_UIIR2,UART Interrupt ID Register" in endif if (((per.b(ad:0x021C0100+0x503))&0x08)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021C0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021C0100+0x503))&0x20)==0x20)&&(((per.b(ad:0x021C0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART1_ULCR2,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART1_UMCR2,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART1_ULSR2,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART1_UMSR2,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART1_USCR2,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART1_UDSR2,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree.end tree "DUART_2" tree "UART_3" base ad:0x021D0000 width 14. endian.be if (((per.b(ad:0x021D0000+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART2_UDLB3,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_URBR3,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_UTHR3,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART2_UDMB3,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART2_UIER3,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART2_UAFR3,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UFCR3,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UIIR3,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_UDLB3,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_URBR3,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART2_UTHR3,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART2_UDMB3,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART2_UIER3,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UAFR3,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART2_UFCR3,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UIIR3,UART Interrupt ID Register" in endif if (((per.b(ad:0x021D0000+0x503))&0x08)==0x00)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x00)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0000+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0000+0x503))&0x20)==0x20)&&(((per.b(ad:0x021D0000+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR3,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART2_UMCR3,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART2_ULSR3,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART2_UMSR3,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART2_USCR3,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART2_UDSR3,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree "UART_4" base ad:0x021D0100 width 14. endian.be if (((per.b(ad:0x021D0100+0x503))&0x80)==0x80) group.byte 0x500++0x00 line.byte 0x00 "DUART2_UDLB4,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_URBR4,UART Receiver Buffer Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_UTHR4,UART Transmitter Holding Register" group.byte 0x501++0x00 line.byte 0x00 "DUART2_UDMB4,UART Divisor Most Significant Byte Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART2_UIER4,UART Interrupt Enable Register" group.byte 0x502++0x00 line.byte 0x00 "DUART2_UAFR4,UART Alternate Function Register" bitfld.byte 0x00 1. " BO ,Baud clock select" "Not gated,Gated" bitfld.byte 0x00 0. " CW ,Concurrent write enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UFCR4,UART FIFO Control Register" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UIIR4,UART Interrupt ID Register" else hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_UDLB4,UART Divisor Least Significant Byte Register" hgroup.byte 0x500++0x00 hide.byte 0x00 "DUART2_URBR4,UART Receiver Buffer Register" in wgroup.byte 0x500++0x00 line.byte 0x00 "DUART2_UTHR4,UART Transmitter Holding Register" hgroup.byte 0x501++0x00 hide.byte 0x00 "DUART2_UDMB4,UART Divisor Most Significant Byte Register" group.byte 0x501++0x00 line.byte 0x00 "DUART2_UIER4,UART Interrupt Enable Register" bitfld.byte 0x00 3. " EMSI ,Enables modem status interrupt" "Disabled,Enabled" bitfld.byte 0x00 2. " ERLSI ,Enables receiver line status interrupt" "Disabled,Enabled" bitfld.byte 0x00 1. " ETHREI ,Enables transmitter holding register empty interrupt" "Disabled,Enabled" newline bitfld.byte 0x00 0. " ERDAI ,Enables received data available interrupt" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UAFR4,UART Alternate Function Register" wgroup.byte 0x502++0x00 line.byte 0x00 "DUART2_UFCR4,UART FIFO Control Register" bitfld.byte 0x00 6.--7. " RTL ,Receiver trigger level" "1 B / 1 B FIFO,4 B / 16 B FIFO,8 B / 32 B FIFO,14 B / 56 B FIFO" bitfld.byte 0x00 5. " EN64 ,Enable 64-byte FIFO" "Disabled,Enabled" bitfld.byte 0x00 3. " DMS ,DMA mode select" "Mode 0,Mode 1" newline bitfld.byte 0x00 2. " TFR ,Transmitter FIFO reset" "No reset,Reset" bitfld.byte 0x00 1. " RFR ,Receiver FIFO reset" "No reset,Reset" bitfld.byte 0x00 0. " FEN ,FIFO enable" "Disabled,Enabled" hgroup.byte 0x502++0x00 hide.byte 0x00 "DUART2_UIIR4,UART Interrupt ID Register" in endif if (((per.b(ad:0x021D0100+0x503))&0x08)==0x00)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,?..." newline bitfld.byte 0x00 4. " EPS ,Even parity select" "0,1" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x00)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Odd,Even" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" elif (((per.b(ad:0x021D0100+0x503))&0x08)==0x08)&&(((per.b(ad:0x021D0100+0x503))&0x20)==0x20)&&(((per.b(ad:0x021D0100+0x503))&0x03)==0x00) group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,1 1/2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" else group.byte 0x503++0x00 line.byte 0x00 "DUART2_ULCR4,UART Line Control Register" bitfld.byte 0x00 7. " DLAB ,Divisor latch access bit" "Not set,Set" bitfld.byte 0x00 6. " SB ,Set break" "Not set,Set" bitfld.byte 0x00 5. " SP ,Stick parity" "Disabled,Enabled" newline bitfld.byte 0x00 4. " EPS ,Even parity select" "Mark,Space" bitfld.byte 0x00 3. " PEN ,Parity enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NSTB ,Number of STOP bits" "1,2" newline bitfld.byte 0x00 0.--1. " WLS ,Word length select" "5 bits,6 bits,7 bits,8 bits" endif sif !cpuis("LS1012*") group.byte 0x504++0x00 line.byte 0x00 "DUART2_UMCR4,UART Modem Control Register" bitfld.byte 0x00 5. " AFE ,Auto flow control enable" "Disabled,Enabled" bitfld.byte 0x00 4. " LOOP ,Local loopback mode" "Normal operation,Loopback mode" bitfld.byte 0x00 1. " RTS ,Ready to send" "Negated,Asserted" endif hgroup.byte 0x505++0x00 hide.byte 0x00 "DUART2_ULSR4,UART Line Status Register" in hgroup.byte 0x506++0x00 hide.byte 0x00 "DUART2_UMSR4,UART Modem Status Register" in group.byte 0x507++0x00 line.byte 0x00 "DUART2_USCR4,UART Scratch Register" rgroup.byte 0x510++0x00 line.byte 0x00 "DUART2_UDSR4,UART DMA Status Register" bitfld.byte 0x00 1. " TXRDY ,Transmitter ready" "Cleared,Set" bitfld.byte 0x00 0. " RXRDY ,Receiver ready" "Cleared,Set" endian.le width 0x0B tree.end tree.end endif tree.end sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") tree "eDMA (Enhanced Direct Memory Access)" base ad:0x02C00000 width 23. endian.be group.long 0x00++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 17. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "Low,High" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "Low,High" newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Arbitration,No arbitration" bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Disabled,Enabled" newline bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Fixed priority,Round robin" bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Fixed priority,Round robin" bitfld.long 0x00 1. " EDBG ,Enable debug" "DMA not stalled,New DMA channel start stalled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "No error,Error" bitfld.long 0x00 16. " ECX ,Transfer canceled" "No error,Error" bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" newline bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" newline bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" newline bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") wgroup.byte 0x18++0x07 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI specified,All EEI bits" bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt for corresponding bit in EEI" "Clear EEI[31],Clear EEI[30],Clear EEI[29],Clear EEI[28],Clear EEI[27],Clear EEI[26],Clear EEI[25],Clear EEI[24],Clear EEI[23],Clear EEI[22],Clear EEI[21],Clear EEI[20],Clear EEI[19],Clear EEI[18],Clear EEI[17],Clear EEI[16],Clear EEI[15],Clear EEI[14],Clear EEI[13],Clear EEI[12],Clear EEI[11],Clear EEI[10],Clear EEI[9],Clear EEI[8],Clear EEI[7],Clear EEI[6],Clear EEI[5],Clear EEI[4],Clear EEI[3],Clear EEI[2],Clear EEI[1],Clear EEI[0]" line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI specified,All EEI bits" bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt for corresponding bit in EEI" "Set EEI[31],Set EEI[30],Set EEI[29],Set EEI[28],Set EEI[27],Set EEI[26],Set EEI[25],Set EEI[24],Set EEI[23],Set EEI[22],Set EEI[21],Set EEI[20],Set EEI[19],Set EEI[18],Set EEI[17],Set EEI[16],Set EEI[15],Set EEI[14],Set EEI[13],Set EEI[12],Set EEI[11],Set EEI[10],Set EEI[9],Set EEI[8],Set EEI[7],Set EEI[6],Set EEI[5],Set EEI[4],Set EEI[3],Set EEI[2],Set EEI[1],Set EEI[0]" line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CERQ specified,All ERQ bits" bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request for corresponding bit in ERQ" "Clear ERQ[31],Clear ERQ[30],Clear ERQ[29],Clear ERQ[28],Clear ERQ[27],Clear ERQ[26],Clear ERQ[25],Clear ERQ[24],Clear ERQ[23],Clear ERQ[22],Clear ERQ[21],Clear ERQ[20],Clear ERQ[19],Clear ERQ[18],Clear ERQ[17],Clear ERQ[16],Clear ERQ[15],Clear ERQ[14],Clear ERQ[13],Clear ERQ[12],Clear ERQ[11],Clear ERQ[10],Clear ERQ[9],Clear ERQ[8],Clear ERQ[7],Clear ERQ[6],Clear ERQ[5],Clear ERQ[4],Clear ERQ[3],Clear ERQ[2],Clear ERQ[1],Clear ERQ[0]" line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x03 6. " SAER ,Set All Enable Requests" "SERQ specified,All ERQ bits" bitfld.byte 0x03 0.--4. " SERQ ,Set enable request for corresponding bit in ERQ" "Set ERQ[31],Set ERQ[30],Set ERQ[29],Set ERQ[28],Set ERQ[27],Set ERQ[26],Set ERQ[25],Set ERQ[24],Set ERQ[23],Set ERQ[22],Set ERQ[21],Set ERQ[20],Set ERQ[19],Set ERQ[18],Set ERQ[17],Set ERQ[16],Set ERQ[15],Set ERQ[14],Set ERQ[13],Set ERQ[12],Set ERQ[11],Set ERQ[10],Set ERQ[9],Set ERQ[8],Set ERQ[7],Set ERQ[6],Set ERQ[5],Set ERQ[4],Set ERQ[3],Set ERQ[2],Set ERQ[1],Set ERQ[0]" line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x04 6. " CADN ,Clears All DONE Bits" "CDNE specified,All CSR[DONE] bits" bitfld.byte 0x04 0.--4. " CDNE ,Clear DONE for TCDn_CSR[DONE]" "Clear TCD31_CSR[DONE],Clear TCD30_CSR[DONE],Clear TCD29_CSR[DONE],Clear TCD28_CSR[DONE],Clear TCD27_CSR[DONE],Clear TCD26_CSR[DONE],Clear TCD25_CSR[DONE],Clear TCD24_CSR[DONE],Clear TCD23_CSR[DONE],Clear TCD22_CSR[DONE],Clear TCD21_CSR[DONE],Clear TCD20_CSR[DONE],Clear TCD19_CSR[DONE],Clear TCD18_CSR[DONE],Clear TCD17_CSR[DONE],Clear TCD16_CSR[DONE],Clear TCD15_CSR[DONE],Clear TCD14_CSR[DONE],Clear TCD13_CSR[DONE],Clear TCD12_CSR[DONE],Clear TCD11_CSR[DONE],Clear TCD10_CSR[DONE],Clear TCD9_CSR[DONE],Clear TCD8_CSR[DONE],Clear TCD7_CSR[DONE],Clear TCD6_CSR[DONE],Clear TCD5_CSR[DONE],Clear TCD4_CSR[DONE],Clear TCD3_CSR[DONE],Clear TCD2_CSR[DONE],Clear TCD1_CSR[DONE],Clear TCD0_CSR[DONE]" line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x05 6. " SAST ,Set all START bits (activates all channels)" "SSRT specified,All CSR[START] bits" bitfld.byte 0x05 0.--4. " SSRT ,Set START for TCDn_CSR[START]" "Set TCD31_CSR[START],Set TCD30_CSR[START],Set TCD29_CSR[START],Set TCD28_CSR[START],Set TCD27_CSR[START],Set TCD26_CSR[START],Set TCD25_CSR[START],Set TCD24_CSR[START],Set TCD23_CSR[START],Set TCD22_CSR[START],Set TCD21_CSR[START],Set TCD20_CSR[START],Set TCD19_CSR[START],Set TCD18_CSR[START],Set TCD17_CSR[START],Set TCD16_CSR[START],Set TCD15_CSR[START],Set TCD14_CSR[START],Set TCD13_CSR[START],Set TCD12_CSR[START],Set TCD11_CSR[START],Set TCD10_CSR[START],Set TCD9_CSR[START],Set TCD8_CSR[START],Set TCD7_CSR[START],Set TCD6_CSR[START],Set TCD5_CSR[START],Set TCD4_CSR[START],Set TCD3_CSR[START],Set TCD2_CSR[START],Set TCD1_CSR[START],Set TCD0_CSR[START]" line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CERR specified,All ERR bits" bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator for corresponding bit in ERR" "Clear ERR[31],Clear ERR[30],Clear ERR[29],Clear ERR[28],Clear ERR[27],Clear ERR[26],Clear ERR[25],Clear ERR[24],Clear ERR[23],Clear ERR[22],Clear ERR[21],Clear ERR[20],Clear ERR[19],Clear ERR[18],Clear ERR[17],Clear ERR[16],Clear ERR[15],Clear ERR[14],Clear ERR[13],Clear ERR[12],Clear ERR[11],Clear ERR[10],Clear ERR[9],Clear ERR[8],Clear ERR[7],Clear ERR[6],Clear ERR[5],Clear ERR[4],Clear ERR[3],Clear ERR[2],Clear ERR[1],Clear ERR[0]" line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt requests" "CINT specified,All INT bits" bitfld.byte 0x07 0.--4. " CINT4 ,Clear interrupt request bit [4]" "Clear INT[31],Clear INT[30],Clear INT[29],Clear INT[28],Clear INT[27],Clear INT[26],Clear INT[25],Clear INT[24],Clear INT[23],Clear INT[22],Clear INT[21],Clear INT[20],Clear INT[19],Clear INT[18],Clear INT[17],Clear INT[16],Clear INT[15],Clear INT[14],Clear INT[13],Clear INT[12],Clear INT[11],Clear INT[10],Clear INT[9],Clear INT[8],Clear INT[7],Clear INT[6],Clear INT[5],Clear INT[4],Clear INT[3],Clear INT[2],Clear INT[1],Clear INT[0]" else wgroup.byte 0x18++0x07 line.byte 0x00 "SERQ,Set Enable Request Register" bitfld.byte 0x00 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x00 6. " SAER ,Set all enable requests" "SERQ specified,All ERQ bits" bitfld.byte 0x00 0.--4. " SERQ ,Set enable request for corresponding bit in ERQ" "Set ERQ[31],Set ERQ[30],Set ERQ[29],Set ERQ[28],Set ERQ[27],Set ERQ[26],Set ERQ[25],Set ERQ[24],Set ERQ[23],Set ERQ[22],Set ERQ[21],Set ERQ[20],Set ERQ[19],Set ERQ[18],Set ERQ[17],Set ERQ[16],Set ERQ[15],Set ERQ[14],Set ERQ[13],Set ERQ[12],Set ERQ[11],Set ERQ[10],Set ERQ[9],Set ERQ[8],Set ERQ[7],Set ERQ[6],Set ERQ[5],Set ERQ[4],Set ERQ[3],Set ERQ[2],Set ERQ[1],Set ERQ[0]" line.byte 0x01 "CERQ,Clear Enable Request Register" bitfld.byte 0x01 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x01 6. " CAER ,Clear all enable requests" "CERQ specified,All ERQ bits" bitfld.byte 0x01 0.--4. " CERQ ,Clear enable request for corresponding bit in ERQ" "Clear ERQ[31],Clear ERQ[30],Clear ERQ[29],Clear ERQ[28],Clear ERQ[27],Clear ERQ[26],Clear ERQ[25],Clear ERQ[24],Clear ERQ[23],Clear ERQ[22],Clear ERQ[21],Clear ERQ[20],Clear ERQ[19],Clear ERQ[18],Clear ERQ[17],Clear ERQ[16],Clear ERQ[15],Clear ERQ[14],Clear ERQ[13],Clear ERQ[12],Clear ERQ[11],Clear ERQ[10],Clear ERQ[9],Clear ERQ[8],Clear ERQ[7],Clear ERQ[6],Clear ERQ[5],Clear ERQ[4],Clear ERQ[3],Clear ERQ[2],Clear ERQ[1],Clear ERQ[0]" line.byte 0x02 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x02 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x02 6. " SAEE ,Sets All Enable Error Interrupts" "SEEI specified,All EEI bits" bitfld.byte 0x02 0.--4. " SEEI ,Set enable error interrupt for corresponding bit in EEI" "Set EEI[31],Set EEI[30],Set EEI[29],Set EEI[28],Set EEI[27],Set EEI[26],Set EEI[25],Set EEI[24],Set EEI[23],Set EEI[22],Set EEI[21],Set EEI[20],Set EEI[19],Set EEI[18],Set EEI[17],Set EEI[16],Set EEI[15],Set EEI[14],Set EEI[13],Set EEI[12],Set EEI[11],Set EEI[10],Set EEI[9],Set EEI[8],Set EEI[7],Set EEI[6],Set EEI[5],Set EEI[4],Set EEI[3],Set EEI[2],Set EEI[1],Set EEI[0]" line.byte 0x03 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x03 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x03 6. " CAEE ,Clear All Enable Error Interrupts" "CEEI specified,All EEI bits" bitfld.byte 0x03 0.--4. " CEEI ,Clear enable error interrupt for corresponding bit in EEI" "Clear EEI[31],Clear EEI[30],Clear EEI[29],Clear EEI[28],Clear EEI[27],Clear EEI[26],Clear EEI[25],Clear EEI[24],Clear EEI[23],Clear EEI[22],Clear EEI[21],Clear EEI[20],Clear EEI[19],Clear EEI[18],Clear EEI[17],Clear EEI[16],Clear EEI[15],Clear EEI[14],Clear EEI[13],Clear EEI[12],Clear EEI[11],Clear EEI[10],Clear EEI[9],Clear EEI[8],Clear EEI[7],Clear EEI[6],Clear EEI[5],Clear EEI[4],Clear EEI[3],Clear EEI[2],Clear EEI[1],Clear EEI[0]" line.byte 0x04 "CINT,Clear Interrupt Request Register" bitfld.byte 0x04 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x04 6. " CAIR ,Clear All Interrupt Requests" "CINT specified,All INT bits" bitfld.byte 0x04 0.--4. " CINT4 ,Clear interrupt request bit [4]" "Clear INT[31],Clear INT[30],Clear INT[29],Clear INT[28],Clear INT[27],Clear INT[26],Clear INT[25],Clear INT[24],Clear INT[23],Clear INT[22],Clear INT[21],Clear INT[20],Clear INT[19],Clear INT[18],Clear INT[17],Clear INT[16],Clear INT[15],Clear INT[14],Clear INT[13],Clear INT[12],Clear INT[11],Clear INT[10],Clear INT[9],Clear INT[8],Clear INT[7],Clear INT[6],Clear INT[5],Clear INT[4],Clear INT[3],Clear INT[2],Clear INT[1],Clear INT[0]" line.byte 0x05 "CERR,Clear Error Register" bitfld.byte 0x05 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x05 6. " CAEI ,Clear All Error Indicators" "CERR specified,All ERR bits" bitfld.byte 0x05 0.--4. " CERR ,Clear error indicator for corresponding bit in ERR" "Clear ERR[31],Clear ERR[30],Clear ERR[29],Clear ERR[28],Clear ERR[27],Clear ERR[26],Clear ERR[25],Clear ERR[24],Clear ERR[23],Clear ERR[22],Clear ERR[21],Clear ERR[20],Clear ERR[19],Clear ERR[18],Clear ERR[17],Clear ERR[16],Clear ERR[15],Clear ERR[14],Clear ERR[13],Clear ERR[12],Clear ERR[11],Clear ERR[10],Clear ERR[9],Clear ERR[8],Clear ERR[7],Clear ERR[6],Clear ERR[5],Clear ERR[4],Clear ERR[3],Clear ERR[2],Clear ERR[1],Clear ERR[0]" line.byte 0x06 "SSRT,Clear DONE Status Bit Register" bitfld.byte 0x06 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x06 6. " SAST ,Set All START Bits (activates all channels)" "SSRT specified,All CSR[START] bits" bitfld.byte 0x06 0.--4. " SSRT ,Set START for TCDn_CSR[START]" "Set TCD31_CSR[START],Set TCD30_CSR[START],Set TCD29_CSR[START],Set TCD28_CSR[START],Set TCD27_CSR[START],Set TCD26_CSR[START],Set TCD25_CSR[START],Set TCD24_CSR[START],Set TCD23_CSR[START],Set TCD22_CSR[START],Set TCD21_CSR[START],Set TCD20_CSR[START],Set TCD19_CSR[START],Set TCD18_CSR[START],Set TCD17_CSR[START],Set TCD16_CSR[START],Set TCD15_CSR[START],Set TCD14_CSR[START],Set TCD13_CSR[START],Set TCD12_CSR[START],Set TCD11_CSR[START],Set TCD10_CSR[START],Set TCD9_CSR[START],Set TCD8_CSR[START],Set TCD7_CSR[START],Set TCD6_CSR[START],Set TCD5_CSR[START],Set TCD4_CSR[START],Set TCD3_CSR[START],Set TCD2_CSR[START],Set TCD1_CSR[START],Set TCD0_CSR[START]" line.byte 0x07 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x07 7. " NOP ,No Op enable" "No effect,Enable" bitfld.byte 0x07 6. " CADN ,Clears All DONE Bits" "CDNE specified,All CSR[DONE] bits" bitfld.byte 0x07 0.--4. " CDNE ,Clear DONE for TCDn_CSR[DONE]" "Clear TCD31_CSR[DONE],Clear TCD30_CSR[DONE],Clear TCD29_CSR[DONE],Clear TCD28_CSR[DONE],Clear TCD27_CSR[DONE],Clear TCD26_CSR[DONE],Clear TCD25_CSR[DONE],Clear TCD24_CSR[DONE],Clear TCD23_CSR[DONE],Clear TCD22_CSR[DONE],Clear TCD21_CSR[DONE],Clear TCD20_CSR[DONE],Clear TCD19_CSR[DONE],Clear TCD18_CSR[DONE],Clear TCD17_CSR[DONE],Clear TCD16_CSR[DONE],Clear TCD15_CSR[DONE],Clear TCD14_CSR[DONE],Clear TCD13_CSR[DONE],Clear TCD12_CSR[DONE],Clear TCD11_CSR[DONE],Clear TCD10_CSR[DONE],Clear TCD9_CSR[DONE],Clear TCD8_CSR[DONE],Clear TCD7_CSR[DONE],Clear TCD6_CSR[DONE],Clear TCD5_CSR[DONE],Clear TCD4_CSR[DONE],Clear TCD3_CSR[DONE],Clear TCD2_CSR[DONE],Clear TCD1_CSR[DONE],Clear TCD0_CSR[DONE]" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "No interrupt,Interrupt" eventfld.long 0x00 28. " [28] ,Interrupt request 28" "No interrupt,Interrupt" newline eventfld.long 0x00 27. " [27] ,Interrupt request 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "No interrupt,Interrupt" eventfld.long 0x00 25. " [25] ,Interrupt request 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "No interrupt,Interrupt" newline eventfld.long 0x00 23. " [23] ,Interrupt request 23" "No interrupt,Interrupt" eventfld.long 0x00 22. " [22] ,Interrupt request 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Interrupt request 20" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " [16] ,Interrupt request 16" "No interrupt,Interrupt" newline eventfld.long 0x00 15. " [15] ,Interrupt request 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,Interrupt request 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,Interrupt request 0" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "Not occurred,Occurred" eventfld.long 0x00 30. " [30] ,Error in channel 30" "Not occurred,Occurred" eventfld.long 0x00 29. " [29] ,Error in channel 29" "Not occurred,Occurred" eventfld.long 0x00 28. " [28] ,Error in channel 28" "Not occurred,Occurred" newline eventfld.long 0x00 27. " [27] ,Error in channel 27" "Not occurred,Occurred" eventfld.long 0x00 26. " [26] ,Error in channel 26" "Not occurred,Occurred" eventfld.long 0x00 25. " [25] ,Error in channel 25" "Not occurred,Occurred" eventfld.long 0x00 24. " [24] ,Error in channel 24" "Not occurred,Occurred" newline eventfld.long 0x00 23. " [23] ,Error in channel 23" "Not occurred,Occurred" eventfld.long 0x00 22. " [22] ,Error in channel 22" "Not occurred,Occurred" eventfld.long 0x00 21. " [21] ,Error in channel 21" "Not occurred,Occurred" eventfld.long 0x00 20. " [20] ,Error in channel 20" "Not occurred,Occurred" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "Not occurred,Occurred" eventfld.long 0x00 18. " [18] ,Error in channel 18" "Not occurred,Occurred" eventfld.long 0x00 17. " [17] ,Error in channel 17" "Not occurred,Occurred" eventfld.long 0x00 16. " [16] ,Error in channel 16" "Not occurred,Occurred" newline eventfld.long 0x00 15. " [15] ,Error in channel 15" "Not occurred,Occurred" eventfld.long 0x00 14. " [14] ,Error in channel 14" "Not occurred,Occurred" eventfld.long 0x00 13. " [13] ,Error in channel 13" "Not occurred,Occurred" eventfld.long 0x00 12. " [12] ,Error in channel 12" "Not occurred,Occurred" newline eventfld.long 0x00 11. " [11] ,Error in channel 11" "Not occurred,Occurred" eventfld.long 0x00 10. " [10] ,Error in channel 10" "Not occurred,Occurred" eventfld.long 0x00 9. " [9] ,Error in channel 9" "Not occurred,Occurred" eventfld.long 0x00 8. " [8] ,Error in channel 8" "Not occurred,Occurred" newline eventfld.long 0x00 7. " [7] ,Error in channel 7" "Not occurred,Occurred" eventfld.long 0x00 6. " [6] ,Error in channel 6" "Not occurred,Occurred" eventfld.long 0x00 5. " [5] ,Error in channel 5" "Not occurred,Occurred" eventfld.long 0x00 4. " [4] ,Error in channel 4" "Not occurred,Occurred" newline eventfld.long 0x00 3. " [3] ,Error in channel 3" "Not occurred,Occurred" eventfld.long 0x00 2. " [2] ,Error in channel 2" "Not occurred,Occurred" eventfld.long 0x00 1. " [1] ,Error in channel 1" "Not occurred,Occurred" eventfld.long 0x00 0. " [0] ,Error in channel 0" "Not occurred,Occurred" rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" bitfld.long 0x00 31. " HRS[30] ,Hardware request status channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status channel 29" "Not present,Present" bitfld.long 0x00 28. " [28] ,Hardware request status channel 28" "Not present,Present" newline bitfld.long 0x00 27. " [27] ,Hardware request status channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status channel 26" "Not present,Present" bitfld.long 0x00 25. " [25] ,Hardware request status channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status channel 24" "Not present,Present" newline bitfld.long 0x00 23. " [23] ,Hardware request status channel 23" "Not present,Present" bitfld.long 0x00 22. " [22] ,Hardware request status channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status channel 17" "Not present,Present" bitfld.long 0x00 16. " [16] ,Hardware request status channel 16" "Not present,Present" newline bitfld.long 0x00 15. " [15] ,Hardware request status channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status channel 13" "Not present,Present" bitfld.long 0x00 12. " [12] ,Hardware request status channel 12" "Not present,Present" newline bitfld.long 0x00 11. " [11] ,Hardware request status channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status channel 10" "Not present,Present" bitfld.long 0x00 9. " [9] ,Hardware request status channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status channel 8" "Not present,Present" newline bitfld.long 0x00 7. " [7] ,Hardware request status channel 7" "Not present,Present" bitfld.long 0x00 6. " [6] ,Hardware request status channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status channel 1" "Not present,Present" bitfld.long 0x00 0. " [0] ,Hardware request status channel 0" "Not present,Present" sif !cpuis("LS1012*")&&!cpuis("LS10?3*")&&!cpuis("LS10?6*") group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register" bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop mode for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop mode for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop mode for channel 29" "Disabled,Enabled" bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop mode for channel 28" "Disabled,Enabled" newline bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop mode for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop mode for channel 26" "Disabled,Enabled" bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop mode for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop mode for channel 24" "Disabled,Enabled" newline bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop mode for channel 23" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop mode for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop mode for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop mode for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop mode for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop mode for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop mode for channel 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop mode for channel 16" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop mode for channel 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop mode for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop mode for channel 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop mode for channel 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop mode for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop mode for channel 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop mode for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop mode for channel 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop mode for channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop mode for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop mode for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop mode for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop mode for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop mode for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop mode for channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop mode for channel 0" "Disabled,Enabled" endif sif !cpuis("LS1012*") group.byte 0x100++0x00 line.byte 0x00 "DCHPRI0 ,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI1 ,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI2 ,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI3 ,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI4 ,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI5 ,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI6 ,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI7 ,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI8 ,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI9 ,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" else group.byte 0x100++0x00 line.byte 0x00 "DCHPRI3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x101++0x00 line.byte 0x00 "DCHPRI2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x102++0x00 line.byte 0x00 "DCHPRI1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x103++0x00 line.byte 0x00 "DCHPRI0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x104++0x00 line.byte 0x00 "DCHPRI7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x105++0x00 line.byte 0x00 "DCHPRI6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x106++0x00 line.byte 0x00 "DCHPRI5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x107++0x00 line.byte 0x00 "DCHPRI4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x108++0x00 line.byte 0x00 "DCHPRI11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x109++0x00 line.byte 0x00 "DCHPRI10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10A++0x00 line.byte 0x00 "DCHPRI9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10B++0x00 line.byte 0x00 "DCHPRI8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10C++0x00 line.byte 0x00 "DCHPRI15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10D++0x00 line.byte 0x00 "DCHPRI14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10E++0x00 line.byte 0x00 "DCHPRI13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x10F++0x00 line.byte 0x00 "DCHPRI12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x110++0x00 line.byte 0x00 "DCHPRI19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x111++0x00 line.byte 0x00 "DCHPRI18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x112++0x00 line.byte 0x00 "DCHPRI17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x113++0x00 line.byte 0x00 "DCHPRI16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x114++0x00 line.byte 0x00 "DCHPRI23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x115++0x00 line.byte 0x00 "DCHPRI22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x116++0x00 line.byte 0x00 "DCHPRI21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x117++0x00 line.byte 0x00 "DCHPRI20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x118++0x00 line.byte 0x00 "DCHPRI27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x119++0x00 line.byte 0x00 "DCHPRI26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11A++0x00 line.byte 0x00 "DCHPRI25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11B++0x00 line.byte 0x00 "DCHPRI24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11C++0x00 line.byte 0x00 "DCHPRI31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11D++0x00 line.byte 0x00 "DCHPRI30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11E++0x00 line.byte 0x00 "DCHPRI29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte 0x11F++0x00 line.byte 0x00 "DCHPRI28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 current group priority" "Lowest,1,2,Highest" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif group.long 0x1000++0x03 line.long 0x00 "TCD0 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1000+0x04)++0x03 line.word 0x00 "TCD0 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD0 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1000+0x04)++0x03 line.word 0x00 "TCD0 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD0 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1000+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1000+0x08))&0xC0000000)==0x00) group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1000+0x08)++0x03 line.long 0x00 "TCD0 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1000+0x0C)++0x07 line.long 0x00 "TCD0 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD0 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1000+0x14)++0x01 line.word 0x00 "TCD0 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1000+0x16))&0x8000)==0x8000) group.word (0x1000+0x16)++0x01 line.word 0x00 "TCD0 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1000+0x16)++0x01 line.word 0x00 "TCD0 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1000+0x14))&0x8000)==0x8000) group.word (0x1000+0x14)++0x01 line.word 0x00 "TCD0 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1000+0x14)++0x01 line.word 0x00 "TCD0 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1000+0x16)++0x01 line.word 0x00 "TCD0 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1000+0x18)++0x03 line.long 0x00 "TCD0 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1000+0x1C)++0x01 line.word 0x00 "TCD0 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1000+0x1C))&0x8000)==0x8000) group.word (0x1000+0x1E)++0x01 line.word 0x00 "TCD0 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1000+0x1E)++0x01 line.word 0x00 "TCD0 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1000+0x1C))&0x8000)==0x8000) group.word (0x1000+0x1C)++0x01 line.word 0x00 "TCD0 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1000+0x1C)++0x01 line.word 0x00 "TCD0 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1000+0x1E)++0x01 line.word 0x00 "TCD0 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1020++0x03 line.long 0x00 "TCD1 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1020+0x04)++0x03 line.word 0x00 "TCD1 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD1 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1020+0x04)++0x03 line.word 0x00 "TCD1 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD1 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1020+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1020+0x08))&0xC0000000)==0x00) group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1020+0x08)++0x03 line.long 0x00 "TCD1 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1020+0x0C)++0x07 line.long 0x00 "TCD1 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD1 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1020+0x14)++0x01 line.word 0x00 "TCD1 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1020+0x16))&0x8000)==0x8000) group.word (0x1020+0x16)++0x01 line.word 0x00 "TCD1 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1020+0x16)++0x01 line.word 0x00 "TCD1 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1020+0x14))&0x8000)==0x8000) group.word (0x1020+0x14)++0x01 line.word 0x00 "TCD1 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1020+0x14)++0x01 line.word 0x00 "TCD1 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1020+0x16)++0x01 line.word 0x00 "TCD1 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1020+0x18)++0x03 line.long 0x00 "TCD1 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1020+0x1C)++0x01 line.word 0x00 "TCD1 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1020+0x1C))&0x8000)==0x8000) group.word (0x1020+0x1E)++0x01 line.word 0x00 "TCD1 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1020+0x1E)++0x01 line.word 0x00 "TCD1 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1020+0x1C))&0x8000)==0x8000) group.word (0x1020+0x1C)++0x01 line.word 0x00 "TCD1 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1020+0x1C)++0x01 line.word 0x00 "TCD1 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1020+0x1E)++0x01 line.word 0x00 "TCD1 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1040++0x03 line.long 0x00 "TCD2 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1040+0x04)++0x03 line.word 0x00 "TCD2 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD2 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1040+0x04)++0x03 line.word 0x00 "TCD2 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD2 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1040+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1040+0x08))&0xC0000000)==0x00) group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1040+0x08)++0x03 line.long 0x00 "TCD2 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1040+0x0C)++0x07 line.long 0x00 "TCD2 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD2 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1040+0x14)++0x01 line.word 0x00 "TCD2 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1040+0x16))&0x8000)==0x8000) group.word (0x1040+0x16)++0x01 line.word 0x00 "TCD2 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1040+0x16)++0x01 line.word 0x00 "TCD2 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1040+0x14))&0x8000)==0x8000) group.word (0x1040+0x14)++0x01 line.word 0x00 "TCD2 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1040+0x14)++0x01 line.word 0x00 "TCD2 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1040+0x16)++0x01 line.word 0x00 "TCD2 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1040+0x18)++0x03 line.long 0x00 "TCD2 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1040+0x1C)++0x01 line.word 0x00 "TCD2 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1040+0x1C))&0x8000)==0x8000) group.word (0x1040+0x1E)++0x01 line.word 0x00 "TCD2 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1040+0x1E)++0x01 line.word 0x00 "TCD2 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1040+0x1C))&0x8000)==0x8000) group.word (0x1040+0x1C)++0x01 line.word 0x00 "TCD2 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1040+0x1C)++0x01 line.word 0x00 "TCD2 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1040+0x1E)++0x01 line.word 0x00 "TCD2 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1060++0x03 line.long 0x00 "TCD3 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1060+0x04)++0x03 line.word 0x00 "TCD3 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD3 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1060+0x04)++0x03 line.word 0x00 "TCD3 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD3 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1060+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1060+0x08))&0xC0000000)==0x00) group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1060+0x08)++0x03 line.long 0x00 "TCD3 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1060+0x0C)++0x07 line.long 0x00 "TCD3 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD3 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1060+0x14)++0x01 line.word 0x00 "TCD3 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1060+0x16))&0x8000)==0x8000) group.word (0x1060+0x16)++0x01 line.word 0x00 "TCD3 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1060+0x16)++0x01 line.word 0x00 "TCD3 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1060+0x14))&0x8000)==0x8000) group.word (0x1060+0x14)++0x01 line.word 0x00 "TCD3 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1060+0x14)++0x01 line.word 0x00 "TCD3 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1060+0x16)++0x01 line.word 0x00 "TCD3 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1060+0x18)++0x03 line.long 0x00 "TCD3 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1060+0x1C)++0x01 line.word 0x00 "TCD3 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1060+0x1C))&0x8000)==0x8000) group.word (0x1060+0x1E)++0x01 line.word 0x00 "TCD3 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1060+0x1E)++0x01 line.word 0x00 "TCD3 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1060+0x1C))&0x8000)==0x8000) group.word (0x1060+0x1C)++0x01 line.word 0x00 "TCD3 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1060+0x1C)++0x01 line.word 0x00 "TCD3 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1060+0x1E)++0x01 line.word 0x00 "TCD3 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1080++0x03 line.long 0x00 "TCD4 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1080+0x04)++0x03 line.word 0x00 "TCD4 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD4 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1080+0x04)++0x03 line.word 0x00 "TCD4 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD4 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1080+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1080+0x08))&0xC0000000)==0x00) group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1080+0x08)++0x03 line.long 0x00 "TCD4 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1080+0x0C)++0x07 line.long 0x00 "TCD4 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD4 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1080+0x14)++0x01 line.word 0x00 "TCD4 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1080+0x16))&0x8000)==0x8000) group.word (0x1080+0x16)++0x01 line.word 0x00 "TCD4 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1080+0x16)++0x01 line.word 0x00 "TCD4 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1080+0x14))&0x8000)==0x8000) group.word (0x1080+0x14)++0x01 line.word 0x00 "TCD4 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1080+0x14)++0x01 line.word 0x00 "TCD4 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1080+0x16)++0x01 line.word 0x00 "TCD4 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1080+0x18)++0x03 line.long 0x00 "TCD4 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1080+0x1C)++0x01 line.word 0x00 "TCD4 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1080+0x1C))&0x8000)==0x8000) group.word (0x1080+0x1E)++0x01 line.word 0x00 "TCD4 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1080+0x1E)++0x01 line.word 0x00 "TCD4 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1080+0x1C))&0x8000)==0x8000) group.word (0x1080+0x1C)++0x01 line.word 0x00 "TCD4 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1080+0x1C)++0x01 line.word 0x00 "TCD4 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1080+0x1E)++0x01 line.word 0x00 "TCD4 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x10A0++0x03 line.long 0x00 "TCD5 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10A0+0x04)++0x03 line.word 0x00 "TCD5 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD5 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x10A0+0x04)++0x03 line.word 0x00 "TCD5 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD5 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10A0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10A0+0x08))&0xC0000000)==0x00) group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x10A0+0x08)++0x03 line.long 0x00 "TCD5 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x10A0+0x0C)++0x07 line.long 0x00 "TCD5 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD5 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10A0+0x14)++0x01 line.word 0x00 "TCD5 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x10A0+0x16))&0x8000)==0x8000) group.word (0x10A0+0x16)++0x01 line.word 0x00 "TCD5 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10A0+0x16)++0x01 line.word 0x00 "TCD5 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10A0+0x14))&0x8000)==0x8000) group.word (0x10A0+0x14)++0x01 line.word 0x00 "TCD5 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10A0+0x14)++0x01 line.word 0x00 "TCD5 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x10A0+0x16)++0x01 line.word 0x00 "TCD5 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x10A0+0x18)++0x03 line.long 0x00 "TCD5 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10A0+0x1C)++0x01 line.word 0x00 "TCD5 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x10A0+0x1C))&0x8000)==0x8000) group.word (0x10A0+0x1E)++0x01 line.word 0x00 "TCD5 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10A0+0x1E)++0x01 line.word 0x00 "TCD5 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10A0+0x1C))&0x8000)==0x8000) group.word (0x10A0+0x1C)++0x01 line.word 0x00 "TCD5 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10A0+0x1C)++0x01 line.word 0x00 "TCD5 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x10A0+0x1E)++0x01 line.word 0x00 "TCD5 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x10C0++0x03 line.long 0x00 "TCD6 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10C0+0x04)++0x03 line.word 0x00 "TCD6 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD6 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x10C0+0x04)++0x03 line.word 0x00 "TCD6 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD6 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10C0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10C0+0x08))&0xC0000000)==0x00) group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x10C0+0x08)++0x03 line.long 0x00 "TCD6 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x10C0+0x0C)++0x07 line.long 0x00 "TCD6 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD6 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10C0+0x14)++0x01 line.word 0x00 "TCD6 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x10C0+0x16))&0x8000)==0x8000) group.word (0x10C0+0x16)++0x01 line.word 0x00 "TCD6 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10C0+0x16)++0x01 line.word 0x00 "TCD6 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10C0+0x14))&0x8000)==0x8000) group.word (0x10C0+0x14)++0x01 line.word 0x00 "TCD6 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10C0+0x14)++0x01 line.word 0x00 "TCD6 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x10C0+0x16)++0x01 line.word 0x00 "TCD6 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x10C0+0x18)++0x03 line.long 0x00 "TCD6 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10C0+0x1C)++0x01 line.word 0x00 "TCD6 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x10C0+0x1C))&0x8000)==0x8000) group.word (0x10C0+0x1E)++0x01 line.word 0x00 "TCD6 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10C0+0x1E)++0x01 line.word 0x00 "TCD6 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10C0+0x1C))&0x8000)==0x8000) group.word (0x10C0+0x1C)++0x01 line.word 0x00 "TCD6 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10C0+0x1C)++0x01 line.word 0x00 "TCD6 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x10C0+0x1E)++0x01 line.word 0x00 "TCD6 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x10E0++0x03 line.long 0x00 "TCD7 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10E0+0x04)++0x03 line.word 0x00 "TCD7 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD7 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x10E0+0x04)++0x03 line.word 0x00 "TCD7 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD7 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10E0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x10E0+0x08))&0xC0000000)==0x00) group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x10E0+0x08)++0x03 line.long 0x00 "TCD7 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x10E0+0x0C)++0x07 line.long 0x00 "TCD7 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD7 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10E0+0x14)++0x01 line.word 0x00 "TCD7 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x10E0+0x16))&0x8000)==0x8000) group.word (0x10E0+0x16)++0x01 line.word 0x00 "TCD7 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10E0+0x16)++0x01 line.word 0x00 "TCD7 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10E0+0x14))&0x8000)==0x8000) group.word (0x10E0+0x14)++0x01 line.word 0x00 "TCD7 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x10E0+0x14)++0x01 line.word 0x00 "TCD7 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x10E0+0x16)++0x01 line.word 0x00 "TCD7 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x10E0+0x18)++0x03 line.long 0x00 "TCD7 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x10E0+0x1C)++0x01 line.word 0x00 "TCD7 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x10E0+0x1C))&0x8000)==0x8000) group.word (0x10E0+0x1E)++0x01 line.word 0x00 "TCD7 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10E0+0x1E)++0x01 line.word 0x00 "TCD7 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x10E0+0x1C))&0x8000)==0x8000) group.word (0x10E0+0x1C)++0x01 line.word 0x00 "TCD7 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x10E0+0x1C)++0x01 line.word 0x00 "TCD7 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x10E0+0x1E)++0x01 line.word 0x00 "TCD7 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1100++0x03 line.long 0x00 "TCD8 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1100+0x04)++0x03 line.word 0x00 "TCD8 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD8 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1100+0x04)++0x03 line.word 0x00 "TCD8 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD8 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1100+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1100+0x08))&0xC0000000)==0x00) group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1100+0x08)++0x03 line.long 0x00 "TCD8 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1100+0x0C)++0x07 line.long 0x00 "TCD8 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD8 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1100+0x14)++0x01 line.word 0x00 "TCD8 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1100+0x16))&0x8000)==0x8000) group.word (0x1100+0x16)++0x01 line.word 0x00 "TCD8 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1100+0x16)++0x01 line.word 0x00 "TCD8 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1100+0x14))&0x8000)==0x8000) group.word (0x1100+0x14)++0x01 line.word 0x00 "TCD8 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1100+0x14)++0x01 line.word 0x00 "TCD8 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1100+0x16)++0x01 line.word 0x00 "TCD8 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1100+0x18)++0x03 line.long 0x00 "TCD8 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1100+0x1C)++0x01 line.word 0x00 "TCD8 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1100+0x1C))&0x8000)==0x8000) group.word (0x1100+0x1E)++0x01 line.word 0x00 "TCD8 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1100+0x1E)++0x01 line.word 0x00 "TCD8 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1100+0x1C))&0x8000)==0x8000) group.word (0x1100+0x1C)++0x01 line.word 0x00 "TCD8 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1100+0x1C)++0x01 line.word 0x00 "TCD8 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1100+0x1E)++0x01 line.word 0x00 "TCD8 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1120++0x03 line.long 0x00 "TCD9 _SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1120+0x04)++0x03 line.word 0x00 "TCD9 _SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD9 _ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1120+0x04)++0x03 line.word 0x00 "TCD9 _ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD9 _SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1120+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9 _NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1120+0x08))&0xC0000000)==0x00) group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9 _NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1120+0x08)++0x03 line.long 0x00 "TCD9 _NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1120+0x0C)++0x07 line.long 0x00 "TCD9 _SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD9 _DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1120+0x14)++0x01 line.word 0x00 "TCD9 _DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1120+0x16))&0x8000)==0x8000) group.word (0x1120+0x16)++0x01 line.word 0x00 "TCD9 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1120+0x16)++0x01 line.word 0x00 "TCD9 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1120+0x14))&0x8000)==0x8000) group.word (0x1120+0x14)++0x01 line.word 0x00 "TCD9 _CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1120+0x14)++0x01 line.word 0x00 "TCD9 _CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1120+0x16)++0x01 line.word 0x00 "TCD9 _DOFF,TCD Signed Destination Address Offset" endif group.long (0x1120+0x18)++0x03 line.long 0x00 "TCD9 _DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1120+0x1C)++0x01 line.word 0x00 "TCD9 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1120+0x1C))&0x8000)==0x8000) group.word (0x1120+0x1E)++0x01 line.word 0x00 "TCD9 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1120+0x1E)++0x01 line.word 0x00 "TCD9 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1120+0x1C))&0x8000)==0x8000) group.word (0x1120+0x1C)++0x01 line.word 0x00 "TCD9 _BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1120+0x1C)++0x01 line.word 0x00 "TCD9 _BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1120+0x1E)++0x01 line.word 0x00 "TCD9 _CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1140++0x03 line.long 0x00 "TCD10_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1140+0x04)++0x03 line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD10_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1140+0x04)++0x03 line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD10_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1140+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1140+0x08))&0xC0000000)==0x00) group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1140+0x08)++0x03 line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1140+0x0C)++0x07 line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD10_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1140+0x14)++0x01 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1140+0x16))&0x8000)==0x8000) group.word (0x1140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1140+0x16)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1140+0x14))&0x8000)==0x8000) group.word (0x1140+0x14)++0x01 line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1140+0x14)++0x01 line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1140+0x16)++0x01 line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1140+0x18)++0x03 line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1140+0x1C)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1140+0x1C))&0x8000)==0x8000) group.word (0x1140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1140+0x1E)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1140+0x1C))&0x8000)==0x8000) group.word (0x1140+0x1C)++0x01 line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1140+0x1C)++0x01 line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1140+0x1E)++0x01 line.word 0x00 "TCD10_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1160++0x03 line.long 0x00 "TCD11_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1160+0x04)++0x03 line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD11_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1160+0x04)++0x03 line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD11_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1160+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1160+0x08))&0xC0000000)==0x00) group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1160+0x08)++0x03 line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1160+0x0C)++0x07 line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD11_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1160+0x14)++0x01 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1160+0x16))&0x8000)==0x8000) group.word (0x1160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1160+0x16)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1160+0x14))&0x8000)==0x8000) group.word (0x1160+0x14)++0x01 line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1160+0x14)++0x01 line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1160+0x16)++0x01 line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1160+0x18)++0x03 line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1160+0x1C)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1160+0x1C))&0x8000)==0x8000) group.word (0x1160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1160+0x1E)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1160+0x1C))&0x8000)==0x8000) group.word (0x1160+0x1C)++0x01 line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1160+0x1C)++0x01 line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1160+0x1E)++0x01 line.word 0x00 "TCD11_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1180++0x03 line.long 0x00 "TCD12_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1180+0x04)++0x03 line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD12_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1180+0x04)++0x03 line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD12_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1180+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1180+0x08))&0xC0000000)==0x00) group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1180+0x08)++0x03 line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1180+0x0C)++0x07 line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD12_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1180+0x14)++0x01 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1180+0x16))&0x8000)==0x8000) group.word (0x1180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1180+0x16)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1180+0x14))&0x8000)==0x8000) group.word (0x1180+0x14)++0x01 line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1180+0x14)++0x01 line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1180+0x16)++0x01 line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1180+0x18)++0x03 line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1180+0x1C)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1180+0x1C))&0x8000)==0x8000) group.word (0x1180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1180+0x1E)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1180+0x1C))&0x8000)==0x8000) group.word (0x1180+0x1C)++0x01 line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1180+0x1C)++0x01 line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1180+0x1E)++0x01 line.word 0x00 "TCD12_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x11A0++0x03 line.long 0x00 "TCD13_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11A0+0x04)++0x03 line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD13_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x11A0+0x04)++0x03 line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD13_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11A0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11A0+0x08))&0xC0000000)==0x00) group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x11A0+0x08)++0x03 line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x11A0+0x0C)++0x07 line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD13_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11A0+0x14)++0x01 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x11A0+0x16))&0x8000)==0x8000) group.word (0x11A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11A0+0x16)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11A0+0x14))&0x8000)==0x8000) group.word (0x11A0+0x14)++0x01 line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11A0+0x14)++0x01 line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x11A0+0x16)++0x01 line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset" endif group.long (0x11A0+0x18)++0x03 line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11A0+0x1C)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x11A0+0x1C))&0x8000)==0x8000) group.word (0x11A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11A0+0x1E)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11A0+0x1C))&0x8000)==0x8000) group.word (0x11A0+0x1C)++0x01 line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11A0+0x1C)++0x01 line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x11A0+0x1E)++0x01 line.word 0x00 "TCD13_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x11C0++0x03 line.long 0x00 "TCD14_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11C0+0x04)++0x03 line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD14_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x11C0+0x04)++0x03 line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD14_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11C0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11C0+0x08))&0xC0000000)==0x00) group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x11C0+0x08)++0x03 line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x11C0+0x0C)++0x07 line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD14_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11C0+0x14)++0x01 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x11C0+0x16))&0x8000)==0x8000) group.word (0x11C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11C0+0x16)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11C0+0x14))&0x8000)==0x8000) group.word (0x11C0+0x14)++0x01 line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11C0+0x14)++0x01 line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x11C0+0x16)++0x01 line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset" endif group.long (0x11C0+0x18)++0x03 line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11C0+0x1C)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x11C0+0x1C))&0x8000)==0x8000) group.word (0x11C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11C0+0x1E)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11C0+0x1C))&0x8000)==0x8000) group.word (0x11C0+0x1C)++0x01 line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11C0+0x1C)++0x01 line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x11C0+0x1E)++0x01 line.word 0x00 "TCD14_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x11E0++0x03 line.long 0x00 "TCD15_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11E0+0x04)++0x03 line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD15_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x11E0+0x04)++0x03 line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD15_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11E0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x11E0+0x08))&0xC0000000)==0x00) group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x11E0+0x08)++0x03 line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x11E0+0x0C)++0x07 line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD15_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11E0+0x14)++0x01 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x11E0+0x16))&0x8000)==0x8000) group.word (0x11E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11E0+0x16)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11E0+0x14))&0x8000)==0x8000) group.word (0x11E0+0x14)++0x01 line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x11E0+0x14)++0x01 line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x11E0+0x16)++0x01 line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset" endif group.long (0x11E0+0x18)++0x03 line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x11E0+0x1C)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x11E0+0x1C))&0x8000)==0x8000) group.word (0x11E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11E0+0x1E)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x11E0+0x1C))&0x8000)==0x8000) group.word (0x11E0+0x1C)++0x01 line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x11E0+0x1C)++0x01 line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x11E0+0x1E)++0x01 line.word 0x00 "TCD15_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1200++0x03 line.long 0x00 "TCD16_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1200+0x04)++0x03 line.word 0x00 "TCD16_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD16_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1200+0x04)++0x03 line.word 0x00 "TCD16_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD16_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1200+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1200+0x08))&0xC0000000)==0x00) group.long (0x1200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1200+0x08)++0x03 line.long 0x00 "TCD16_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1200+0x0C)++0x07 line.long 0x00 "TCD16_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD16_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1200+0x14)++0x01 line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1200+0x16))&0x8000)==0x8000) group.word (0x1200+0x16)++0x01 line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1200+0x16)++0x01 line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1200+0x14))&0x8000)==0x8000) group.word (0x1200+0x14)++0x01 line.word 0x00 "TCD16_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1200+0x14)++0x01 line.word 0x00 "TCD16_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1200+0x16)++0x01 line.word 0x00 "TCD16_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1200+0x18)++0x03 line.long 0x00 "TCD16_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1200+0x1C)++0x01 line.word 0x00 "TCD16_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1200+0x1C))&0x8000)==0x8000) group.word (0x1200+0x1E)++0x01 line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1200+0x1E)++0x01 line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1200+0x1C))&0x8000)==0x8000) group.word (0x1200+0x1C)++0x01 line.word 0x00 "TCD16_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1200+0x1C)++0x01 line.word 0x00 "TCD16_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1200+0x1E)++0x01 line.word 0x00 "TCD16_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1220++0x03 line.long 0x00 "TCD17_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1220+0x04)++0x03 line.word 0x00 "TCD17_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD17_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1220+0x04)++0x03 line.word 0x00 "TCD17_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD17_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1220+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1220+0x08))&0xC0000000)==0x00) group.long (0x1220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1220+0x08)++0x03 line.long 0x00 "TCD17_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1220+0x0C)++0x07 line.long 0x00 "TCD17_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD17_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1220+0x14)++0x01 line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1220+0x16))&0x8000)==0x8000) group.word (0x1220+0x16)++0x01 line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1220+0x16)++0x01 line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1220+0x14))&0x8000)==0x8000) group.word (0x1220+0x14)++0x01 line.word 0x00 "TCD17_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1220+0x14)++0x01 line.word 0x00 "TCD17_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1220+0x16)++0x01 line.word 0x00 "TCD17_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1220+0x18)++0x03 line.long 0x00 "TCD17_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1220+0x1C)++0x01 line.word 0x00 "TCD17_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1220+0x1C))&0x8000)==0x8000) group.word (0x1220+0x1E)++0x01 line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1220+0x1E)++0x01 line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1220+0x1C))&0x8000)==0x8000) group.word (0x1220+0x1C)++0x01 line.word 0x00 "TCD17_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1220+0x1C)++0x01 line.word 0x00 "TCD17_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1220+0x1E)++0x01 line.word 0x00 "TCD17_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1240++0x03 line.long 0x00 "TCD18_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1240+0x04)++0x03 line.word 0x00 "TCD18_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD18_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1240+0x04)++0x03 line.word 0x00 "TCD18_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD18_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1240+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1240+0x08))&0xC0000000)==0x00) group.long (0x1240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1240+0x08)++0x03 line.long 0x00 "TCD18_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1240+0x0C)++0x07 line.long 0x00 "TCD18_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD18_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1240+0x14)++0x01 line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1240+0x16))&0x8000)==0x8000) group.word (0x1240+0x16)++0x01 line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1240+0x16)++0x01 line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1240+0x14))&0x8000)==0x8000) group.word (0x1240+0x14)++0x01 line.word 0x00 "TCD18_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1240+0x14)++0x01 line.word 0x00 "TCD18_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1240+0x16)++0x01 line.word 0x00 "TCD18_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1240+0x18)++0x03 line.long 0x00 "TCD18_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1240+0x1C)++0x01 line.word 0x00 "TCD18_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1240+0x1C))&0x8000)==0x8000) group.word (0x1240+0x1E)++0x01 line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1240+0x1E)++0x01 line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1240+0x1C))&0x8000)==0x8000) group.word (0x1240+0x1C)++0x01 line.word 0x00 "TCD18_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1240+0x1C)++0x01 line.word 0x00 "TCD18_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1240+0x1E)++0x01 line.word 0x00 "TCD18_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1260++0x03 line.long 0x00 "TCD19_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1260+0x04)++0x03 line.word 0x00 "TCD19_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD19_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1260+0x04)++0x03 line.word 0x00 "TCD19_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD19_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1260+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1260+0x08))&0xC0000000)==0x00) group.long (0x1260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1260+0x08)++0x03 line.long 0x00 "TCD19_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1260+0x0C)++0x07 line.long 0x00 "TCD19_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD19_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1260+0x14)++0x01 line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1260+0x16))&0x8000)==0x8000) group.word (0x1260+0x16)++0x01 line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1260+0x16)++0x01 line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1260+0x14))&0x8000)==0x8000) group.word (0x1260+0x14)++0x01 line.word 0x00 "TCD19_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1260+0x14)++0x01 line.word 0x00 "TCD19_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1260+0x16)++0x01 line.word 0x00 "TCD19_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1260+0x18)++0x03 line.long 0x00 "TCD19_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1260+0x1C)++0x01 line.word 0x00 "TCD19_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1260+0x1C))&0x8000)==0x8000) group.word (0x1260+0x1E)++0x01 line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1260+0x1E)++0x01 line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1260+0x1C))&0x8000)==0x8000) group.word (0x1260+0x1C)++0x01 line.word 0x00 "TCD19_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1260+0x1C)++0x01 line.word 0x00 "TCD19_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1260+0x1E)++0x01 line.word 0x00 "TCD19_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1280++0x03 line.long 0x00 "TCD20_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1280+0x04)++0x03 line.word 0x00 "TCD20_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD20_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1280+0x04)++0x03 line.word 0x00 "TCD20_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD20_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1280+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1280+0x08))&0xC0000000)==0x00) group.long (0x1280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1280+0x08)++0x03 line.long 0x00 "TCD20_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1280+0x0C)++0x07 line.long 0x00 "TCD20_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD20_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1280+0x14)++0x01 line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1280+0x16))&0x8000)==0x8000) group.word (0x1280+0x16)++0x01 line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1280+0x16)++0x01 line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1280+0x14))&0x8000)==0x8000) group.word (0x1280+0x14)++0x01 line.word 0x00 "TCD20_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1280+0x14)++0x01 line.word 0x00 "TCD20_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1280+0x16)++0x01 line.word 0x00 "TCD20_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1280+0x18)++0x03 line.long 0x00 "TCD20_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1280+0x1C)++0x01 line.word 0x00 "TCD20_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1280+0x1C))&0x8000)==0x8000) group.word (0x1280+0x1E)++0x01 line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1280+0x1E)++0x01 line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1280+0x1C))&0x8000)==0x8000) group.word (0x1280+0x1C)++0x01 line.word 0x00 "TCD20_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1280+0x1C)++0x01 line.word 0x00 "TCD20_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1280+0x1E)++0x01 line.word 0x00 "TCD20_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x12A0++0x03 line.long 0x00 "TCD21_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12A0+0x04)++0x03 line.word 0x00 "TCD21_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD21_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x12A0+0x04)++0x03 line.word 0x00 "TCD21_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD21_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12A0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x12A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12A0+0x08))&0xC0000000)==0x00) group.long (0x12A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x12A0+0x08)++0x03 line.long 0x00 "TCD21_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x12A0+0x0C)++0x07 line.long 0x00 "TCD21_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD21_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12A0+0x14)++0x01 line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x12A0+0x16))&0x8000)==0x8000) group.word (0x12A0+0x16)++0x01 line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12A0+0x16)++0x01 line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12A0+0x14))&0x8000)==0x8000) group.word (0x12A0+0x14)++0x01 line.word 0x00 "TCD21_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12A0+0x14)++0x01 line.word 0x00 "TCD21_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x12A0+0x16)++0x01 line.word 0x00 "TCD21_DOFF,TCD Signed Destination Address Offset" endif group.long (0x12A0+0x18)++0x03 line.long 0x00 "TCD21_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12A0+0x1C)++0x01 line.word 0x00 "TCD21_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x12A0+0x1C))&0x8000)==0x8000) group.word (0x12A0+0x1E)++0x01 line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12A0+0x1E)++0x01 line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12A0+0x1C))&0x8000)==0x8000) group.word (0x12A0+0x1C)++0x01 line.word 0x00 "TCD21_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12A0+0x1C)++0x01 line.word 0x00 "TCD21_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x12A0+0x1E)++0x01 line.word 0x00 "TCD21_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x12C0++0x03 line.long 0x00 "TCD22_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12C0+0x04)++0x03 line.word 0x00 "TCD22_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD22_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x12C0+0x04)++0x03 line.word 0x00 "TCD22_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD22_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12C0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x12C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12C0+0x08))&0xC0000000)==0x00) group.long (0x12C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x12C0+0x08)++0x03 line.long 0x00 "TCD22_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x12C0+0x0C)++0x07 line.long 0x00 "TCD22_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD22_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12C0+0x14)++0x01 line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x12C0+0x16))&0x8000)==0x8000) group.word (0x12C0+0x16)++0x01 line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12C0+0x16)++0x01 line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12C0+0x14))&0x8000)==0x8000) group.word (0x12C0+0x14)++0x01 line.word 0x00 "TCD22_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12C0+0x14)++0x01 line.word 0x00 "TCD22_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x12C0+0x16)++0x01 line.word 0x00 "TCD22_DOFF,TCD Signed Destination Address Offset" endif group.long (0x12C0+0x18)++0x03 line.long 0x00 "TCD22_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12C0+0x1C)++0x01 line.word 0x00 "TCD22_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x12C0+0x1C))&0x8000)==0x8000) group.word (0x12C0+0x1E)++0x01 line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12C0+0x1E)++0x01 line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12C0+0x1C))&0x8000)==0x8000) group.word (0x12C0+0x1C)++0x01 line.word 0x00 "TCD22_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12C0+0x1C)++0x01 line.word 0x00 "TCD22_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x12C0+0x1E)++0x01 line.word 0x00 "TCD22_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x12E0++0x03 line.long 0x00 "TCD23_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12E0+0x04)++0x03 line.word 0x00 "TCD23_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD23_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x12E0+0x04)++0x03 line.word 0x00 "TCD23_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD23_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12E0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x12E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x12E0+0x08))&0xC0000000)==0x00) group.long (0x12E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x12E0+0x08)++0x03 line.long 0x00 "TCD23_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x12E0+0x0C)++0x07 line.long 0x00 "TCD23_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD23_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12E0+0x14)++0x01 line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x12E0+0x16))&0x8000)==0x8000) group.word (0x12E0+0x16)++0x01 line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12E0+0x16)++0x01 line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12E0+0x14))&0x8000)==0x8000) group.word (0x12E0+0x14)++0x01 line.word 0x00 "TCD23_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x12E0+0x14)++0x01 line.word 0x00 "TCD23_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x12E0+0x16)++0x01 line.word 0x00 "TCD23_DOFF,TCD Signed Destination Address Offset" endif group.long (0x12E0+0x18)++0x03 line.long 0x00 "TCD23_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x12E0+0x1C)++0x01 line.word 0x00 "TCD23_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x12E0+0x1C))&0x8000)==0x8000) group.word (0x12E0+0x1E)++0x01 line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12E0+0x1E)++0x01 line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x12E0+0x1C))&0x8000)==0x8000) group.word (0x12E0+0x1C)++0x01 line.word 0x00 "TCD23_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x12E0+0x1C)++0x01 line.word 0x00 "TCD23_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x12E0+0x1E)++0x01 line.word 0x00 "TCD23_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1300++0x03 line.long 0x00 "TCD24_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1300+0x04)++0x03 line.word 0x00 "TCD24_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD24_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1300+0x04)++0x03 line.word 0x00 "TCD24_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD24_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1300+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1300+0x08))&0xC0000000)==0x00) group.long (0x1300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1300+0x08)++0x03 line.long 0x00 "TCD24_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1300+0x0C)++0x07 line.long 0x00 "TCD24_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD24_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1300+0x14)++0x01 line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1300+0x16))&0x8000)==0x8000) group.word (0x1300+0x16)++0x01 line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1300+0x16)++0x01 line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1300+0x14))&0x8000)==0x8000) group.word (0x1300+0x14)++0x01 line.word 0x00 "TCD24_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1300+0x14)++0x01 line.word 0x00 "TCD24_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1300+0x16)++0x01 line.word 0x00 "TCD24_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1300+0x18)++0x03 line.long 0x00 "TCD24_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1300+0x1C)++0x01 line.word 0x00 "TCD24_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1300+0x1C))&0x8000)==0x8000) group.word (0x1300+0x1E)++0x01 line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1300+0x1E)++0x01 line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1300+0x1C))&0x8000)==0x8000) group.word (0x1300+0x1C)++0x01 line.word 0x00 "TCD24_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1300+0x1C)++0x01 line.word 0x00 "TCD24_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1300+0x1E)++0x01 line.word 0x00 "TCD24_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1320++0x03 line.long 0x00 "TCD25_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1320+0x04)++0x03 line.word 0x00 "TCD25_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD25_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1320+0x04)++0x03 line.word 0x00 "TCD25_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD25_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1320+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1320+0x08))&0xC0000000)==0x00) group.long (0x1320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1320+0x08)++0x03 line.long 0x00 "TCD25_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1320+0x0C)++0x07 line.long 0x00 "TCD25_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD25_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1320+0x14)++0x01 line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1320+0x16))&0x8000)==0x8000) group.word (0x1320+0x16)++0x01 line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1320+0x16)++0x01 line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1320+0x14))&0x8000)==0x8000) group.word (0x1320+0x14)++0x01 line.word 0x00 "TCD25_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1320+0x14)++0x01 line.word 0x00 "TCD25_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1320+0x16)++0x01 line.word 0x00 "TCD25_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1320+0x18)++0x03 line.long 0x00 "TCD25_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1320+0x1C)++0x01 line.word 0x00 "TCD25_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1320+0x1C))&0x8000)==0x8000) group.word (0x1320+0x1E)++0x01 line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1320+0x1E)++0x01 line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1320+0x1C))&0x8000)==0x8000) group.word (0x1320+0x1C)++0x01 line.word 0x00 "TCD25_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1320+0x1C)++0x01 line.word 0x00 "TCD25_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1320+0x1E)++0x01 line.word 0x00 "TCD25_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1340++0x03 line.long 0x00 "TCD26_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1340+0x04)++0x03 line.word 0x00 "TCD26_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD26_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1340+0x04)++0x03 line.word 0x00 "TCD26_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD26_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1340+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1340+0x08))&0xC0000000)==0x00) group.long (0x1340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1340+0x08)++0x03 line.long 0x00 "TCD26_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1340+0x0C)++0x07 line.long 0x00 "TCD26_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD26_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1340+0x14)++0x01 line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1340+0x16))&0x8000)==0x8000) group.word (0x1340+0x16)++0x01 line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1340+0x16)++0x01 line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1340+0x14))&0x8000)==0x8000) group.word (0x1340+0x14)++0x01 line.word 0x00 "TCD26_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1340+0x14)++0x01 line.word 0x00 "TCD26_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1340+0x16)++0x01 line.word 0x00 "TCD26_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1340+0x18)++0x03 line.long 0x00 "TCD26_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1340+0x1C)++0x01 line.word 0x00 "TCD26_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1340+0x1C))&0x8000)==0x8000) group.word (0x1340+0x1E)++0x01 line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1340+0x1E)++0x01 line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1340+0x1C))&0x8000)==0x8000) group.word (0x1340+0x1C)++0x01 line.word 0x00 "TCD26_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1340+0x1C)++0x01 line.word 0x00 "TCD26_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1340+0x1E)++0x01 line.word 0x00 "TCD26_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1360++0x03 line.long 0x00 "TCD27_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1360+0x04)++0x03 line.word 0x00 "TCD27_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD27_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1360+0x04)++0x03 line.word 0x00 "TCD27_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD27_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1360+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1360+0x08))&0xC0000000)==0x00) group.long (0x1360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1360+0x08)++0x03 line.long 0x00 "TCD27_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1360+0x0C)++0x07 line.long 0x00 "TCD27_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD27_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1360+0x14)++0x01 line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1360+0x16))&0x8000)==0x8000) group.word (0x1360+0x16)++0x01 line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1360+0x16)++0x01 line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1360+0x14))&0x8000)==0x8000) group.word (0x1360+0x14)++0x01 line.word 0x00 "TCD27_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1360+0x14)++0x01 line.word 0x00 "TCD27_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1360+0x16)++0x01 line.word 0x00 "TCD27_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1360+0x18)++0x03 line.long 0x00 "TCD27_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1360+0x1C)++0x01 line.word 0x00 "TCD27_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1360+0x1C))&0x8000)==0x8000) group.word (0x1360+0x1E)++0x01 line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1360+0x1E)++0x01 line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1360+0x1C))&0x8000)==0x8000) group.word (0x1360+0x1C)++0x01 line.word 0x00 "TCD27_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1360+0x1C)++0x01 line.word 0x00 "TCD27_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1360+0x1E)++0x01 line.word 0x00 "TCD27_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x1380++0x03 line.long 0x00 "TCD28_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1380+0x04)++0x03 line.word 0x00 "TCD28_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD28_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x1380+0x04)++0x03 line.word 0x00 "TCD28_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD28_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1380+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x1380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x1380+0x08))&0xC0000000)==0x00) group.long (0x1380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1380+0x08)++0x03 line.long 0x00 "TCD28_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x1380+0x0C)++0x07 line.long 0x00 "TCD28_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD28_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1380+0x14)++0x01 line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x1380+0x16))&0x8000)==0x8000) group.word (0x1380+0x16)++0x01 line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1380+0x16)++0x01 line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1380+0x14))&0x8000)==0x8000) group.word (0x1380+0x14)++0x01 line.word 0x00 "TCD28_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x1380+0x14)++0x01 line.word 0x00 "TCD28_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x1380+0x16)++0x01 line.word 0x00 "TCD28_DOFF,TCD Signed Destination Address Offset" endif group.long (0x1380+0x18)++0x03 line.long 0x00 "TCD28_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x1380+0x1C)++0x01 line.word 0x00 "TCD28_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x1380+0x1C))&0x8000)==0x8000) group.word (0x1380+0x1E)++0x01 line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1380+0x1E)++0x01 line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x1380+0x1C))&0x8000)==0x8000) group.word (0x1380+0x1C)++0x01 line.word 0x00 "TCD28_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x1380+0x1C)++0x01 line.word 0x00 "TCD28_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x1380+0x1E)++0x01 line.word 0x00 "TCD28_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x13A0++0x03 line.long 0x00 "TCD29_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13A0+0x04)++0x03 line.word 0x00 "TCD29_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD29_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x13A0+0x04)++0x03 line.word 0x00 "TCD29_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD29_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13A0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x13A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13A0+0x08))&0xC0000000)==0x00) group.long (0x13A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x13A0+0x08)++0x03 line.long 0x00 "TCD29_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x13A0+0x0C)++0x07 line.long 0x00 "TCD29_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD29_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13A0+0x14)++0x01 line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x13A0+0x16))&0x8000)==0x8000) group.word (0x13A0+0x16)++0x01 line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13A0+0x16)++0x01 line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13A0+0x14))&0x8000)==0x8000) group.word (0x13A0+0x14)++0x01 line.word 0x00 "TCD29_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13A0+0x14)++0x01 line.word 0x00 "TCD29_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x13A0+0x16)++0x01 line.word 0x00 "TCD29_DOFF,TCD Signed Destination Address Offset" endif group.long (0x13A0+0x18)++0x03 line.long 0x00 "TCD29_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13A0+0x1C)++0x01 line.word 0x00 "TCD29_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x13A0+0x1C))&0x8000)==0x8000) group.word (0x13A0+0x1E)++0x01 line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13A0+0x1E)++0x01 line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13A0+0x1C))&0x8000)==0x8000) group.word (0x13A0+0x1C)++0x01 line.word 0x00 "TCD29_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13A0+0x1C)++0x01 line.word 0x00 "TCD29_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x13A0+0x1E)++0x01 line.word 0x00 "TCD29_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x13C0++0x03 line.long 0x00 "TCD30_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13C0+0x04)++0x03 line.word 0x00 "TCD30_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD30_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x13C0+0x04)++0x03 line.word 0x00 "TCD30_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD30_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13C0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x13C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13C0+0x08))&0xC0000000)==0x00) group.long (0x13C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x13C0+0x08)++0x03 line.long 0x00 "TCD30_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x13C0+0x0C)++0x07 line.long 0x00 "TCD30_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD30_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13C0+0x14)++0x01 line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x13C0+0x16))&0x8000)==0x8000) group.word (0x13C0+0x16)++0x01 line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13C0+0x16)++0x01 line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13C0+0x14))&0x8000)==0x8000) group.word (0x13C0+0x14)++0x01 line.word 0x00 "TCD30_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13C0+0x14)++0x01 line.word 0x00 "TCD30_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x13C0+0x16)++0x01 line.word 0x00 "TCD30_DOFF,TCD Signed Destination Address Offset" endif group.long (0x13C0+0x18)++0x03 line.long 0x00 "TCD30_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13C0+0x1C)++0x01 line.word 0x00 "TCD30_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x13C0+0x1C))&0x8000)==0x8000) group.word (0x13C0+0x1E)++0x01 line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13C0+0x1E)++0x01 line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13C0+0x1C))&0x8000)==0x8000) group.word (0x13C0+0x1C)++0x01 line.word 0x00 "TCD30_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13C0+0x1C)++0x01 line.word 0x00 "TCD30_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x13C0+0x1E)++0x01 line.word 0x00 "TCD30_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif group.long 0x13E0++0x03 line.long 0x00 "TCD31_SADDR,TCD Source Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13E0+0x04)++0x03 line.word 0x00 "TCD31_SOFF,TCD Signed Source Address Offset" line.word 0x02 "TCD31_ATTR,TCD Transfer Attributes" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,64-bit,,32-byte,?..." else group.word (0x13E0+0x04)++0x03 line.word 0x00 "TCD31_ATTR,TCD Transfer Attributes" bitfld.word 0x00 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8.--10. " SSIZE ,Source data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." bitfld.word 0x00 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--2. " DSIZE ,Destination data transfer size" "8-bit,16-bit,32-bit,,16-byte,32-byte,?..." line.word 0x02 "TCD31_SOFF,TCD Signed Source Address Offset" endif if (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13E0+0x08))&0xC0000000)==(0xC0000000||0x80000000||0x40000000)) group.long (0x13E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 10.--29. 0x04 " MLOFF ,A sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" elif (((per.l.be(ad:0x02C00000))&0x80)==0x80)&&(((per.l.be(ad:0x02C00000+0x13E0+0x08))&0xC0000000)==0x00) group.long (0x13E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x13E0+0x08)++0x03 line.long 0x00 "TCD31_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Disabled)" endif group.long (0x13E0+0x0C)++0x07 line.long 0x00 "TCD31_SLAST,TCD Last Source Address Adjustment" line.long 0x04 "TCD31_DADDR,TCD Destination Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13E0+0x14)++0x01 line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset" if (((per.w.be(ad:0x02C00000+0x13E0+0x16))&0x8000)==0x8000) group.word (0x13E0+0x16)++0x01 line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13E0+0x16)++0x01 line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13E0+0x14))&0x8000)==0x8000) group.word (0x13E0+0x14)++0x01 line.word 0x00 "TCD31_CITER_ELINKYES,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" else group.word (0x13E0+0x14)++0x01 line.word 0x00 "TCD31_CITER_ELINKNO,TCD Current Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" endif group.word (0x13E0+0x16)++0x01 line.word 0x00 "TCD31_DOFF,TCD Signed Destination Address Offset" endif group.long (0x13E0+0x18)++0x03 line.long 0x00 "TCD31_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" sif cpuis("LS10?3*")||cpuis("LS10?6*") group.word (0x13E0+0x1C)++0x01 line.word 0x00 "TCD31_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,,4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "None channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" if (((per.w.be(ad:0x02C00000+0x13E0+0x1C))&0x8000)==0x8000) group.word (0x13E0+0x1E)++0x01 line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13E0+0x1E)++0x01 line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif else if (((per.w.be(ad:0x02C00000+0x13E0+0x1C))&0x8000)==0x8000) group.word (0x13E0+0x1C)++0x01 line.word 0x00 "TCD31_BITER_ELINKYES,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else group.word (0x13E0+0x1C)++0x01 line.word 0x00 "TCD31_BITER_ELINKNO,TCD Beginning Minor Loop Link, Major Loop Count" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" endif group.word (0x13E0+0x1E)++0x01 line.word 0x00 "TCD31_CSR,TCD Control and Status" bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "No eDMA stalls,HPE(no eDMA engine stalls),4 cycles,8 cycles" bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endian.le width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "eSDHC (Enhanced Secured Digital Host Controller)" base ad:0x02140000 width 23. endian.le group.long 0x00++0x03 line.long 0x00 "DSADDR_BLKATTR2,SDMA system address register/Block attributes 2" group.long 0x04++0x03 line.long 0x00 "BLKATTR,Block attributes register" hexmask.long.word 0x00 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLKSIZE ,Transfer block size" if (per.l.le(ad:0x02140000+0x24)&0x01)==0x01 rgroup.long 0x08++0x03 line.long 0x00 "CMDARG,Command argument register" else group.long 0x08++0x03 line.long 0x00 "CMDARG,Command argument register" endif group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer type register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command Type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136,48,48-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "CMDRSP0,Command response 0 register" rgroup.long 0x14++0x03 line.long 0x00 "CMDRSP1,Command response 1 register" rgroup.long 0x18++0x03 line.long 0x00 "CMDRSP2,Command response 2 register" rgroup.long 0x1C++0x03 line.long 0x00 "CMDRSP3,Command response 3 register" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer data port register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present state register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Protected,Not protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" group.long 0x28++0x03 line.long 0x00 "PROCTL,Protocol control register" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stop" bitfld.long 0x00 10. " VOLT_SEL ,Voltage selection" "3.0 V,1.8 V" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "Single DMA,ADMA1,,64-bit ADMA2" newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SD CD pin,CDTL bit" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not inserted,Inserted" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,,Little endian,?..." newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." if (((per.l.le(ad:0x02140000+0x40C))&0x10000)==0x10000) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System control register when ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System control register when ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif group.long 0x30++0x03 line.long 0x00 "IRQSTAT,Interrupt status register" eventfld.long 0x00 29. " RTOE ,Register access timeout error" "No error,Error" eventfld.long 0x00 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x00 26. " TNE ,Tuning Error" "No error,Error" newline eventfld.long 0x00 25. " ADMAE ,ADMA error" "No error,Error" eventfld.long 0x00 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x00 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x00 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x00 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x00 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x00 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x00 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x00 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x00 12. " RTE ,Re-tuning event" "Not required,Required" rbitfld.long 0x00 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " CRM ,Card removal" "Inserted/unstable,Removed" newline eventfld.long 0x00 6. " CINS ,Card insertion" "Removed/unstable,Inserted" eventfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" newline eventfld.long 0x00 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BGE ,Block gap event" "No block gap,Stopped at block gap" eventfld.long 0x00 1. " TC ,Transfer complete" "Not completed,Completed" newline eventfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" group.long 0x34++0x03 line.long 0x00 "IRQSTATEN,Interrupt status enable register" bitfld.long 0x00 29. " RTOESEN ,Register access timeout status enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x00 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " ADMAESEN ,ADMA error status enable" "Disabled,Enabled" bitfld.long 0x00 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x00 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x00 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x00 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" bitfld.long 0x00 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x00 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" bitfld.long 0x00 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x00 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" bitfld.long 0x00 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "IRQSIGEN,Interrupt signal enable register" bitfld.long 0x00 29. " RTOEIEN ,Register access timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " ADMAEIEN ,ADMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " RTEIEN ,Re-tuning event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " CINTIEN ,Card interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CINIEN ,Card insertion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DINTIEN ,DMA interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute Tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by Auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " ACIE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " ACEBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " ACCE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " ACTOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" rgroup.long 0x40++0x03 line.long 0x00 "HOSTCAPBLT,Host controller capabilities register" bitfld.long 0x00 29. " AIS ,Asynchronous Interrupt Support" "Not supported,Supported" bitfld.long 0x00 28. " 64BSBS ,64-bit system bus support" "Not supported,Supported" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" newline bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/resume support" "Not supported,Supported" newline bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" newline bitfld.long 0x00 16.--18. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." rgroup.long 0x44++0x03 line.long 0x00 "WML,Watermark level register" bitfld.long 0x00 24.--27. " WR_BRST_LEN ,Max write burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. " WR_WML ,Write watermark level" bitfld.long 0x00 8.--11. " RD_BRST_LEN ,Max read burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--6. 1. " RD_WML ,Read watermark level" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force event register" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 25. " FEVTADMAE ,Force event ADMA error" "No effect,Force" bitfld.long 0x00 24. " FEVTAC12E ,Force event Auto CMD12 error" "No effect,Force" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No effect,Force" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No effect,Force" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by Auto CMD12 error" "No effect,Force" bitfld.long 0x00 4. " FEVTAC12IE ,Force event Auto CMD12 index error" "No effect,Force" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event Auto CMD12 end bit error" "No effect,Force" bitfld.long 0x00 2. " FEVTAC12CE ,Force event Auto CMD12 CRC error" "No effect,Force" bitfld.long 0x00 1. " EVTAC12TOE ,Force event Auto CMD12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event Auto CMD12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA error status register" bitfld.long 0x00 4. " ADMAIBE ,ADMA internal bus error" "No error,Error" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" newline bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "Idle,Fetch descriptor,Data transfer,Wait for ADMA to stop" group.long 0x58++0x07 line.long 0x00 "ADSADDRL,ADMA system address low register" line.long 0x04 "ADSADDRH,ADMA system address high register" rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host controller version register" hexmask.long.byte 0x00 8.--15. 1. " VVM ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" rgroup.long 0x104++0x0B line.long 0x00 "DMAERRADDRL,DMA error address low register" line.long 0x04 "DMAERRADDRH,DMA error address high register" line.long 0x08 "DMAERRATTR,DMA error attribute register" bitfld.long 0x08 4.--6. " DMA_SIZE ,System bus burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. " DMA_LEN ,System bus burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "HOSTCAPBLT2,Host controller capabilities register 2" bitfld.long 0x00 14.--15. " RTM ,Re-tuning modes" "Mode 1,Mode 2,Mode 3,?..." bitfld.long 0x00 13. " UTSDR50 ,Use tuning for SDR50" "Not supported,Supported" bitfld.long 0x00 8.--11. " TCRT ,Timer Count for Re-Tuning" "Disabled,1s,2s,4s,8s,16s,32s,64s,128s,256s,512s,1024s,,,,Other source" newline bitfld.long 0x00 6. " DTDS ,Driver type D support" "Not supported,Supported" bitfld.long 0x00 5. " DTCS ,Driver type C support" "Not supported,Supported" bitfld.long 0x00 4. " DTAS ,Driver type A support" "Not supported,Supported" newline bitfld.long 0x00 2. " DDR50 ,DDR50 support" "Not supported,Supported" bitfld.long 0x00 1. " SDR104 ,SDR104 Support" "Not supported,Supported" bitfld.long 0x00 0. " SDR50 ,SDR50 support" "Not supported,Supported" group.long 0x120++0x0B line.long 0x00 "TBCTL,Tuning block control register" bitfld.long 0x00 2. " TB_EN ,Tuning block enabled" "Disabled,Enabled" bitfld.long 0x00 0.--1. " TB_MODE ,Tuning Mode" "Mode 1,Mode 2,Mode 3,Software" line.long 0x04 "TBSTAT,Tuning block status register" hexmask.long 0x04 0.--31. 1. " TB_STATUS ,Tuning status" line.long 0x08 "TBPTR,Tuning block pointer register" hexmask.long.byte 0x08 8.--14. 1. " TB_WNDW_STRT_PTR ,Selects window start pointer for software tuning mode" hexmask.long.byte 0x08 0.--6. 1. " TB_WNDW_END_PTR ,Selects window end pointer for software tuning mode" group.long 0x140++0x03 line.long 0x00 "SDDIRCTL,SD direction control register" bitfld.long 0x00 0.--2. " DIR_CTL ,Direction control-SD clock periods for turnaround" "Not required,1 SD clk,2 SD clk,3 SD clk,4 SD clk,5 SD clk,6 SD clk,7 SD clk" group.long 0x40C++0x03 line.long 0x00 "ESDHCCTL,eSDHC control register" bitfld.long 0x00 20.--21. " RTOCV ,Register timeout count value" "2^10 clocks,2^11 clocks,2^12 clocks,2^13 clocks" bitfld.long 0x00 19. " PCS ,Peripheral clock select" "Platform,Peripheral/2" bitfld.long 0x00 18. " FAF ,Flush asynchronous FIFO" "No effect,Flush" newline rbitfld.long 0x00 17. " RTR ,Re-tuning request" "Not requested,Requested" bitfld.long 0x00 16. " CRS ,Clock register select" "8-bit/DVS active,10-bit/CGS active" bitfld.long 0x00 8.--12. " RD_PRFTCH_BLKCNT ,Read prefetch block count" "No prefetch,1 SD block,2 SD blocks,3 SD blocks,4 SD blocks,5 SD blocks,6 SD blocks,7 SD blocks,8 SD blocks,9 SD blocks,10 SD blocks,11 SD blocks,12 SD blocks,13 SD blocks,14 SD blocks,15 SD blocks,16 SD blocks,17 SD blocks,18 SD blocks,19 SD blocks,20 SD blocks,21 SD blocks,22 SD blocks,23 SD blocks,24 SD blocks,25 SD blocks,26 SD blocks,27 SD blocks,28 SD blocks,29 SD blocks,30 SD blocks,31 SD blocks" newline bitfld.long 0x00 7. " PAD_DIS ,Pad disable" "No,Yes" bitfld.long 0x00 6. " SNOOP ,Snoop attribute" "Not snooped,Snooped" bitfld.long 0x00 3. " WR_BUF ,Write bufferable" "Not bufferable,Bufferable" newline bitfld.long 0x00 2. " RD_SAFE ,Read safe (to read more bytes that were intended)" "Not safe,Safe" endian.le width 0x0B tree.end elif cpuis("LS1012*") tree.open "eSDHC (Enhanced Secured Digital Host Controller)" tree "eSDHC 1" base ad:0x01560000 width 23. endian.be group.long 0x00++0x07 line.long 0x00 "DSADDR_BLKATTR2,SDMA System Address Register/Block Attributes 2" line.long 0x04 "BLKATTR,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x04 0.--11. 1. " BLKSIZE ,Transfer block size" if (((per.l.be(ad:0x01560000+0x24))&0x01)==0x01) rgroup.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" else group.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" endif sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) if (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x80000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x180000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x00) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x80000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x180000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif endif else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136,48,48-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif rgroup.long 0x10++0x0F line.long 0x00 "CMDRSP0,Command Response 0 Register" line.long 0x04 "CMDRSP1,Command Response 1 Register" line.long 0x08 "CMDRSP2,Command Response 2 Register" line.long 0x0C "CMDRSP3,Command Response 3 Register" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer Data Port Register" sif cpuis("LS1012*") rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Not protected,Protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" else rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Not protected,Protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" endif group.long 0x28++0x03 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Restart a transaction which was stopped using the stop at block gap request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stop" bitfld.long 0x00 10. " VOLT_SEL ,Voltage selection" "3.0 V,1.8 V" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "Single DMA,ADMA1,32-bit ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SD CD pin,CDTL bit" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not inserted,Inserted" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,,Little endian,?..." newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." if (((per.l.be(ad:0x01560000+0x40C))&0x10000)==0x10000) sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif endif group.long 0x30++0x0B line.long 0x00 "IRQSTAT,Interrupt Status Register" eventfld.long 0x00 29. " RTOE ,Register access timeout error" "No error,Error" eventfld.long 0x00 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x00 26. " TNE ,Tuning error" "No error,Error" newline eventfld.long 0x00 25. " ADMAE ,ADMA error" "No error,Error" eventfld.long 0x00 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x00 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x00 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x00 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x00 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x00 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x00 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x00 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x00 12. " RTE ,Re-tuning event" "Not required,Required" rbitfld.long 0x00 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " CRM ,Card removal" "Inserted or unstable,Removed" newline eventfld.long 0x00 6. " CINS ,Card insertion" "Removed or unstable,Inserted" eventfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" newline eventfld.long 0x00 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BGE ,Block gap event" "No block gap,Stopped at block gap" eventfld.long 0x00 1. " TC ,Transfer complete" "Not completed,Completed" newline eventfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x04 29. " RTOESEN ,Register access timeout status enable" "Disabled,Enabled" bitfld.long 0x04 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x04 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " ADMAESEN ,ADMA error status enable" "Disabled,Enabled" bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x04 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x04 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x04 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x04 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x04 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" bitfld.long 0x04 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" bitfld.long 0x04 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x04 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x04 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x08 29. " RTOEIEN ,Register access timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 25. " ADMAEIEN ,ADMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " RTEIEN ,Re-tuning event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " CINTIEN ,Card interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " DINTIEN ,DMA interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x30))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " AC12IE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " AC12EBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " AC12CE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x3C++0x03 hide.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" endif else group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " ACIE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " ACEBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " ACCE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " ACTOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif rgroup.long 0x40++0x07 line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities Register" bitfld.long 0x00 29. " AIS ,Asynchronous interrupt support" "Not supported,Supported" bitfld.long 0x00 28. " SBS64B ,64-bit system bus support" "Not supported,Supported" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" newline bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/resume support" "Not supported,Supported" newline bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" newline bitfld.long 0x00 16.--18. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." line.long 0x04 "WML,Watermark Level Register" bitfld.long 0x04 24.--27. " WR_BRST_LEN ,Max write burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--22. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--11. " RD_BRST_LEN ,Max read burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 0.--6. 1. " RD_WML ,Read watermark level" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 25. " FEVTADMAE ,Force event ADMA error" "No effect,Force" bitfld.long 0x00 24. " FEVTAC12E ,Force event auto CMD12 error" "No effect,Force" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No effect,Force" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No effect,Force" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto CMD12 error" "No effect,Force" bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto CMD12 index error" "No effect,Force" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto CMD12 end bit error" "No effect,Force" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto CMD12 CRC error" "No effect,Force" bitfld.long 0x00 1. " EVTAC12TOE ,Force event auto CMD12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto CMD12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 4. " ADMAIBE ,ADMA internal bus error" "No error,Error" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" newline bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "Idle,Fetch descriptor,Data transfer,Wait for ADMA to stop" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host Controller Version Register" hexmask.long.byte 0x00 8.--15. 1. " VVM ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" rgroup.long 0x104++0x03 line.long 0x00 "DMAERRADDR,DMA Error Address Register" rgroup.long 0x10C++0x03 line.long 0x00 "DMAERRATTR,DMA Error Attribute Register" bitfld.long 0x00 4.--6. " DMA_SIZE ,System bus burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DMA_LEN ,System bus burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "HOSTCAPBLT2,Host Controller Capabilities Register 2" bitfld.long 0x00 14.--15. " RTM ,Re-tuning modes" "Mode 1,Mode 2,Mode 3,?..." bitfld.long 0x00 13. " UTSDR50 ,Use tuning for SDR50" "Not supported,Supported" bitfld.long 0x00 8.--11. " TCRT ,Timer count for re-tuning" "Disabled,1s,2s,4s,8s,16s,32s,64s,128s,256s,512s,1024s,,,,Other source" newline bitfld.long 0x00 6. " DTDS ,Driver type D support" "Not supported,Supported" bitfld.long 0x00 5. " DTCS ,Driver type C support" "Not supported,Supported" bitfld.long 0x00 4. " DTAS ,Driver type A support" "Not supported,Supported" newline bitfld.long 0x00 2. " DDR50 ,DDR50 support" "Not supported,Supported" bitfld.long 0x00 1. " SDR104 ,SDR104 support" "Not supported,Supported" bitfld.long 0x00 0. " SDR50 ,SDR50 support" "Not supported,Supported" group.long 0x120++0x07 line.long 0x00 "TBCTL,Tuning Block Control Register" bitfld.long 0x00 2. " TB_EN ,Tuning block enabled" "Disabled,Enabled" bitfld.long 0x00 0.--1. " TB_MODE ,Tuning mode" "Mode 1,Mode 2,Mode 3,Software" line.long 0x04 "TBSTAT,Tuning Block Status Register" if (((per.l.be(ad:0x01560000+0x120))&0x03)==0x03) group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" hexmask.long.byte 0x00 8.--14. 0x01 " TB_WNDW_STRT_PTR ,Selects window start pointer for software tuning mode" hexmask.long.byte 0x00 0.--6. 0x01 " TB_WNDW_END_PTR ,Selects window end pointer for software tuning mode" else group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" endif group.long 0x140++0x07 line.long 0x00 "SDDIRCTL,SD Direction Control Register" bitfld.long 0x00 0.--2. " DIR_CTL ,Direction control-SD clock periods for turnaround" "Not required,1 SD clk,2 SD clk,3 SD clk,4 SD clk,5 SD clk,6 SD clk,7 SD clk" line.long 0x04 "SDCLKCTL,SD Clock Control Register" bitfld.long 0x04 31. " LPBK_CLK_SEL ,SD loopback clock select" "Internal,External" bitfld.long 0x04 30. " LPBK_SD_CLK_DLY_DIR ,SD loopback clock delay direction" "Delayed,Early" hexmask.long.word 0x04 16.--27. 1. " LPBK_CLK_DLY ,SSD loopback clock delay" newline bitfld.long 0x04 15. " CMD_CLK_CTL ,Command logic clock control" "Same,25% earlier" group.long 0x40C++0x03 line.long 0x00 "ESDHCCTL,ESDHC Control Register" bitfld.long 0x00 20.--21. " RTOCV ,Register timeout count value" "2^10 clocks,2^11 clocks,2^12 clocks,2^13 clocks" bitfld.long 0x00 19. " PCS ,Peripheral clock select" "Platform,Peripheral" bitfld.long 0x00 18. " FAF ,Flush asynchronous FIFO" "No effect,Flush" newline rbitfld.long 0x00 17. " RTR ,Re-tuning request" "Not requested,Requested" bitfld.long 0x00 16. " CRS ,Clock register select" "8-bit/DVS active,10-bit/CGS active" bitfld.long 0x00 8.--12. " RD_PRFTCH_BLKCNT ,Read prefetch block count" "No prefetch,1 SD block,2 SD blocks,3 SD blocks,4 SD blocks,5 SD blocks,6 SD blocks,7 SD blocks,8 SD blocks,9 SD blocks,10 SD blocks,11 SD blocks,12 SD blocks,13 SD blocks,14 SD blocks,15 SD blocks,16 SD blocks,17 SD blocks,18 SD blocks,19 SD blocks,20 SD blocks,21 SD blocks,22 SD blocks,23 SD blocks,24 SD blocks,25 SD blocks,26 SD blocks,27 SD blocks,28 SD blocks,29 SD blocks,30 SD blocks,31 SD blocks" newline bitfld.long 0x00 7. " PAD_DIS ,Pad disable" "No,Yes" bitfld.long 0x00 6. " SNOOP ,Snoop attribute" "Not snooped,Snooped" bitfld.long 0x00 3. " WR_BUF ,Write bufferable" "Not bufferable,Bufferable" newline bitfld.long 0x00 2. " RD_SAFE ,Read safe (to read more bytes that were intended)" "Not safe,Safe" endian.le width 0x0B tree.end tree "eSDHC 2" base ad:0x01580000 width 23. endian.be group.long 0x00++0x07 line.long 0x00 "DSADDR_BLKATTR2,SDMA System Address Register/Block Attributes 2" line.long 0x04 "BLKATTR,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x04 0.--11. 1. " BLKSIZE ,Transfer block size" if (((per.l.be(ad:0x01580000+0x24))&0x01)==0x01) rgroup.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" else group.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" endif sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01580000+0x24))&0x03)!=0x00) if (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x80000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x180000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x00) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x80000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01580000+0x0C))&0x180000)==0x180000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif endif else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136,48,48-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif rgroup.long 0x10++0x0F line.long 0x00 "CMDRSP0,Command Response 0 Register" line.long 0x04 "CMDRSP1,Command Response 1 Register" line.long 0x08 "CMDRSP2,Command Response 2 Register" line.long 0x0C "CMDRSP3,Command Response 3 Register" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer Data Port Register" sif cpuis("LS1012*") rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" newline bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" newline bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" else rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Not protected,Protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" endif group.long 0x28++0x03 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Restart a transaction which was stopped using the stop at block gap request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stop" bitfld.long 0x00 10. " VOLT_SEL ,Voltage selection" "3.0 V,1.8 V" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "Single DMA,ADMA1,32-bit ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SD CD pin,CDTL bit" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not inserted,Inserted" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,,Little endian,?..." newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." if (((per.l.be(ad:0x01580000+0x40C))&0x10000)==0x10000) sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01580000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01580000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif endif group.long 0x30++0x0B line.long 0x00 "IRQSTAT,Interrupt Status Register" eventfld.long 0x00 29. " RTOE ,Register access timeout error" "No error,Error" eventfld.long 0x00 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x00 26. " TNE ,Tuning error" "No error,Error" newline eventfld.long 0x00 25. " ADMAE ,ADMA error" "No error,Error" eventfld.long 0x00 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x00 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x00 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x00 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x00 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x00 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x00 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x00 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x00 12. " RTE ,Re-tuning event" "Not required,Required" rbitfld.long 0x00 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " CRM ,Card removal" "Inserted or unstable,Removed" newline eventfld.long 0x00 6. " CINS ,Card insertion" "Removed or unstable,Inserted" eventfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" newline eventfld.long 0x00 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BGE ,Block gap event" "No block gap,Stopped at block gap" eventfld.long 0x00 1. " TC ,Transfer complete" "Not completed,Completed" newline eventfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x04 29. " RTOESEN ,Register access timeout status enable" "Disabled,Enabled" bitfld.long 0x04 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x04 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " ADMAESEN ,ADMA error status enable" "Disabled,Enabled" bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x04 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x04 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x04 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x04 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x04 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" bitfld.long 0x04 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" bitfld.long 0x04 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x04 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x04 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x08 29. " RTOEIEN ,Register access timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 25. " ADMAEIEN ,ADMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " RTEIEN ,Re-tuning event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " CINTIEN ,Card interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " DINTIEN ,DMA interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01580000+0x30))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " AC12IE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " AC12EBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " AC12CE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x3C++0x03 hide.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" endif else group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " ACIE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " ACEBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " ACCE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " ACTOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif rgroup.long 0x40++0x07 line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities Register" bitfld.long 0x00 29. " AIS ,Asynchronous interrupt support" "Not supported,Supported" bitfld.long 0x00 28. " SBS64B ,64-bit system bus support" "Not supported,Supported" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" newline bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/resume support" "Not supported,Supported" newline bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" newline bitfld.long 0x00 16.--18. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." line.long 0x04 "WML,Watermark Level Register" bitfld.long 0x04 24.--27. " WR_BRST_LEN ,Max write burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--22. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--11. " RD_BRST_LEN ,Max read burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 0.--6. 1. " RD_WML ,Read watermark level" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 25. " FEVTADMAE ,Force event ADMA error" "No effect,Force" bitfld.long 0x00 24. " FEVTAC12E ,Force event auto CMD12 error" "No effect,Force" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No effect,Force" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No effect,Force" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto CMD12 error" "No effect,Force" bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto CMD12 index error" "No effect,Force" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto CMD12 end bit error" "No effect,Force" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto CMD12 CRC error" "No effect,Force" bitfld.long 0x00 1. " EVTAC12TOE ,Force event auto CMD12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto CMD12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 4. " ADMAIBE ,ADMA internal bus error" "No error,Error" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" newline bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "Idle,Fetch descriptor,Data transfer,Wait for ADMA to stop" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host Controller Version Register" hexmask.long.byte 0x00 8.--15. 1. " VVM ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" rgroup.long 0x104++0x03 line.long 0x00 "DMAERRADDR,DMA Error Address Register" rgroup.long 0x10C++0x03 line.long 0x00 "DMAERRATTR,DMA Error Attribute Register" bitfld.long 0x00 4.--6. " DMA_SIZE ,System bus burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DMA_LEN ,System bus burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "HOSTCAPBLT2,Host Controller Capabilities Register 2" bitfld.long 0x00 14.--15. " RTM ,Re-tuning modes" "Mode 1,Mode 2,Mode 3,?..." bitfld.long 0x00 13. " UTSDR50 ,Use tuning for SDR50" "Not supported,Supported" bitfld.long 0x00 8.--11. " TCRT ,Timer count for re-tuning" "Disabled,1s,2s,4s,8s,16s,32s,64s,128s,256s,512s,1024s,,,,Other source" newline bitfld.long 0x00 6. " DTDS ,Driver type D support" "Not supported,Supported" bitfld.long 0x00 5. " DTCS ,Driver type C support" "Not supported,Supported" bitfld.long 0x00 4. " DTAS ,Driver type A support" "Not supported,Supported" newline bitfld.long 0x00 2. " DDR50 ,DDR50 support" "Not supported,Supported" bitfld.long 0x00 1. " SDR104 ,SDR104 support" "Not supported,Supported" bitfld.long 0x00 0. " SDR50 ,SDR50 support" "Not supported,Supported" group.long 0x120++0x07 line.long 0x00 "TBCTL,Tuning Block Control Register" bitfld.long 0x00 2. " TB_EN ,Tuning block enabled" "Disabled,Enabled" bitfld.long 0x00 0.--1. " TB_MODE ,Tuning mode" "Mode 1,Mode 2,Mode 3,Software" line.long 0x04 "TBSTAT,Tuning Block Status Register" if (((per.l.be(ad:0x01580000+0x120))&0x03)==0x03) group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" hexmask.long.byte 0x00 8.--14. 0x01 " TB_WNDW_STRT_PTR ,Selects window start pointer for software tuning mode" hexmask.long.byte 0x00 0.--6. 0x01 " TB_WNDW_END_PTR ,Selects window end pointer for software tuning mode" else group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" endif group.long 0x140++0x07 line.long 0x00 "SDDIRCTL,SD Direction Control Register" bitfld.long 0x00 0.--2. " DIR_CTL ,Direction control-SD clock periods for turnaround" "Not required,1 SD clk,2 SD clk,3 SD clk,4 SD clk,5 SD clk,6 SD clk,7 SD clk" line.long 0x04 "SDCLKCTL,SD Clock Control Register" bitfld.long 0x04 31. " LPBK_CLK_SEL ,SD loopback clock select" "Internal,External" bitfld.long 0x04 30. " LPBK_SD_CLK_DLY_DIR ,SD loopback clock delay direction" "Delayed,Early" hexmask.long.word 0x04 16.--27. 1. " LPBK_CLK_DLY ,SSD loopback clock delay" newline bitfld.long 0x04 15. " CMD_CLK_CTL ,Command logic clock control" "Same,25% earlier" group.long 0x40C++0x03 line.long 0x00 "ESDHCCTL,ESDHC Control Register" bitfld.long 0x00 20.--21. " RTOCV ,Register timeout count value" "2^10 clocks,2^11 clocks,2^12 clocks,2^13 clocks" bitfld.long 0x00 19. " PCS ,Peripheral clock select" "Platform,Peripheral" bitfld.long 0x00 18. " FAF ,Flush asynchronous FIFO" "No effect,Flush" newline rbitfld.long 0x00 17. " RTR ,Re-tuning request" "Not requested,Requested" bitfld.long 0x00 16. " CRS ,Clock register select" "8-bit/DVS active,10-bit/CGS active" bitfld.long 0x00 8.--12. " RD_PRFTCH_BLKCNT ,Read prefetch block count" "No prefetch,1 SD block,2 SD blocks,3 SD blocks,4 SD blocks,5 SD blocks,6 SD blocks,7 SD blocks,8 SD blocks,9 SD blocks,10 SD blocks,11 SD blocks,12 SD blocks,13 SD blocks,14 SD blocks,15 SD blocks,16 SD blocks,17 SD blocks,18 SD blocks,19 SD blocks,20 SD blocks,21 SD blocks,22 SD blocks,23 SD blocks,24 SD blocks,25 SD blocks,26 SD blocks,27 SD blocks,28 SD blocks,29 SD blocks,30 SD blocks,31 SD blocks" newline bitfld.long 0x00 7. " PAD_DIS ,Pad disable" "No,Yes" bitfld.long 0x00 6. " SNOOP ,Snoop attribute" "Not snooped,Snooped" bitfld.long 0x00 3. " WR_BUF ,Write bufferable" "Not bufferable,Bufferable" newline bitfld.long 0x00 2. " RD_SAFE ,Read safe (to read more bytes that were intended)" "Not safe,Safe" endian.le width 0x0B tree.end tree.end else tree "eSDHC (Enhanced Secured Digital Host Controller)" base ad:0x01560000 width 23. endian.be group.long 0x00++0x07 line.long 0x00 "DSADDR_BLKATTR2,SDMA System Address Register/Block Attributes 2" line.long 0x04 "BLKATTR,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x04 0.--11. 1. " BLKSIZE ,Transfer block size" if (((per.l.be(ad:0x01560000+0x24))&0x01)==0x01) rgroup.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" else group.long 0x08++0x03 line.long 0x00 "CMDARG,Command Argument Register" endif sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) if (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x00) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x80000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x180000) rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else rgroup.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x00) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R3/R4,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x80000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,R2,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x01560000+0x0C))&0x180000)==0x180000) group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,R1/R5/R6/R7,R1b/R5b" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136 length,48 length,48 length-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif endif else group.long 0x0C++0x03 line.long 0x00 "XFERTYP,Transfer Type Register" bitfld.long 0x00 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 22.--23. " CMDTYP ,Command type" "Normal,Suspend CMD52,Resume CMD52,Abort CMD12 CMD52" bitfld.long 0x00 21. " DPSEL ,Data present select" "No data present,Data present" newline bitfld.long 0x00 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCEN ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSPTYP ,Response type select" "No response,136,48,48-check busy after" newline bitfld.long 0x00 5. " MSBSEL ,Multi-/single-block select" "Single,Multiple" bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write (host to card),Read (card to host)" bitfld.long 0x00 2.--3. " ACEN ,Auto CMD12 enable" "Auto CMD disabled,Auto CMD12 enabled,Auto CMD23 enabled,?..." newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif rgroup.long 0x10++0x0F line.long 0x00 "CMDRSP0,Command Response 0 Register" line.long 0x04 "CMDRSP1,Command Response 1 Register" line.long 0x08 "CMDRSP2,Command Response 2 Register" line.long 0x0C "CMDRSP3,Command Response 3 Register" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer Data Port Register" sif cpuis("LS1012*") rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Not protected,Protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" else rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" hexmask.long.byte 0x00 24.--31. 1. " DLSL ,DAT[7:0] line signal level" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "0,1" bitfld.long 0x00 19. " WPS ,Write protect state" "Not protected,Protected" newline bitfld.long 0x00 18. " CDS ,Card detect state" "Not present,Present" bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active" newline bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Inactive,Active" newline bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not inhibited,Inhibited" bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not inhibited,Inhibited" endif group.long 0x28++0x03 line.long 0x00 "PROCTL,Protocol Control Register" bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Restart a transaction which was stopped using the stop at block gap request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stop" bitfld.long 0x00 10. " VOLT_SEL ,Voltage selection" "3.0 V,1.8 V" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "Single DMA,ADMA1,32-bit ADMA2,?..." newline bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SD CD pin,CDTL bit" bitfld.long 0x00 6. " CDTL ,Card detect test level" "Not inserted,Inserted" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,,Little endian,?..." newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." if (((per.l.be(ad:0x01560000+0x40C))&0x10000)==0x10000) sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_1,System Control Register When ESDHCCTL[CRS=1]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 6.--7. " USDCLKFS ,Upper bits of SDCLK frequency select" "0,1,2,3" bitfld.long 0x00 5. " CGS ,10-bit SDCLKFS clock mode select" "Divided,Programmable" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x24))&0x03)!=0x00) group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,?..." bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif else group.long 0x2C++0x03 line.long 0x00 "SYSCTL_ESDHCCTL_CRS_0,System Control Register When ESDHCCTL[CRS=0]" bitfld.long 0x00 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x00 26. " RSTD ,Software reset for DAT line" "No reset,Reset" bitfld.long 0x00 25. " RSTC ,Software reset for CMD line" "No reset,Reset" newline bitfld.long 0x00 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,SDCLK x 2^23,SDCLK x 2^24,SDCLK x 2^25,SDCLK x 2^26,SDCLK x 2^27,?..." hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x00 4.--7. " DVS ,Provides more exact divisor to generate desired SD clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" bitfld.long 0x00 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" endif endif group.long 0x30++0x0B line.long 0x00 "IRQSTAT,Interrupt Status Register" eventfld.long 0x00 29. " RTOE ,Register access timeout error" "No error,Error" eventfld.long 0x00 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x00 26. " TNE ,Tuning error" "No error,Error" newline eventfld.long 0x00 25. " ADMAE ,ADMA error" "No error,Error" eventfld.long 0x00 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x00 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x00 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x00 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x00 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x00 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x00 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x00 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x00 12. " RTE ,Re-tuning event" "Not required,Required" rbitfld.long 0x00 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " CRM ,Card removal" "Inserted or unstable,Removed" newline eventfld.long 0x00 6. " CINS ,Card insertion" "Removed or unstable,Inserted" eventfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" newline eventfld.long 0x00 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BGE ,Block gap event" "No block gap,Stopped at block gap" eventfld.long 0x00 1. " TC ,Transfer complete" "Not completed,Completed" newline eventfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x04 29. " RTOESEN ,Register access timeout status enable" "Disabled,Enabled" bitfld.long 0x04 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x04 26. " TNESEN ,Tuning error status enable" "Disabled,Enabled" newline bitfld.long 0x04 25. " ADMAESEN ,ADMA error status enable" "Disabled,Enabled" bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x04 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x04 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x04 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x04 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x04 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x04 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " RTESEN ,Re-tuning event status enable" "Disabled,Enabled" bitfld.long 0x04 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" bitfld.long 0x04 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x04 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" bitfld.long 0x04 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x04 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x08 29. " RTOEIEN ,Register access timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x08 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 26. " TNEIEN ,Tuning error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 25. " ADMAEIEN ,ADMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 12. " RTEIEN ,Re-tuning event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 8. " CINTIEN ,Card interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" bitfld.long 0x08 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x08 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 3. " DINTIEN ,DMA interrupt interrupt enable" "Disabled,Enabled" bitfld.long 0x08 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x08 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x01560000+0x30))&0x1000000)==0x1000000) group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " AC12IE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " AC12EBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " AC12CE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " AC12TOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x3C++0x03 hide.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" endif else group.long 0x3C++0x03 line.long 0x00 "AUTOCERR_SYSCTL2,Auto CMD Error Status Register / System Control 2 Register" bitfld.long 0x00 30. " AIE ,Asynchronous interrupt enable" "Disabled,Enabled" bitfld.long 0x00 23. " SMPCLKSEL ,Sampling clock select" "Unsuccessful,Successful" bitfld.long 0x00 22. " EXTN ,Execute tuning" "Not executed,Executed" newline bitfld.long 0x00 16.--18. " UHSM[0:2] ,UHS mode select" "SD: SDR12 SD2.0: 52Mhz,SD: SDR25,SD: SDR50,SD: SDR104 MMC: HS200,DDR,?..." rbitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Error" rbitfld.long 0x00 4. " ACIE ,Auto CMD index error" "No error,Error" newline rbitfld.long 0x00 3. " ACEBE ,Auto CMD end bit error" "No error,Error" rbitfld.long 0x00 2. " ACCE ,Auto CMD CRC error" "No error,Error" rbitfld.long 0x00 1. " ACTOE ,Auto CMD timeout error" "No error,Error" newline rbitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif rgroup.long 0x40++0x07 line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities Register" bitfld.long 0x00 29. " AIS ,Asynchronous interrupt support" "Not supported,Supported" bitfld.long 0x00 28. " SBS64B ,64-bit system bus support" "Not supported,Supported" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported" newline bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/resume support" "Not supported,Supported" newline bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" newline bitfld.long 0x00 16.--18. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." line.long 0x04 "WML,Watermark Level Register" bitfld.long 0x04 24.--27. " WR_BRST_LEN ,Max write burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--22. 1. " WR_WML ,Write watermark level" bitfld.long 0x04 8.--11. " RD_BRST_LEN ,Max read burst length" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x04 0.--6. 1. " RD_WML ,Read watermark level" wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 28. " FEVTDMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 25. " FEVTADMAE ,Force event ADMA error" "No effect,Force" bitfld.long 0x00 24. " FEVTAC12E ,Force event auto CMD12 error" "No effect,Force" newline bitfld.long 0x00 22. " FEVTDEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " FEVTDCE ,Force event data CRC error" "No effect,Force" bitfld.long 0x00 20. " FEVTDTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " FEVTCIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " FEVTCEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " FEVTCCE ,Force event command CRC error" "No effect,Force" newline bitfld.long 0x00 16. " FEVTCTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force event command not executed by auto CMD12 error" "No effect,Force" bitfld.long 0x00 4. " FEVTAC12IE ,Force event auto CMD12 index error" "No effect,Force" newline bitfld.long 0x00 3. " FEVTAC12EBE ,Force event auto CMD12 end bit error" "No effect,Force" bitfld.long 0x00 2. " FEVTAC12CE ,Force event auto CMD12 CRC error" "No effect,Force" bitfld.long 0x00 1. " EVTAC12TOE ,Force event auto CMD12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " FEVTAC12NE ,Force event auto CMD12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 4. " ADMAIBE ,ADMA internal bus error" "No error,Error" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" newline bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "Idle,Fetch descriptor,Data transfer,Wait for ADMA to stop" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host Controller Version Register" hexmask.long.byte 0x00 8.--15. 1. " VVM ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" rgroup.long 0x104++0x03 line.long 0x00 "DMAERRADDR,DMA Error Address Register" rgroup.long 0x10C++0x03 line.long 0x00 "DMAERRATTR,DMA Error Attribute Register" bitfld.long 0x00 4.--6. " DMA_SIZE ,System bus burst size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " DMA_LEN ,System bus burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x114++0x03 line.long 0x00 "HOSTCAPBLT2,Host Controller Capabilities Register 2" bitfld.long 0x00 14.--15. " RTM ,Re-tuning modes" "Mode 1,Mode 2,Mode 3,?..." bitfld.long 0x00 13. " UTSDR50 ,Use tuning for SDR50" "Not supported,Supported" bitfld.long 0x00 8.--11. " TCRT ,Timer count for re-tuning" "Disabled,1s,2s,4s,8s,16s,32s,64s,128s,256s,512s,1024s,,,,Other source" newline bitfld.long 0x00 6. " DTDS ,Driver type D support" "Not supported,Supported" bitfld.long 0x00 5. " DTCS ,Driver type C support" "Not supported,Supported" bitfld.long 0x00 4. " DTAS ,Driver type A support" "Not supported,Supported" newline bitfld.long 0x00 2. " DDR50 ,DDR50 support" "Not supported,Supported" bitfld.long 0x00 1. " SDR104 ,SDR104 support" "Not supported,Supported" bitfld.long 0x00 0. " SDR50 ,SDR50 support" "Not supported,Supported" group.long 0x120++0x07 line.long 0x00 "TBCTL,Tuning Block Control Register" bitfld.long 0x00 2. " TB_EN ,Tuning block enabled" "Disabled,Enabled" bitfld.long 0x00 0.--1. " TB_MODE ,Tuning mode" "Mode 1,Mode 2,Mode 3,Software" line.long 0x04 "TBSTAT,Tuning Block Status Register" if (((per.l.be(ad:0x01560000+0x120))&0x03)==0x03) group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" hexmask.long.byte 0x00 8.--14. 0x01 " TB_WNDW_STRT_PTR ,Selects window start pointer for software tuning mode" hexmask.long.byte 0x00 0.--6. 0x01 " TB_WNDW_END_PTR ,Selects window end pointer for software tuning mode" else group.long 0x128++0x03 line.long 0x00 "TBPTR,Tuning Block Pointer Register" endif group.long 0x140++0x07 line.long 0x00 "SDDIRCTL,SD Direction Control Register" bitfld.long 0x00 0.--2. " DIR_CTL ,Direction control-SD clock periods for turnaround" "Not required,1 SD clk,2 SD clk,3 SD clk,4 SD clk,5 SD clk,6 SD clk,7 SD clk" line.long 0x04 "SDCLKCTL,SD Clock Control Register" bitfld.long 0x04 31. " LPBK_CLK_SEL ,SD loopback clock select" "Internal,External" bitfld.long 0x04 30. " LPBK_SD_CLK_DLY_DIR ,SD loopback clock delay direction" "Delayed,Early" hexmask.long.word 0x04 16.--27. 1. " LPBK_CLK_DLY ,SSD loopback clock delay" newline bitfld.long 0x04 15. " CMD_CLK_CTL ,Command logic clock control" "Same,25% earlier" group.long 0x40C++0x03 line.long 0x00 "ESDHCCTL,ESDHC Control Register" bitfld.long 0x00 20.--21. " RTOCV ,Register timeout count value" "2^10 clocks,2^11 clocks,2^12 clocks,2^13 clocks" bitfld.long 0x00 19. " PCS ,Peripheral clock select" "Platform,Peripheral" bitfld.long 0x00 18. " FAF ,Flush asynchronous FIFO" "No effect,Flush" newline rbitfld.long 0x00 17. " RTR ,Re-tuning request" "Not requested,Requested" bitfld.long 0x00 16. " CRS ,Clock register select" "8-bit/DVS active,10-bit/CGS active" bitfld.long 0x00 8.--12. " RD_PRFTCH_BLKCNT ,Read prefetch block count" "No prefetch,1 SD block,2 SD blocks,3 SD blocks,4 SD blocks,5 SD blocks,6 SD blocks,7 SD blocks,8 SD blocks,9 SD blocks,10 SD blocks,11 SD blocks,12 SD blocks,13 SD blocks,14 SD blocks,15 SD blocks,16 SD blocks,17 SD blocks,18 SD blocks,19 SD blocks,20 SD blocks,21 SD blocks,22 SD blocks,23 SD blocks,24 SD blocks,25 SD blocks,26 SD blocks,27 SD blocks,28 SD blocks,29 SD blocks,30 SD blocks,31 SD blocks" newline bitfld.long 0x00 7. " PAD_DIS ,Pad disable" "No,Yes" bitfld.long 0x00 6. " SNOOP ,Snoop attribute" "Not snooped,Snooped" bitfld.long 0x00 3. " WR_BUF ,Write bufferable" "Not bufferable,Bufferable" newline bitfld.long 0x00 2. " RD_SAFE ,Read safe (to read more bytes that were intended)" "Not safe,Safe" endian.le width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree.open "FTM (FlexTimer Module)" tree "FTM_1" base ad:0x02800000 width 10. if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02800000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02800000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02800000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02800000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if (((per.l(ad:0x02800000+0x54))&0x80000000)==0x01) group.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" endif if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" group.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" group.long 0x90++0x03 line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x00 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x00 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x00 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x00 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x00 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x00 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x00 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x00 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x00 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x00 0. " CH0SEL ,Channel 0 Select" "Not included,Included" else rgroup.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x04 7. " CH7F ,Channel 7 event Flag" "Not occurred,Occurred" bitfld.long 0x04 6. " CH6F ,Channel 6 event Flag" "Not occurred,Occurred" bitfld.long 0x04 5. " CH5F ,Channel 5 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 4. " CH4F ,Channel 4 event Flag" "Not occurred,Occurred" bitfld.long 0x04 3. " CH3F ,Channel 3 event Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " CH2F ,Channel 2 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " CH1F ,Channel 1 event Flag" "Not occurred,Occurred" bitfld.long 0x04 0. " CH0F ,Channel 0 event Flag" "Not occurred,Occurred" if (((per.l(ad:0x02800000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" endif rgroup.long 0x58++0x07 line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" rgroup.long 0x60++0x0F line.long 0x00 "OUTMASK,Output Mask Register" bitfld.long 0x00 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x00 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x00 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x00 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x00 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x00 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" line.long 0x04 "COMBINE,Function For Linked Channels Register" bitfld.long 0x04 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x04 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x04 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x04 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x04 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x04 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x04 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x04 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x04 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x04 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x04 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x04 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x04 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x04 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x04 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" line.long 0x08 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x08 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x08 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EXTTRIG,FTM External Trigger Register" bitfld.long 0x0C 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x0C 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rgroup.long 0x74++0x03 line.long 0x00 "FMS,Fault Mode Status Register" bitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FAULTIN ,Fault Inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "Not detected,Detected" endif rgroup.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" rgroup.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" rgroup.long 0x90++0x0B line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" line.long 0x04 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x04 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" line.long 0x08 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x08 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x08 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x08 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x08 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x08 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x08 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x08 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x08 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x08 0. " CH0SEL ,Channel 0 Select" "Not included,Included" endif width 0x0B tree.end tree "FTM_2" base ad:0x02810000 width 10. if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02810000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02810000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02810000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02810000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if (((per.l(ad:0x02810000+0x54))&0x80000000)==0x01) group.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" endif if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" group.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" group.long 0x90++0x03 line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x00 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x00 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x00 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x00 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x00 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x00 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x00 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x00 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x00 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x00 0. " CH0SEL ,Channel 0 Select" "Not included,Included" else rgroup.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x04 7. " CH7F ,Channel 7 event Flag" "Not occurred,Occurred" bitfld.long 0x04 6. " CH6F ,Channel 6 event Flag" "Not occurred,Occurred" bitfld.long 0x04 5. " CH5F ,Channel 5 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 4. " CH4F ,Channel 4 event Flag" "Not occurred,Occurred" bitfld.long 0x04 3. " CH3F ,Channel 3 event Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " CH2F ,Channel 2 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " CH1F ,Channel 1 event Flag" "Not occurred,Occurred" bitfld.long 0x04 0. " CH0F ,Channel 0 event Flag" "Not occurred,Occurred" if (((per.l(ad:0x02810000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" endif rgroup.long 0x58++0x07 line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" rgroup.long 0x60++0x0F line.long 0x00 "OUTMASK,Output Mask Register" bitfld.long 0x00 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x00 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x00 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x00 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x00 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x00 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" line.long 0x04 "COMBINE,Function For Linked Channels Register" bitfld.long 0x04 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x04 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x04 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x04 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x04 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x04 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x04 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x04 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x04 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x04 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x04 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x04 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x04 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x04 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x04 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" line.long 0x08 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x08 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x08 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EXTTRIG,FTM External Trigger Register" bitfld.long 0x0C 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x0C 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rgroup.long 0x74++0x03 line.long 0x00 "FMS,Fault Mode Status Register" bitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FAULTIN ,Fault Inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "Not detected,Detected" endif rgroup.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" rgroup.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" rgroup.long 0x90++0x0B line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" line.long 0x04 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x04 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" line.long 0x08 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x08 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x08 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x08 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x08 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x08 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x08 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x08 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x08 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x08 0. " CH0SEL ,Channel 0 Select" "Not included,Included" endif width 0x0B tree.end tree "FTM_3" base ad:0x02820000 width 10. if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02820000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02820000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02820000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02820000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if (((per.l(ad:0x02820000+0x54))&0x80000000)==0x01) group.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" endif if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" group.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" group.long 0x90++0x03 line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x00 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x00 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x00 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x00 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x00 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x00 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x00 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x00 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x00 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x00 0. " CH0SEL ,Channel 0 Select" "Not included,Included" else rgroup.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x04 7. " CH7F ,Channel 7 event Flag" "Not occurred,Occurred" bitfld.long 0x04 6. " CH6F ,Channel 6 event Flag" "Not occurred,Occurred" bitfld.long 0x04 5. " CH5F ,Channel 5 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 4. " CH4F ,Channel 4 event Flag" "Not occurred,Occurred" bitfld.long 0x04 3. " CH3F ,Channel 3 event Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " CH2F ,Channel 2 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " CH1F ,Channel 1 event Flag" "Not occurred,Occurred" bitfld.long 0x04 0. " CH0F ,Channel 0 event Flag" "Not occurred,Occurred" if (((per.l(ad:0x02820000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" endif rgroup.long 0x58++0x07 line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" rgroup.long 0x60++0x0F line.long 0x00 "OUTMASK,Output Mask Register" bitfld.long 0x00 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x00 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x00 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x00 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x00 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x00 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" line.long 0x04 "COMBINE,Function For Linked Channels Register" bitfld.long 0x04 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x04 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x04 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x04 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x04 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x04 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x04 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x04 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x04 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x04 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x04 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x04 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x04 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x04 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x04 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" line.long 0x08 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x08 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x08 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EXTTRIG,FTM External Trigger Register" bitfld.long 0x0C 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x0C 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rgroup.long 0x74++0x03 line.long 0x00 "FMS,Fault Mode Status Register" bitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FAULTIN ,Fault Inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "Not detected,Detected" endif rgroup.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" rgroup.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" rgroup.long 0x90++0x0B line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" line.long 0x04 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x04 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" line.long 0x08 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x08 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x08 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x08 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x08 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x08 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x08 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x08 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x08 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x08 0. " CH0SEL ,Channel 0 Select" "Not included,Included" endif width 0x0B tree.end tree "FTM_4" base ad:0x02830000 width 10. if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02830000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02830000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02830000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02830000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" if (((per.l(ad:0x02830000+0x54))&0x80000000)==0x01) group.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" line.long 0x08 "OUTMASK,Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" endif if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" newline bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" endif group.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" group.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" group.long 0x90++0x03 line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x00 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x00 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x00 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" group.long 0x98++0x03 line.long 0x00 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x00 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x00 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x00 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x00 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x00 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x00 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x00 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x00 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x00 0. " CH0SEL ,Channel 0 Select" "Not included,Included" else rgroup.long 0x4C++0x07 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial Value Of The FTM Counter" line.long 0x04 "STATUS,Capture And Compare Status Register" bitfld.long 0x04 7. " CH7F ,Channel 7 event Flag" "Not occurred,Occurred" bitfld.long 0x04 6. " CH6F ,Channel 6 event Flag" "Not occurred,Occurred" bitfld.long 0x04 5. " CH5F ,Channel 5 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 4. " CH4F ,Channel 4 event Flag" "Not occurred,Occurred" bitfld.long 0x04 3. " CH3F ,Channel 3 event Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " CH2F ,Channel 2 event Flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " CH1F ,Channel 1 event Flag" "Not occurred,Occurred" bitfld.long 0x04 0. " CH0F ,Channel 0 event Flag" "Not occurred,Occurred" if (((per.l(ad:0x02830000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" newline bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rbitfld.long 0x00 7. " FAULTIE ,Fault Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault Control Mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture Test Mode Enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write Protection Disable" "No,Yes" bitfld.long 0x00 0. " FTMEN ,FTM Enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " INIT ,Initialize The Channels Output" "No effect,Initialize" endif rgroup.long 0x58++0x07 line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM Synchronization Software Trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM Synchronization Hardware Trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM Synchronization Hardware Trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM Synchronization Hardware Trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output Mask Synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM Counter Reinitialization By Synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum Loading Point Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum Loading Point Enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 Output Initialization Value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 Output Initialization Value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 Output Initialization Value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 Output Initialization Value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 Output Initialization Value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 Output Initialization Value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 Output Initialization Value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 Output Initialization Value" "0,1" rgroup.long 0x60++0x0F line.long 0x00 "OUTMASK,Output Mask Register" bitfld.long 0x00 7. " CH7OM ,Channel 7 Output Mask" "Not masked,Masked" bitfld.long 0x00 6. " CH6OM ,Channel 6 Output Mask" "Not masked,Masked" bitfld.long 0x00 5. " CH5OM ,Channel 5 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 4. " CH4OM ,Channel 4 Output Mask" "Not masked,Masked" bitfld.long 0x00 3. " CH3OM ,Channel 3 Output Mask" "Not masked,Masked" bitfld.long 0x00 2. " CH2OM ,Channel 2 Output Mask" "Not masked,Masked" newline bitfld.long 0x00 1. " CH1OM ,Channel 1 Output Mask" "Not masked,Masked" bitfld.long 0x00 0. " CH0OM ,Channel 0 Output Mask" "Not masked,Masked" line.long 0x04 "COMBINE,Function For Linked Channels Register" bitfld.long 0x04 30. " FAULTEN3 ,Fault Control Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 29. " SYNCEN3 ,Synchronization Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 28. " DTEN3 ,Deadtime Enable For n = 6" "Disabled,Enabled" newline bitfld.long 0x04 27. " DECAP3 ,Dual Edge Capture Mode Captures For n = 6" "Inactive,Active" bitfld.long 0x04 26. " DECAPEN3 ,Dual Edge Capture Mode Enable For n = 6" "Disabled,Enabled" bitfld.long 0x04 25. " COMP3 ,Complement Of Channel (n) for n = 6" "The same,Complement" newline bitfld.long 0x04 24. " COMBINE3 ,Combine Channels For n = 6" "Independent,Combined" bitfld.long 0x04 22. " FAULTEN2 ,Fault Control Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 21. " SYNCEN2 ,Synchronization Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 20. " DTEN2 ,Deadtime Enable For n = 4" "Disabled,Enabled" bitfld.long 0x04 19. " DECAP2 ,Dual Edge Capture Mode Captures For n = 4" "Inactive,Active" bitfld.long 0x04 18. " DECAPEN2 ,Dual Edge Capture Mode Enable For n = 4" "Disabled,Enabled" newline bitfld.long 0x04 17. " COMP2 ,Complement Of Channel (n) for n = 4" "The same,Complement" bitfld.long 0x04 16. " COMBINE2 ,Combine Channels For n = 4" "Independent,Combined" bitfld.long 0x04 14. " FAULTEN1 ,Fault Control Enable For n = 2" "Disabled,Enabled" newline bitfld.long 0x04 13. " SYNCEN1 ,Synchronization Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 12. " DTEN1 ,Deadtime Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 11. " DECAP1 ,Dual Edge Capture Mode Captures For n = 2" "Inactive,Active" newline bitfld.long 0x04 10. " DECAPEN1 ,Dual Edge Capture Mode Enable For n = 2" "Disabled,Enabled" bitfld.long 0x04 9. " COMP1 ,Complement Of Channel (n) for n = 2" "The same,Complement" bitfld.long 0x04 8. " COMBINE1 ,Combine Channels For n = 2" "Independent,Combined" newline bitfld.long 0x04 6. " FAULTEN0 ,Fault Control Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 5. " SYNCEN0 ,Synchronization Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 4. " DTEN0 ,Deadtime Enable For n = 0" "Disabled,Enabled" newline bitfld.long 0x04 3. " DECAP0 ,Dual Edge Capture Mode Captures For n = 0" "Inactive,Active" bitfld.long 0x04 2. " DECAPEN0 ,Dual Edge Capture Mode Enable For n = 0" "Disabled,Enabled" bitfld.long 0x04 1. " COMP0 ,Complement Of Channel (n) for n = 0" "The same,Complement" newline bitfld.long 0x04 0. " COMBINE0 ,Combine Channels For n = 0" "Independent,Combined" line.long 0x08 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x08 6.--7. " DTPS ,Deadtime Prescaler Value" "/1,/1,/4,/16" bitfld.long 0x08 0.--5. " DTVAL ,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "EXTTRIG,FTM External Trigger Register" bitfld.long 0x0C 7. " TRIGF ,Channel Trigger Flag" "Not triggered,Triggered" bitfld.long 0x0C 6. " INITTRIGEN ,Initialization Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 5. " CH1TRIG ,Channel 1 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 4. " CH0TRIG ,Channel 0 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " CH5TRIG ,Channel 5 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CH4TRIG ,Channel 4 Trigger Enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH3TRIG ,Channel 3 Trigger Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CH2TRIG ,Channel 2 Trigger Enable" "Disabled,Enabled" rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" bitfld.long 0x00 7. " POL7 ,Channel 7 Polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 Polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 Polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 Polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 Polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 Polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 Polarity" "Active high,Active low" bitfld.long 0x00 0. " POL0 ,Channel 0 Polarity" "Active high,Active low" sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") rgroup.long 0x74++0x03 line.long 0x00 "FMS,Fault Mode Status Register" bitfld.long 0x00 7. " FAULTF ,Fault Detection Flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write Protection Enable" "Disabled,Enabled" bitfld.long 0x00 5. " FAULTIN ,Fault Inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault Detection Flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault Detection Flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault Detection Flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault Detection Flag 0" "Not detected,Detected" endif rgroup.long 0x78++0x03 line.long 0x00 "FILTER,Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 Input Filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global Time Base Output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global Time Base Enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM Mode" "0,1,2,3" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency. the ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not 2 next,First-not 3 next,First-not 4 next,First-not 5 next,First-not 6 next,First-not 7 next,First-not 8 next,First-not 9 next,First-not 10 next,First-not 11 next,First-not 12 next,First-not 13 next,First-not 14 next,First-not 15 next,First-not 16 next,First-not 17 next,First-not 18 next,First-not 19 next,First-not 20 next,First-not 21 next,First-not 22 next,First-not 23 next,First-not 24 next,First-not 25 next,First-not 26 next,First-not 27 next,First-not 28 next,First-not 29 next,First-not 30 next,First-not 31 next" rgroup.long 0x8C++0x03 line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD CNTIN and CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD CNTIN and CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization Mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL Register Synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN Register Synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware Trigger Mode" "Cleared,Not cleared" rgroup.long 0x90++0x0B line.long 0x00 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x00 3. " INV3EN ,Pair Channels 3 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 2. " INV2EN ,Pair Channels 2 Inverting Enable" "Disabled,Enabled" bitfld.long 0x00 1. " INV1EN ,Pair Channels 1 Inverting Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " INV0EN ,Pair Channels 0 Inverting Enable" "Disabled,Enabled" line.long 0x04 "SWOCTRL,FTM Software Output Control Register" bitfld.long 0x04 15. " CH7OCV ,Channel 7 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 14. " CH6OCV ,Channel 6 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 13. " CH5OCV ,Channel 5 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 12. " CH4OCV ,Channel 4 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 11. " CH3OCV ,Channel 3 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 10. " CH2OCV ,Channel 2 Software Output Control Value" "Forced 0,Forced 1" newline bitfld.long 0x04 9. " CH1OCV ,Channel 1 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 8. " CH0OCV ,Channel 0 Software Output Control Value" "Forced 0,Forced 1" bitfld.long 0x04 7. " CH7OC ,Channel 7 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 6. " CH6OC ,Channel 6 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 5. " CH5OC ,Channel 5 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 4. " CH4OC ,Channel 4 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 3. " CH3OC ,Channel 3 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 2. " CH2OC ,Channel 2 Software Output Control Enable" "Disabled,Enabled" bitfld.long 0x04 1. " CH1OC ,Channel 1 Software Output Control Enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " CH0OC ,Channel 0 Software Output Control Enable" "Disabled,Enabled" line.long 0x08 "PWMLOAD,FTM PWM Load Register" bitfld.long 0x08 9. " LDOK ,Load Enable" "Disabled,Enabled" bitfld.long 0x08 7. " CH7SEL ,Channel 7 Select" "Not included,Included" bitfld.long 0x08 6. " CH6SEL ,Channel 6 Select" "Not included,Included" newline bitfld.long 0x08 5. " CH5SEL ,Channel 5 Select" "Not included,Included" bitfld.long 0x08 4. " CH4SEL ,Channel 4 Select" "Not included,Included" bitfld.long 0x08 3. " CH3SEL ,Channel 3 Select" "Not included,Included" newline bitfld.long 0x08 2. " CH2SEL ,Channel 2 Select" "Not included,Included" bitfld.long 0x08 1. " CH1SEL ,Channel 1 Select" "Not included,Included" bitfld.long 0x08 0. " CH0SEL ,Channel 0 Select" "Not included,Included" endif width 0x0B tree.end tree.end else tree.open "FTM (FlexTimer Module)" tree "FTM_1" base ad:0x029D0000 width 10. endian.be if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029D0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029D0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029D0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel 4 && 5" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel n = 4 && 5" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x029D0000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_2" base ad:0x029E0000 width 10. endian.be if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029E0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029E0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029E0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel 4 && 5" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel n = 4 && 5" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x029E0000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end sif !cpuis("LS1012*") tree "FTM_3" base ad:0x029F0000 width 10. endian.be if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x029F0000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x029F0000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x029F0000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel 4 && 5" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel n = 4 && 5" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x029F0000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_4" base ad:0x02A00000 width 10. endian.be if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x2C++0x03 line.long 0x00 "C4SC,Channel (4) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x10000)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x10000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x40000)==0x40000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x34++0x03 line.long 0x00 "C5SC,Channel (5) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x3C++0x03 line.long 0x00 "C6SC,Channel (6) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x1000000)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x1000000)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x4000000)==0x4000000)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x44++0x03 line.long 0x00 "C7SC,Channel (7) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A00000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A00000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A00000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x30++0x03 line.long 0x00 "C4V,Channel (4) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x38++0x03 line.long 0x00 "C5V,Channel (5) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x40++0x03 line.long 0x00 "C6V,Channel (6) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x48++0x03 line.long 0x00 "C7V,Channel (7) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " CH7F ,Channel 7 event flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 event flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 event flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" newline bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" newline bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complement of channel 4 && 5" "The same,Complement" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,Synchronization enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Deadtime enable for channel 6 && 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures for channel 6 && 7" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channel 6 && 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complement of channel 6 && 7" "The same,Complement" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 && 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,Synchronization enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Deadtime enable for channel 4 && 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures for channel 4 && 5" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channel 4 && 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complement of channel n = 4 && 5" "The same,Complement" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 && 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 7. " POL7 ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " POL6 ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " POL5 ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " POL4 ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x02A00000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 15. " CH7OCV ,Channel 7 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 7. " CH7SEL ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SEL ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SEL ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SEL ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_5" base ad:0x02A10000 width 10. endian.be if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A10000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A10000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A10000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x02A10000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_6" base ad:0x02A20000 width 10. endian.be if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A20000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A20000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A20000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x02A20000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_7" base ad:0x02A30000 width 10. endian.be if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A30000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A30000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A30000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x02A30000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end tree "FTM_8" base ad:0x02A40000 width 10. endian.be if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" rbitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,Status And Control Register" rbitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up,Up-Down" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "None,System,Fixed frequency,External" bitfld.long 0x00 0.--2. " PS ,Prescale factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif group.long 0x04++0x07 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,Modulo Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" sif cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif elif cpuis("LS1012*") if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "C0SC,Channel (0) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x01)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x01)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x04)==0x04)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "C1SC,Channel (1) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "C2SC,Channel (2) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) if (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" rbitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif else if (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x20) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x100)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x00)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" elif (((per.l.be(ad:0x02A40000+0x64))&0x100)==0x00)&&(((per.l.be(ad:0x02A40000+0x64))&0x400)==0x400)&&(((per.l.be(ad:0x02A40000))&0x20)==0x00) group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "C3SC,Channel (3) Status And Control Register" bitfld.long 0x00 7. " CHF ,Set by hardware when an event occurs on the channel" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" endif endif endif sif cpuis("LS1012*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x20++0x03 line.long 0x00 "C2V,Channel (2) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x28++0x03 line.long 0x00 "C3V,Channel (3) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" elif cpuis("LS10?3*")||cpuis("LS10?6*") group.long 0x10++0x03 line.long 0x00 "C0V,Channel (0) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" group.long 0x18++0x03 line.long 0x00 "C1V,Channel (1) Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel value" endif group.long 0x4C++0x03 line.long 0x00 "CNTIN,Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of the FTM counter" rgroup.long 0x50++0x03 line.long 0x00 "STATUS,Capture And Compare Status Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" else bitfld.long 0x00 3. " CH3F ,Channel 3 event flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 event flag" "Not occurred,Occurred" bitfld.long 0x00 1. " CH1F ,Channel 1 event flag" "Not occurred,Occurred" newline bitfld.long 0x00 0. " CH0F ,Channel 0 event flag" "Not occurred,Occurred" endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "All disabled,Even enabled/Manual clear,All enabled/Manual clear,All enabled/Auto clear" bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " PWMSYNC ,PWM Synchronization Mode" "No restrictions,SW: MOD CnV / HW: OUTMASK FTM" bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "No effect,Initialize" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" newline bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "All rising edges,PWM synchronization" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Not reinitialized,Reinitialized" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" line.long 0x04 "OUTINIT,Initial State For Channels Output Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" else bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" newline bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" endif line.long 0x08 "OUTMASK,Output Mask Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" else bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" newline bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" newline rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" else rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Deadtime enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for channel 2 && 3" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channel 2 && 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complement of channel 2 && 3" "The same,Complement" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 && 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for channel 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Deadtime enable for channel 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for channel 0 && 1" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channel 0 && 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complement of channel 0 && 1" "The same,Complement" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 && 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,Function For Linked Channels Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" newline bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" else bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable for channel 2 && 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,Synchronization enable for channel 2 && 3" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Deadtime enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures for n = 2 && 3" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for n = 2 && 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complement of channel (n) for n = 2 && 3" "The same,Complement" bitfld.long 0x00 8. " COMBINE1 ,Combine channels for n = 2 && 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,Synchronization enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Deadtime enable for n = 0 && 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures for n = 0 && 1" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for n = 0 && 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complement of channel (n) for n = 0 && 1" "The same,Complement" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels for n = 0 && 1" "Independent,Combined" endif endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x68++0x03 line.long 0x00 "DEADTIME,Deadtime Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Deadtime prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Deadtime value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM External Trigger Register" rbitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not triggered,Triggered" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) rgroup.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif else group.long 0x70++0x03 line.long 0x00 "POL,Channels Polarity Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" else bitfld.long 0x00 3. " POL3 ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " POL2 ,Channel 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " POL1 ,Channel 1 polarity" "Active high,Active low" newline bitfld.long 0x00 0. " POL0 ,Channel 0 polarity" "Active high,Active low" endif endif group.long 0x74++0x07 line.long 0x00 "FMS,Fault Mode Status Register" rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Fault inputs" "0,1" newline rbitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" rbitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" rbitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline rbitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" line.long 0x04 "FILTER,Input Capture Filter Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") else bitfld.long 0x04 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A and B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "TOF on the bottom,TOF on the top" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " NUMTOF ,TOF frequency. Ratio between the number of counter overflows to the number of times the TOF bit is set" "Each,First-not next,First-not next 2,First-not next 3,First-not next 4,First-not next 5,First-not next 6,First-not next 7,First-not next 8,First-not next 9,First-not next 10,First-not next 11,First-not next 12,First-not next 13,First-not next 14,First-not next 15,First-not next 16,First-not next 17,First-not next 18,First-not next 19,First-not next 20,First-not next 21,First-not next 22,First-not next 23,First-not next 24,First-not next 25,First-not next 26,First-not next 27,First-not next 28,First-not next 29,First-not next 30,First-not next 31" if (((per.l.be(ad:0x02A40000+0x54))&0x04)==0x00) rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM Fault Input Polarity Register" bitfld.long 0x00 7. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 6. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 5. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization is activated by a hardware trigger" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization is activated by a hardware trigger" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD/CNTIN/CV registers synchronization is activated by the software trigger" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization is activated by the software trigger" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,Synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "Rising edge,PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "Rising edge,PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM Software Output Control Register" sif cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" else bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "Forced 0,Forced 1" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "Forced 0,Forced 1" newline bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "Forced 0,Forced 1" endif sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" else bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" endif line.long 0x0C "PWMLOAD,FTM PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" sif cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" else bitfld.long 0x0C 3. " CH3SEL ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SEL ,Channel 2 select" "Not included,Included" bitfld.long 0x0C 1. " CH1SEL ,Channel 1 select" "Not included,Included" newline bitfld.long 0x0C 0. " CH0SEL ,Channel 0 select" "Not included,Included" endif endian.le width 0x0B tree.end endif tree.end endif sif cpuis("LS10?3A")||cpuis("LS10?6A") tree.open "GPIO (General Purpose I/O)" tree "GPIO_1" base ad:0x2300000 width 16. endian.be group.long 0x00++0x17 line.long 0x00 "GPIO1_GPDIR,GPIO Direction Register" bitfld.long 0x00 18. " DR[13] ,Pin 13 direction" ",Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" newline bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" newline bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" newline bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" newline bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" bitfld.long 0x00 0. " [31] ,Pin 31 direction" "Input,Output" line.long 0x04 "GPIO1_GPODR,GPIO Open Drain Register" bitfld.long 0x04 18. " OD[13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 0. " [31] ,Pin 31 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO1_GPDAT,GPIO Data Register" bitfld.long 0x08 18. " D[13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" newline bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" newline bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" newline bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" newline bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" bitfld.long 0x08 0. " [31] ,Pin 31 data" "Low,High" line.long 0x0C "GPIO1_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 18. " EV[13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [31] ,Pin 31 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO1_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 18. " IM[13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" bitfld.long 0x10 0. " [31] ,Pin 31 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO1_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 18. " ED[13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" bitfld.long 0x14 0. " [31] ,Pin 31 edge detection mode" "Any change,Falling" endian.le width 0x0B tree.end tree "GPIO_2" base ad:0x2310000 width 16. endian.be group.long 0x00++0x17 line.long 0x00 "GPIO2_GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" newline bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" line.long 0x04 "GPIO2_GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO2_GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" newline bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" line.long 0x0C "GPIO2_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO2_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO2_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" endian.le width 0x0B tree.end tree "GPIO_3" base ad:0x2320000 width 16. endian.be group.long 0x00++0x17 line.long 0x00 "GPIO3_GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" newline bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" newline bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" newline bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" newline bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" newline bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" newline bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" newline bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" newline bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" line.long 0x04 "GPIO3_GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO3_GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" newline bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" newline bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" newline bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" newline bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" newline bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" newline bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" newline bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" newline bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" line.long 0x0C "GPIO3_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO3_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO3_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" endian.le width 0x0B tree.end tree "GPIO_4" base ad:0x2330000 width 16. endian.be group.long 0x00++0x17 line.long 0x00 "GPIO4_GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" newline bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" newline bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" line.long 0x04 "GPIO4_GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO4_GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" newline bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" newline bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" line.long 0x0C "GPIO4_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO4_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO4_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" endian.le width 0x0B tree.end tree.end elif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree.open "GPIO (General Purpose I/O)" tree "GPIO_1" base ad:0x2300000 width 16. group.long 0x00++0x17 line.long 0x00 "GPIO1_GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" newline bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" newline bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" newline bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" newline bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" line.long 0x04 "GPIO1_GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO1_GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" newline bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" newline bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" newline bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" newline bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" line.long 0x0C "GPIO1_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO1_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO1_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.long 0x18++0x03 line.long 0x00 "GPIO1_GPIBE,GPIO Input Buffer Enable Register" bitfld.long 0x00 31. " IBE[0] ,Pin 0 input enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pin 1 input enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pin 2 input enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Pin 3 input enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Pin 4 input enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Pin 5 input enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Pin 6 input enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Pin 7 input enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Pin 8 input enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Pin 9 input enable" "Disabled,Enabled" bitfld.long 0x00 21. " [10] ,Pin 10 input enable" "Disabled,Enabled" bitfld.long 0x00 20. " [11] ,Pin 11 input enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [12] ,Pin 12 input enable" "Disabled,Enabled" bitfld.long 0x00 18. " [13] ,Pin 13 input enable" "Disabled,Enabled" bitfld.long 0x00 17. " [14] ,Pin 14 input enable" "Disabled,Enabled" bitfld.long 0x00 16. " [15] ,Pin 15 input enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [16] ,Pin 16 input enable" "Disabled,Enabled" bitfld.long 0x00 14. " [17] ,Pin 17 input enable" "Disabled,Enabled" bitfld.long 0x00 13. " [18] ,Pin 18 input enable" "Disabled,Enabled" bitfld.long 0x00 12. " [19] ,Pin 19 input enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [20] ,Pin 20 input enable" "Disabled,Enabled" bitfld.long 0x00 10. " [21] ,Pin 21 input enable" "Disabled,Enabled" bitfld.long 0x00 9. " [22] ,Pin 22 input enable" "Disabled,Enabled" bitfld.long 0x00 8. " [23] ,Pin 23 input enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [24] ,Pin 24 input enable" "Disabled,Enabled" bitfld.long 0x00 6. " [25] ,Pin 25 input enable" "Disabled,Enabled" bitfld.long 0x00 5. " [26] ,Pin 26 input enable" "Disabled,Enabled" bitfld.long 0x00 4. " [27] ,Pin 27 input enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [28] ,Pin 28 input enable" "Disabled,Enabled" endif width 0x0B tree.end tree "GPIO_2" base ad:0x2310000 width 16. group.long 0x00++0x17 line.long 0x00 "GPIO2_GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" newline bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" newline bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" newline bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" newline bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" line.long 0x04 "GPIO2_GPODR,Gpio Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO2_GPDAT,Gpio Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" newline bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" newline bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" newline bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" newline bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" line.long 0x0C "GPIO2_GPIER,Gpio Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO2_GPIMR,Gpio Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO2_GPICR,Gpio Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.long 0x18++0x03 line.long 0x00 "GPIO2_GPIBE,GPIO Input Buffer Enable Register" bitfld.long 0x00 31. " IBE[0] ,Pin 0 input enable" "Disabled,Enabled" bitfld.long 0x00 30. " [1] ,Pin 1 input enable" "Disabled,Enabled" bitfld.long 0x00 29. " [2] ,Pin 2 input enable" "Disabled,Enabled" bitfld.long 0x00 28. " [3] ,Pin 3 input enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " [4] ,Pin 4 input enable" "Disabled,Enabled" bitfld.long 0x00 26. " [5] ,Pin 5 input enable" "Disabled,Enabled" bitfld.long 0x00 25. " [6] ,Pin 6 input enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Pin 7 input enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " [8] ,Pin 8 input enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Pin 9 input enable" "Disabled,Enabled" bitfld.long 0x00 21. " [10] ,Pin 10 input enable" "Disabled,Enabled" bitfld.long 0x00 20. " [11] ,Pin 11 input enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [12] ,Pin 12 input enable" "Disabled,Enabled" bitfld.long 0x00 18. " [13] ,Pin 13 input enable" "Disabled,Enabled" bitfld.long 0x00 17. " [14] ,Pin 14 input enable" "Disabled,Enabled" bitfld.long 0x00 16. " [15] ,Pin 15 input enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " [16] ,Pin 16 input enable" "Disabled,Enabled" bitfld.long 0x00 14. " [17] ,Pin 17 input enable" "Disabled,Enabled" bitfld.long 0x00 13. " [18] ,Pin 18 input enable" "Disabled,Enabled" bitfld.long 0x00 12. " [19] ,Pin 19 input enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [20] ,Pin 20 input enable" "Disabled,Enabled" bitfld.long 0x00 10. " [21] ,Pin 21 input enable" "Disabled,Enabled" bitfld.long 0x00 9. " [22] ,Pin 22 input enable" "Disabled,Enabled" bitfld.long 0x00 8. " [23] ,Pin 23 input enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " [24] ,Pin 24 input enable" "Disabled,Enabled" bitfld.long 0x00 6. " [25] ,Pin 25 input enable" "Disabled,Enabled" bitfld.long 0x00 5. " [26] ,Pin 26 input enable" "Disabled,Enabled" bitfld.long 0x00 4. " [27] ,Pin 27 input enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [28] ,Pin 28 input enable" "Disabled,Enabled" bitfld.long 0x00 2. " [29] ,Pin 29 input enable" "Disabled,Enabled" bitfld.long 0x00 1. " [30] ,Pin 30 input enable" "Disabled,Enabled" endif width 0x0B tree.end tree "GPIO_3" base ad:0x2320000 width 16. group.long 0x00++0x17 line.long 0x00 "GPIO3_GPDIR,GPIO Direction Register" bitfld.long 0x00 25. " DR[6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" newline bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" newline bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" newline bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" newline bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" newline bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" newline bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" line.long 0x04 "GPIO3_GPODR,GPIO Open Drain Register" bitfld.long 0x04 25. " OD[6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPIO3_GPDAT,GPIO Data Register" bitfld.long 0x08 25. " D[6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" newline bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" newline bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" newline bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" newline bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" newline bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" newline bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" line.long 0x0C "GPIO3_GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 25. " EV[6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIO3_GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 25. " IM[6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" line.long 0x14 "GPIO3_GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 25. " E[6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.long 0x18++0x03 line.long 0x00 "GPIO3_GPIBE,GPIO Input Buffer Enable Register" bitfld.long 0x00 25. " IB[6] ,Pin 6 input enable" "Disabled,Enabled" bitfld.long 0x00 24. " [7] ,Pin 7 input enable" "Disabled,Enabled" bitfld.long 0x00 23. " [8] ,Pin 8 input enable" "Disabled,Enabled" bitfld.long 0x00 22. " [9] ,Pin 9 input enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " [10] ,Pin 10 input enable" "Disabled,Enabled" bitfld.long 0x00 20. " [11] ,Pin 11 input enable" "Disabled,Enabled" bitfld.long 0x00 19. " [12] ,Pin 12 input enable" "Disabled,Enabled" bitfld.long 0x00 18. " [13] ,Pin 13 input enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " [14] ,Pin 14 input enable" "Disabled,Enabled" bitfld.long 0x00 16. " [15] ,Pin 15 input enable" "Disabled,Enabled" bitfld.long 0x00 15. " [16] ,Pin 16 input enable" "Disabled,Enabled" bitfld.long 0x00 14. " [17] ,Pin 17 input enable" "Disabled,Enabled" newline bitfld.long 0x00 13. " [18] ,Pin 18 input enable" "Disabled,Enabled" bitfld.long 0x00 12. " [19] ,Pin 19 input enable" "Disabled,Enabled" bitfld.long 0x00 11. " [20] ,Pin 20 input enable" "Disabled,Enabled" bitfld.long 0x00 10. " [21] ,Pin 21 input enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " [22] ,Pin 22 input enable" "Disabled,Enabled" bitfld.long 0x00 8. " [23] ,Pin 23 input enable" "Disabled,Enabled" bitfld.long 0x00 7. " [24] ,Pin 24 input enable" "Disabled,Enabled" bitfld.long 0x00 6. " [25] ,Pin 25 input enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [26] ,Pin 26 input enable" "Disabled,Enabled" bitfld.long 0x00 4. " [27] ,Pin 27 input enable" "Disabled,Enabled" bitfld.long 0x00 3. " [28] ,Pin 28 input enable" "Disabled,Enabled" bitfld.long 0x00 2. " [29] ,Pin 29 input enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [30] ,Pin 30 input enable" "Disabled,Enabled" endif width 0x0B tree.end tree "GPIO_4" base ad:0x2330000 width 7. sif cpuis("LS10?3A")||cpuis("LS10?6A")||cpuis("LS1044A")||cpuis("LS1012A") endian.be endif group.long 0x00++0x1B line.long 0x00 "GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" newline bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" newline bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" newline bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" newline bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" bitfld.long 0x00 0. " [31] ,Pin 31 direction" "Input,Output" line.long 0x04 "GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 0. " [31] ,Pin 31 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" newline bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" newline bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" newline bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" newline bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" bitfld.long 0x08 0. " [31] ,Pin 31 data" "Low,High" line.long 0x0C "GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [31] ,Pin 31 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" bitfld.long 0x10 0. " [31] ,Pin 31 interrupt mask" "Masked,Not masked" line.long 0x14 "GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" bitfld.long 0x14 0. " [31] ,Pin 31 edge detection mode" "Any change,Falling" line.long 0x18 "GPIBE,GPIO Input Buffer Enable Register" bitfld.long 0x18 31. " IBE[0] ,Pin 0 input enable" "Disabled,Enabled" bitfld.long 0x18 30. " [1] ,Pin 1 input enable" "Disabled,Enabled" bitfld.long 0x18 29. " [2] ,Pin 2 input enable" "Disabled,Enabled" bitfld.long 0x18 28. " [3] ,Pin 3 input enable" "Disabled,Enabled" newline bitfld.long 0x18 27. " [4] ,Pin 4 input enable" "Disabled,Enabled" bitfld.long 0x18 26. " [5] ,Pin 5 input enable" "Disabled,Enabled" bitfld.long 0x18 25. " [6] ,Pin 6 input enable" "Disabled,Enabled" bitfld.long 0x18 24. " [7] ,Pin 7 input enable" "Disabled,Enabled" newline bitfld.long 0x18 23. " [8] ,Pin 8 input enable" "Disabled,Enabled" bitfld.long 0x18 22. " [9] ,Pin 9 input enable" "Disabled,Enabled" bitfld.long 0x18 21. " [10] ,Pin 10 input enable" "Disabled,Enabled" bitfld.long 0x18 20. " [11] ,Pin 11 input enable" "Disabled,Enabled" newline bitfld.long 0x18 19. " [12] ,Pin 12 input enable" "Disabled,Enabled" bitfld.long 0x18 18. " [13] ,Pin 13 input enable" "Disabled,Enabled" bitfld.long 0x18 17. " [14] ,Pin 14 input enable" "Disabled,Enabled" bitfld.long 0x18 16. " [15] ,Pin 15 input enable" "Disabled,Enabled" newline bitfld.long 0x18 15. " [16] ,Pin 16 input enable" "Disabled,Enabled" bitfld.long 0x18 14. " [17] ,Pin 17 input enable" "Disabled,Enabled" bitfld.long 0x18 13. " [18] ,Pin 18 input enable" "Disabled,Enabled" bitfld.long 0x18 12. " [19] ,Pin 19 input enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " [20] ,Pin 20 input enable" "Disabled,Enabled" bitfld.long 0x18 10. " [21] ,Pin 21 input enable" "Disabled,Enabled" bitfld.long 0x18 9. " [22] ,Pin 22 input enable" "Disabled,Enabled" bitfld.long 0x18 8. " [23] ,Pin 23 input enable" "Disabled,Enabled" newline bitfld.long 0x18 7. " [24] ,Pin 24 input enable" "Disabled,Enabled" bitfld.long 0x18 6. " [25] ,Pin 25 input enable" "Disabled,Enabled" bitfld.long 0x18 5. " [26] ,Pin 26 input enable" "Disabled,Enabled" bitfld.long 0x18 4. " [27] ,Pin 27 input enable" "Disabled,Enabled" newline bitfld.long 0x18 3. " [28] ,Pin 28 input enable" "Disabled,Enabled" bitfld.long 0x18 2. " [29] ,Pin 29 input enable" "Disabled,Enabled" bitfld.long 0x18 1. " [30] ,Pin 30 input enable" "Disabled,Enabled" bitfld.long 0x18 0. " [31] ,Pin 31 input enable" "Disabled,Enabled" endian.le width 0x0B tree.end tree.end elif cpuis("LS1012A") tree.open "GPIO (General Purpose I/O)" tree "GPIO_1" base ad:0x2300000 width 7. sif cpuis("LS10?3A")||cpuis("LS10?6A")||cpuis("LS1044A")||cpuis("LS1012A") endian.be endif group.long 0x00++0x1B line.long 0x00 "GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" "Input,Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 23. " [8] ,Pin 8 direction" "Input,Output" bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" newline bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" "Input,Output" newline bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,Output" bitfld.long 0x00 13. " [18] ,Pin 18 direction" "Input,Output" bitfld.long 0x00 12. " [19] ,Pin 19 direction" "Input,Output" newline bitfld.long 0x00 11. " [20] ,Pin 20 direction" "Input,Output" bitfld.long 0x00 10. " [21] ,Pin 21 direction" "Input,Output" bitfld.long 0x00 9. " [22] ,Pin 22 direction" "Input,Output" bitfld.long 0x00 8. " [23] ,Pin 23 direction" "Input,Output" newline bitfld.long 0x00 7. " [24] ,Pin 24 direction" "Input,Output" bitfld.long 0x00 6. " [25] ,Pin 25 direction" "Input,Output" bitfld.long 0x00 5. " [26] ,Pin 26 direction" "Input,Output" bitfld.long 0x00 4. " [27] ,Pin 27 direction" "Input,Output" newline bitfld.long 0x00 3. " [28] ,Pin 28 direction" "Input,Output" bitfld.long 0x00 2. " [29] ,Pin 29 direction" "Input,Output" bitfld.long 0x00 1. " [30] ,Pin 30 direction" "Input,Output" bitfld.long 0x00 0. " [31] ,Pin 31 direction" "Input,Output" line.long 0x04 "GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 23. " [8] ,Pin 8 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 13. " [18] ,Pin 18 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 12. " [19] ,Pin 19 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 11. " [20] ,Pin 20 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 10. " [21] ,Pin 21 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 9. " [22] ,Pin 22 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 8. " [23] ,Pin 23 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 7. " [24] ,Pin 24 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 6. " [25] ,Pin 25 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 5. " [26] ,Pin 26 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 4. " [27] ,Pin 27 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 3. " [28] ,Pin 28 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 2. " [29] ,Pin 29 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 1. " [30] ,Pin 30 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 0. " [31] ,Pin 31 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 23. " [8] ,Pin 8 data" "Low,High" bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" newline bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" newline bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" bitfld.long 0x08 13. " [18] ,Pin 18 data" "Low,High" bitfld.long 0x08 12. " [19] ,Pin 19 data" "Low,High" newline bitfld.long 0x08 11. " [20] ,Pin 20 data" "Low,High" bitfld.long 0x08 10. " [21] ,Pin 21 data" "Low,High" bitfld.long 0x08 9. " [22] ,Pin 22 data" "Low,High" bitfld.long 0x08 8. " [23] ,Pin 23 data" "Low,High" newline bitfld.long 0x08 7. " [24] ,Pin 24 data" "Low,High" bitfld.long 0x08 6. " [25] ,Pin 25 data" "Low,High" bitfld.long 0x08 5. " [26] ,Pin 26 data" "Low,High" bitfld.long 0x08 4. " [27] ,Pin 27 data" "Low,High" newline bitfld.long 0x08 3. " [28] ,Pin 28 data" "Low,High" bitfld.long 0x08 2. " [29] ,Pin 29 data" "Low,High" bitfld.long 0x08 1. " [30] ,Pin 30 data" "Low,High" bitfld.long 0x08 0. " [31] ,Pin 31 data" "Low,High" line.long 0x0C "GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [8] ,Pin 8 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 13. " [18] ,Pin 18 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [19] ,Pin 19 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [20] ,Pin 20 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [21] ,Pin 21 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 9. " [22] ,Pin 22 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [23] ,Pin 23 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [24] ,Pin 24 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [25] ,Pin 25 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 5. " [26] ,Pin 26 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [27] ,Pin 27 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [28] ,Pin 28 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [29] ,Pin 29 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 1. " [30] ,Pin 30 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [31] ,Pin 31 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 23. " [8] ,Pin 8 interrupt mask" "Masked,Not masked" bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" bitfld.long 0x10 13. " [18] ,Pin 18 interrupt mask" "Masked,Not masked" bitfld.long 0x10 12. " [19] ,Pin 19 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 11. " [20] ,Pin 20 interrupt mask" "Masked,Not masked" bitfld.long 0x10 10. " [21] ,Pin 21 interrupt mask" "Masked,Not masked" bitfld.long 0x10 9. " [22] ,Pin 22 interrupt mask" "Masked,Not masked" bitfld.long 0x10 8. " [23] ,Pin 23 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 7. " [24] ,Pin 24 interrupt mask" "Masked,Not masked" bitfld.long 0x10 6. " [25] ,Pin 25 interrupt mask" "Masked,Not masked" bitfld.long 0x10 5. " [26] ,Pin 26 interrupt mask" "Masked,Not masked" bitfld.long 0x10 4. " [27] ,Pin 27 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 3. " [28] ,Pin 28 interrupt mask" "Masked,Not masked" bitfld.long 0x10 2. " [29] ,Pin 29 interrupt mask" "Masked,Not masked" bitfld.long 0x10 1. " [30] ,Pin 30 interrupt mask" "Masked,Not masked" bitfld.long 0x10 0. " [31] ,Pin 31 interrupt mask" "Masked,Not masked" line.long 0x14 "GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 23. " [8] ,Pin 8 edge detection mode" "Any change,Falling" bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" bitfld.long 0x14 13. " [18] ,Pin 18 edge detection mode" "Any change,Falling" bitfld.long 0x14 12. " [19] ,Pin 19 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 11. " [20] ,Pin 20 edge detection mode" "Any change,Falling" bitfld.long 0x14 10. " [21] ,Pin 21 edge detection mode" "Any change,Falling" bitfld.long 0x14 9. " [22] ,Pin 22 edge detection mode" "Any change,Falling" bitfld.long 0x14 8. " [23] ,Pin 23 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 7. " [24] ,Pin 24 edge detection mode" "Any change,Falling" bitfld.long 0x14 6. " [25] ,Pin 25 edge detection mode" "Any change,Falling" bitfld.long 0x14 5. " [26] ,Pin 26 edge detection mode" "Any change,Falling" bitfld.long 0x14 4. " [27] ,Pin 27 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 3. " [28] ,Pin 28 edge detection mode" "Any change,Falling" bitfld.long 0x14 2. " [29] ,Pin 29 edge detection mode" "Any change,Falling" bitfld.long 0x14 1. " [30] ,Pin 30 edge detection mode" "Any change,Falling" bitfld.long 0x14 0. " [31] ,Pin 31 edge detection mode" "Any change,Falling" line.long 0x18 "GPIBE,GPIO Input Buffer Enable Register" bitfld.long 0x18 31. " IBE[0] ,Pin 0 input enable" "Disabled,Enabled" bitfld.long 0x18 30. " [1] ,Pin 1 input enable" "Disabled,Enabled" bitfld.long 0x18 29. " [2] ,Pin 2 input enable" "Disabled,Enabled" bitfld.long 0x18 28. " [3] ,Pin 3 input enable" "Disabled,Enabled" newline bitfld.long 0x18 27. " [4] ,Pin 4 input enable" "Disabled,Enabled" bitfld.long 0x18 26. " [5] ,Pin 5 input enable" "Disabled,Enabled" bitfld.long 0x18 25. " [6] ,Pin 6 input enable" "Disabled,Enabled" bitfld.long 0x18 24. " [7] ,Pin 7 input enable" "Disabled,Enabled" newline bitfld.long 0x18 23. " [8] ,Pin 8 input enable" "Disabled,Enabled" bitfld.long 0x18 22. " [9] ,Pin 9 input enable" "Disabled,Enabled" bitfld.long 0x18 21. " [10] ,Pin 10 input enable" "Disabled,Enabled" bitfld.long 0x18 20. " [11] ,Pin 11 input enable" "Disabled,Enabled" newline bitfld.long 0x18 19. " [12] ,Pin 12 input enable" "Disabled,Enabled" bitfld.long 0x18 18. " [13] ,Pin 13 input enable" "Disabled,Enabled" bitfld.long 0x18 17. " [14] ,Pin 14 input enable" "Disabled,Enabled" bitfld.long 0x18 16. " [15] ,Pin 15 input enable" "Disabled,Enabled" newline bitfld.long 0x18 15. " [16] ,Pin 16 input enable" "Disabled,Enabled" bitfld.long 0x18 14. " [17] ,Pin 17 input enable" "Disabled,Enabled" bitfld.long 0x18 13. " [18] ,Pin 18 input enable" "Disabled,Enabled" bitfld.long 0x18 12. " [19] ,Pin 19 input enable" "Disabled,Enabled" newline bitfld.long 0x18 11. " [20] ,Pin 20 input enable" "Disabled,Enabled" bitfld.long 0x18 10. " [21] ,Pin 21 input enable" "Disabled,Enabled" bitfld.long 0x18 9. " [22] ,Pin 22 input enable" "Disabled,Enabled" bitfld.long 0x18 8. " [23] ,Pin 23 input enable" "Disabled,Enabled" newline bitfld.long 0x18 7. " [24] ,Pin 24 input enable" "Disabled,Enabled" bitfld.long 0x18 6. " [25] ,Pin 25 input enable" "Disabled,Enabled" bitfld.long 0x18 5. " [26] ,Pin 26 input enable" "Disabled,Enabled" bitfld.long 0x18 4. " [27] ,Pin 27 input enable" "Disabled,Enabled" newline bitfld.long 0x18 3. " [28] ,Pin 28 input enable" "Disabled,Enabled" bitfld.long 0x18 2. " [29] ,Pin 29 input enable" "Disabled,Enabled" bitfld.long 0x18 1. " [30] ,Pin 30 input enable" "Disabled,Enabled" bitfld.long 0x18 0. " [31] ,Pin 31 input enable" "Disabled,Enabled" endian.le width 0x0B tree.end tree "GPIO_2" base ad:0x2310000 width 7. endian.be group.long 0x00++0x17 line.long 0x00 "GPDIR,GPIO Direction Register" bitfld.long 0x00 31. " DR[0] ,Pin 0 direction" ",Output" bitfld.long 0x00 30. " [1] ,Pin 1 direction" "Input,Output" bitfld.long 0x00 29. " [2] ,Pin 2 direction" "Input,Output" bitfld.long 0x00 28. " [3] ,Pin 3 direction" "Input,Output" newline bitfld.long 0x00 27. " [4] ,Pin 4 direction" "Input,Output" bitfld.long 0x00 26. " [5] ,Pin 5 direction" "Input,Output" bitfld.long 0x00 25. " [6] ,Pin 6 direction" "Input,Output" bitfld.long 0x00 24. " [7] ,Pin 7 direction" "Input,Output" newline bitfld.long 0x00 22. " [9] ,Pin 9 direction" "Input,Output" bitfld.long 0x00 21. " [10] ,Pin 10 direction" "Input,Output" bitfld.long 0x00 20. " [11] ,Pin 11 direction" "Input,Output" bitfld.long 0x00 19. " [12] ,Pin 12 direction" "Input,Output" newline bitfld.long 0x00 18. " [13] ,Pin 13 direction" "Input,Output" bitfld.long 0x00 17. " [14] ,Pin 14 direction" "Input,Output" bitfld.long 0x00 16. " [15] ,Pin 15 direction" ",Output" bitfld.long 0x00 15. " [16] ,Pin 16 direction" "Input,Output" newline bitfld.long 0x00 14. " [17] ,Pin 17 direction" "Input,?..." line.long 0x04 "GPODR,GPIO Open Drain Register" bitfld.long 0x04 31. " OD[0] ,Pin 0 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 30. " [1] ,Pin 1 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 29. " [2] ,Pin 2 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 28. " [3] ,Pin 3 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 27. " [4] ,Pin 4 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 26. " [5] ,Pin 5 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 25. " [6] ,Pin 6 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 24. " [7] ,Pin 7 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 22. " [9] ,Pin 9 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 21. " [10] ,Pin 10 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 20. " [11] ,Pin 11 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 19. " [12] ,Pin 12 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 18. " [13] ,Pin 13 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 17. " [14] ,Pin 14 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 16. " [15] ,Pin 15 open-drain configuration" "Push-pull,Open-drain" bitfld.long 0x04 15. " [16] ,Pin 16 open-drain configuration" "Push-pull,Open-drain" newline bitfld.long 0x04 14. " [17] ,Pin 17 open-drain configuration" "Push-pull,Open-drain" line.long 0x08 "GPDAT,GPIO Data Register" bitfld.long 0x08 31. " D[0] ,Pin 0 data" "Low,High" bitfld.long 0x08 30. " [1] ,Pin 1 data" "Low,High" bitfld.long 0x08 29. " [2] ,Pin 2 data" "Low,High" bitfld.long 0x08 28. " [3] ,Pin 3 data" "Low,High" newline bitfld.long 0x08 27. " [4] ,Pin 4 data" "Low,High" bitfld.long 0x08 26. " [5] ,Pin 5 data" "Low,High" bitfld.long 0x08 25. " [6] ,Pin 6 data" "Low,High" bitfld.long 0x08 24. " [7] ,Pin 7 data" "Low,High" newline bitfld.long 0x08 22. " [9] ,Pin 9 data" "Low,High" bitfld.long 0x08 21. " [10] ,Pin 10 data" "Low,High" bitfld.long 0x08 20. " [11] ,Pin 11 data" "Low,High" bitfld.long 0x08 19. " [12] ,Pin 12 data" "Low,High" newline bitfld.long 0x08 18. " [13] ,Pin 13 data" "Low,High" bitfld.long 0x08 17. " [14] ,Pin 14 data" "Low,High" bitfld.long 0x08 16. " [15] ,Pin 15 data" "Low,High" bitfld.long 0x08 15. " [16] ,Pin 16 data" "Low,High" newline bitfld.long 0x08 14. " [17] ,Pin 17 data" "Low,High" line.long 0x0C "GPIER,GPIO Interrupt Event Register" eventfld.long 0x0C 31. " EV[0] ,Pin 0 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [1] ,Pin 1 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 29. " [2] ,Pin 2 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [3] ,Pin 3 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [4] ,Pin 4 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [5] ,Pin 5 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 25. " [6] ,Pin 6 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [7] ,Pin 7 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 22. " [9] ,Pin 9 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 21. " [10] ,Pin 10 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [11] ,Pin 11 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 19. " [12] ,Pin 12 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 18. " [13] ,Pin 13 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 17. " [14] ,Pin 14 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [15] ,Pin 15 interrupt event" "No interrupt,Interrupt" eventfld.long 0x0C 15. " [16] ,Pin 16 interrupt event" "No interrupt,Interrupt" newline eventfld.long 0x0C 14. " [17] ,Pin 17 interrupt event" "No interrupt,Interrupt" line.long 0x10 "GPIMR,GPIO Interrupt Mask Register" bitfld.long 0x10 31. " IM[0] ,Pin 0 interrupt mask" "Masked,Not masked" bitfld.long 0x10 30. " [1] ,Pin 1 interrupt mask" "Masked,Not masked" bitfld.long 0x10 29. " [2] ,Pin 2 interrupt mask" "Masked,Not masked" bitfld.long 0x10 28. " [3] ,Pin 3 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 27. " [4] ,Pin 4 interrupt mask" "Masked,Not masked" bitfld.long 0x10 26. " [5] ,Pin 5 interrupt mask" "Masked,Not masked" bitfld.long 0x10 25. " [6] ,Pin 6 interrupt mask" "Masked,Not masked" bitfld.long 0x10 24. " [7] ,Pin 7 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 22. " [9] ,Pin 9 interrupt mask" "Masked,Not masked" bitfld.long 0x10 21. " [10] ,Pin 10 interrupt mask" "Masked,Not masked" bitfld.long 0x10 20. " [11] ,Pin 11 interrupt mask" "Masked,Not masked" bitfld.long 0x10 19. " [12] ,Pin 12 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 18. " [13] ,Pin 13 interrupt mask" "Masked,Not masked" bitfld.long 0x10 17. " [14] ,Pin 14 interrupt mask" "Masked,Not masked" bitfld.long 0x10 16. " [15] ,Pin 15 interrupt mask" "Masked,Not masked" bitfld.long 0x10 15. " [16] ,Pin 16 interrupt mask" "Masked,Not masked" newline bitfld.long 0x10 14. " [17] ,Pin 17 interrupt mask" "Masked,Not masked" line.long 0x14 "GPICR,GPIO Interrupt Control Register" bitfld.long 0x14 31. " ED[0] ,Pin 0 edge detection mode" "Any change,Falling" bitfld.long 0x14 30. " [1] ,Pin 1 edge detection mode" "Any change,Falling" bitfld.long 0x14 29. " [2] ,Pin 2 edge detection mode" "Any change,Falling" bitfld.long 0x14 28. " [3] ,Pin 3 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 27. " [4] ,Pin 4 edge detection mode" "Any change,Falling" bitfld.long 0x14 26. " [5] ,Pin 5 edge detection mode" "Any change,Falling" bitfld.long 0x14 25. " [6] ,Pin 6 edge detection mode" "Any change,Falling" bitfld.long 0x14 24. " [7] ,Pin 7 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 22. " [9] ,Pin 9 edge detection mode" "Any change,Falling" bitfld.long 0x14 21. " [10] ,Pin 10 edge detection mode" "Any change,Falling" bitfld.long 0x14 20. " [11] ,Pin 11 edge detection mode" "Any change,Falling" bitfld.long 0x14 19. " [12] ,Pin 12 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 18. " [13] ,Pin 13 edge detection mode" "Any change,Falling" bitfld.long 0x14 17. " [14] ,Pin 14 edge detection mode" "Any change,Falling" bitfld.long 0x14 16. " [15] ,Pin 15 edge detection mode" "Any change,Falling" bitfld.long 0x14 15. " [16] ,Pin 16 edge detection mode" "Any change,Falling" newline bitfld.long 0x14 14. " [17] ,Pin 17 edge detection mode" "Any change,Falling" endian.le width 0x0B tree.end tree.end endif sif cpuis("LS10?3A")||cpuis("LS10?6A") tree "IFC (Integrated Flash Controller)" base ad:0x01530000 endian.be width 12. rgroup.long 0x00++0x03 line.long 0x00 "REV,IFC Revision Control Register" hexmask.long.byte 0x00 24.--27. 1. " REV_MAJ ,Major revision" hexmask.long.byte 0x00 16.--19. 1. " REV_MIN ,Minor revision" group.long (0x0C+0x0)++0x03 line.long 0x00 "CSPR0_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x0))&0x06)==(0x00||0x02)) group.long (0x10+0x0)++0x03 line.long 0x00 "CSPR0,Chip-select Property Register 0" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_0 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_0 are valid" "Invalid,Valid" else group.long (0x10+0x0)++0x03 line.long 0x00 "CSPR0,Chip-select Property Register 0" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_0 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_0 are valid" "Invalid,Valid" endif group.long (0x0C+0xC)++0x03 line.long 0x00 "CSPR1_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0xC))&0x06)==(0x00||0x02)) group.long (0x10+0xC)++0x03 line.long 0x00 "CSPR1,Chip-select Property Register 1" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_1 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_1 are valid" "Invalid,Valid" else group.long (0x10+0xC)++0x03 line.long 0x00 "CSPR1,Chip-select Property Register 1" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_1 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_1 are valid" "Invalid,Valid" endif group.long (0x0C+0x18)++0x03 line.long 0x00 "CSPR2_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x18))&0x06)==(0x00||0x02)) group.long (0x10+0x18)++0x03 line.long 0x00 "CSPR2,Chip-select Property Register 2" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_2 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_2 are valid" "Invalid,Valid" else group.long (0x10+0x18)++0x03 line.long 0x00 "CSPR2,Chip-select Property Register 2" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_2 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_2 are valid" "Invalid,Valid" endif group.long (0x0C+0x24)++0x03 line.long 0x00 "CSPR3_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x24))&0x06)==(0x00||0x02)) group.long (0x10+0x24)++0x03 line.long 0x00 "CSPR3,Chip-select Property Register 3" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_3 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_3 are valid" "Invalid,Valid" else group.long (0x10+0x24)++0x03 line.long 0x00 "CSPR3,Chip-select Property Register 3" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_3 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_3 are valid" "Invalid,Valid" endif group.long (0x0C+0x30)++0x03 line.long 0x00 "CSPR4_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x30))&0x06)==(0x00||0x02)) group.long (0x10+0x30)++0x03 line.long 0x00 "CSPR4,Chip-select Property Register 4" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_4 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_4 are valid" "Invalid,Valid" else group.long (0x10+0x30)++0x03 line.long 0x00 "CSPR4,Chip-select Property Register 4" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_4 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_4 are valid" "Invalid,Valid" endif group.long (0x0C+0x3C)++0x03 line.long 0x00 "CSPR5_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x3C))&0x06)==(0x00||0x02)) group.long (0x10+0x3C)++0x03 line.long 0x00 "CSPR5,Chip-select Property Register 5" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_5 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_5 are valid" "Invalid,Valid" else group.long (0x10+0x3C)++0x03 line.long 0x00 "CSPR5,Chip-select Property Register 5" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_5 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_5 are valid" "Invalid,Valid" endif group.long (0x0C+0x48)++0x03 line.long 0x00 "CSPR6_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l.be(ad:0x01530000+0x10+0x48))&0x06)==(0x00||0x02)) group.long (0x10+0x48)++0x03 line.long 0x00 "CSPR6,Chip-select Property Register 6" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_6 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_6 are valid" "Invalid,Valid" else group.long (0x10+0x48)++0x03 line.long 0x00 "CSPR6,Chip-select Property Register 6" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_6 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_6 are valid" "Invalid,Valid" endif group.long (0xA0+0x0)++0x03 line.long 0x00 "AMASK0,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0xC)++0x03 line.long 0x00 "AMASK1,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x18)++0x03 line.long 0x00 "AMASK2,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x24)++0x03 line.long 0x00 "AMASK3,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x30)++0x03 line.long 0x00 "AMASK4,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x3C)++0x03 line.long 0x00 "AMASK5,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x48)++0x03 line.long 0x00 "AMASK6,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" newline if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x0))&0xE060)==0xC000) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS0 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x0))&0xE060)==0xC020) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS0 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x0))&0x60)==0x20) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x10))&0x06)==0x00) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x10))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x0))&0x80000000)==0x00) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x0)++0x03 hide.long 0x00 "CSOR0_X,Chip-Select Option Register" hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x02) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0xC))&0xE060)==0xC000) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS1 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0xC))&0xE060)==0xC020) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS1 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0xC))&0x60)==0x20) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x00) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0xC))&0x80000000)==0x00) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0xC)++0x03 hide.long 0x00 "CSOR1_X,Chip-Select Option Register" hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x28))&0x06)==0x02) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x18))&0xE060)==0xC000) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS2 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x18))&0xE060)==0xC020) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS2 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x18))&0x60)==0x20) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x28))&0x06)==0x00) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x28))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x18))&0x80000000)==0x00) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x18)++0x03 hide.long 0x00 "CSOR2_X,Chip-Select Option Register" hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x34))&0x06)==0x02) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x24))&0xE060)==0xC000) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS3 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x24))&0xE060)==0xC020) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS3 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x24))&0x60)==0x20) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x34))&0x06)==0x00) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x34))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x24))&0x80000000)==0x00) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x24)++0x03 hide.long 0x00 "CSOR3_X,Chip-Select Option Register" hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x40))&0x06)==0x02) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x30))&0xE060)==0xC000) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS4 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x30))&0xE060)==0xC020) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS4 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x30))&0x60)==0x20) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x40))&0x06)==0x00) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x40))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x30))&0x80000000)==0x00) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x30)++0x03 hide.long 0x00 "CSOR4_X,Chip-Select Option Register" hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x02) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x3C))&0xE060)==0xC000) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS5 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x3C))&0xE060)==0xC020) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS5 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x3C))&0x60)==0x20) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x00) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x3C))&0x80000000)==0x00) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x3C)++0x03 hide.long 0x00 "CSOR5_X,Chip-Select Option Register" hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l.be(ad:0x01530000+0x58))&0x06)==0x02) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--20. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB" bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l.be(ad:0x01530000+0x130+0x48))&0xE060)==0xC000) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS6 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x48))&0xE060)==0xC020) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS6 ,Spare region bytes number" elif (((per.l.be(ad:0x01530000+0x130+0x48))&0x60)==0x20) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l.be(ad:0x01530000+0x58))&0x06)==0x00) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l.be(ad:0x01530000+0x58))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130+0x48))&0x80000000)==0x00) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x48)++0x03 hide.long 0x00 "CSOR6_X,Chip-Select Option Register" hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif newline width 27. if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x130))&0x60)==0x20) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NAND,Flash Timing Register 0 for Chip Select 0 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NAND,Flash Timing Register 1 for Chip-Select 0 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NAND,Flash Timing Register 2 for Chip Select 0 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_NAND,Flash Timing Register 3 for Chip Select 0 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x130))&0x60)==0x00) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 0 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 0 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 0 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 0 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x10))&0x06)==0x00) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NOR,Flash Timing Register 0 for CS0 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NOR,Flash Timing Register 1 for CS0 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NOR,Flash Timing Register 2 for CS0 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0x0)++0x03 hide.long 0x00 "FTIM3_CS0_NOR,Flash Timing Register 3 for CS0 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x10))&0x06)==0x04) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_GPCM,Flash Timing Register 0 for CS0 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_GPCM,Flash Timing Register 1 for CS0 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_GPCM,Flash Timing Register 2 for CS0 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_GPCM,Flash Timing Register 3 for CS0 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x0)++0x03 hide.long 0x00 "FTIM0_CS0,Flash Timing Register 0 for CS0" hgroup.long (0x1C4+0x0)++0x03 hide.long 0x00 "FTIM1_CS0,Flash Timing Register 1 for CS0" hgroup.long (0x1C8+0x0)++0x03 hide.long 0x00 "FTIM2_CS0,Flash Timing Register 2 for CS0" hgroup.long (0x1CC+0x0)++0x03 hide.long 0x00 "FTIM3_CS0,Flash Timing Register 3 for CS0" endif if (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x13C))&0x60)==0x20) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NAND,Flash Timing Register 0 for Chip Select 1 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NAND,Flash Timing Register 1 for Chip-Select 1 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NAND,Flash Timing Register 2 for Chip Select 1 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_NAND,Flash Timing Register 3 for Chip Select 1 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x13C))&0x60)==0x00) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 1 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 1 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 1 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 1 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x00) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NOR,Flash Timing Register 0 for CS1 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NOR,Flash Timing Register 1 for CS1 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NOR,Flash Timing Register 2 for CS1 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0x30)++0x03 hide.long 0x00 "FTIM3_CS1_NOR,Flash Timing Register 3 for CS1 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x1C))&0x06)==0x04) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_GPCM,Flash Timing Register 0 for CS1 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_GPCM,Flash Timing Register 1 for CS1 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_GPCM,Flash Timing Register 2 for CS1 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_GPCM,Flash Timing Register 3 for CS1 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x30)++0x03 hide.long 0x00 "FTIM0_CS1,Flash Timing Register 0 for CS1" hgroup.long (0x1C4+0x30)++0x03 hide.long 0x00 "FTIM1_CS1,Flash Timing Register 1 for CS1" hgroup.long (0x1C8+0x30)++0x03 hide.long 0x00 "FTIM2_CS1,Flash Timing Register 2 for CS1" hgroup.long (0x1CC+0x30)++0x03 hide.long 0x00 "FTIM3_CS1,Flash Timing Register 3 for CS1" endif if (((per.l.be(ad:0x01530000+0x28))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x148))&0x60)==0x20) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NAND,Flash Timing Register 0 for Chip Select 2 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NAND,Flash Timing Register 1 for Chip-Select 2 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NAND,Flash Timing Register 2 for Chip Select 2 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_NAND,Flash Timing Register 3 for Chip Select 2 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x28))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x148))&0x60)==0x00) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 2 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 2 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 2 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 2 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x28))&0x06)==0x00) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NOR,Flash Timing Register 0 for CS2 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NOR,Flash Timing Register 1 for CS2 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NOR,Flash Timing Register 2 for CS2 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0x60)++0x03 hide.long 0x00 "FTIM3_CS2_NOR,Flash Timing Register 3 for CS2 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x28))&0x06)==0x04) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_GPCM,Flash Timing Register 0 for CS2 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_GPCM,Flash Timing Register 1 for CS2 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_GPCM,Flash Timing Register 2 for CS2 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_GPCM,Flash Timing Register 3 for CS2 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x60)++0x03 hide.long 0x00 "FTIM0_CS2,Flash Timing Register 0 for CS2" hgroup.long (0x1C4+0x60)++0x03 hide.long 0x00 "FTIM1_CS2,Flash Timing Register 1 for CS2" hgroup.long (0x1C8+0x60)++0x03 hide.long 0x00 "FTIM2_CS2,Flash Timing Register 2 for CS2" hgroup.long (0x1CC+0x60)++0x03 hide.long 0x00 "FTIM3_CS2,Flash Timing Register 3 for CS2" endif if (((per.l.be(ad:0x01530000+0x34))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x154))&0x60)==0x20) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NAND,Flash Timing Register 0 for Chip Select 3 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NAND,Flash Timing Register 1 for Chip-Select 3 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NAND,Flash Timing Register 2 for Chip Select 3 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_NAND,Flash Timing Register 3 for Chip Select 3 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x34))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x154))&0x60)==0x00) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 3 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 3 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 3 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 3 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x34))&0x06)==0x00) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NOR,Flash Timing Register 0 for CS3 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NOR,Flash Timing Register 1 for CS3 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NOR,Flash Timing Register 2 for CS3 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0x90)++0x03 hide.long 0x00 "FTIM3_CS3_NOR,Flash Timing Register 3 for CS3 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x34))&0x06)==0x04) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_GPCM,Flash Timing Register 0 for CS3 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_GPCM,Flash Timing Register 1 for CS3 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_GPCM,Flash Timing Register 2 for CS3 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_GPCM,Flash Timing Register 3 for CS3 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x90)++0x03 hide.long 0x00 "FTIM0_CS3,Flash Timing Register 0 for CS3" hgroup.long (0x1C4+0x90)++0x03 hide.long 0x00 "FTIM1_CS3,Flash Timing Register 1 for CS3" hgroup.long (0x1C8+0x90)++0x03 hide.long 0x00 "FTIM2_CS3,Flash Timing Register 2 for CS3" hgroup.long (0x1CC+0x90)++0x03 hide.long 0x00 "FTIM3_CS3,Flash Timing Register 3 for CS3" endif if (((per.l.be(ad:0x01530000+0x40))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x160))&0x60)==0x20) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NAND,Flash Timing Register 0 for Chip Select 4 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NAND,Flash Timing Register 1 for Chip-Select 4 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NAND,Flash Timing Register 2 for Chip Select 4 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_NAND,Flash Timing Register 3 for Chip Select 4 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x40))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x160))&0x60)==0x00) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 4 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 4 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 4 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 4 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x40))&0x06)==0x00) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NOR,Flash Timing Register 0 for CS4 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NOR,Flash Timing Register 1 for CS4 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NOR,Flash Timing Register 2 for CS4 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0xC0)++0x03 hide.long 0x00 "FTIM3_CS4_NOR,Flash Timing Register 3 for CS4 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x40))&0x06)==0x04) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_GPCM,Flash Timing Register 0 for CS4 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_GPCM,Flash Timing Register 1 for CS4 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_GPCM,Flash Timing Register 2 for CS4 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_GPCM,Flash Timing Register 3 for CS4 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0xC0)++0x03 hide.long 0x00 "FTIM0_CS4,Flash Timing Register 0 for CS4" hgroup.long (0x1C4+0xC0)++0x03 hide.long 0x00 "FTIM1_CS4,Flash Timing Register 1 for CS4" hgroup.long (0x1C8+0xC0)++0x03 hide.long 0x00 "FTIM2_CS4,Flash Timing Register 2 for CS4" hgroup.long (0x1CC+0xC0)++0x03 hide.long 0x00 "FTIM3_CS4,Flash Timing Register 3 for CS4" endif if (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x16C))&0x60)==0x20) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NAND,Flash Timing Register 0 for Chip Select 5 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NAND,Flash Timing Register 1 for Chip-Select 5 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NAND,Flash Timing Register 2 for Chip Select 5 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_NAND,Flash Timing Register 3 for Chip Select 5 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x16C))&0x60)==0x00) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 5 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 5 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 5 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 5 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x00) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NOR,Flash Timing Register 0 for CS5 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NOR,Flash Timing Register 1 for CS5 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NOR,Flash Timing Register 2 for CS5 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0xF0)++0x03 hide.long 0x00 "FTIM3_CS5_NOR,Flash Timing Register 3 for CS5 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x4C))&0x06)==0x04) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_GPCM,Flash Timing Register 0 for CS5 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_GPCM,Flash Timing Register 1 for CS5 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_GPCM,Flash Timing Register 2 for CS5 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_GPCM,Flash Timing Register 3 for CS5 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0xF0)++0x03 hide.long 0x00 "FTIM0_CS5,Flash Timing Register 0 for CS5" hgroup.long (0x1C4+0xF0)++0x03 hide.long 0x00 "FTIM1_CS5,Flash Timing Register 1 for CS5" hgroup.long (0x1C8+0xF0)++0x03 hide.long 0x00 "FTIM2_CS5,Flash Timing Register 2 for CS5" hgroup.long (0x1CC+0xF0)++0x03 hide.long 0x00 "FTIM3_CS5,Flash Timing Register 3 for CS5" endif if (((per.l.be(ad:0x01530000+0x58))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x178))&0x60)==0x20) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NAND,Flash Timing Register 0 for Chip Select 6 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NAND,Flash Timing Register 1 for Chip-Select 6 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NAND,Flash Timing Register 2 for Chip Select 6 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_NAND,Flash Timing Register 3 for Chip Select 6 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x58))&0x06)==0x02)&&(((per.l.be(ad:0x01530000+0x178))&0x60)==0x00) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 6 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 6 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 6 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 6 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l.be(ad:0x01530000+0x58))&0x06)==0x00) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NOR,Flash Timing Register 0 for CS6 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NOR,Flash Timing Register 1 for CS6 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NOR,Flash Timing Register 2 for CS6 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" hgroup.long (0x1CC+0x120)++0x03 hide.long 0x00 "FTIM3_CS6_NOR,Flash Timing Register 3 for CS6 - NOR Flash Mode" elif (((per.l.be(ad:0x01530000+0x58))&0x06)==0x04) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_GPCM,Flash Timing Register 0 for CS6 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_GPCM,Flash Timing Register 1 for CS6 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_GPCM,Flash Timing Register 2 for CS6 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_GPCM,Flash Timing Register 3 for CS6 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x120)++0x03 hide.long 0x00 "FTIM0_CS6,Flash Timing Register 0 for CS6" hgroup.long (0x1C4+0x120)++0x03 hide.long 0x00 "FTIM1_CS6,Flash Timing Register 1 for CS6" hgroup.long (0x1C8+0x120)++0x03 hide.long 0x00 "FTIM2_CS6,Flash Timing Register 2 for CS6" hgroup.long (0x1CC+0x120)++0x03 hide.long 0x00 "FTIM3_CS6,Flash Timing Register 3 for CS6" endif newline width 20. rgroup.long 0x400++0x03 line.long 0x00 "RB_STAT,Ready Busy Status for each Chip Select" bitfld.long 0x00 31. " RB0 ,Ready busy input from CS0" "Busy,Ready" bitfld.long 0x00 30. " RB1 ,Ready busy input from CS1" "Busy,Ready" bitfld.long 0x00 29. " RB2 ,Ready busy input from CS2" "Busy,Ready" newline bitfld.long 0x00 28. " RB3 ,Ready busy input from CS3" "Busy,Ready" bitfld.long 0x00 27. " RB4 ,Ready busy input from CS4" "Busy,Ready" bitfld.long 0x00 26. " RB5 ,Ready busy input from CS5" "Busy,Ready" newline bitfld.long 0x00 25. " RB6 ,Ready busy input from CS6" "Busy,Ready" group.long 0x40C++0x03 line.long 0x00 "GCR,General Control Register" bitfld.long 0x00 31. " SOFT_RST_ALL ,Software reset all" "No reset,Reset" bitfld.long 0x00 11.--15. " TBCTL_TRN_TIME ,Turnaround time of external buffer in terms of number of IFC module input clock cycles" ",1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk,5 IFC clk,6 IFC clk,7 IFC clk,8 IFC clk,9 IFC clk,10 IFC clk,11 IFC clk,12 IFC clk,13 IFC clk,14 IFC clk,15 IFC clk,16 IFC clk,17 IFC clk,18 IFC clk,19 IFC clk,20 IFC clk,21 IFC clk,22 IFC clk,23 IFC clk,24 IFC clk,25 IFC clk,26 IFC clk,27 IFC clk,28 IFC clk,29 IFC clk,30 IFC clk,31 IFC clk" group.long 0x418++0x03 line.long 0x00 "CM_EVTER_STAT,Common Event and Error Status Register" eventfld.long 0x00 31. " CSER ,Chip-select error" "No error,Error" group.long 0x424++0x03 line.long 0x00 "CM_EVTER_EN,Common Event and Error Enable Register" bitfld.long 0x00 31. " CSEREN ,Chip-select error checking enable" "Disabled,Enabled" group.long 0x430++0x03 line.long 0x00 "CM_EVTER_INTR_EN,Common Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " CSERIREN ,Chip-select error interrupt enable" "Disabled,Enabled" rgroup.long 0x43C++0x07 line.long 0x00 "CM_ERATTR0,Common Transfer Error Attributes Register 0" bitfld.long 0x00 31. " ERTYP ,Transaction type of the error" "Write,Read" hexmask.long.byte 0x00 20.--27. 1. " ERAID ,ID of the error transaction" hexmask.long.byte 0x00 8.--15. 1. " ERSRCID ,Source ID of the error transaction" line.long 0x04 "CM_ERATTR1,Common Transfer Error Attributes Register 1" group.long 0x44C++0x03 line.long 0x00 "CCR,Clock Control Register" sif cpuis("LS10?3*") bitfld.long 0x00 24.--27. " CLKDIV ,Clock division ratio" ",/2,/3,/4,,,,/8,?..." else bitfld.long 0x00 24.--27. " CLKDIV ,Clock division ratio" ",/2,,/4,,,,/8,?..." endif bitfld.long 0x00 16.--19. " CLK_DLY ,IFC clock delay" "No delay,1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk,5 IFC clk,6 IFC clk,7 IFC clk,8 IFC clk,9 IFC clk,10 IFC clk,11 IFC clk,12 IFC clk,13 IFC clk,14 IFC clk,15 IFC clk" bitfld.long 0x00 15. " INV_CLK_EN ,IFC clock inversion" "Not inverted,Inverted" rgroup.long 0x450++0x03 line.long 0x00 "CSR,Clock Status Register" bitfld.long 0x00 31. " CLK_STAT ,Clock status" "Unstable,Stable" if (((per.l.be(ad:0x01530000+0x130))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x13C))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x148))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x154))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x160))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x16C))&0x60)==0x20)||(((per.l.be(ad:0x01530000+0x178))&0x60)==0x20) group.long 0x454++0x03 line.long 0x00 "DDR_CCR,DDR Clock Control Register" bitfld.long 0x00 29. " GLOBAL_DDR_CLK_EN ,Switches off the IFC DDR clock" "Disabled,Enabled" bitfld.long 0x00 28. " PGM_DDR_CLK_STOP ,DDR clock stop in case of program operation" "Enabled,Stopped" bitfld.long 0x00 23.--26. " DDR_LOW_CLKDIV ,Clock division ratio" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" newline bitfld.long 0x00 20. " TDQSS ,Data input to first DQS transition delay" "0.75 DDR_CLOCK,1.25 DDR_CLOCK" else group.long 0x454++0x03 line.long 0x00 "DDR_CCR,DDR Clock Control Register" bitfld.long 0x00 29. " GLOBAL_DDR_CLK_EN ,Switches off the IFC DDR clock" "Disabled,Enabled" bitfld.long 0x00 23.--26. " DDR_LOW_CLKDIV ,Clock division ratio" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" endif if (((per.l.be(ad:0x01530000+0x130))&0x60)==0x20) if (((per.l.be(ad:0x01530000+0x1000))&0xC00000)==0x400000) group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 27. " SINGLE_DATA_MODE ,Single data mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,?..." hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" else group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 27. " SINGLE_DATA_MODE ,Single data mode enable" "Disabled,Enabled" newline bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" endif else if (((per.l.be(ad:0x01530000+0x1000))&0xC00000)==0x400000) group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." newline bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,?..." hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" else group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." newline bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" endif endif group.long 0x1014++0x07 line.long 0x00 "NAND_FCR0,NAND Flash Command Register 0" hexmask.long.byte 0x00 24.--31. 1. " CMD0 ,General purpose FCM flash command byte 0" hexmask.long.byte 0x00 16.--23. 1. " CMD1 ,General purpose FCM flash command byte 1" hexmask.long.byte 0x00 8.--15. 1. " CMD2 ,General purpose FCM flash command byte 2" newline hexmask.long.byte 0x00 0.--7. 1. " CMD3 ,General purpose FCM flash command byte 3" line.long 0x04 "NAND_FCR1,NAND Flash Command Register 1" hexmask.long.byte 0x04 24.--31. 1. " CMD4 ,General purpose FCM flash command byte 4" hexmask.long.byte 0x04 16.--23. 1. " CMD5 ,General purpose FCM flash command byte 5" hexmask.long.byte 0x04 8.--15. 1. " CMD6 ,General purpose FCM flash command byte 6" newline hexmask.long.byte 0x04 0.--7. 1. " CMD7 ,General purpose FCM flash command byte 7" group.long (0x103C+0x0)++0x03 line.long 0x00 "ROW0,Flash Row Address Register 0" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x1108))&0x3FFF)==0x00) if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0_8KB,Flash COL Address 8 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address 4 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address 2 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0_8KB,Flash COL Address 8 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address 4 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address 2 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long (0x1044+0x0)++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long (0x103C+0x10)++0x03 line.long 0x00 "ROW1,Flash Row Address Register 1" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x1108))&0x3FFF)==0x00) if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1_8KB,Flash COL Address 8 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address 4 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address 2 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1_8KB,Flash COL Address 8 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address 4 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address 2 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long (0x1044+0x10)++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long (0x103C+0x20)++0x03 line.long 0x00 "ROW2,Flash Row Address Register 2" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x1108))&0x3FFF)==0x00) if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2_8KB,Flash COL Address 8 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address 4 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address 2 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2_8KB,Flash COL Address 8 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address 4 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address 2 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long (0x1044+0x20)++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long (0x103C+0x30)++0x03 line.long 0x00 "ROW3,Flash Row Address Register 3" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x1108))&0x3FFF)==0x00) if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3_8KB,Flash COL Address 8 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address 4 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address 2 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3_8KB,Flash COL Address 8 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address 4 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address 2 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long (0x1044+0x30)++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long 0x1108++0x03 line.long 0x00 "NAND_BC,Flash Byte Count Register for NAND Flash" hexmask.long.word 0x00 0.--13. 1. " BC ,Count of bytes transferred during RBCD or WBCD opcode" group.long 0x1110++0x0B line.long 0x00 "NAND_FIR0,NAND Flash Instruction Register 0" bitfld.long 0x00 26.--31. " OP0 ,Opcode 0" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 20.--25. " OP1 ,Opcode 1" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 14.--19. " OP2 ,Opcode 2" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x00 8.--13. " OP3 ,Opcode 3" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 2.--7. " OP4 ,Opcode 4" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." line.long 0x04 "NAND_FIR1,NAND Flash Instruction Register 1" bitfld.long 0x04 26.--31. " OP5 ,Opcode 5" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 20.--25. " OP6 ,Opcode 6" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 14.--19. " OP7 ,Opcode 7" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x04 8.--13. " OP8 ,Opcode 8" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 2.--7. " OP9 ,Opcode 9" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." line.long 0x08 "NAND_FIR2,NAND Flash Instruction Register 2" bitfld.long 0x08 26.--31. " OP10 ,Opcode 10" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 20.--25. " OP11 ,Opcode 11" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 14.--19. " OP12 ,Opcode 12" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x08 8.--13. " OP13 ,Opcode 13" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 2.--7. " OP14 ,Opcode 14" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." group.long 0x115C++0x03 line.long 0x00 "NAND_CSEL,NAND Chip-Select Register" bitfld.long 0x00 26.--28. " CSEL ,Chip-Select for NAND flash operation" "CS 0,CS 1,CS 2,CS 3,CS 4,CS 5,CS 6,?..." group.long 0x1164++0x03 line.long 0x00 "NANDSEQ_STRT,NAND Operation Sequence Start" bitfld.long 0x00 31. " NAND_FIR_STRT ,NAND flash operation start" "No effect,Start" bitfld.long 0x00 23. " AUTO_ERS ,Automatic erase start" "No effect,Start" bitfld.long 0x00 20. " AUTO_PGM ,Automatic program start" "No effect,Start" newline bitfld.long 0x00 17. " AUTO_CPB ,Automatic copyback start" "No effect,Start" bitfld.long 0x00 14. " AUTO_RD ,Automatic read operation start" "No effect,Start" bitfld.long 0x00 11. " AUTO_STAT_RD ,Automatic status read start" "No effect,Start" group.long 0x116C++0x03 line.long 0x00 "NAND_EVTER_STAT,NAND Event and Error Status Register" eventfld.long 0x00 31. " OPC ,NAND flash operation complete event" "Not completed,Completed" eventfld.long 0x00 27. " FTOER ,Flash timeout error" "No error,Error" eventfld.long 0x00 26. " WPER ,Write protect error" "No error,Error" newline eventfld.long 0x00 25. " ECCER ,ECC error" "No error,Error" eventfld.long 0x00 15. " RCW_DN ,Page read from dev and written to SRAM buffer during RCW load" "Not occurred,Occurred" eventfld.long 0x00 14. " BOOT_DN ,Page read from dev and written to SRAM buffer during BOOT load" "Not occurred,Occurred" newline eventfld.long 0x00 11. " BBI_SRCH_SEL ,Bad block indicator search select" "Page 0 & 1,Page 0 & last" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x180000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" hexmask.long.word 0x00 16.--31. 1. " SEC_DONE ,Single page of 8KB done" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x100000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" hexmask.long.byte 0x00 24.--31. 1. " SEC_DONE[8:15] ,Page 1 done" hexmask.long.byte 0x00 16.--23. 1. " [0:7] ,Page 0 done" elif (((per.l.be(ad:0x01530000+0x130))&0x180000)==0x80000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" bitfld.long 0x00 28.--31. " SEC_DONE[12:15] ,Page 3 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " [8:11] ,Page 2 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " [4:7] ,Page 1 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. " [0:3] ,Page 0 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" eventfld.long 0x00 31. " SEC_DONE15 ,Page 15 done" "Not done,Done" eventfld.long 0x00 30. " SEC_DONE14 ,Page 14 done" "Not done,Done" eventfld.long 0x00 29. " SEC_DONE13 ,Page 13 done" "Not done,Done" newline eventfld.long 0x00 28. " SEC_DONE12 ,Page 12 done" "Not done,Done" eventfld.long 0x00 27. " SEC_DONE11 ,Page 11 done" "Not done,Done" eventfld.long 0x00 26. " SEC_DONE10 ,Page 10 done" "Not done,Done" newline eventfld.long 0x00 25. " SEC_DONE9 ,Page 9 done" "Not done,Done" eventfld.long 0x00 24. " SEC_DONE8 ,Page 8 done" "Not done,Done" eventfld.long 0x00 23. " SEC_DONE7 ,Page 7 done" "Not done,Done" newline eventfld.long 0x00 22. " SEC_DONE6 ,Page 6 done" "Not done,Done" eventfld.long 0x00 21. " SEC_DONE5 ,Page 5 done" "Not done,Done" eventfld.long 0x00 20. " SEC_DONE4 ,Page 4 done" "Not done,Done" newline eventfld.long 0x00 19. " SEC_DONE3 ,Page 3 done" "Not done,Done" eventfld.long 0x00 18. " SEC_DONE2 ,Page 2 done" "Not done,Done" eventfld.long 0x00 17. " SEC_DONE1 ,Page 1 done" "Not done,Done" newline eventfld.long 0x00 16. " SEC_DONE0 ,Page 0 done" "Not done,Done" endif else hgroup.long 0x1174++0x03 hide.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" endif group.long 0x1180++0x03 line.long 0x00 "NAND_EVTER_EN,NAND Event and Error Enable Register" bitfld.long 0x00 31. " OPCEN ,NAND flash operation complete event enable" "Disabled,Enabled" bitfld.long 0x00 29. " PGRDCMPLEN ,NAND flash page read completion event enable" "Disabled,Enabled" bitfld.long 0x00 27. " FTOEREN ,Flash time out error enable (for R/B timeout and DQS timeout)" "Disabled,Enabled" newline bitfld.long 0x00 26. " WPEREN ,Write protect error checking enable" "Disabled,Enabled" bitfld.long 0x00 25. " ECCEREN ,ECC error logging enable" "Disabled,Enabled" group.long 0x118C++0x03 line.long 0x00 "NAND_EVTER_INTR_EN,NAND Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " OPCIREN ,NAND flash operation complete event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " PGRDCMPLIREN ,Page read completion event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FTOERIREN ,Flash timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " WPERIREN ,Write protect error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " ECCERIREN ,ECC error interrupt enable" "Disabled,Enabled" rgroup.long 0x1198++0x07 line.long 0x00 "NAND_ERATTR0,NAND Transfer Error Attributes Register 0" bitfld.long 0x00 26.--28. " ERCS ,Chip-select corresponding to NAND error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,?..." bitfld.long 0x00 19. " ERTTYPE ,Transaction type of NAND error" "Write,Read" line.long 0x04 "NAND_ERATTR1,NAND Transfer Error Attributes Register 1" rgroup.long 0x11E0++0x03 line.long 0x00 "NAND_FSR,NAND Flash Status Register" hexmask.long.byte 0x00 24.--31. 1. " RS0 ,First byte of data read from read status operation" hexmask.long.byte 0x00 16.--23. 1. " RS1 ,Second byte of data read from read status operation" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x02) if (((per.l.be(ad:0x01530000+0x130))&0x30000000)==(0x00||0x10000000)) rgroup.long 0x11E8++0x0F line.long 0x00 "ECCSTAT0,ECC Status and Result of Flash Operation Register 0" bitfld.long 0x00 24.--29. " NUMER0 ,Number of ECC errors on sector #0 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." bitfld.long 0x00 16.--21. " NUMER1 ,Number of ECC errors on sector #1 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." bitfld.long 0x00 8.--13. " NUMER2 ,Number of ECC errors on sector #2 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." newline bitfld.long 0x00 0.--5. " NUMER3 ,Number of ECC errors on sector #3 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." line.long 0x04 "ECCSTAT1,ECC Status and Result of Flash Operation Register 1" bitfld.long 0x04 24.--29. " NUMER4 ,Number of ECC errors on sector #4 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." bitfld.long 0x04 16.--21. " NUMER5 ,Number of ECC errors on sector #5 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." bitfld.long 0x04 8.--13. " NUMER6 ,Number of ECC errors on sector #6 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." newline bitfld.long 0x04 0.--5. " NUMER7 ,Number of ECC errors on sector #7 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,,,,,,,Uncorrectable errors,?..." line.long 0x08 "ECCSTAT2,ECC Status and Result of Flash Operation Register 2" bitfld.long 0x08 24.--27. " NUMER8 ,Number of ECC errors on sector #8 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. " NUMER9 ,Number of ECC errors on sector #9 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " NUMER10 ,Number of ECC errors on sector #10 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " NUMER11 ,Number of ECC errors on sector #11 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ECCSTAT3,ECC Status and Result of Flash Operation Register 3" bitfld.long 0x0C 24.--27. " NUMER12 ,Number of ECC errors on sector #12 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " NUMER13 ,Number of ECC errors on sector #13 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " NUMER14 ,Number of ECC errors on sector #14 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " NUMER15 ,Number of ECC errors on sector #15 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x11E8++0x0F line.long 0x00 "ECCSTAT0,ECC Status and Result of Flash Operation Register 0" bitfld.long 0x00 24.--29. " NUMER0 ,Number of ECC errors on sector #0 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" bitfld.long 0x00 16.--21. " NUMER1 ,Number of ECC errors on sector #1 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" bitfld.long 0x00 8.--13. " NUMER2 ,Number of ECC errors on sector #2 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" newline bitfld.long 0x00 0.--5. " NUMER3 ,Number of ECC errors on sector #3 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" line.long 0x04 "ECCSTAT1,ECC Status and Result of Flash Operation Register 1" bitfld.long 0x04 24.--29. " NUMER4 ,Number of ECC errors on sector #4 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" bitfld.long 0x04 16.--21. " NUMER5 ,Number of ECC errors on sector #5 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" bitfld.long 0x04 8.--13. " NUMER6 ,Number of ECC errors on sector #6 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" newline bitfld.long 0x04 0.--5. " NUMER7 ,Number of ECC errors on sector #7 of SRAM buffer" "No error,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,,,,,,,,,,,,,,,,,,,,,,,Uncorrectable errors" line.long 0x08 "ECCSTAT2,ECC Status and Result of Flash Operation Register 2" bitfld.long 0x08 24.--27. " NUMER8 ,Number of ECC errors on sector #8 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. " NUMER9 ,Number of ECC errors on sector #9 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " NUMER10 ,Number of ECC errors on sector #10 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " NUMER11 ,Number of ECC errors on sector #11 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "ECCSTAT3,ECC Status and Result of Flash Operation Register 3" bitfld.long 0x0C 24.--27. " NUMER12 ,Number of ECC errors on sector #12 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 16.--19. " NUMER13 ,Number of ECC errors on sector #13 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. " NUMER14 ,Number of ECC errors on sector #14 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " NUMER15 ,Number of ECC errors on sector #15 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else hgroup.long 0x11E8++0x03 hide.long 0x00 "ECCSTAT0,ECC Status and Result of Flash Operation Register 0" hgroup.long 0x11EC++0x03 hide.long 0x00 "ECCSTAT1,ECC Status and Result of Flash Operation Register 1" hgroup.long 0x11F0++0x03 hide.long 0x00 "ECCSTAT2,ECC Status and Result of Flash Operation Register 2" hgroup.long 0x11F4++0x03 hide.long 0x00 "ECCSTAT3,ECC Status and Result of Flash Operation Register 3" endif group.long 0x1278++0x03 line.long 0x00 "NANDCR,NAND Control Register" bitfld.long 0x00 25.--28. " FTOCNT ,Flash timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" wgroup.long 0x1284++0x03 line.long 0x00 "NAND_AUTOBOOT_TRGR,NAND Autoboot Trigger Register" bitfld.long 0x00 31. " RCW_LD ,RCW load" "No effect,Load" bitfld.long 0x00 29. " BOOT_LD ,BOOT load" "No effect,Load" rgroup.long 0x128C++0x03 line.long 0x00 "NAND_MDR,NAND Flash Memory Data Register" hexmask.long.byte 0x00 24.--31. 1. " RDATA0 ,1st read data byte when opcode SBRD is used for read" hexmask.long.byte 0x00 16.--23. 1. " RDATA1 ,Second read data byte when opcode SBRD is used for read" group.long 0x1300++0x07 line.long 0x00 "NAND_DLL_LOW_CFG0,Nand DLL Low Config 0 Register" bitfld.long 0x00 31. " DLL_ENABLE ,This bit enables the DLL" "Disabled,Enabled" bitfld.long 0x00 30. " DLL_RESET ,This bit resets the DLL" "No reset,Reset" line.long 0x04 "NAND_DLL_LOW_CFG1,Nand DLL Low Config 1 Register" bitfld.long 0x04 31. " DLL_PD_PULSE_STRETCH_SEL ,Select between 2 or 4 delays cells for pulse width detection logic" "4 cells,2 cells" bitfld.long 0x04 16.--19. " DLL_REF_UPDATE_INT ,Overrides the default update interval of the reference delay line" "2 REF clk cycles,3 REF clk cycles,4 REF clk cycles,5 REF clk cycles,6 REF clk cycles,7 REF clk cycles,8 REF clk cycles,9 REF clk cycles,10 REF clk cycles,11 REF clk cycles,12 REF clk cycles,13 REF clk cycles,14 REF clk cycles,15 REF clk cycles,16 REF clk cycles,17 REF clk cycles" hexmask.long.byte 0x04 0.--7. 1. " DLL_SLV_UPDATE_INT ,Overrides the default update interval of the slave delay line" rgroup.long 0x130C++0x03 line.long 0x00 "NANDDLLLOWSTAT,NAND DLL Low Status Register" bitfld.long 0x00 31. " DLLSTSREFLOCK ,DLL reference delay line lock status" "0,1" bitfld.long 0x00 27. " DLL_STS_SLV_LOCK ,DLL slave delay chain lock status" "0,1" hexmask.long.byte 0x00 12.--19. 1. " DLL_STS_REF_SEL ,Status of selected tap for reference delay line" newline hexmask.long.byte 0x00 0.--7. 1. " DLL_STS_SLV_SEL ,Status of selected tap for slave delay line" group.long 0x1400++0x03 line.long 0x00 "NOR_EVTER_STAT,NOR Event and Error Status Register" eventfld.long 0x00 31. " OPC_NOR ,NOR command sequence operation complete event indication" "Not complete,Complete" eventfld.long 0x00 26. " WPER ,Write protect error" "No error,Error" eventfld.long 0x00 24. " STOER ,Command sequence timeout error" "No error,Error" group.long 0x140C++0x03 line.long 0x00 "NOR_EVTER_EN,NOR Event and Error Enable Register" bitfld.long 0x00 31. " OPCEN_NOR ,NOR command sequence operation complete event enable" "Disabled,Enabled" bitfld.long 0x00 26. " WPEREN ,Write protect error checking enable" "Disabled,Enabled" bitfld.long 0x00 24. " STOEREN ,Command sequence timeout error enable" "Disabled,Enabled" group.long 0x1418++0x03 line.long 0x00 "NOR_EVTER_INTR_EN,NOR Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " OPCIREN_NOR ,NOR command sequence operation complete event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " WPERIREN ,Write protect error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " STOERIREN ,NOR command sequence timeout error interrupt enable" "Disabled,Enabled" rgroup.long 0x1424++0x0B line.long 0x00 "NOR_ERATTR0,NOR Transfer Error Attributes Register 0" hexmask.long.byte 0x00 24.--31. 1. " ERSRCID ,SRCID corresponding to error transaction" hexmask.long.byte 0x00 12.--19. 1. " ERAID ,ID of the error transaction" bitfld.long 0x00 6.--8. " ERCS ,Chip-select corresponding to NOR error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,?..." newline bitfld.long 0x00 0. " ERTYPE ,Type of the transaction" "Write,Read" line.long 0x04 "NOR_ERATTR1,NOR Transfer Error Attribute Register 1" line.long 0x08 "NOR_ERATTR2,NOR Transfer Error Attribute Register 2" bitfld.long 0x08 16.--19. " ER_NUM_PHASE_EXP ,Number of phase expected in command sequence which timed-out by system side" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x08 8.--11. " ER_NUM_PHASE_PER ,Number of command sequence phases performed before timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1440++0x03 line.long 0x00 "NORCR,NOR Control Register" bitfld.long 0x00 24.--27. " NUM_PHASE ,Number of address/data phases on device for which chip-select has to be asserted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " STOCNT ,Sequence timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" group.long 0x1800++0x03 line.long 0x00 "GPCM_EVTER_STAT,GPCM Event and Error Status Register" eventfld.long 0x00 26. " TOER ,Timeout error" "No error,Error" eventfld.long 0x00 24. " PER ,Parity error" "No error,Error" eventfld.long 0x00 22. " ABER ,Abort error" "No error,Error" group.long 0x180C++0x03 line.long 0x00 "GPCM_EVTER_EN,GPCM Event and Error Enable Register" bitfld.long 0x00 26. " TOEREN ,Timeout error checking enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEREN ,Parity error checking enable" "Disabled,Enabled" bitfld.long 0x00 22. " ABEREN ,Abort error checking enable" "Disabled,Enabled" group.long 0x1818++0x03 line.long 0x00 "GPCM_EVTER_INTR_EN,GPCM Event and Error Interrupt Enable Register" bitfld.long 0x00 26. " TOERIREN ,Timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PERIREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " ABERIREN ,Abort error interrupt enable" "Disabled,Enabled" rgroup.long 0x1824++0x07 line.long 0x00 "GPCM_ERATTR0,GPCM Transfer Error Attributes Register 0" hexmask.long.byte 0x00 24.--31. 1. " ERSRCID ,SRCID corresponding to error transaction" hexmask.long.byte 0x00 12.--19. 1. " ERAID ,ID of the error transaction" bitfld.long 0x00 6.--8. " ERCS ,Chip-select corresponding to GPCM error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,?..." newline bitfld.long 0x00 0. " ERTYPE ,Type of the transaction" "Write,Read" line.long 0x04 "GPCM_ERATTR1,GPCM Transfer Error Attributes Register 1" if (((per.l.be(ad:0x01530000+0x10))&0x06)==0x04) if (((per.l.be(ad:0x01530000+0x130))&0x80000000)==0x80000000) rgroup.long 0x182C++0x03 line.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" bitfld.long 0x00 10.--11. " PERR_BEAT ,Gives information on which beat of address/data parity error is observed" "0,1,2,3" bitfld.long 0x00 7. " PERR_BYTE0 ,Parity error on byte 0" "No error,Error" bitfld.long 0x00 6. " PERR_BYTE1 ,Parity error on byte 1" "No error,Error" newline bitfld.long 0x00 5. " PERR_BYTE2 ,Parity error on byte 2" "No error,Error" bitfld.long 0x00 4. " PERR_BYTE3 ,Parity error on byte 3" "No error,Error" bitfld.long 0x00 0. " PERR_AD ,Parity error reported in address or data phase" "Address,Data" else rgroup.long 0x182C++0x03 line.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" bitfld.long 0x00 7. " PERR_BYTE0 ,Parity error on byte 0" "No error,Error" bitfld.long 0x00 6. " PERR_BYTE1 ,Parity error on byte 1" "No error,Error" bitfld.long 0x00 5. " PERR_BYTE2 ,Parity error on byte 2" "No error,Error" newline bitfld.long 0x00 4. " PERR_BYTE3 ,Parity error on byte 3" "No error,Error" endif else hgroup.long 0x182C++0x03 hide.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" endif rgroup.long 0x1830++0x03 line.long 0x00 "GPCM_STAT,GPCM Status Register" bitfld.long 0x00 0. " GPCM_BSY ,GPCM busy" "Idle,Busy" endian.le width 0x0B tree.end elif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "IFC (Integrated Flash Controller)" base ad:0x02240000 width 12. rgroup.long 0x00++0x03 line.long 0x00 "REV,IFC Revision Control Register" hexmask.long.byte 0x00 24.--27. 1. " REV_MAJ ,Major revision" hexmask.long.byte 0x00 16.--19. 1. " REV_MIN ,Minor revision" group.long (0x0C+0x0)++0x03 line.long 0x00 "CSPR0_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x0))&0x06)==(0x00||0x02)) group.long (0x10+0x0)++0x03 line.long 0x00 "CSPR0,Chip-select Property Register 0" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_0 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_0 are valid" "Invalid,Valid" else group.long (0x10+0x0)++0x03 line.long 0x00 "CSPR0,Chip-select Property Register 0" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_0 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_0 are valid" "Invalid,Valid" endif group.long (0x0C+0xC)++0x03 line.long 0x00 "CSPR1_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0xC))&0x06)==(0x00||0x02)) group.long (0x10+0xC)++0x03 line.long 0x00 "CSPR1,Chip-select Property Register 1" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_1 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_1 are valid" "Invalid,Valid" else group.long (0x10+0xC)++0x03 line.long 0x00 "CSPR1,Chip-select Property Register 1" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_1 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_1 are valid" "Invalid,Valid" endif group.long (0x0C+0x18)++0x03 line.long 0x00 "CSPR2_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x18))&0x06)==(0x00||0x02)) group.long (0x10+0x18)++0x03 line.long 0x00 "CSPR2,Chip-select Property Register 2" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_2 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_2 are valid" "Invalid,Valid" else group.long (0x10+0x18)++0x03 line.long 0x00 "CSPR2,Chip-select Property Register 2" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_2 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_2 are valid" "Invalid,Valid" endif group.long (0x0C+0x24)++0x03 line.long 0x00 "CSPR3_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x24))&0x06)==(0x00||0x02)) group.long (0x10+0x24)++0x03 line.long 0x00 "CSPR3,Chip-select Property Register 3" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_3 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_3 are valid" "Invalid,Valid" else group.long (0x10+0x24)++0x03 line.long 0x00 "CSPR3,Chip-select Property Register 3" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_3 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_3 are valid" "Invalid,Valid" endif group.long (0x0C+0x30)++0x03 line.long 0x00 "CSPR4_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x30))&0x06)==(0x00||0x02)) group.long (0x10+0x30)++0x03 line.long 0x00 "CSPR4,Chip-select Property Register 4" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_4 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_4 are valid" "Invalid,Valid" else group.long (0x10+0x30)++0x03 line.long 0x00 "CSPR4,Chip-select Property Register 4" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_4 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_4 are valid" "Invalid,Valid" endif group.long (0x0C+0x3C)++0x03 line.long 0x00 "CSPR5_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x3C))&0x06)==(0x00||0x02)) group.long (0x10+0x3C)++0x03 line.long 0x00 "CSPR5,Chip-select Property Register 5" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_5 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_5 are valid" "Invalid,Valid" else group.long (0x10+0x3C)++0x03 line.long 0x00 "CSPR5,Chip-select Property Register 5" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_5 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_5 are valid" "Invalid,Valid" endif group.long (0x0C+0x48)++0x03 line.long 0x00 "CSPR6_EXT,Extended Chip Select Property Register" hexmask.long.byte 0x00 0.--7. 0x01 " BA_EXT ,Extended base address" if (((per.l(ad:0x02240000+0x10+0x48))&0x06)==(0x00||0x02)) group.long (0x10+0x48)++0x03 line.long 0x00 "CSPR6,Chip-select Property Register 6" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." bitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_6 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_6 are valid" "Invalid,Valid" else group.long (0x10+0x48)++0x03 line.long 0x00 "CSPR6,Chip-select Property Register 6" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" bitfld.long 0x00 7.--8. " PS ,Specifies the port size of this memory region" ",8 bit,16 bit,?..." rbitfld.long 0x00 6. " WP ,Write protect" "Read/Write,Read only" bitfld.long 0x00 4. " TE ,Specifies value that will be driven on TE pin when CS_6 is selected" "Logic 0,Logic 1" newline bitfld.long 0x00 1.--2. " MSEL ,Machine select" "NOR flash,NAND flash,GPCM,?..." bitfld.long 0x00 0. " V ,Indicates that the contents of CSPR_6 are valid" "Invalid,Valid" endif newline group.long (0xA0+0x0)++0x03 line.long 0x00 "AMASK0,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0xC)++0x03 line.long 0x00 "AMASK1,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x18)++0x03 line.long 0x00 "AMASK2,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x24)++0x03 line.long 0x00 "AMASK3,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x30)++0x03 line.long 0x00 "AMASK4,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x3C)++0x03 line.long 0x00 "AMASK5,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" group.long (0xA0+0x48)++0x03 line.long 0x00 "AMASK6,Address Mask Register" bitfld.long 0x00 31. " AM ,16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 30. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 29. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 28. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 27. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 26. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 25. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 24. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 23. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 22. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 21. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 20. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 19. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 18. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 17. ",16-bit address mask corresponding to memory bank" "0,1" bitfld.long 0x00 16. ",16-bit address mask corresponding to memory bank" "0,1" newline if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x0))&0xE060)==0xC000) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS0 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x0))&0xE060)==0xC020) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS0 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x0))&0x60)==0x20) group.long (0x134+0x0)++0x03 line.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x10))&0x06)==0x00) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x10))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x0))&0x80000000)==0x00) group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x0)++0x03 line.long 0x00 "CSOR0_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x0)++0x03 hide.long 0x00 "CSOR0_X,Chip-Select Option Register" hgroup.long (0x134+0x0)++0x03 hide.long 0x00 "CSOR0_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x1C))&0x06)==0x02) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0xC))&0xE060)==0xC000) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS1 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0xC))&0xE060)==0xC020) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS1 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0xC))&0x60)==0x20) group.long (0x134+0xC)++0x03 line.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x1C))&0x06)==0x00) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x1C))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0xC))&0x80000000)==0x00) group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0xC)++0x03 line.long 0x00 "CSOR1_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0xC)++0x03 hide.long 0x00 "CSOR1_X,Chip-Select Option Register" hgroup.long (0x134+0xC)++0x03 hide.long 0x00 "CSOR1_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x28))&0x06)==0x02) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x18))&0xE060)==0xC000) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS2 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x18))&0xE060)==0xC020) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS2 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x18))&0x60)==0x20) group.long (0x134+0x18)++0x03 line.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x28))&0x06)==0x00) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x28))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x18))&0x80000000)==0x00) group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x18)++0x03 line.long 0x00 "CSOR2_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x18)++0x03 hide.long 0x00 "CSOR2_X,Chip-Select Option Register" hgroup.long (0x134+0x18)++0x03 hide.long 0x00 "CSOR2_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x34))&0x06)==0x02) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x24))&0xE060)==0xC000) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS3 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x24))&0xE060)==0xC020) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS3 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x24))&0x60)==0x20) group.long (0x134+0x24)++0x03 line.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x34))&0x06)==0x00) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x34))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x24))&0x80000000)==0x00) group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x24)++0x03 line.long 0x00 "CSOR3_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x24)++0x03 hide.long 0x00 "CSOR3_X,Chip-Select Option Register" hgroup.long (0x134+0x24)++0x03 hide.long 0x00 "CSOR3_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x40))&0x06)==0x02) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x30))&0xE060)==0xC000) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS4 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x30))&0xE060)==0xC020) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS4 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x30))&0x60)==0x20) group.long (0x134+0x30)++0x03 line.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x40))&0x06)==0x00) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x40))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x30))&0x80000000)==0x00) group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x30)++0x03 line.long 0x00 "CSOR4_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x30)++0x03 hide.long 0x00 "CSOR4_X,Chip-Select Option Register" hgroup.long (0x134+0x30)++0x03 hide.long 0x00 "CSOR4_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x4C))&0x06)==0x02) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x3C))&0xE060)==0xC000) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS5 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x3C))&0xE060)==0xC020) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS5 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x3C))&0x60)==0x20) group.long (0x134+0x3C)++0x03 line.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x4C))&0x06)==0x00) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x4C))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x3C))&0x80000000)==0x00) group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x3C)++0x03 line.long 0x00 "CSOR5_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x3C)++0x03 hide.long 0x00 "CSOR5_X,Chip-Select Option Register" hgroup.long (0x134+0x3C)++0x03 hide.long 0x00 "CSOR5_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif if (((per.l(ad:0x02240000+0x58))&0x06)==0x02) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_NAND,Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 31. " ECC_ENC_EN ,ECC encoder enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " ECC_MODE ,ECC mode of operation" "4 bit,8 bit,24 bit,40 bit" bitfld.long 0x00 26. " ECC_DEC_EN ,ECC decoding enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " RAL ,Row address length" "1 byte,2 bytes,3 bytes,4 bytes" newline bitfld.long 0x00 19.--21. " PGS ,Page size" "512 bytes,2 KB,4 KB,8 KB,16 KB,?..." bitfld.long 0x00 13.--15. " SPRZ ,Spare size" "16 bytes,64 bytes,128 bytes,210 bytes,218 bytes,224 bytes,CSORn_EXT,?..." bitfld.long 0x00 8.--10. " PB ,Pages per block" "32 pages,64 pages,128 pages,256 pages,512 pages,?..." bitfld.long 0x00 5.--6. " NAND_MODE ,NAND mode of operation" "Async,NVDDR,?..." newline bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP clk,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" if (((per.l(ad:0x02240000+0x130+0x48))&0xE060)==0xC000) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS6 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x48))&0xE060)==0xC020) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." hexmask.long.word 0x00 0.--10. 1. " SPARE_BYTES_CS6 ,Spare region bytes number" elif (((per.l(ad:0x02240000+0x130+0x48))&0x60)==0x20) group.long (0x134+0x48)++0x03 line.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" bitfld.long 0x00 20. " AUTO_TIM_PARAMS_SEL ,Timing parameters selection" "User programmed,Automatically calculated" bitfld.long 0x00 16.--18. " MODE_FREQ ,Synchronous device programming timing mode" "20 MHz,33 MHz,50 MHz,66 MHz,83 MHz,100 MHz,?..." else hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif elif (((per.l(ad:0x02240000+0x58))&0x06)==0x00) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_NOR,Chip-Select Option Register - NOR Flash Mode" bitfld.long 0x00 31. " ADM_SHFT_MODE ,Address shift mode" "AD-MSB ADDR-LSB,AD-LSB ADDR-MSB" bitfld.long 0x00 28. " PGRD_EN ,Page read enable from NOR device" "Per-beat accesses,Single-page read" bitfld.long 0x00 24. " AVD_TGL_PGM_EN ,AVD toggle enable during burst program" "Disabled,Enabled" bitfld.long 0x00 23. " SYNC_RD_TYPE ,Synchronous NOR burst read enable" "Disabled,Enabled" newline bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." bitfld.long 0x00 5.--6. " NOR_MODE ,Type of the NOR device" "Simple async NOR,Intern latch based AVD NOR,?..." bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IP clk,40 IP clk,60 IP cls,80 IP clk,100 IP clk,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" elif (((per.l(ad:0x02240000+0x58))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130+0x48))&0x80000000)==0x00) group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 19. " RGETA ,GPCM external access termination mode for read access" "Abort mode,ACK mode" bitfld.long 0x00 18. " WGETA ,GPCM external access termination mode for write access" "Abort mode,ACK mode" bitfld.long 0x00 13.--17. " ADM_SHFT ,Address data multiplexing shift" "No shift,Shift by 1,Shift by 2,Shift by 3,Shift by 4,Shift by 5,Shift by 6,Shift by 7,Shift by 8,Shift by 9,Shift by 10,Shift by 11,Shift by 12,Shift by 13,Shift by 14,Shift by 15,Shift by 16,Shift by 17,Shift by 18,Shift by 19,Shift by 20,?..." newline bitfld.long 0x00 9.--11. " BURST_LEN ,GPCM burst length" "Non-burst mode,2,4,8,16,32,64,128" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" else group.long (0x130+0x48)++0x03 line.long 0x00 "CSOR6_GPCM,Chip-Select Option Register - GPCM" bitfld.long 0x00 31. " GPMODE ,GPCM mode of operation" "Normal GPCM,Generic ASIC" bitfld.long 0x00 30. " PAR ,Parity mode" "Odd,Even" bitfld.long 0x00 29. " PAR_EN ,Parity checking enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " GPTO ,GPCM timeout count" "256 cycles,512 cycles,1K cycles,K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" newline bitfld.long 0x00 20. " ABRT_RSP_EN ,Abort error response enable" "Disabled,Enabled" bitfld.long 0x00 7.--8. " GAPERRD ,Generic ASIC parity error indication delay" "1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk" bitfld.long 0x00 2.--4. " TRHZ ,Time for read enable high to output high impedance" "20 IFC,40 IFC,60 IFC,80 IFC,100 IFC,?..." bitfld.long 0x00 0. " BCTLD ,Buffer control disable" "No,Yes" endif hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" else hgroup.long (0x130+0x48)++0x03 hide.long 0x00 "CSOR6_X,Chip-Select Option Register" hgroup.long (0x134+0x48)++0x03 hide.long 0x00 "CSOR6_EXT,Extended Chip-Select Option Register - NAND Flash Mode" endif newline width 27. if (((per.l(ad:0x02240000+0x10))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x130))&0x60)==0x20) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NAND,Flash Timing Register 0 for Chip Select 0 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NAND,Flash Timing Register 1 for Chip-Select 0 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NAND,Flash Timing Register 2 for Chip Select 0 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_NAND,Flash Timing Register 3 for Chip Select 0 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x10))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x130))&0x60)==0x00) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 0 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 0 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 0 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 0 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x10))&0x06)==0x00) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_NOR,Flash Timing Register 0 for CS0 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_NOR,Flash Timing Register 1 for CS0 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_NOR,Flash Timing Register 2 for CS0 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_NOR,Flash Timing Register 3 for CS0 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x10))&0x06)==0x04) group.long (0x1C0+0x0)++0x03 line.long 0x00 "FTIM0_CS0_GPCM,Flash Timing Register 0 for CS0 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x0)++0x03 line.long 0x00 "FTIM1_CS0_GPCM,Flash Timing Register 1 for CS0 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x0)++0x03 line.long 0x00 "FTIM2_CS0_GPCM,Flash Timing Register 2 for CS0 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x0)++0x03 line.long 0x00 "FTIM3_CS0_GPCM,Flash Timing Register 3 for CS0 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x0)++0x03 hide.long 0x00 "FTIM0_CS0,Flash Timing Register 0 for CS0" hgroup.long (0x1C4+0x0)++0x03 hide.long 0x00 "FTIM1_CS0,Flash Timing Register 1 for CS0" hgroup.long (0x1C8+0x0)++0x03 hide.long 0x00 "FTIM2_CS0,Flash Timing Register 2 for CS0" hgroup.long (0x1CC+0x0)++0x03 hide.long 0x00 "FTIM3_CS0,Flash Timing Register 3 for CS0" endif if (((per.l(ad:0x02240000+0x1C))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x13C))&0x60)==0x20) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NAND,Flash Timing Register 0 for Chip Select 1 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NAND,Flash Timing Register 1 for Chip-Select 1 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NAND,Flash Timing Register 2 for Chip Select 1 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_NAND,Flash Timing Register 3 for Chip Select 1 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x1C))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x13C))&0x60)==0x00) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 1 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 1 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 1 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 1 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x1C))&0x06)==0x00) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_NOR,Flash Timing Register 0 for CS1 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_NOR,Flash Timing Register 1 for CS1 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_NOR,Flash Timing Register 2 for CS1 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_NOR,Flash Timing Register 3 for CS1 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x1C))&0x06)==0x04) group.long (0x1C0+0x30)++0x03 line.long 0x00 "FTIM0_CS1_GPCM,Flash Timing Register 0 for CS1 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x30)++0x03 line.long 0x00 "FTIM1_CS1_GPCM,Flash Timing Register 1 for CS1 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x30)++0x03 line.long 0x00 "FTIM2_CS1_GPCM,Flash Timing Register 2 for CS1 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x30)++0x03 line.long 0x00 "FTIM3_CS1_GPCM,Flash Timing Register 3 for CS1 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x30)++0x03 hide.long 0x00 "FTIM0_CS1,Flash Timing Register 0 for CS1" hgroup.long (0x1C4+0x30)++0x03 hide.long 0x00 "FTIM1_CS1,Flash Timing Register 1 for CS1" hgroup.long (0x1C8+0x30)++0x03 hide.long 0x00 "FTIM2_CS1,Flash Timing Register 2 for CS1" hgroup.long (0x1CC+0x30)++0x03 hide.long 0x00 "FTIM3_CS1,Flash Timing Register 3 for CS1" endif if (((per.l(ad:0x02240000+0x28))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x148))&0x60)==0x20) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NAND,Flash Timing Register 0 for Chip Select 2 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NAND,Flash Timing Register 1 for Chip-Select 2 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NAND,Flash Timing Register 2 for Chip Select 2 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_NAND,Flash Timing Register 3 for Chip Select 2 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x28))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x148))&0x60)==0x00) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 2 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 2 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 2 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 2 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x28))&0x06)==0x00) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_NOR,Flash Timing Register 0 for CS2 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_NOR,Flash Timing Register 1 for CS2 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_NOR,Flash Timing Register 2 for CS2 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_NOR,Flash Timing Register 3 for CS2 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x28))&0x06)==0x04) group.long (0x1C0+0x60)++0x03 line.long 0x00 "FTIM0_CS2_GPCM,Flash Timing Register 0 for CS2 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x60)++0x03 line.long 0x00 "FTIM1_CS2_GPCM,Flash Timing Register 1 for CS2 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x60)++0x03 line.long 0x00 "FTIM2_CS2_GPCM,Flash Timing Register 2 for CS2 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x60)++0x03 line.long 0x00 "FTIM3_CS2_GPCM,Flash Timing Register 3 for CS2 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x60)++0x03 hide.long 0x00 "FTIM0_CS2,Flash Timing Register 0 for CS2" hgroup.long (0x1C4+0x60)++0x03 hide.long 0x00 "FTIM1_CS2,Flash Timing Register 1 for CS2" hgroup.long (0x1C8+0x60)++0x03 hide.long 0x00 "FTIM2_CS2,Flash Timing Register 2 for CS2" hgroup.long (0x1CC+0x60)++0x03 hide.long 0x00 "FTIM3_CS2,Flash Timing Register 3 for CS2" endif if (((per.l(ad:0x02240000+0x34))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x154))&0x60)==0x20) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NAND,Flash Timing Register 0 for Chip Select 3 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NAND,Flash Timing Register 1 for Chip-Select 3 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NAND,Flash Timing Register 2 for Chip Select 3 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_NAND,Flash Timing Register 3 for Chip Select 3 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x34))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x154))&0x60)==0x00) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 3 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 3 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 3 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 3 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x34))&0x06)==0x00) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_NOR,Flash Timing Register 0 for CS3 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_NOR,Flash Timing Register 1 for CS3 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_NOR,Flash Timing Register 2 for CS3 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_NOR,Flash Timing Register 3 for CS3 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x34))&0x06)==0x04) group.long (0x1C0+0x90)++0x03 line.long 0x00 "FTIM0_CS3_GPCM,Flash Timing Register 0 for CS3 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x90)++0x03 line.long 0x00 "FTIM1_CS3_GPCM,Flash Timing Register 1 for CS3 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x90)++0x03 line.long 0x00 "FTIM2_CS3_GPCM,Flash Timing Register 2 for CS3 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x90)++0x03 line.long 0x00 "FTIM3_CS3_GPCM,Flash Timing Register 3 for CS3 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x90)++0x03 hide.long 0x00 "FTIM0_CS3,Flash Timing Register 0 for CS3" hgroup.long (0x1C4+0x90)++0x03 hide.long 0x00 "FTIM1_CS3,Flash Timing Register 1 for CS3" hgroup.long (0x1C8+0x90)++0x03 hide.long 0x00 "FTIM2_CS3,Flash Timing Register 2 for CS3" hgroup.long (0x1CC+0x90)++0x03 hide.long 0x00 "FTIM3_CS3,Flash Timing Register 3 for CS3" endif if (((per.l(ad:0x02240000+0x40))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x160))&0x60)==0x20) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NAND,Flash Timing Register 0 for Chip Select 4 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NAND,Flash Timing Register 1 for Chip-Select 4 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NAND,Flash Timing Register 2 for Chip Select 4 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_NAND,Flash Timing Register 3 for Chip Select 4 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x40))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x160))&0x60)==0x00) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 4 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 4 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 4 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 4 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x40))&0x06)==0x00) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_NOR,Flash Timing Register 0 for CS4 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_NOR,Flash Timing Register 1 for CS4 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_NOR,Flash Timing Register 2 for CS4 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_NOR,Flash Timing Register 3 for CS4 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x40))&0x06)==0x04) group.long (0x1C0+0xC0)++0x03 line.long 0x00 "FTIM0_CS4_GPCM,Flash Timing Register 0 for CS4 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xC0)++0x03 line.long 0x00 "FTIM1_CS4_GPCM,Flash Timing Register 1 for CS4 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0xC0)++0x03 line.long 0x00 "FTIM2_CS4_GPCM,Flash Timing Register 2 for CS4 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xC0)++0x03 line.long 0x00 "FTIM3_CS4_GPCM,Flash Timing Register 3 for CS4 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0xC0)++0x03 hide.long 0x00 "FTIM0_CS4,Flash Timing Register 0 for CS4" hgroup.long (0x1C4+0xC0)++0x03 hide.long 0x00 "FTIM1_CS4,Flash Timing Register 1 for CS4" hgroup.long (0x1C8+0xC0)++0x03 hide.long 0x00 "FTIM2_CS4,Flash Timing Register 2 for CS4" hgroup.long (0x1CC+0xC0)++0x03 hide.long 0x00 "FTIM3_CS4,Flash Timing Register 3 for CS4" endif if (((per.l(ad:0x02240000+0x4C))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x16C))&0x60)==0x20) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NAND,Flash Timing Register 0 for Chip Select 5 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NAND,Flash Timing Register 1 for Chip-Select 5 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NAND,Flash Timing Register 2 for Chip Select 5 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_NAND,Flash Timing Register 3 for Chip Select 5 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x4C))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x16C))&0x60)==0x00) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 5 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 5 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 5 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 5 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x4C))&0x06)==0x00) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_NOR,Flash Timing Register 0 for CS5 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_NOR,Flash Timing Register 1 for CS5 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_NOR,Flash Timing Register 2 for CS5 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_NOR,Flash Timing Register 3 for CS5 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x4C))&0x06)==0x04) group.long (0x1C0+0xF0)++0x03 line.long 0x00 "FTIM0_CS5_GPCM,Flash Timing Register 0 for CS5 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0xF0)++0x03 line.long 0x00 "FTIM1_CS5_GPCM,Flash Timing Register 1 for CS5 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0xF0)++0x03 line.long 0x00 "FTIM2_CS5_GPCM,Flash Timing Register 2 for CS5 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0xF0)++0x03 line.long 0x00 "FTIM3_CS5_GPCM,Flash Timing Register 3 for CS5 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0xF0)++0x03 hide.long 0x00 "FTIM0_CS5,Flash Timing Register 0 for CS5" hgroup.long (0x1C4+0xF0)++0x03 hide.long 0x00 "FTIM1_CS5,Flash Timing Register 1 for CS5" hgroup.long (0x1C8+0xF0)++0x03 hide.long 0x00 "FTIM2_CS5,Flash Timing Register 2 for CS5" hgroup.long (0x1CC+0xF0)++0x03 hide.long 0x00 "FTIM3_CS5,Flash Timing Register 3 for CS5" endif if (((per.l(ad:0x02240000+0x58))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x178))&0x60)==0x20) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NAND,Flash Timing Register 0 for Chip Select 6 - NAND Flash NVDDR" bitfld.long 0x00 24.--29. " TCS ,Chip Enable (CE) setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TCAD ,Command address data delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NAND,Flash Timing Register 1 for Chip-Select 6 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWB ,Clock Rising Edge to SR[6] (R/B) low" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWRCK ,W/R low to data output cycle" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NAND,Flash Timing Register 2 for Chip Select 6 - NAND Flash NVDDR Mode" hexmask.long.byte 0x00 24.--31. 1. " TCKWR ,Data output end to W/R high" hexmask.long.byte 0x00 16.--23. 0x01 " TWHR ,Command/address/data input cycle to data output cycle" hexmask.long.byte 0x00 8.--15. 0x01 " TRHW ,Data output cycle to command/address/data input cycle" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_NAND,Flash Timing Register 3 for Chip Select 6 - NAND Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x58))&0x06)==0x02)&&(((per.l(ad:0x02240000+0x178))&0x60)==0x00) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NAND_ASYNC_MODE,Flash Timing Register 0 for Chip Select 6 - NAND Flash Asynchronous Mode" bitfld.long 0x00 25.--30. " TCCST ,CLE assertion time after CS / CLE/ALE assertion time after prev. CLE/ALE" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--23. 1. " TWP ,Write enable (WE) pulse width" bitfld.long 0x00 8.--13. " TWCHT ,WE to command hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TWH ,WE high hold time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NAND_ASYNC_MODE,Flash Timing Register 1 for Chip Select 6 - Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 0x01 " TADLE ,Effective address to data loading time" hexmask.long.byte 0x00 16.--23. 1. " TWBE ,WE high (after TWH time) to ready busy (RB_B) low time" bitfld.long 0x00 8.--13. " TRR ,Ready busy high to read enable (RE) low time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TRP ,RE pulse width" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NAND_ASYNC_MODE,Flash Timing Register 2 for Chip Select 6 - NAND Flash Asynchronous Mode" hexmask.long.word 0x00 21.--28. 1. " TRAD ,Flash read access delay" bitfld.long 0x00 11.--16. " TREH ,RE_B high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWHRE ,WE_B high to RE_B low effective" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_NAND_ASYNC_MODE,Flash Timing Register 3 for Chip Select 6 - NAND Flash Asynchronous Mode" hexmask.long.byte 0x00 24.--31. 1. " TWW ,Write protect WP_B transition time" elif (((per.l(ad:0x02240000+0x58))&0x06)==0x00) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_NOR,Flash Timing Register 0 for CS6 - NOR Flash Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TAVDS ,Delay between CS assertion to AVD/ALE assertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,Latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_NOR,Flash Timing Register 1 for CS6 - NOR Flash Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" hexmask.long.byte 0x00 8.--15. 1. " TRAD_NOR ,NOR flash read access delay" hexmask.long.byte 0x00 0.--7. 1. " TSEQRAD_NOR ,NOR flash sequential read access delay" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_NOR,Flash Timing Register 2 for CS6 - NOR Flash Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--15. " TWPH ,Write enable pulse high time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_NOR,Flash Timing Register 3 for CS6 - NOR Flash Mode" bitfld.long 0x00 24.--29. " TCHVL ,Rising edge of IFC_CLK to CS assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " TAVDP ,AVD_B assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " TVHAX ,Address hold time from AVD_B deassertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TIACC ,Initial data access latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.l(ad:0x02240000+0x58))&0x06)==0x04) group.long (0x1C0+0x120)++0x03 line.long 0x00 "FTIM0_CS6_GPCM,Flash Timing Register 0 for CS6 - Normal GPCM Mode" bitfld.long 0x00 28.--31. " TACSE ,Address phase end to chip enable assertion time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--21. " TEADC ,External latch address delay cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TEAHC ,External latch address hold cycles" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C4+0x120)++0x03 line.long 0x00 "FTIM1_CS6_GPCM,Flash Timing Register 1 for CS6 - Normal GPCM Mode" hexmask.long.byte 0x00 24.--31. 1. " TACO ,CS assertion to output enable (OE) assertion setup time" bitfld.long 0x00 8.--13. " TRAD ,GPCM read access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1C8+0x120)++0x03 line.long 0x00 "FTIM2_CS6_GPCM,Flash Timing Register 2 for CS6 - Normal GPCM Mode" bitfld.long 0x00 24.--27. " TCS ,Chip-select assertion to WE assertion setup time" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18.--21. " TCH ,Chip-select hold time with respect to WE deassertion" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " TWP ,Write enable pulse width" group.long (0x1CC+0x120)++0x03 line.long 0x00 "FTIM3_CS6_GPCM,Flash Timing Register 3 for CS6 - Normal GPCM Mode" bitfld.long 0x00 26.--31. " TAAD ,GPCM address access delay" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long (0x1C0+0x120)++0x03 hide.long 0x00 "FTIM0_CS6,Flash Timing Register 0 for CS6" hgroup.long (0x1C4+0x120)++0x03 hide.long 0x00 "FTIM1_CS6,Flash Timing Register 1 for CS6" hgroup.long (0x1C8+0x120)++0x03 hide.long 0x00 "FTIM2_CS6,Flash Timing Register 2 for CS6" hgroup.long (0x1CC+0x120)++0x03 hide.long 0x00 "FTIM3_CS6,Flash Timing Register 3 for CS6" endif newline width 20. rgroup.long 0x400++0x03 line.long 0x00 "RB_STAT,Ready Busy Status for each Chip Select" bitfld.long 0x00 31. " RB0 ,Ready busy input from CS0" "Busy,Ready" bitfld.long 0x00 30. " RB1 ,Ready busy input from CS1" "Busy,Ready" bitfld.long 0x00 29. " RB2 ,Ready busy input from CS2" "Busy,Ready" bitfld.long 0x00 28. " RB3 ,Ready busy input from CS3" "Busy,Ready" newline bitfld.long 0x00 27. " RB4 ,Ready busy input from CS4" "Busy,Ready" bitfld.long 0x00 26. " RB5 ,Ready busy input from CS5" "Busy,Ready" bitfld.long 0x00 25. " RB6 ,Ready busy input from CS6" "Busy,Ready" group.long 0x404++0x07 line.long 0x00 "RB_MAP,Ready Busy Map Register" bitfld.long 0x00 28.--30. " CS0_RB ,Ready/Busy_B mapping to chip-select0" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 24.--26. " CS1_RB ,Ready/Busy_B mapping to chip-select1" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 20.--22. " CS2_RB ,Ready/Busy_B mapping to chip-select2" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 16.--18. " CS3_RB ,Ready/Busy_B mapping to chip-select3" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" newline bitfld.long 0x00 12.--14. " CS4_RB ,Ready/Busy_B mapping to chip-select4" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 8.--10. " CS5_RB ,Ready/Busy_B mapping to chip-select5" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 4.--6. " CS6_RB ,Ready/Busy_B mapping to chip-select6" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" bitfld.long 0x00 0.--2. " CS7_RB ,Ready/Busy_B mapping to chip-select7" "Ready/Busy-0,Ready/Busy-1,Ready/Busy-2,Ready/Busy-3,Ready/Busy-4,Ready/Busy-5,Ready/Busy-6,Ready/Busy-7" line.long 0x04 "WP_MAP,Write Protect Map Register" rbitfld.long 0x04 28.--30. " CS0_WP ,Write Protect_B mapping to chip-select0" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 24.--26. " CS1_WP ,Write Protect_B mapping to chip-select1" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 20.--22. " CS2_WP ,Write Protect_B mapping to chip-select2" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 16.--18. " CS3_WP ,Write Protect_B mapping to chip-select3" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" newline bitfld.long 0x04 12.--14. " CS4_WP ,Write Protect_B mapping to chip-select4" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 8.--10. " CS5_WP ,Write Protect_B mapping to chip-select5" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 4.--6. " CS6_WP ,Write Protect_B mapping to chip-select6" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" bitfld.long 0x04 0.--2. " CS7_WP ,Write Protect_B mapping to chip-select7" "WP-0,WP-1,WP-2,WP-3,WP-4,WP-5,WP-6,WP-7" group.long 0x40C++0x03 line.long 0x00 "GCR,General Control Register" bitfld.long 0x00 31. " SOFT_RST_ALL ,Software reset all" "No reset,Reset" bitfld.long 0x00 11.--15. " TBCTL_TRN_TIME ,Turnaround time of external buffer in terms of number of IFC module input clock cycles" ",1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk,5 IFC clk,6 IFC clk,7 IFC clk,8 IFC clk,9 IFC clk,10 IFC clk,11 IFC clk,12 IFC clk,13 IFC clk,14 IFC clk,15 IFC clk,16 IFC clk,17 IFC clk,18 IFC clk,19 IFC clk,20 IFC clk,21 IFC clk,22 IFC clk,23 IFC clk,24 IFC clk,25 IFC clk,26 IFC clk,27 IFC clk,28 IFC clk,29 IFC clk,30 IFC clk,31 IFC clk" group.long 0x418++0x03 line.long 0x00 "CM_EVTER_STAT,Common Event and Error Status Register" eventfld.long 0x00 31. " CSER ,Chip-select error" "No error,Error" group.long 0x424++0x03 line.long 0x00 "CM_EVTER_EN,Common Event and Error Enable Register" bitfld.long 0x00 31. " CSEREN ,Chip-select error checking enable" "Disabled,Enabled" group.long 0x430++0x03 line.long 0x00 "CM_EVTER_INTR_EN,Common Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " CSERIREN ,Chip-select error interrupt enable" "Disabled,Enabled" rgroup.long 0x43C++0x07 line.long 0x00 "CM_ERATTR0,Common Transfer Error Attributes Register 0" bitfld.long 0x00 31. " ERTYP ,Transaction type of the error" "Write,Read" hexmask.long.byte 0x00 20.--27. 1. " ERAID ,ID of the error transaction" hexmask.long.byte 0x00 8.--15. 1. " ERSRCID ,Source ID of the error transaction" line.long 0x04 "CM_ERATTR1,Common Transfer Error Attributes Register 1" group.long 0x44C++0x03 line.long 0x00 "CCR,Clock Control Register" bitfld.long 0x00 24.--27. " CLKDIV ,Clock division ratio" ",/2,,/4,,,,/8,?..." bitfld.long 0x00 16.--19. " CLK_DLY ,IFC clock delay" "No delay,1 IFC clk,2 IFC clk,3 IFC clk,4 IFC clk,5 IFC clk,6 IFC clk,7 IFC clk,8 IFC clk,9 IFC clk,10 IFC clk,11 IFC clk,12 IFC clk,13 IFC clk,14 IFC clk,15 IFC clk" bitfld.long 0x00 15. " INV_CLK_EN ,IFC clock inversion" "Not inverted,Inverted" rgroup.long 0x450++0x03 line.long 0x00 "CSR,Clock Status Register" bitfld.long 0x00 31. " CLK_STAT ,Clock status" "Unstable,Stable" if (((per.l(ad:0x02240000+0x130))&0x60)==0x20)||(((per.l(ad:0x02240000+0x13C))&0x60)==0x20)||(((per.l(ad:0x02240000+0x148))&0x60)==0x20)||(((per.l(ad:0x02240000+0x154))&0x60)==0x20)||(((per.l(ad:0x02240000+0x160))&0x60)==0x20)||(((per.l(ad:0x02240000+0x16C))&0x60)==0x20)||(((per.l(ad:0x02240000+0x178))&0x60)==0x20) group.long 0x454++0x03 line.long 0x00 "DDR_CCR,DDR Clock Control Register" bitfld.long 0x00 29. " GLOBAL_DDR_CLK_EN ,Switches off the IFC DDR clock" "Disabled,Enabled" bitfld.long 0x00 28. " PGM_DDR_CLK_STOP ,DDR clock stop in case of program operation" "Enabled,Stopped" bitfld.long 0x00 23.--26. " DDR_LOW_CLKDIV ,Clock division ratio" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" bitfld.long 0x00 20. " TDQSS ,Data input to first DQS transition delay" "0.75 DDR_CLOCK,1.25 DDR_CLOCK" else group.long 0x454++0x03 line.long 0x00 "DDR_CCR,DDR Clock Control Register" bitfld.long 0x00 29. " GLOBAL_DDR_CLK_EN ,Switches off the IFC DDR clock" "Disabled,Enabled" bitfld.long 0x00 23.--26. " DDR_LOW_CLKDIV ,Clock division ratio" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32" endif if (((per.l(ad:0x02240000+0x130))&0x60)==0x20) if (((per.l(ad:0x02240000+0x1000))&0xC00000)==0x400000) group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 27. " SINGLE_DATA_MODE ,Single data mode enable" "Disabled,Enabled" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." newline bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,?..." hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" else group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 27. " SINGLE_DATA_MODE ,Single data mode enable" "Disabled,Enabled" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." newline bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" endif else if (((per.l(ad:0x02240000+0x1000))&0xC00000)==0x400000) group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,?..." newline hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" else group.long 0x1000++0x03 line.long 0x00 "NCFGR,NAND Configuration Register" bitfld.long 0x00 31. " BOOT ,NAND flash auto-boot load mode" "Normal mode,Boot mode" bitfld.long 0x00 29. " SRAM_INIT_EN ,SRAM initialization enable" "Not initialized,Initialized" bitfld.long 0x00 22.--23. " ADDR_MODE ,Addressing mode" "All per iteration,One per iteration,?..." bitfld.long 0x00 12.--15. " NUM_LOOP ,Number of loop iterations of FIR sequences for multi page operations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline hexmask.long.byte 0x00 0.--7. 1. " NUM_WAIT ,Number of wait cycles" endif endif newline group.long 0x1014++0x07 line.long 0x00 "NAND_FCR0,NAND Flash Command Register 0" hexmask.long.byte 0x00 24.--31. 1. " CMD0 ,General purpose FCM flash command byte 0" hexmask.long.byte 0x00 16.--23. 1. " CMD1 ,General purpose FCM flash command byte 1" hexmask.long.byte 0x00 8.--15. 1. " CMD2 ,General purpose FCM flash command byte 2" hexmask.long.byte 0x00 0.--7. 1. " CMD3 ,General purpose FCM flash command byte 3" line.long 0x04 "NAND_FCR1,NAND Flash Command Register 1" hexmask.long.byte 0x04 24.--31. 1. " CMD4 ,General purpose FCM flash command byte 4" hexmask.long.byte 0x04 16.--23. 1. " CMD5 ,General purpose FCM flash command byte 5" hexmask.long.byte 0x04 8.--15. 1. " CMD6 ,General purpose FCM flash command byte 6" hexmask.long.byte 0x04 0.--7. 1. " CMD7 ,General purpose FCM flash command byte 7" group.long ((0x103C+0x0))++0x03 line.long 0x00 "ROW0,Flash Row Address Register 0" if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) if (((per.l(ad:0x02240000+0x1108))&0x3FFF)==0x00) if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address 4 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address 2 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address 4 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address 2 KB Large-Page Device Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long ((0x1044+0x0))++0x03 line.long 0x00 "COL0,Flash COL Address Register 0" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long ((0x103C+0x10))++0x03 line.long 0x00 "ROW1,Flash Row Address Register 1" if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) if (((per.l(ad:0x02240000+0x1108))&0x3FFF)==0x00) if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address 4 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address 2 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address 4 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address 2 KB Large-Page Device Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long ((0x1044+0x10))++0x03 line.long 0x00 "COL1,Flash COL Address Register 1" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long ((0x103C+0x20))++0x03 line.long 0x00 "ROW2,Flash Row Address Register 2" if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) if (((per.l(ad:0x02240000+0x1108))&0x3FFF)==0x00) if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address 4 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address 2 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address 4 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address 2 KB Large-Page Device Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long ((0x1044+0x20))++0x03 line.long 0x00 "COL2,Flash COL Address Register 2" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long ((0x103C+0x30))++0x03 line.long 0x00 "ROW3,Flash Row Address Register 3" if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) if (((per.l(ad:0x02240000+0x1108))&0x3FFF)==0x00) if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address 4 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address 2 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Main region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif else if (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address 4 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address 2 KB Large-Page Device Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" else group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" bitfld.long 0x00 31. " MS ,Main/spare region locator" "Main region,Spare region" hexmask.long.word 0x00 0.--12. 0x01 " CA ,Column address" endif endif else group.long ((0x1044+0x30))++0x03 line.long 0x00 "COL3,Flash COL Address Register 3" hexmask.long.word 0x00 19.--31. 0x08 " CA ,Column address" bitfld.long 0x00 0. " MS ,Main/spare region locator" "Main region,Spare region" endif group.long 0x1108++0x03 line.long 0x00 "NAND_BC,Flash Byte Count Register for NAND Flash" hexmask.long.word 0x00 0.--13. 1. " BC ,Count of bytes transferred during RBCD or WBCD opcode" group.long 0x1110++0x0B line.long 0x00 "NAND_FIR0,NAND Flash Instruction Register 0" bitfld.long 0x00 26.--31. " OP0 ,Opcode 0" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 20.--25. " OP1 ,Opcode 1" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 14.--19. " OP2 ,Opcode 2" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x00 8.--13. " OP3 ,Opcode 3" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x00 2.--7. " OP4 ,Opcode 4" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." line.long 0x04 "NAND_FIR1,NAND Flash Instruction Register 1" bitfld.long 0x04 26.--31. " OP5 ,Opcode 5" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 20.--25. " OP6 ,Opcode 6" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 14.--19. " OP7 ,Opcode 7" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x04 8.--13. " OP8 ,Opcode 8" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x04 2.--7. " OP9 ,Opcode 9" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." line.long 0x08 "NAND_FIR2,NAND Flash Instruction Register 2" bitfld.long 0x08 26.--31. " OP10 ,Opcode 10" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 20.--25. " OP11 ,Opcode 11" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 14.--19. " OP12 ,Opcode 12" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." bitfld.long 0x08 8.--13. " OP13 ,Opcode 13" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." newline bitfld.long 0x08 2.--7. " OP14 ,Opcode 14" "NOOP,CA0,CA1,CA2,CA3,RA0,RA1,RA2,RA3,CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CW0,CW1,CW2,CW3,CW4,CW5,CW6,CW7,WBCD,RBCD,BTRD,RDSTAT,NWAIT,WFR,SBRD,UA,RB,?..." group.long 0x115C++0x03 line.long 0x00 "NAND_CSEL,NAND Chip-Select Register" bitfld.long 0x00 26.--28. " CSEL ,Chip-Select for NAND flash operation" "CS 0,CS 1,CS 2,CS 3,CS 4,CS 5,CS 6,CS 7" group.long 0x1164++0x03 line.long 0x00 "NANDSEQ_STRT,NAND Operation Sequence Start" bitfld.long 0x00 31. " NAND_FIR_STRT ,NAND flash operation start" "No effect,Start" bitfld.long 0x00 23. " AUTO_ERS ,Automatic erase start" "No effect,Start" bitfld.long 0x00 20. " AUTO_PGM ,Automatic program start" "No effect,Start" bitfld.long 0x00 17. " AUTO_CPB ,Automatic copyback start" "No effect,Start" newline bitfld.long 0x00 14. " AUTO_RD ,Automatic read operation start" "No effect,Start" bitfld.long 0x00 11. " AUTO_STAT_RD ,Automatic status read start" "No effect,Start" group.long 0x116C++0x03 line.long 0x00 "NAND_EVTER_STAT,NAND Event and Error Status Register" eventfld.long 0x00 31. " OPC ,NAND flash operation complete event" "Not completed,Completed" eventfld.long 0x00 27. " FTOER ,Flash timeout error" "No error,Error" eventfld.long 0x00 26. " WPER ,Write protect error" "No error,Error" eventfld.long 0x00 25. " ECCER ,ECC error" "No error,Error" newline eventfld.long 0x00 15. " RCW_DN ,Page read from dev and written to SRAM buffer during RCW load" "Not occurred,Occurred" eventfld.long 0x00 14. " BOOT_DN ,Page read from dev and written to SRAM buffer during BOOT load" "Not occurred,Occurred" eventfld.long 0x00 11. " BBI_SRCH_SEL ,Bad block indicator search select" "Page 0 & 1,Page 0 & last" newline if (((per.l(ad:0x02240000+0x10))&0x06)==0x02) if (((per.l(ad:0x02240000+0x130))&0x180000)==0x180000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" hexmask.long.word 0x00 16.--31. 1. " SEC_DONE ,Single page of 8KB done" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x100000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" hexmask.long.byte 0x00 24.--31. 1. " SEC_DONE[8:15] ,Page 1 done" hexmask.long.byte 0x00 16.--23. 1. " [0:7] ,Page 0 done" elif (((per.l(ad:0x02240000+0x130))&0x180000)==0x80000) group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" bitfld.long 0x00 28.--31. " SEC_DONE[12:15] ,Page 3 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " [8:11] ,Page 2 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " [4:7] ,Page 1 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " [0:3] ,Page 0 done" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x1174++0x03 line.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" eventfld.long 0x00 31. " SEC_DONE15 ,Page 15 done" "Not done,Done" eventfld.long 0x00 30. " SEC_DONE14 ,Page 14 done" "Not done,Done" eventfld.long 0x00 29. " SEC_DONE13 ,Page 13 done" "Not done,Done" eventfld.long 0x00 28. " SEC_DONE12 ,Page 12 done" "Not done,Done" newline eventfld.long 0x00 27. " SEC_DONE11 ,Page 11 done" "Not done,Done" eventfld.long 0x00 26. " SEC_DONE10 ,Page 10 done" "Not done,Done" eventfld.long 0x00 25. " SEC_DONE9 ,Page 9 done" "Not done,Done" eventfld.long 0x00 24. " SEC_DONE8 ,Page 8 done" "Not done,Done" newline eventfld.long 0x00 23. " SEC_DONE7 ,Page 7 done" "Not done,Done" eventfld.long 0x00 22. " SEC_DONE6 ,Page 6 done" "Not done,Done" eventfld.long 0x00 21. " SEC_DONE5 ,Page 5 done" "Not done,Done" eventfld.long 0x00 20. " SEC_DONE4 ,Page 4 done" "Not done,Done" newline eventfld.long 0x00 19. " SEC_DONE3 ,Page 3 done" "Not done,Done" eventfld.long 0x00 18. " SEC_DONE2 ,Page 2 done" "Not done,Done" eventfld.long 0x00 17. " SEC_DONE1 ,Page 1 done" "Not done,Done" eventfld.long 0x00 16. " SEC_DONE0 ,Page 0 done" "Not done,Done" endif else hgroup.long 0x1174++0x03 hide.long 0x00 "PGRDCMPL_EVT_STAT,NAND Page Read Completion Event Status Register" endif group.long 0x1180++0x03 line.long 0x00 "NAND_EVTER_EN,NAND Event and Error Enable Register" bitfld.long 0x00 31. " OPCEN ,NAND flash operation complete event enable" "Disabled,Enabled" bitfld.long 0x00 29. " PGRDCMPLEN ,NAND flash page read completion event enable" "Disabled,Enabled" bitfld.long 0x00 27. " FTOEREN ,Flash time out error enable (for R/B timeout and DQS timeout)" "Disabled,Enabled" bitfld.long 0x00 26. " WPEREN ,Write protect error checking enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " ECCEREN ,ECC error logging enable" "Disabled,Enabled" group.long 0x118C++0x03 line.long 0x00 "NAND_EVTER_INTR_EN,NAND Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " OPCIREN ,NAND flash operation complete event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " PGRDCMPLIREN ,Page read completion event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FTOERIREN ,Flash timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " WPERIREN ,Write protect error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " ECCERIREN ,ECC error interrupt enable" "Disabled,Enabled" rgroup.long 0x1198++0x07 line.long 0x00 "NAND_ERATTR0,NAND Transfer Error Attributes Register 0" bitfld.long 0x00 26.--28. " ERCS ,Chip-select corresponding to NAND error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,?..." bitfld.long 0x00 19. " ERTTYPE ,Transaction type of NAND error" "Write,Read" line.long 0x04 "NAND_ERATTR1,NAND Transfer Error Attributes Register 1" rgroup.long 0x11E0++0x03 line.long 0x00 "NAND_FSR,NAND Flash Status Register" hexmask.long.byte 0x00 24.--31. 1. " RS0 ,First byte of data read from read status operation" hexmask.long.byte 0x00 16.--23. 1. " RS1 ,Second byte of data read from read status operation" newline group.long 0x11F0++0x07 line.long 0x00 "ECCSTAT2,ECC Status And Result Of Flash Operation Register 2" bitfld.long 0x00 24.--29. " NUMER8 ,Number of ECC errors on sector #8 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " NUMER9 ,Number of ECC errors on sector #9 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " NUMER10 ,Number of ECC errors on sector #10 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " NUMER11 ,Number of ECC errors on sector #11 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "ECCSTAT3,ECC Status And Result Of Flash Operation Register 3" bitfld.long 0x04 24.--29. " NUMER12 ,Number of ECC errors on sector #12 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 16.--21. " NUMER13 ,Number of ECC errors on sector #13 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--13. " NUMER14 ,Number of ECC errors on sector #14 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 0.--5. " NUMER15 ,Number of ECC errors on sector #15 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long (0x1000+0x1F8)++0x03 line.long 0x00 "ECCSTAT4,ECC Status And Result Of Flash Operation Register 4" bitfld.long 0x00 24.--27. " NUMER16 ,Number of ECC errors on sector #16 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NUMER17 ,Number of ECC errors on sector #17 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUMER18 ,Number of ECC errors on sector #18 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUMER19 ,Number of ECC errors on sector #19 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1000+0x1FC)++0x03 line.long 0x00 "ECCSTAT5,ECC Status And Result Of Flash Operation Register 5" bitfld.long 0x00 24.--27. " NUMER20 ,Number of ECC errors on sector #20 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NUMER21 ,Number of ECC errors on sector #21 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUMER22 ,Number of ECC errors on sector #22 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUMER23 ,Number of ECC errors on sector #23 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1000+0x200)++0x03 line.long 0x00 "ECCSTAT6,ECC Status And Result Of Flash Operation Register 6" bitfld.long 0x00 24.--27. " NUMER24 ,Number of ECC errors on sector #24 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NUMER25 ,Number of ECC errors on sector #25 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUMER26 ,Number of ECC errors on sector #26 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUMER27 ,Number of ECC errors on sector #27 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1000+0x204)++0x03 line.long 0x00 "ECCSTAT7,ECC Status And Result Of Flash Operation Register 7" bitfld.long 0x00 24.--27. " NUMER28 ,Number of ECC errors on sector #28 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NUMER29 ,Number of ECC errors on sector #29 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUMER30 ,Number of ECC errors on sector #30 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " NUMER31 ,Number of ECC errors on sector #31 of SRAM buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline group.long 0x1278++0x03 line.long 0x00 "NANDCR,NAND Control Register" bitfld.long 0x00 25.--28. " FTOCNT ,Flash timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" wgroup.long 0x1284++0x03 line.long 0x00 "NAND_AUTOBOOT_TRGR,NAND Autoboot Trigger Register" bitfld.long 0x00 31. " RCW_LD ,RCW load" "No effect,Load" bitfld.long 0x00 29. " BOOT_LD ,BOOT load" "No effect,Load" rgroup.long 0x128C++0x03 line.long 0x00 "NAND_MDR,NAND Flash Memory Data Register" hexmask.long.byte 0x00 24.--31. 1. " RDATA0 ,1st read data byte when opcode SBRD is used for read" hexmask.long.byte 0x00 16.--23. 1. " RDATA1 ,Second read data byte when opcode SBRD is used for read" group.long 0x1300++0x07 line.long 0x00 "NAND_DLL_LOW_CFG0,Nand DLL Low Config 0 Register" bitfld.long 0x00 31. " DLL_ENABLE ,This bit enables the DLL" "Disabled,Enabled" bitfld.long 0x00 30. " DLL_RESET ,This bit resets the DLL" "No reset,Reset" line.long 0x04 "NAND_DLL_LOW_CFG1,Nand DLL Low Config 1 Register" bitfld.long 0x04 31. " DLL_PD_PULSE_STRETCH_SEL ,Select between 2 or 4 delays cells for pulse width detection logic" "4 cells,2 cells" bitfld.long 0x04 16.--19. " DLL_REF_UPDATE_INT ,Overrides the default update interval of the reference delay line" "2 REF clk cycles,3 REF clk cycles,4 REF clk cycles,5 REF clk cycles,6 REF clk cycles,7 REF clk cycles,8 REF clk cycles,9 REF clk cycles,10 REF clk cycles,11 REF clk cycles,12 REF clk cycles,13 REF clk cycles,14 REF clk cycles,15 REF clk cycles,16 REF clk cycles,17 REF clk cycles" hexmask.long.byte 0x04 0.--7. 1. " DLL_SLV_UPDATE_INT ,Overrides the default update interval of the slave delay line" rgroup.long (0x130C)++0x03 line.long 0x00 "NAND_DLL_LOW_STAT,NAND DLL Low Status Register" bitfld.long 0x00 31. " DLL_STS_REF_LOCK ,DLL reference delay line lock status" "Not locked,Locked" bitfld.long 0x00 27. " DLL_STS_SLV_LOCK ,DLL slave delay chain lock status" "Not locked,Locked" newline hexmask.long.byte 0x00 12.--19. 1. " DLL_STS_REF_SEL ,Status of selected tap for reference delay line" hexmask.long.byte 0x00 0.--7. 1. " DLL_STS_SLV_SEL ,Status of selected tap for slave delay line" group.long 0x1400++0x03 line.long 0x00 "NOR_EVTER_STAT,NOR Event and Error Status Register" eventfld.long 0x00 31. " OPC_NOR ,NOR command sequence operation complete event indication" "Not complete,Complete" eventfld.long 0x00 26. " WPER ,Write protect error" "No error,Error" eventfld.long 0x00 24. " STOER ,Command sequence timeout error" "No error,Error" group.long 0x140C++0x03 line.long 0x00 "NOR_EVTER_EN,NOR Event and Error Enable Register" bitfld.long 0x00 31. " OPCEN_NOR ,NOR command sequence operation complete event enable" "Disabled,Enabled" bitfld.long 0x00 26. " WPEREN ,Write protect error checking enable" "Disabled,Enabled" bitfld.long 0x00 24. " STOEREN ,Command sequence timeout error enable" "Disabled,Enabled" group.long 0x1418++0x03 line.long 0x00 "NOR_EVTER_INTR_EN,NOR Event and Error Interrupt Enable Register" bitfld.long 0x00 31. " OPCIREN_NOR ,NOR command sequence operation complete event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " WPERIREN ,Write protect error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " STOERIREN ,NOR command sequence timeout error interrupt enable" "Disabled,Enabled" rgroup.long 0x1424++0x0B line.long 0x00 "NOR_ERATTR0,NOR Transfer Error Attributes Register 0" hexmask.long.byte 0x00 24.--31. 1. " ERSRCID ,SRCID corresponding to error transaction" hexmask.long.byte 0x00 12.--19. 1. " ERAID ,ID of the error transaction" bitfld.long 0x00 6.--8. " ERCS ,Chip-select corresponding to NOR error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" bitfld.long 0x00 0. " ERTYPE ,Type of the transaction" "Write,Read" line.long 0x04 "NOR_ERATTR1,NOR Transfer Error Attribute Register 1" line.long 0x08 "NOR_ERATTR2,NOR Transfer Error Attribute Register 2" bitfld.long 0x08 16.--19. " ER_NUM_PHASE_EXP ,Number of phase expected in command sequence which timed-out by system side" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x08 8.--11. " ER_NUM_PHASE_PER ,Number of command sequence phases performed before timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1440++0x03 line.long 0x00 "NORCR,NOR Control Register" bitfld.long 0x00 24.--27. " NUM_PHASE ,Number of address/data phases on device for which chip-select has to be asserted" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 16.--19. " STOCNT ,Sequence timeout count" "256 cycles,512 cycles,1K cycles,2K cycles,4K cycles,8K cycles,16K cycles,32K cycles,64K cycles,128K cycles,256K cycles,512K cycles,1M cycles,2M cycles,4M cycles,8M cycles" group.long 0x1800++0x03 line.long 0x00 "GPCM_EVTER_STAT,GPCM Event and Error Status Register" eventfld.long 0x00 26. " TOER ,Timeout error" "No error,Error" eventfld.long 0x00 24. " PER ,Parity error" "No error,Error" eventfld.long 0x00 22. " ABER ,Abort error" "No error,Error" group.long 0x180C++0x03 line.long 0x00 "GPCM_EVTER_EN,GPCM Event and Error Enable Register" bitfld.long 0x00 26. " TOEREN ,Timeout error checking enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEREN ,Parity error checking enable" "Disabled,Enabled" bitfld.long 0x00 22. " ABEREN ,Abort error checking enable" "Disabled,Enabled" group.long 0x1818++0x03 line.long 0x00 "GPCM_EVTER_INTR_EN,GPCM Event and Error Interrupt Enable Register" bitfld.long 0x00 26. " TOERIREN ,Timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PERIREN ,Parity error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " ABERIREN ,Abort error interrupt enable" "Disabled,Enabled" rgroup.long 0x1824++0x07 line.long 0x00 "GPCM_ERATTR0,GPCM Transfer Error Attributes Register 0" hexmask.long.byte 0x00 24.--31. 1. " ERSRCID ,SRCID corresponding to error transaction" hexmask.long.byte 0x00 12.--19. 1. " ERAID ,ID of the error transaction" bitfld.long 0x00 6.--8. " ERCS ,Chip-select corresponding to GPCM error" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,?..." bitfld.long 0x00 0. " ERTYPE ,Type of the transaction" "Write,Read" line.long 0x04 "GPCM_ERATTR1,GPCM Transfer Error Attributes Register 1" if (((per.l(ad:0x02240000+0x10))&0x06)==0x04) if (((per.l(ad:0x02240000+0x130))&0x80000000)==0x80000000) rgroup.long (0x182C)++0x03 line.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" bitfld.long 0x00 10.--11. " PERR_BEAT ,Gives information on which beat of address/data parity error is observed" "0,1,2,3" bitfld.long 0x00 7. " PERR_BYTE0 ,Parity error on byte 0" "No error,Error" bitfld.long 0x00 6. " PERR_BYTE1 ,Parity error on byte 1" "No error,Error" bitfld.long 0x00 5. " PERR_BYTE2 ,Parity error on byte 2" "No error,Error" newline bitfld.long 0x00 4. " PERR_BYTE3 ,Parity error on byte 3" "No error,Error" bitfld.long 0x00 0. " PERR_AD ,Parity error reported in address or data phase" "Address,Data" else rgroup.long 0x182C++0x03 line.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" bitfld.long 0x00 7. " PERR_BYTE0 ,Parity error on byte 0" "No error,Error" bitfld.long 0x00 6. " PERR_BYTE1 ,Parity error on byte 1" "No error,Error" bitfld.long 0x00 5. " PERR_BYTE2 ,Parity error on byte 2" "No error,Error" bitfld.long 0x00 4. " PERR_BYTE3 ,Parity error on byte 3" "No error,Error" endif else hgroup.long 0x182C++0x03 hide.long 0x00 "GPCM_ERATTR2,GPCM Transfer Error Attributes Register 2" endif rgroup.long 0x1830++0x03 line.long 0x00 "GPCM_STAT,GPCM Status Register" bitfld.long 0x00 0. " GPCM_BSY ,GPCM busy" "Idle,Busy" width 0x0B tree.end endif sif cpuis("LS1012*") tree.open "I2C (Inter-Integrated Circuit)" tree "I2C_1" base ad:0x2180000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C1_IBAD,I2C Bus Address Register" hexmask.byte 0x00 0.--6. 0x01 " ADR ,Slave address" if (((per.b(ad:0x2180000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2180000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2180000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C1_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" bitfld.byte 0x00 6. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RSTA ,Repeat start generation" "No effect,Generate" bitfld.byte 0x00 4. " NOACK ,Data acknowledge disable" "No,Yes" newline bitfld.byte 0x00 3. " TXRX ,Transmit/receive mode select" "Receive,Transmit" bitfld.byte 0x00 2. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 1. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " MDIS ,Module disable" "No,Yes" if (((per.b(ad:0x2180000+0x02))&0x05)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " RXAK ,Received acknowledge" "Received,Not received" eventfld.byte 0x00 6. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 5. " SRW ,Slave read/write" "Slave Rx,Slave Tx" newline eventfld.byte 0x00 3. " IBAL ,Arbitration lost" "Not lost,Lost" rbitfld.byte 0x00 2. " IBB ,Bus busy" "Idle,Busy" rbitfld.byte 0x00 1. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 0. " TCF ,Transfer complete" "In progress,Completed" elif (((per.b(ad:0x2180000+0x02))&0x05)==0x04) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " RXAK ,Received acknowledge" "Received,Not received" eventfld.byte 0x00 6. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " IBAL ,Arbitration lost" "Not lost,Lost" rbitfld.byte 0x00 2. " IBB ,Bus busy" "Idle,Busy" rbitfld.byte 0x00 1. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 0. " TCF ,Transfer complete" "In progress,Completed" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C1_IBDR,I2C Bus Data I/O Register" in if (((per.b(ad:0x2180000+0x02))&0x01)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 1. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 0. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_2" base ad:0x2190000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C2_IBAD,I2C Bus Address Register" hexmask.byte 0x00 0.--6. 0x01 " ADR ,Slave address" if (((per.b(ad:0x2190000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2190000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2190000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C2_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" bitfld.byte 0x00 6. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RSTA ,Repeat start generation" "No effect,Generate" bitfld.byte 0x00 4. " NOACK ,Data acknowledge disable" "No,Yes" newline bitfld.byte 0x00 3. " TXRX ,Transmit/receive mode select" "Receive,Transmit" bitfld.byte 0x00 2. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 1. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " MDIS ,Module disable" "No,Yes" if (((per.b(ad:0x2190000+0x02))&0x05)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " RXAK ,Received acknowledge" "Received,Not received" eventfld.byte 0x00 6. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 5. " SRW ,Slave read/write" "Slave Rx,Slave Tx" newline eventfld.byte 0x00 3. " IBAL ,Arbitration lost" "Not lost,Lost" rbitfld.byte 0x00 2. " IBB ,Bus busy" "Idle,Busy" rbitfld.byte 0x00 1. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 0. " TCF ,Transfer complete" "In progress,Completed" elif (((per.b(ad:0x2190000+0x02))&0x05)==0x04) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " RXAK ,Received acknowledge" "Received,Not received" eventfld.byte 0x00 6. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " IBAL ,Arbitration lost" "Not lost,Lost" rbitfld.byte 0x00 2. " IBB ,Bus busy" "Idle,Busy" rbitfld.byte 0x00 1. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 0. " TCF ,Transfer complete" "In progress,Completed" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" endif hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C2_IBDR,I2C Bus Data I/O Register" in if (((per.b(ad:0x2190000+0x02))&0x01)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 1. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 0. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end tree.end elif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree.open "I2C (Inter-Integrated Circuit)" tree "I2C_1" base ad:0x2000000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C1_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2000000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2000000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2000000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C1_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2000000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2000000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C1_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2000000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C1_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_2" base ad:0x2010000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C2_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2010000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2010000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2010000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C2_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2010000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2010000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C2_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2010000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C2_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_3" base ad:0x2020000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C3_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2020000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2020000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2020000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C3_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2020000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2020000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C3_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2020000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C3_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C3_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C3_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_4" base ad:0x2030000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C4_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2030000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2030000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2030000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C4_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2030000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2030000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C4_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2030000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C4_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C4_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C4_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree.end else tree.open "I2C (Inter-Integrated Circuit)" tree "I2C_1" base ad:0x2180000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C1_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2180000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2180000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2180000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C1_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C1_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2180000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2180000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C1_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C1_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2180000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C1_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C1_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_2" base ad:0x2190000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C2_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x2190000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x2190000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x2190000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C2_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C2_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x2190000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x2190000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C2_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C2_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x2190000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C2_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C2_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_3" base ad:0x21A0000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C3_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x21A0000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x21A0000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x21A0000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C3_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C3_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x21A0000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x21A0000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C3_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C3_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x21A0000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C3_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C3_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C3_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree "I2C_4" base ad:0x21B0000 width 11. group.byte 0x00++0x00 line.byte 0x00 "I2C4_IBAD,I2C Bus Address Register" hexmask.byte 0x00 1.--7. 0x02 " ADR ,Slave address" if (((per.b(ad:0x21B0000+0x01))&0xC0)==0x00) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" elif (((per.b(ad:0x21B0000+0x01))&0xC0)==0x40) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "40/14/12/22,44/14/14/24,48/16/16/26,52/16/18/28,56/18/20/30,60/18/22/32,68/20/26/36,80/20/32/42,56/14/20/30,64/14/24/34,72/18/28/38,80/18/32/42,88/22/36/46,96/22/40/50,112/26/48/58,136/26/60/70,96/18/36/50,112/18/44/58,128/26/52/66,144/26/60/74,160/34/68/82,176/34/76/90,208/42/92/106,256/42/116/130,160/18/76/82,192/18/92/98,224/34/108/114,256/34/124/130,288/50/140/146,320/50/156/162,384/66/188/194,480/66/236/242,320/34/156/162,384/34/188/194,448/66/220/226,512/66/252/258,576/98/284/290,640/98/316/322,768/130/380/386,960/130/476/482,640/98/316/322,768/130/380/386,896/130/444/450,1024/130/508/514,1152/194/572/578,1280/194/636/642,1536/258/764/770,1920/258/956/962,1280/130/636/642,1536/130/764/770,1792/258/892/898,2048/258/1020/1026,2304/386/1148/1154,2560/386/1276/1282,3072/514/1532/1538,3840/514/1916/1922,2560/258/1276/1282,3072/258/1532/1538,3584/514/1788/1794,4096/514/2044/2050,4608/770/2300/2306,5120/770/2556/2562,6144/1026/3068/3074,7680/1026/3836/3842" elif (((per.b(ad:0x21B0000+0x01))&0xC0)==0x80) group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "80/28/24/44,88/28/28/48,96/32/32/52,104/32/36/56,112/36/40/60,120/36/44/64,136/40/52/72,160/40/64/84,112/28/40/60,128/28/48/68,144/36/56/76,160/36/64/84,176/44/72/92,192/44/80/100,224/52/96/116,272/52/120/140,192/36/72/100,224/36/88/116,256/52/104/132,288/52/120/148,320/68/136/164,352/68/152/180,416/84/184/212,512/84/232/260,320/36/152/164,384/36/184/196,448/68/216/228,512/68/248/260,576/100/280/292,640/100/312/324,768/132/376/388,960/132/472/484,640/68/312/324,768/68/376/388,896/132/440/452,1024/132/504/516,1152/196/568/580,1280/196/632/644,1536/260/760/772,1920/260/952/964,1280/132/632/644,1536/132/760/772,1792/260/888/900,2048/260/1016/1028,2304/388/1144/1156,2560/388/1272/1284,3072/516/1528/1540,3840/516/1912/1924,2560/260/1272/1284,3072/260/1528/1540,3584/516/1784/1796,4096/516/2040/2052,4680/772/2296/2308,5120/772/2552/2564,6144/1028/3064/3076,7680/1028/3832/3844,5120/516/2552/2564,6144/516/3064/3076,7168/1028/3576/3588,8192/1028/4088/4100,9216/1540/4600/4612,10240/1540/5112/5124,12288/2052/6136/6148,15360/2052/7672/7684" else group.byte 0x01++0x00 line.byte 0x00 "I2C4_IBFD,I2C Bus Frequency Divider Register" bitfld.byte 0x00 6.--7. " IBC[6:7] ,Divider value multiplier" "x1,x2,x4,?..." bitfld.byte 0x00 0.--5. " IBC[0:5] ,SCL divider/SDA hold/SCL hold (start)/SCL hold(stop)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x02++0x00 line.byte 0x00 "I2C4_IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MDIS ,Module disable" "No,Yes" bitfld.byte 0x00 6. " IBIE ,I-Bus interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " MSSL ,Master/slave mode select" "Slave,Master" bitfld.byte 0x00 4. " TXRX ,Transmit/receive mode select" "Receive,Transmit" newline bitfld.byte 0x00 3. " NOACK ,Data acknowledge disable" "No,Yes" bitfld.byte 0x00 2. " RSTA ,Repeat start generation" "No effect,Generate" sif (!cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*")) bitfld.byte 0x00 1. " DMAEN ,DMA enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IBDOZE ,I-Bus interface stop in DOZE mode" "Normal,Halt" endif if (((per.b(ad:0x21B0000+0x02))&0xA0)==0x00) group.byte 0x03++0x00 line.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline rbitfld.byte 0x00 2. " SRW ,Slave read/write" "Slave Rx,Slave Tx" eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" elif (((per.b(ad:0x21B0000+0x02))&0xA0)==0x20) group.byte 0x03++0x00 line.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" rbitfld.byte 0x00 7. " TCF ,Transfer complete" "In progress,Completed" rbitfld.byte 0x00 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x00 5. " IBB ,Bus busy" "Idle,Busy" eventfld.byte 0x00 4. " IBAL ,Arbitration lost" "Not lost,Lost" newline eventfld.byte 0x00 1. " IBIF ,I-Bus interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x00 0. " RXAK ,Received acknowledge" "Received,Not received" else hgroup.byte 0x03++0x00 hide.byte 0x00 "I2C4_IBSR,I2C Bus Status Register" endif newline hgroup.byte 0x04++0x00 hide.byte 0x00 "I2C4_IBDR,I2C Bus Data I/O Register" in newline if (((per.b(ad:0x21B0000+0x02))&0x80)==0x00) group.byte 0x05++0x00 line.byte 0x00 "I2C4_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 7. " BIIE ,Bus idle interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" else group.byte 0x05++0x00 line.byte 0x00 "I2C4_IBIC,I2C Bus Interrupt Config Register" bitfld.byte 0x00 6. " BYTERXIE ,Byte receive interrupt enable" "Disabled,Enabled" endif sif cpuis("LS10?6A")||cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") group.byte 0x06++0x00 line.byte 0x00 "I2C4_IBDBG,I2C Bus Debug Register" bitfld.byte 0x00 3. " GLFLT_EN ,Glitch filter enable" "Disabled,Enabled" rbitfld.byte 0x00 1. " IPG_DEBUG_HALTED ,Debug halted bit" "Not halted,Halted" bitfld.byte 0x00 0. " IPG_DEBUG_EN ,Debug mode enable bit" "Disabled,Enabled" endif width 0x0B tree.end tree.end endif sif cpuis("LS10?3A")||cpuis("LS10?6A") tree.open "LPUART (Low Power Universal Asynchronous Receiver/Transmitter)" tree "LPUART_1" base ad:0x2950000 width 7. endian.be if ((per.l.be(ad:0x2950000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2950000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2950000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x2950000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2950000)&0x20002000)==0x00) if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2950000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2950000)&0x20002000)==0x2000))||(((per.l.be(ad:0x2950000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2950000)&0x20002000)==0x00)) if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2950000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2950000)&0x20002000)==0x2000))||((per.l.be(ad:0x2950000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x2950000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x2950000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x2950000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x2950000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree "LPUART_2" base ad:0x2960000 width 7. endian.be if ((per.l.be(ad:0x2960000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2960000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2960000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x2960000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2960000)&0x20002000)==0x00) if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2960000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2960000)&0x20002000)==0x2000))||(((per.l.be(ad:0x2960000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2960000)&0x20002000)==0x00)) if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2960000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2960000)&0x20002000)==0x2000))||((per.l.be(ad:0x2960000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x2960000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x2960000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x2960000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x2960000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree "LPUART_3" base ad:0x2970000 width 7. endian.be if ((per.l.be(ad:0x2970000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2970000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2970000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x2970000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2970000)&0x20002000)==0x00) if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2970000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2970000)&0x20002000)==0x2000))||(((per.l.be(ad:0x2970000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2970000)&0x20002000)==0x00)) if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2970000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2970000)&0x20002000)==0x2000))||((per.l.be(ad:0x2970000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x2970000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x2970000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x2970000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x2970000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree "LPUART_4" base ad:0x2980000 width 7. endian.be if ((per.l.be(ad:0x2980000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2980000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2980000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x2980000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2980000)&0x20002000)==0x00) if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2980000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2980000)&0x20002000)==0x2000))||(((per.l.be(ad:0x2980000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2980000)&0x20002000)==0x00)) if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2980000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2980000)&0x20002000)==0x2000))||((per.l.be(ad:0x2980000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x2980000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x2980000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x2980000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x2980000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree "LPUART_5" base ad:0x2990000 width 7. endian.be if ((per.l.be(ad:0x2990000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2990000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x2990000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x2990000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2990000)&0x20002000)==0x00) if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2990000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x2990000)&0x20002000)==0x2000))||(((per.l.be(ad:0x2990000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2990000)&0x20002000)==0x00)) if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x2990000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x2990000)&0x20002000)==0x2000))||((per.l.be(ad:0x2990000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x2990000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x2990000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x2990000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x2990000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree "LPUART_6" base ad:0x29A0000 width 7. endian.be if ((per.l.be(ad:0x29A0000+0x08)&0x10)==0x10) if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x29A0000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "9-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif else if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==(0xC0000||0x40000)) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" rbitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" rbitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" elif ((per.l.be(ad:0x29A0000+0x08)&0x80000)==0x80000) group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" rbitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" rbitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" else group.long 0x00++0x03 line.long 0x00 "BAUD,LPUART Baud Rate Register" bitfld.long 0x00 31. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.long 0x00 30. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.long 0x00 29. " M10 ,10-bit mode select" "8-bit,10-bit" bitfld.long 0x00 24.--28. " OSR ,Over sampling ratio" ",,,4x,5x,6x,7x,8x,9x,10x,11x,12x,13x,14x,15x,16x,17x,18x,19x,20x,21x,22x,23x,24x,25x,26x,27x,28x,29x,30x,31x,32x" newline bitfld.long 0x00 23. " TDMAE ,Transmitter DMA enable" "Disabled,Enabled" bitfld.long 0x00 21. " RDMAE ,Receiver full DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " BOTHEDGE ,Both edge sampling" "Disabled,Enabled" bitfld.long 0x00 16. " RESYNCDIS ,Resynchronization disable" "No,Yes" newline bitfld.long 0x00 15. " LBKDIE ,LIN break detect interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXEDGIE ,RX input active edge interrupt enable" "Disabled,Enabled" bitfld.long 0x00 13. " SBNS ,Stop bit number select" "1 bit,2 bits" hexmask.long.word 0x00 0.--12. 1. " SBR ,Baud rate modulo divisor" endif endif if ((per.l.be(ad:0x29A0000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x29A0000)&0x20002000)==0x00) if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "10,13" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "10,11" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x29A0000+0x08)&0x10)==0x00)&&((per.l.be(ad:0x29A0000)&0x20002000)==0x2000))||(((per.l.be(ad:0x29A0000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x29A0000)&0x20002000)==0x00)) if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "11,14" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "11,12" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif elif (((per.l.be(ad:0x29A0000+0x08)&0x10)==0x10)&&((per.l.be(ad:0x29A0000)&0x20002000)==0x2000))||((per.l.be(ad:0x29A0000)&0x20002000)==0x20000000) if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "12,15" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "12,14" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif else if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0xC0000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x80000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" rbitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" elif ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x40000) group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" rbitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline rbitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" else group.long 0x04++0x03 line.long 0x00 "STAT,LPUART Status Register" eventfld.long 0x00 31. " LBKDIF ,LIN break detect interrupt flag" "Not detected,Detected" eventfld.long 0x00 30. " RXEDGIF ,LPUART_RX pin active edge interrupt flag" "Not detected,Detected" bitfld.long 0x00 29. " MSBF ,MSB first" "LSB first,MSB first" bitfld.long 0x00 28. " RXINV ,Receive data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " RWUID ,Receive wake up idle detect enable" "Disabled,Enabled" bitfld.long 0x00 26. " BRK13 ,Break character generation length" "13,16" bitfld.long 0x00 25. " LBKDE ,LIN break detection enable" "13,15" rbitfld.long 0x00 24. " RAF ,Receiver active flag" "Not active,Active" newline rbitfld.long 0x00 23. " TDRE ,Transmit data register empty flag" "Full,Empty" rbitfld.long 0x00 22. " TC ,Transmission complete flag" "Active,Idle" rbitfld.long 0x00 21. " RDRF ,Receive data register full flag" "Empty,Full" eventfld.long 0x00 20. " IDLE ,Idle line flag" "Not detected,Detected" newline eventfld.long 0x00 19. " OR ,Receiver overrun flag" "No overrun,Overrun" eventfld.long 0x00 18. " NF ,Noise flag" "Not detected,Detected" eventfld.long 0x00 17. " FE ,Framing error flag" "No error,Error" eventfld.long 0x00 16. " PF ,Parity error flag" "No error,Error" endif endif if ((per.l.be(ad:0x29A0000+0x08)&0xC0000)==0x00) group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" bitfld.long 0x00 31. " R8T9 ,Receive bit 8 / Transmit bit 9" "0,1" bitfld.long 0x00 30. " R9T8 ,Receive bit 9 / Transmit bit 8" "0,1" bitfld.long 0x00 29. " TXDIR ,LPUART_TX pin direction in single-wire mode" "Input,Output" bitfld.long 0x00 28. " TXINV ,Transmit data inversion" "Not inverted,Inverted" newline bitfld.long 0x00 27. " ORIE ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " TIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 22. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RIE ,Receiver interrupt enable" "Disabled,Enabled" bitfld.long 0x00 20. " ILIE ,Idle line interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 17. " RWU ,Receiver wakeup control" "Normal operation,Standby" bitfld.long 0x00 16. " SBK ,Send break" "Normal operation,Sent" newline bitfld.long 0x00 7. " LOOPS ,Loop mode select" "Normal operation,Loop/single-wire" bitfld.long 0x00 6. " DOZEEN ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 5. " RSRC ,Receiver source select" "Internal loop back,Single-wire LPUART" bitfld.long 0x00 4. " M ,9-Bit or 8-Bit mode select" "8-bit,9-bit" newline bitfld.long 0x00 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" bitfld.long 0x00 2. " ILT ,Idle line type select. Idle character bit count starts after start/stop bit" "Start bit,Stop bit" bitfld.long 0x00 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 0. " PT ,Parity type" "Even,Odd" else group.long 0x08++0x03 line.long 0x00 "CTRL,LPUART Control Register" newline newline newline bitfld.long 0x00 19. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 18. " RE ,Receiver enable" "Disabled,Enabled" endif newline hgroup.long 0x0C++0x03 hide.long 0x00 "DATA,LPUART Data Register" in newline group.long 0x10++0x03 line.long 0x00 "MATCH,LPUART Match Address Register" hexmask.long.byte 0x00 16.--23. 0x01 " MA2 ,Match address 2" hexmask.long.byte 0x00 0.--7. 0x01 " MA1 ,Match address 1" group.long 0x14++0x03 line.long 0x00 "MODIR,LPUART Modem IrDA Register" bitfld.long 0x00 18. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TNP ,Transmitter narrow pulse" "1/OSR,2/OSR,3/OSR,4/OSR" bitfld.long 0x00 3. " RXRTSE ,Receiver request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" newline bitfld.long 0x00 1. " TXRTSE ,Transmitter request-to-send enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "Disabled,Enabled" if ((((per.l.be(ad:0x29A0000+0x08)&0xC0000))==0x00)&&(((per.l.be(ad:0x29A0000+0x18)&0x800000))==0x800000)) group.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" rbitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" eventfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" rbitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." else rgroup.long 0x18++0x03 line.long 0x00 "FIFO,LPUART FIFO Register" bitfld.long 0x00 23. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 22. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" bitfld.long 0x00 17. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RXUF ,Receiver buffer underflow flag" "No underflow,Underflow" newline bitfld.long 0x00 15. " TXFLUSH ,Transmit FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 14. " RXFLUSH ,Receive FIFO/Buffer flush" "No effect,Flush" bitfld.long 0x00 9. " TXOFE ,Transmit FIFO overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " RXUFE ,Receive FIFO underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO. Buffer depth (datawords)" ",,,,,16,?..." bitfld.long 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO. Buffer depth (datawords)" ",,,,,16,?..." endif if (per.l.be(ad:0x29A0000+0x08)&0x80000)==0x80000 rgroup.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" else group.long 0x1C++0x03 line.long 0x00 "WATER,LPUART Watermark Register" hexmask.long.byte 0x00 24.--31. 1. " RXCOUNT ,Receive counter" hexmask.long.byte 0x00 16.--23. 1. " RXWATER ,Receive watermark" hexmask.long.byte 0x00 8.--15. 1. " TXCOUNT ,Transmit counter" hexmask.long.byte 0x00 0.--7. 1. " TXWATER ,Transmit watermark" endif endian.le width 0x0B tree.end tree.end endif sif cpuis("LS1012A") tree "MMDC (Multi Mode DDR Controller)" base ad:0x1080000 width 13. endian.be group.long 0x00++0x23 line.long 0x00 "MDCTL,MMDC Core Control Register" bitfld.long 0x00 31. " SDE_0 ,Access from the MMDC toward chip select 0 enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " ROW ,Row address width select" "11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..." newline bitfld.long 0x00 20.--22. " COL ,Column address width select" ",10 bits,11 bits,?..." bitfld.long 0x00 19. " BL ,Burst length" "4,8" line.long 0x04 "MDPDC,MMDC Core Power Down Control Register" bitfld.long 0x04 24.--26. " PRCT_0 ,Precharge timer for chip select 0" "Off,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks" bitfld.long 0x04 16.--18. " TCKE ,CKE minimum pulse width" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x04 8.--11. " PWDT_0 ,Power down timer - chip select 0 number of cycles to precharge/active power down" "Disabled,16,32,64,128,256,512,1024,2048,4096,8196,16384,32768,?..." newline bitfld.long 0x04 7. " SLOW_PD ,Power down mode select" "Fast,Slow" bitfld.long 0x04 3.--5. " TCKSRX ,Valid clock cycles before self-refresh exit" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " TCKSRE ,Valid clock cycles after self-refresh entry" "0,1,2,3,4,5,6,7" line.long 0x08 "MDOTC,MMDC Core ODT Timing Control Register" bitfld.long 0x08 27.--29. " TAOFPD ,Asynchronous RTT turn-off delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 24.--26. " TAONPD ,Asynchronous RTT turn-on delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x08 20.--23. " TANPD ,Asynchronous ODT to power down entry delay" "1 clock,2 clocks,3 clocks,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 clocks,16 clocks" newline bitfld.long 0x08 16.--19. " TAXPD ,Asynchronous ODT to power down exit delay" "1 clock,2 clocks,3 clocks,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 clocks,16 clocks" bitfld.long 0x08 11.--13. " TODTLON ,ODT turn on latency" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,?..." bitfld.long 0x08 4.--8. " TODT_IDLE_OFF ,ODT turn off latency" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles" line.long 0x0C "MDCFG0,MMDC Core Timing Configuration Register 0" hexmask.long.byte 0x0C 24.--31. 1. " TRFC ,Refresh command to active or refresh command time" hexmask.long.byte 0x0C 16.--23. 1. " TXS ,Exit self refresh to non READ command" bitfld.long 0x0C 13.--15. " TXP ,Exit power down with DLL-on to any valid command" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x0C 9.--12. " TXPDLL ,Exit precharge power down with DLL frozen to commands requiring DLL" "1 clock,2 clocks,3 clocks,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 clocks,16 clocks" bitfld.long 0x0C 4.--8. " TFAW ,Four active windows (all banks)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" bitfld.long 0x0C 0.--3. " TCL ,CAS read latency" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,?..." line.long 0x10 "MDCFG1,MMDC Core Timing Configuration Register 1" bitfld.long 0x10 29.--31. " TRCD ,Active command to internal read or write delay time (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x10 26.--28. " TRP ,Precharge command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks" bitfld.long 0x10 21.--25. " TRC ,Active to active or refresh command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks" newline bitfld.long 0x10 16.--20. " TRAS ,Active to precharge command period (same bank)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,?..." bitfld.long 0x10 15. " TRPA ,Precharge-all command period" "TRP,TRP+1" bitfld.long 0x10 9.--11. " TWR ,Write recovery time (same bank)" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x10 5.--8. " TMRD ,Mode register set command cycle (all banks)" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks" bitfld.long 0x10 0.--2. " TCWL ,CAS write latency (DDR3L)" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..." line.long 0x14 "MDCFG2,MMDC Core Timing Configuration Register 2" hexmask.long.word 0x14 16.--24. 1. " TDLLK ,DLL locking time" bitfld.long 0x14 6.--8. " TRTP ,Internal READ command to precharge command delay (same bank)" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" newline bitfld.long 0x14 3.--5. " TWTR ,Internal WRITE to READ command delay (same bank)" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x14 0.--2. " TRRD ,Active to active command period (all banks)" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,?..." line.long 0x18 "MDMISC,MMDC Core Miscellaneous Register" rbitfld.long 0x18 31. " CS0_RDY ,External status device on CS0" "Wake-up period,Ready for init" bitfld.long 0x18 21. " CK1_GATING ,Secondary DDR clock disable" "No,Yes" bitfld.long 0x18 12. " BI_ON ,Bank interleaving enable" "Disabled,Enabled" newline bitfld.long 0x18 6.--8. " RALAT ,Read additional latency" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" bitfld.long 0x18 5. " DDR_4_BANK ,Number of banks per DDR device" "8 banks,?..." newline bitfld.long 0x18 3.--4. " DDR_TYPE ,DDR type" "DDR3L,?..." bitfld.long 0x18 1. " RST ,Software reset" "No reset,Reset" line.long 0x1C "MDSCR,MMDC Core Special Command Register" hexmask.long.byte 0x1C 24.--31. 0x01 " CMD_ADDR_MSB_MR_OP ,Command/address MSB" hexmask.long.byte 0x1C 16.--23. 0x01 " CMD_ADDR_LSB_MR_ADDR ,Command/address LSB" bitfld.long 0x1C 15. " CON_REQ ,Configuration request" "Not requested,Requested" newline bitfld.long 0x1C 14. " CON_ACK ,Configuration acknowledge" "Forbidden,Permitted" bitfld.long 0x1C 10. " MRR_READ_DATA_VALID ,MRR read data valid" "Not valid,Valid" bitfld.long 0x1C 9. " WL_EN ,Write-leveling entry enable" "Disabled,Enabled" newline bitfld.long 0x1C 4.--6. " CMD ,Command mode" "Normal,,Auto-Refresh,Load Reg CMD,ZQ calibration,Precharge all,MRR command,?..." bitfld.long 0x1C 3. " CMD_CS ,Chip select" "Chip-select 0,?..." bitfld.long 0x1C 0.--2. " CMD_BA ,Targeted bank address select" "0,1,2,3,4,5,6,7" line.long 0x20 "MDREF,MMDC Core Refresh Control Register" hexmask.long.word 0x20 16.--31. 1. " REF_CNT ,Refresh counter at DDR clock period" bitfld.long 0x20 14.--15. " REF_SEL ,Refresh frequency selector" "64KHz,32KHz,REF_CNT,No refresh" newline bitfld.long 0x20 11.--13. " REFR ,Refresh rate in every refresh cycle" "1,2,3,4,5,6,7,8" bitfld.long 0x20 0. " START_REF ,Manual start of refresh cycle" "Do nothing,Start refresh" group.long 0x2C++0x07 line.long 0x00 "MDRWD,MMDC Core Read/Write Command Delay Register" bitfld.long 0x00 12.--14. " RTW_SAME ,Read to write delay for same chip-select" "0 cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles" line.long 0x04 "MDOR,MMDC Core Out Of Reset Delays Register" hexmask.long.byte 0x04 16.--23. 1. " TXPR ,CKE HIGH to a valid command" bitfld.long 0x04 8.--13. " SDE_TO_RST ,Time from SDE enable until DDR reset is high" ",,,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" bitfld.long 0x04 0.--5. " RST_TO_CKE ,Time from SDE enable to CKE rise" ",,,1 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles" if (((per.l.be(ad:0x1080000+0x400))&0x80000000)==0x00) group.long 0x400++0x03 line.long 0x00 "MAARCR,MMDC Core AXI Reordering Control Register" bitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock bit" "Not locked,Locked" bitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation result" "OKAY,SLAVE Error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation result" "OKAY,SLAVE Error" newline bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel and bypass enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR page hit rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR access hit rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR dynamic jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR dynamic maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR guard additional cycles after reach maximum dynamic score value" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" else group.long 0x400++0x03 line.long 0x00 "MAARCR,MMDC Core AXI Reordering Control Register" rbitfld.long 0x00 31. " ARCR_SEC_ERR_LOCK ,ARCR_SEC_ERR_EN lock bit" "Not locked,Locked" rbitfld.long 0x00 30. " ARCR_SEC_ERR_EN ,Security read/write access violation result" "OKAY,SLAVE Error" bitfld.long 0x00 28. " ARCR_EXC_ERR_EN ,Exclusive read/write access violation result" "OKAY,SLAVE Error" newline bitfld.long 0x00 24. " ARCR_RCH_EN ,Real time channel and bypass enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " ARCR_PAG_HIT ,ARCR page hit rate" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " ARCR_ACC_HIT ,ARCR access hit rate" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. " ARCR_DYN_JMP ,ARCR dynamic jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " ARCR_DYN_MAX ,ARCR dynamic maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ARCR_GUARD ,ARCR guard additional cycles after reach maximum dynamic score value" "15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30" endif group.long 0x404++0x13 line.long 0x00 "MAPSR,MMDC Core Power Saving Control And Status Register" rbitfld.long 0x00 25. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted" rbitfld.long 0x00 24. " LPACK ,General low-power acknowledge" "Not asserted,Asserted" bitfld.long 0x00 21. " DVFS ,General DVFS request" "Not requested,Requested" newline bitfld.long 0x00 20. " LPMD ,General LPMD request" "No request,Requested" hexmask.long.byte 0x00 8.--15. 1. " PST ,Automatic power saving timer" rbitfld.long 0x00 6. " WIS ,Write idle status" "Idle,Not idle" newline rbitfld.long 0x00 5. " RIS ,Read idle status" "Idle,Not idle" rbitfld.long 0x00 4. " PSS ,Power saving status" "Not active,Active" bitfld.long 0x00 0. " PSD ,Automatic power saving disable" "No,Yes" line.long 0x04 "MAEXIDR0,MMDC Core Exclusive ID Monitor Register 0" hexmask.long.word 0x04 16.--31. 1. " EXC_ID_MONITOR1 ,ID for exclusive monitor #1" hexmask.long.word 0x04 0.--15. 1. " EXC_ID_MONITOR0 ,ID for exclusive monitor #0" line.long 0x08 "MAEXIDR1,MMDC Core Exclusive ID Monitor Register 1" hexmask.long.word 0x08 16.--31. 1. " EXC_ID_MONITOR3 ,ID for exclusive monitor #3" hexmask.long.word 0x08 0.--15. 1. " EXC_ID_MONITOR2 ,ID for exclusive monitor #2" line.long 0x0C "MADPCR0,MMDC Core Debug And Profiling Control Register 0" bitfld.long 0x0C 9. " SBS ,Step by step trigger" "No launch,Launch" bitfld.long 0x0C 8. " SBS_EN ,Step by step debug enable" "Disabled,Enabled" eventfld.long 0x0C 3. " CYC_OVF ,Total profiling cycles count overflow" "No overflow,Overflow" newline bitfld.long 0x0C 2. " PRF_FRZ ,Profiling counters freeze" "Not frozen,Frozen" bitfld.long 0x0C 1. " DBG_RST ,Debug and profiling reset" "No reset,Reset" bitfld.long 0x0C 0. " DBG_EN ,Debug and profiling enable" "Disabled,Enabled" line.long 0x10 "MADPCR1,MMDC Core Debug And Profiling Control Register 1" hexmask.long.word 0x10 16.--31. 1. " PRF_AXI_ID_MASK ,Profiling AXI ID mask" hexmask.long.word 0x10 0.--15. 1. " PRF_AXI_ID ,Profiling AXI ID" rgroup.long 0x418++0x1F line.long 0x00 "MADPSR0,MMDC Core Debug And Profiling Status Register 0" line.long 0x04 "MADPSR1,MMDC Core Debug And Profiling Status Register 1" line.long 0x08 "MADPSR2,MMDC Core Debug And Profiling Status Register 2" line.long 0x0C "MADPSR3,MMDC Core Debug And Profiling Status Register 3" line.long 0x10 "MADPSR4,MMDC Core Debug And Profiling Status Register 4" line.long 0x14 "MADPSR5,MMDC Core Debug And Profiling Status Register 5" line.long 0x18 "MASBS0,MMDC Core Step By Step Address Register" line.long 0x1C "MASBS1,MMDC Core Step By Step Address Attributes Register" hexmask.long.word 0x1C 16.--31. 1. " SBS_AXI_ID ,Step by step AXI ID" bitfld.long 0x1C 13.--15. " SBS_LEN ,Step by step length" "1,2,,,,,,8" bitfld.long 0x1C 12. " SBS_BUFF ,Step by step buffered" "Not buffered,Buffered" newline bitfld.long 0x1C 10.--11. " SBS_BURST ,Step by step burst mode" "Fixed,INCR,WRAP,?..." bitfld.long 0x1C 7.--9. " SBS_SIZE ,Step by step size" "8 bits,16 bits,32 bits,64 bits,128 bits,?..." bitfld.long 0x1C 4.--6. " SBS_PROT ,Step by step protection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 2.--3. " SBS_LOCK ,Step by step lock" "0,1,2,3" bitfld.long 0x1C 1. " SBS_TYPE ,Step by step request type" "Write,Read" bitfld.long 0x1C 0. " SBS_VLD ,Step by step valid" "Not valid,Valid" group.long 0x440++0x03 line.long 0x00 "MAGENP,MMDC Core General Purpose Register" if (((per.l.be(ad:0x1080000+0x800))&0x03)==0x01)||(((per.l.be(ad:0x1080000+0x800))&0x03)==0x03) group.long 0x800++0x03 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZW_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." newline bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process enable" "Disabled,Enabled" rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down resistor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up resistor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "No ZQ calib,Pad + long CMD,CMD long/short,Pad + CMD long/short" else group.long 0x800++0x03 line.long 0x00 "MPZQHWCTRL,MMDC PHY ZQ HW Control Register" bitfld.long 0x00 27.--31. " ZW_EARLY_COMPARATOR_EN_TIMER ,ZQ early comparator enable timer" ",,,,,,,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" bitfld.long 0x00 23.--25. " TZQ_CS ,Device ZQ short time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 20.--22. " TZQ_OPER ,Device ZQ long/oper time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." newline bitfld.long 0x00 17.--19. " TZQ_INIT ,Device ZQ long/init time" ",,128 cycles,256 cycles,512 cycles,1024 cycles,?..." bitfld.long 0x00 16. " ZQ_HW_FOR ,Force ZQ automatic calibration process enable" "Disabled,?..." rbitfld.long 0x00 11.--15. " ZQ_HW_PD_RES ,ZQ HW calibration pull-down resistor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 6.--10. " ZQ_HW_PU_RES ,ZQ automatic calibration pull-up resistor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " ZQ_HW_PER ,ZQ periodic calibration time" "1 ms,2 ms,4 ms,8 ms,16 ms,32 ms,64 ms,128 ms,256 ms,512 ms,1 sec,2 sec,4 sec,8 sec,16 sec,32 sec" bitfld.long 0x00 0.--1. " ZQ_MODE ,ZQ calibration mode" "No ZQ calib,Pad + long CMD,CMD long/short,Pad + CMD long/short" endif group.long 0x804++0x0B line.long 0x00 "MPZQSWCTRL,MMDC PHY ZQ SW Control Register" bitfld.long 0x00 16.--17. " ZQ_CMP_OUT_SMP ,Amount of cycles between driving the ZQ signals to the ZQ pad" "7 cycles,15 cycles,23 cycles,31 cycles" bitfld.long 0x00 13. " USE_ZQ_SW_VAL ,Use ZQ configured value for I/O pads resistor controls select" "HW values,SW values" bitfld.long 0x00 12. " ZQ_SW_PD ,ZQ software PU/PD calibration select" "PU,PD" newline bitfld.long 0x00 7.--11. " ZQ_SW_PD_VAL ,ZQ software pull-down resistance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--6. " ZQ_SW_PU_VAL ,ZQ software pull-up resistance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 1. " ZQ_SW_RES ,ZQ software calibration result" "Less than VDD/2,More than VDD/2" bitfld.long 0x00 0. " ZQ_SW_FOR ,ZQ SW calibration enable" "Disabled,Enabled" line.long 0x04 "MPWLGCR,MMDC PHY Write Leveling Configuration And Error Status Register" rbitfld.long 0x04 9. " WL_HW_ERR1 ,Byte 1 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x04 8. " WL_HW_ERR0 ,Byte 0 write-leveling HW calibration error" "No error,Error" rbitfld.long 0x04 5. " WL_SW_RES1 ,Byte 1 write-leveling software result" "Low CK,High CK" newline rbitfld.long 0x04 4. " WL_SW_RES0 ,Byte 0 write-leveling software result" "Low CK,High CK" bitfld.long 0x04 2. " SW_WL_CNT_EN ,SW write-leveling count down enable" "Disabled,Enabled" newline bitfld.long 0x04 1. " SW_WL_EN ,Write-leveling SW enable" "Disabled,Enabled" bitfld.long 0x04 0. " HW_WL_EN ,Write-leveling HW (automatic) enable" "Disabled,Enabled" line.long 0x08 "MPWLDECTRL0,MMDC PHY Write Leveling Delay Control Register 0" bitfld.long 0x08 25.--26. " WL_CYC_DEL1 ,Write leveling cycle delay for byte 1" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x08 24. " WL_HC_DEL1 ,Write leveling half cycle delay for byte 1" "No delay,Half-cycle delay" hexmask.long.byte 0x08 16.--22. 0x01 " WL_DL_ABS_OFFSET1 ,Absolute write-leveling delay offset for byte 1" newline bitfld.long 0x08 9.--10. " WL_CYC_DEL0 ,Write leveling cycle delay for byte 0" "No delay,1 cycle,2 cycles,?..." bitfld.long 0x08 8. " WL_HC_DEL0 ,Write leveling half cycle delay for byte 0" "No delay,Half-cycle delay" hexmask.long.byte 0x08 0.--6. 0x01 " WL_DL_ABS_OFFSET0 ,Absolute write-leveling delay offset for byte 0" rgroup.long 0x814++0x03 line.long 0x00 "MPWLDLST,MMDC PHY Write Leveling Delay-Line Status Register" hexmask.long.byte 0x00 8.--14. 1. " WL_DL_UNIT_NUM1 ,Number of delay units that are actually used by write leveling delay-line 1" hexmask.long.byte 0x00 0.--6. 1. " WL_DL_UNIT_NUM0 ,Number of delay units that are actually used by write leveling delay-line 0" group.long 0x818++0x0B line.long 0x00 "MPODTCTRL,MMDC PHY ODT Control Register" bitfld.long 0x00 8.--10. " ODT1_INT_RES ,On chip ODT byte 1 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" bitfld.long 0x00 4.--6. " ODT0_INT_RES ,On chip ODT byte 0 resistor" "Disabled,120 Ohm,60 Ohm,40 Ohm,30 Ohm,24 Ohm,20 Ohm,17 Ohm" newline bitfld.long 0x00 3. " ODT_RD_ACT_EN ,Active read CS ODT enable" "Disabled,Enabled" bitfld.long 0x00 1. " ODT_WR_ACT_EN ,Active write CS ODT enable" "Disabled,Enabled" line.long 0x04 "MPRDDQBY0DL,MMDC PHY Read DQ Byte 0 Delay Register" bitfld.long 0x04 28.--30. " RD_DQ7_DEL ,Number of delay units that are (read) added to dq7 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x04 24.--26. " RD_DQ6_DEL ,Number of delay units that are (read) added to dq6 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x04 20.--22. " RD_DQ5_DEL ,Number of delay units that are (read) added to dq5 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" newline bitfld.long 0x04 16.--18. " RD_DQ4_DEL ,Number of delay units that are (read) added to dq4 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x04 12.--14. " RD_DQ3_DEL ,Number of delay units that are (read) added to dq3 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x04 8.--10. " RD_DQ2_DEL ,Number of delay units that are (read) added to dq2 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" newline bitfld.long 0x04 4.--6. " RD_DQ1_DEL ,Number of delay units that are (read) added to dq1 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x04 0.--2. " RD_DQ0_DEL ,Number of delay units that are (read) added to dq0 relative to dqs0" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" line.long 0x08 "MPRDDQBY1DL,MMDC PHY Read DQ Byte 1 Delay Register" bitfld.long 0x08 28.--30. " RD_DQ15_DEL ,Number of delay units (read) that are added to dq15 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x08 24.--26. " RD_DQ14_DEL ,Number of delay units (read) that are added to dq14 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x08 20.--22. " RD_DQ13_DEL ,Number of delay units (read) that are added to dq13 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" newline bitfld.long 0x08 16.--18. " RD_DQ12_DEL ,Number of delay units (read) that are added to dq12 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x08 12.--14. " RD_DQ11_DEL ,Number of delay units (read) that are added to dq11 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x08 8.--10. " RD_DQ10_DEL ,Number of delay units (read) that are added to dq10 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" newline bitfld.long 0x08 4.--6. " RD_DQ9_DEL ,Number of delay units (read) that are added to dq9 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" bitfld.long 0x08 0.--2. " RD_DQ8_DEL ,Number of delay units (read) that are added to dq8 relative to dqs1" "0,1 unit,2 units,3 units,4 units,5 units,6 units,7 units" group.long 0x82C++0x07 line.long 0x00 "MPWRDQBY0DL,MMDC PHY Write DQ Byte 0 Delay Register" bitfld.long 0x00 30.--31. " WR_DM0_DEL ,Number of delay units (write) that are added to dm0 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 28.--29. " WR_DQ7_DEL ,Number of delay units (write) that are added to dq7 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 24.--25. " WR_DQ6_DEL ,Number of delay units (write) that are added to dq6 relative to dqs0" "0,1 unit,2 units,3 units" newline bitfld.long 0x00 20.--21. " WR_DQ5_DEL ,Number of delay units (write) that are added to dq5 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 16.--17. " WR_DQ4_DEL ,Number of delay units (write) that are added to dq4 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 12.--13. " WR_DQ3_DEL ,Number of delay units (write) that are added to dq3 relative to dqs0" "0,1 unit,2 units,3 units" newline bitfld.long 0x00 8.--9. " WR_DQ2_DEL ,Number of delay units (write) that are added to dq2 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 4.--5. " WR_DQ1_DEL ,Number of delay units (write) that are added to dq1 relative to dqs0" "0,1 unit,2 units,3 units" bitfld.long 0x00 0.--1. " WR_DQ0_DEL ,Number of delay units (write) that are added to dq0 relative to dqs0" "0,1 unit,2 units,3 units" line.long 0x04 "MPWRDQBY1DL,MMDC PHY Write DQ Byte 1 Delay Register" bitfld.long 0x04 30.--31. " WR_DM1_DEL ,Number of delay units (write) that are added to dm1 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 28.--29. " WR_DQ15_DEL ,Number of delay units (write) that are added to dq15 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 24.--25. " WR_DQ14_DEL ,Number of delay units (write) that are added to dq14 relative to dqs1" "0,1 unit,2 units,3 units" newline bitfld.long 0x04 20.--21. " WR_DQ13_DEL ,Number of delay units (write) that are added to dq13 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 16.--17. " WR_DQ12_DEL ,Number of delay units (write) that are added to dq12 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 12.--13. " WR_DQ11_DEL ,Number of delay units (write) that are added to dq11 relative to dqs1" "0,1 unit,2 units,3 units" newline bitfld.long 0x04 8.--9. " WR_DQ10_DEL ,Number of delay units (write) that are added to dq10 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 4.--5. " WR_DQ9_DEL ,Number of delay units (write) that are added to dq9 relative to dqs1" "0,1 unit,2 units,3 units" bitfld.long 0x04 0.--1. " WR_DQ8_DEL ,Number of delay units (write) that are added to dq8 relative to dqs1" "0,1 unit,2 units,3 units" group.long 0x83C++0x03 line.long 0x00 "MPDGCTRL0,MMDC PHY Read DQS Gating Control Register 0" bitfld.long 0x00 31. " RST_RD_FIFO ,Reset read data FIFO and associated pointers" "No reset,Reset" bitfld.long 0x00 30. " DG_CMP_CYC ,Read DQS gating sample cycle" "16 DDR cycles,32 DDR cycles" bitfld.long 0x00 29. " DG_DIS ,Read DQS gating disable" "No,Yes" newline bitfld.long 0x00 28. " HW_DG_EN ,Enable automatic read DQS gating calibration" "Disabled,Enabled" bitfld.long 0x00 24.--27. " DG_HC_DEL1 ,Read DQS gating half cycles delay for byte 1" "0 cycles,Half cycle,1 cycle,1.5 cycle,2 cycle,2.5 cycle,3 cycle,3.5 cycle,4 cycle,4.5 cycle,5 cycle,5.5 cycle,6 cycle,6.5 cycle,?..." bitfld.long 0x00 23. " DG_EXT_UP ,DG extend upper boundary set according to chosen comparison" "First falling,Last passing" newline hexmask.long.byte 0x00 16.--22. 0x01 " DG_DL_ABS_OFFSET1 ,Absolute read DQS gating delay offset for byte 1" rbitfld.long 0x00 12. " HW_DG_ERR ,HW DQS gating error" "No error,Error" newline bitfld.long 0x00 8.--11. " DG_HC_DEL0 ,Read DQS gating half cycles delay for byte 0" "0 cycles,Half cycle,1 cycle,1.5 cycle,2 cycle,2.5 cycle,3 cycle,3.5 cycle,4 cycle,4.5 cycle,5 cycle,5.5 cycle,6 cycle,6.5 cycle,?..." hexmask.long.byte 0x00 0.--6. 0x01 " DG_DL_ABS_OFFSET0 ,Absolute read DQS gating delay offset for byte 0" rgroup.long 0x844++0x03 line.long 0x00 "MPDGDLST0,MMDC PHY Read DQS Gating Delay-Line Status Register" hexmask.long.byte 0x00 8.--14. 1. " DG_DL_UNIT_NUM1 ,Reflects the number of delay units that are actually used by read DQS gating delay-line 1" hexmask.long.byte 0x00 0.--6. 1. " DG_DL_UNIT_NUM0 ,Reflects the number of delay units that are actually used by read DQS gating delay-line 0" group.long 0x848++0x03 line.long 0x00 "MPRDDLCTL,MMDC PHY Read Delay-Lines Configuration Register" hexmask.long.byte 0x00 8.--14. 0x01 " RD_DL_ABS_OFFSET1 ,Absolute read delay offset for byte 1" hexmask.long.byte 0x00 0.--6. 0x01 " RD_DL_ABS_OFFSET0 ,Absolute read delay offset for byte 0" rgroup.long 0x84C++0x03 line.long 0x00 "MPRDDLST,MMDC PHY Read Delay-Lines Status Register" hexmask.long.byte 0x00 8.--14. 1. " RD_DL_UNIT_NUM1 ,Number of delay units that are actually used by read delay-line 1" hexmask.long.byte 0x00 0.--6. 1. " RD_DL_UNIT_NUM0 ,Number of delay units that are actually used by read delay-line 0" group.long 0x850++0x03 line.long 0x00 "MPWRDLCTL,MMDC PHY Write Delay-Lines Configuration Register" hexmask.long.byte 0x00 8.--14. 0x01 " WR_DL_ABS_OFFSET1 ,Absolute write delay offset for byte 1" hexmask.long.byte 0x00 0.--6. 0x01 " WR_DL_ABS_OFFSET0 ,Absolute write delay offset for byte 0" rgroup.long 0x854++0x03 line.long 0x00 "MPWRDLST,MMDC PHY Write Delay-Lines Status Register" hexmask.long.byte 0x00 8.--14. 1. " WR_DL_UNIT_NUM1 ,Number of delay units that are actually used by write delay-line 1" hexmask.long.byte 0x00 0.--6. 1. " WR_DL_UNIT_NUM0 ,Number of delay units that are actually used by write delay-line 0" group.long 0x858++0x03 line.long 0x00 "MPSDCTRL,MMDC PHY CK Control Register" bitfld.long 0x00 10.--11. " SDCLK1_DEL ,DDR clock1 number of delay units that are added to DDR clock1 (CK1)" "0,1 unit,2 units,3 units" bitfld.long 0x00 8.--9. " SDCLK0_DEL ,DDR clock0 number of delay units that are added to DDR clock0 (CK0)" "0,1 unit,2 units,3 units" group.long 0x860++0x07 line.long 0x00 "MPRDDLHWCTL,MMDC PHY Read Delay HW Calibration Control Register" bitfld.long 0x00 5. " HW_RD_DL_CMP_CYC ,Automatic (HW) read comparison delay" "16 cycles,32 cycles" bitfld.long 0x00 4. " HW_RD_DL_EN ,Enable automatic (HW) read calibration" "Disabled,Enabled" newline rbitfld.long 0x00 1. " HW_RD_DL_ERR1 ,Automatic (HW) read calibration error of byte 1" "No error,Error" rbitfld.long 0x00 0. " HW_RD_DL_ERR0 ,Automatic (HW) read calibration error of byte 0" "No error,Error" line.long 0x04 "MPWRDLHWCTL,MMDC PHY Write Delay HW Calibration Control Register" bitfld.long 0x04 5. " HW_WR_DL_CMP_CYC ,Automatic (HW) write comparison delay" "16 cycles,32 cycles" bitfld.long 0x04 4. " HW_WR_DL_EN ,Enable automatic (HW) write calibration" "Disabled,Enabled" newline rbitfld.long 0x04 1. " HW_WR_DL_ERR1 ,Automatic (HW) write calibration error of byte 1" "No error,Error" rbitfld.long 0x04 0. " HW_WR_DL_ERR0 ,Automatic (HW) write calibration error of byte 0" "No error,Error" rgroup.long 0x868++0x03 line.long 0x00 "MPRDDLHWST0,MMDC PHY Read Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_RD_DL_UP1 ,Automatic (HW) read calibration result of upper boundary of byte 1" hexmask.long.byte 0x00 16.--22. 1. " HW_RD_DL_LOW1 ,Automatic (HW) read calibration result of lower boundary of byte 1" newline hexmask.long.byte 0x00 8.--14. 1. " HW_RD_DL_UP0 ,Automatic (HW) read calibration result of upper boundary of byte 0" hexmask.long.byte 0x00 0.--6. 1. " HW_RD_DL_LOW0 ,Automatic (HW) read calibration result of lower boundary of byte 0" rgroup.long 0x870++0x03 line.long 0x00 "MPWRDLHWST0,MMDC PHY Write Delay HW Calibration Status Register 0" hexmask.long.byte 0x00 24.--30. 1. " HW_WR_DL_UP1 ,Automatic (HW) write calibration result of upper boundary of byte 1" hexmask.long.byte 0x00 16.--22. 1. " HW_WR_DL_LOW1 ,Automatic (HW) write calibration result of lower boundary of byte 1" newline hexmask.long.byte 0x00 8.--14. 1. " HW_WR_DL_UP0 ,Automatic (HW) write calibration result of upper boundary of byte 0" hexmask.long.byte 0x00 0.--6. 1. " HW_WR_DL_LOW0 ,Automatic (HW) write calibration result of lower boundary of byte 0" rgroup.long 0x878++0x0B line.long 0x00 "MPWLHWERR,MMDC PHY Write Leveling HW Error Register" hexmask.long.byte 0x00 8.--15. 1. " HW_WL1_DQ ,HW write-leveling calibration result of byte 1" hexmask.long.byte 0x00 0.--7. 1. " HW_WL0_DQ ,HW write-leveling calibration result of byte 0" line.long 0x04 "MPDGHWST0,MMDC PHY Read DQS Gating HW Status Register 0" hexmask.long.word 0x04 16.--26. 1. " HW_DG_UP0 ,HW DQS gating calibration result of the upper boundary of byte 0" hexmask.long.word 0x04 0.--10. 1. " HW_DG_LOW0 ,HW DQS gating calibration result of the lower boundary of byte 0" line.long 0x08 "MPDGHWST1,MMDC PHY Read DQS Gating HW Status Register 1" hexmask.long.word 0x08 16.--26. 1. " HW_DG_UP1 ,HW DQS gating calibration result of the upper boundary of byte 1" hexmask.long.word 0x08 0.--10. 1. " HW_DG_LOW1 ,HW DQS gating calibration result of the lower boundary of byte 1" group.long 0x88C++0x0B line.long 0x00 "MPPDCMPR1,MMDC PHY Pre-defined Compare Register 1" hexmask.long.word 0x00 16.--31. 1. " PDV2 ,MMDC pre defined compare value2" hexmask.long.word 0x00 0.--15. 1. " PDV1 ,MMDC pre defined compare value1" line.long 0x04 "MPPDCMPR2,MMDC PHY Pre-defined Compare And CA Delay-Line Configuration Register" hexmask.long.byte 0x04 24.--30. 0x01 " PHY_CA_DL_UNIT ,The number of delay units that are actually used by CA(command/address) delay-line" hexmask.long.byte 0x04 16.--22. 0x01 " CA_DL_ABS_OFFSET ,Absolute CA (command/address of LPDDRR2) offset" bitfld.long 0x04 11. " ZQ_PU_OFFSET[3] ,Direction of offset in ZQ_PU_OFFSET[0-2]" "Add,Subtract" newline hexmask.long.byte 0x04 8.--10. 0x01 " ZQ_PU_OFFSET[0-2] ,Programmable offset added to the MMDC_MPZQHWCTRL[ZQ_HW_PU_RES] field when ZQ_OFFSET_EN is enabled" bitfld.long 0x04 7. " ZQ_PD_OFFSET[3] ,Direction of offset in ZQ_PD_OFFSET[0-2]" "Add,Subtract" hexmask.long.byte 0x04 4.--6. 0x10 " ZQ_PD_OFFSET[0-2] ,Programmable offset added to the MMDC_MPZQHWCTRL[ZQ_HW_PD_RES] field when ZQ_OFFSET_EN is enabled" newline bitfld.long 0x04 3. " ZW_OFFSET_EN ,Hardware ZQ offset enable" "Disabled,Enabled" bitfld.long 0x04 2. " READ_LEVEL_PATTERN ,MPR(DDR3L) read compare pattern" "1010,?..." newline bitfld.long 0x04 1. " MPR_FULL_CMP ,MPR(DDR3L) full compare enable" "Disabled,Enabled" bitfld.long 0x04 0. " MPR_CMP ,MPR(DDR3L) compare enable" "Disabled,Enabled" line.long 0x08 "MPSWDAR0,MMDC PHY SW Dummy Access Register" rbitfld.long 0x08 3. " SW_DUM_CMP1 ,SW dummy read byte 1 compare result" "Fail,Pass" rbitfld.long 0x08 2. " SW_DUM_CMP0 ,SW dummy read byte 0 compare result" "Fail,Pass" newline bitfld.long 0x08 1. " SW_DUMMY_RD ,SW dummy read enable" "Disabled,Enabled" bitfld.long 0x08 0. " SW_DUMMY_WR ,SW dummy write enable" "Disabled,Enabled" rgroup.long 0x898++0x03 line.long 0x00 "MPSWDRDR0,MMDC PHY SW Dummy Read Data Register 0" rgroup.long 0x89C++0x03 line.long 0x00 "MPSWDRDR1,MMDC PHY SW Dummy Read Data Register 1" rgroup.long 0x8A0++0x03 line.long 0x00 "MPSWDRDR2,MMDC PHY SW Dummy Read Data Register 2" rgroup.long 0x8A4++0x03 line.long 0x00 "MPSWDRDR3,MMDC PHY SW Dummy Read Data Register 3" rgroup.long 0x8A8++0x03 line.long 0x00 "MPSWDRDR4,MMDC PHY SW Dummy Read Data Register 4" rgroup.long 0x8AC++0x03 line.long 0x00 "MPSWDRDR5,MMDC PHY SW Dummy Read Data Register 5" rgroup.long 0x8B0++0x03 line.long 0x00 "MPSWDRDR6,MMDC PHY SW Dummy Read Data Register 6" rgroup.long 0x8B4++0x03 line.long 0x00 "MPSWDRDR7,MMDC PHY SW Dummy Read Data Register 7" group.long 0x8B8++0x03 line.long 0x00 "MPMUR0,MMDC PHY Measure Unit Register" hexmask.long.word 0x00 16.--25. 1. " MU_UNIT_DEL_NUM ,Number of delay units measured per cycle" bitfld.long 0x00 11. " FRC_MSR ,Force measurement on delay-lines performed" "Not performed,Performed" newline bitfld.long 0x00 10. " MU_BYP_EN ,Measure unit bypass enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. " MU_BYP_VAL ,Number of delay units for measurement bypass" group.long 0x8C0++0x03 line.long 0x00 "MPDCCR,MMDC Duty Cycle Control Register" bitfld.long 0x00 22.--24. " RQ_DQS1_FT_DCC ,Read DQS duty cycle fine tuning control of byte 1 (in percent - low/high)" ",51.5/48.5,50/50,,48.5/51.5,?..." bitfld.long 0x00 19.--21. " RQ_DQS0_FT_DCC ,Read DQS duty cycle fine tuning control of byte 0 (in percent - low/high)" ",51.5/48.5,50/50,,48.5/51.5,?..." bitfld.long 0x00 16.--18. " CK_FT1_DCC ,Secondary duty cycle fine tuning control of DDR clock (in percent - low/high)" ",48.5/51.5,50/50,,51.5/48.5,?..." newline bitfld.long 0x00 12.--14. " CK_FT1_DCC ,Primary duty cycle fine tuning control of DDR clock (in percent - low/high)" ",48.5/51.5,50/50,,51.5/48.5,?..." bitfld.long 0x00 3.--5. " WR_DQS1_FT_DCC ,Write DQS duty cycle fine tuning control of byte 1 (in percent - low/high)" ",51.5/48.5,50/50,,48.5/51.5,?..." bitfld.long 0x00 0.--2. " WR_DQS0_FT_DCC ,Write DQS duty cycle fine tuning control of byte 0 (in percent - low/high)" ",51.5/48.5,50/50,,48.5/51.5,?..." endian.le width 0x0B tree.end endif sif cpuis("LS1012*") tree.open "I2S/SAI (Integrated Interchip Sound/Synchronous Audio Interface)" tree "SAI1" base ad:0x2B50000 width 6. group.long 0x00++0x07 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B50000))&0x80000000)==0x00) group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with receiver,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Master 1,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x08++0x03 hide.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" hgroup.long 0x0C++0x03 hide.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" hgroup.long 0x10++0x03 hide.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" hgroup.long 0x14++0x03 hide.long 0x00 "TCR5,SAI Transmit Configuration 5 Register" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B50000+0x80))&0x80000000)==0x00) group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x04 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x88++0x03 hide.long 0x00 "RCR2,SAI Receive Configuration 2 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "RCR3,SAI Receive Configuration 3 Register" hgroup.long 0x90++0x03 hide.long 0x00 "RCR4,SAI Receive Configuration 4 Register" hgroup.long 0x94++0x03 hide.long 0x00 "RCR5,SAI Receive Configuration 5 Register" endif newline rgroup.long 0xA0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive word 0 mask" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "Clock 0,,Clock 2,Clock 3" line.long 0x04 "MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "SAI2" base ad:0x2B60000 width 6. group.long 0x00++0x07 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B60000))&0x80000000)==0x00) group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with receiver,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Master 1,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x08++0x03 hide.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" hgroup.long 0x0C++0x03 hide.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" hgroup.long 0x10++0x03 hide.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" hgroup.long 0x14++0x03 hide.long 0x00 "TCR5,SAI Transmit Configuration 5 Register" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B60000+0x80))&0x80000000)==0x00) group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x04 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x88++0x03 hide.long 0x00 "RCR2,SAI Receive Configuration 2 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "RCR3,SAI Receive Configuration 3 Register" hgroup.long 0x90++0x03 hide.long 0x00 "RCR4,SAI Receive Configuration 4 Register" hgroup.long 0x94++0x03 hide.long 0x00 "RCR5,SAI Receive Configuration 5 Register" endif newline rgroup.long 0xA0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive word 0 mask" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "Clock 0,,Clock 2,Clock 3" line.long 0x04 "MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "SAI3" base ad:0x2B70000 width 6. group.long 0x00++0x07 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B70000))&0x80000000)==0x00) group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with receiver,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Master 1,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x08++0x03 hide.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" hgroup.long 0x0C++0x03 hide.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" hgroup.long 0x10++0x03 hide.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" hgroup.long 0x14++0x03 hide.long 0x00 "TCR5,SAI Transmit Configuration 5 Register" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B70000+0x80))&0x80000000)==0x00) group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x04 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x88++0x03 hide.long 0x00 "RCR2,SAI Receive Configuration 2 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "RCR3,SAI Receive Configuration 3 Register" hgroup.long 0x90++0x03 hide.long 0x00 "RCR4,SAI Receive Configuration 4 Register" hgroup.long 0x94++0x03 hide.long 0x00 "RCR5,SAI Receive Configuration 5 Register" endif newline rgroup.long 0xA0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive word 0 mask" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "Clock 0,,Clock 2,Clock 3" line.long 0x04 "MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "SAI4" base ad:0x2B80000 width 6. group.long 0x00++0x07 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B80000))&0x80000000)==0x00) group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with receiver,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Master 1,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x08++0x03 hide.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" hgroup.long 0x0C++0x03 hide.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" hgroup.long 0x10++0x03 hide.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" hgroup.long 0x14++0x03 hide.long 0x00 "TCR5,SAI Transmit Configuration 5 Register" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B80000+0x80))&0x80000000)==0x00) group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x04 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x88++0x03 hide.long 0x00 "RCR2,SAI Receive Configuration 2 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "RCR3,SAI Receive Configuration 3 Register" hgroup.long 0x90++0x03 hide.long 0x00 "RCR4,SAI Receive Configuration 4 Register" hgroup.long 0x94++0x03 hide.long 0x00 "RCR5,SAI Receive Configuration 5 Register" endif newline rgroup.long 0xA0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive word 0 mask" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "Clock 0,,Clock 2,Clock 3" line.long 0x04 "MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "SAI5" base ad:0x2B90000 width 6. group.long 0x00++0x07 line.long 0x00 "TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No effect,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No effect,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--4. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B90000))&0x80000000)==0x00) group.long 0x08++0x0F line.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous with receiver,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Master 1,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x04 16. " TCE ,Transmit channel enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "TCR4,SAI Transmit Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x08++0x03 hide.long 0x00 "TCR2,SAI Transmit Configuration 2 Register" hgroup.long 0x0C++0x03 hide.long 0x00 "TCR3,SAI Transmit Configuration 3 Register" hgroup.long 0x10++0x03 hide.long 0x00 "TCR4,SAI Transmit Configuration 4 Register" hgroup.long 0x14++0x03 hide.long 0x00 "TCR5,SAI Transmit Configuration 5 Register" endif wgroup.long 0x20++0x03 line.long 0x00 "TDR0,SAI Transmit Data Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TFR0,SAI Transmit FIFO Register 0" bitfld.long 0x00 16.--21. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x60++0x03 line.long 0x00 "TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Transmit word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Transmit word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Transmit word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Transmit word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " [27] ,Transmit word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Transmit word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Transmit word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Transmit word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " [23] ,Transmit word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Transmit word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Transmit word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Transmit word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " [19] ,Transmit word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Transmit word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Transmit word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Transmit word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,Transmit word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Transmit word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Transmit word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Transmit word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " [11] ,Transmit word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Transmit word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Transmit word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Transmit word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,Transmit word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Transmit word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Transmit word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Transmit word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " [3] ,Transmit word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Transmit word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Transmit word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Transmit word 0 mask" "Not masked,Masked" group.long 0x80++0x07 line.long 0x00 "RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit clock enable" "Disabled,Enabled" bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" newline eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" newline rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--4. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x2B90000+0x80))&0x80000000)==0x00) group.long 0x88++0x0F line.long 0x00 "RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x00 30.--31. " SYNC ,Synchronous mode" "Asynchronous,Synchronous,?..." bitfld.long 0x00 29. " BCS ,Bit clock swap" "Normal,Swapped" bitfld.long 0x00 28. " BCI ,Bit clock input" "No effect,External" bitfld.long 0x00 26.--27. " MSEL ,MCLK select" "Bus clock,Master 1,Master 2,Master 3" newline bitfld.long 0x00 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x00 24. " BCD ,Bit clock direction" "External in slave mode,Internal in master mode" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Bit clock divide" line.long 0x04 "RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x04 16. " RCE ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x04 0.--4. " WDFL ,Word flag configuration" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "RCR4,SAI Receive Configuration 4 Register" bitfld.long 0x08 16.--20. " FRSZ ,Frame size" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 8.--12. " SYWD ,Sync width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x08 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x08 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" newline bitfld.long 0x08 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x08 0. " FSD ,Frame sync direction" "External in slave mode,Internal in master mode" line.long 0x0C "RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x0C 24.--28. " WNW ,Word N width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--20. " W0W ,Word 0 width" ",,,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0x88++0x03 hide.long 0x00 "RCR2,SAI Receive Configuration 2 Register" hgroup.long 0x8C++0x03 hide.long 0x00 "RCR3,SAI Receive Configuration 3 Register" hgroup.long 0x90++0x03 hide.long 0x00 "RCR4,SAI Receive Configuration 4 Register" hgroup.long 0x94++0x03 hide.long 0x00 "RCR5,SAI Receive Configuration 5 Register" endif newline rgroup.long 0xA0++0x03 line.long 0x00 "RDR0,SAI Receive Data 0 Register" rgroup.long 0xC0++0x03 line.long 0x00 "RFR0,SAI Receive FIFO 0 Register" hexmask.long.byte 0x00 16.--21. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--5. 0x01 " RFP ,Read FIFO pointer" group.long 0xE0++0x03 line.long 0x00 "RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive word 31 mask" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive word 30 mask" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive word 29 mask" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive word 28 mask" "Not masked,Masked" newline bitfld.long 0x00 27. " RWM27 ,Receive word 27 mask" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive word 26 mask" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive word 25 mask" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive word 24 mask" "Not masked,Masked" newline bitfld.long 0x00 23. " RWM23 ,Receive word 23 mask" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive word 22 mask" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive word 21 mask" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive word 20 mask" "Not masked,Masked" newline bitfld.long 0x00 19. " RWM19 ,Receive word 19 mask" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive word 18 mask" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive word 17 mask" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive word 16 mask" "Not masked,Masked" newline bitfld.long 0x00 15. " RWM15 ,Receive word 15 mask" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive word 14 mask" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive word 13 mask" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive word 12 mask" "Not masked,Masked" newline bitfld.long 0x00 11. " RWM11 ,Receive word 11 mask" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive word 10 mask" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive word 9 mask" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive word 8 mask" "Not masked,Masked" newline bitfld.long 0x00 7. " RWM7 ,Receive word 7 mask" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive word 6 mask" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive word 5 mask" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive word 4 mask" "Not masked,Masked" newline bitfld.long 0x00 3. " RWM3 ,Receive word 3 mask" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive word 2 mask" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive word 1 mask" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive word 0 mask" "Not masked,Masked" group.long 0x100++0x07 line.long 0x00 "MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider update flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK output enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK input clock select" "Clock 0,,Clock 2,Clock 3" line.long 0x04 "MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree.end endif sif cpuis("LS1012*") tree.open "PCI-E (PCI Express)" tree "PCI_1" base ad:0x3400000 width 34. group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,INTx interrupt message generation disable" "No,Yes" bitfld.word 0x04 8. " SERR ,SERR# enable" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Parity error response" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Bus master enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Memory space enable" "Disabled,Enabled" rbitfld.word 0x04 0. " I/O_SPACE ,I/O space enable" "Disabled,Enabled" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Detected parity error" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Signaled system error" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Master abort received" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Target abort received" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Target abort signaled" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Master data parity error detected" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,Capabilities list" "Not implemented,Implemented" eventfld.word 0x06 3. " INTERRUPT_STATUS ,INTx interrupt message status" "No interrupt,Interrupt" group.byte 0x08++0x04 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" line.byte 0x01 "CLASS_CODE_A,PCI Express Class Code Register" line.byte 0x02 "CLASS_CODE_B,PCI Express Class Code Register" line.byte 0x03 "CLASS_CODE_C,PCI Express Class Code Register" line.byte 0x04 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Multiple function support" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "Memory,I/O" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.long 0x14++0x13 line.long 0x00 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "Memory,I/O" line.long 0x04 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "Memory,I/O" line.long 0x08 "BAR3,PCI Express Base Address Register 3" line.long 0x0C "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x0C 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x0C 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x0C 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x0C 0. " MEMSP ,Memory space indicator" "Memory,I/O" line.long 0x10 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" else group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " IO_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " IO_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." newline group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" endif rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" else hgroup.long 0x30++0x03 hide.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" endif group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.byte 0x3E++0x01 line.byte 0x00 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x01 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" else group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" endif width 37. newline rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" newline bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" width 27. newline if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.l.be(ad:0x1EE0000+0x0D))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" newline bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" newline bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" newline bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" newline bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" else group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,?..." bitfld.word 0x00 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" endif rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" newline bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED_VECTOR[3] ,8.0 GT/s link speed support" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed support" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,2.5 GT/s link speed support" "Not supported,Supported" newline group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" newline eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" newline eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" newline eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" newline bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" newline bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" newline bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" newline bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" newline bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" newline bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" newline eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" newline eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" newline bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" newline bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" newline bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" newline rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.l.be(ad:0x1EE0000+0x120))&0x800000)==0x00) group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" newline eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" newline eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" else hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 0. " LANE_ERR_STATUS[0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word 0x154++0x01 line.word 0x00 "LANE_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control Register 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control Register 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" newline hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3400000+0x900))&0x80000000)==0x80000000) if (((per.l.be(ad:0x1EE0000+0x120))&0x800000)==0x800000) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" endif group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.l.be(ad:0x1EE0000+0x0D))&0x01)==0x01) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_RC,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif base ad:0x3400000+0x80000 endian.be width 18. tree "PEX1_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" eventfld.long 0x00 31. " LUTM ,Lookup table miss" "Not missed,Missed" eventfld.long 0x00 30. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" hexmask.long.word 0x00 0.--15. 1. " CREQID ,Captured REQID" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" bitfld.long 0x04 31. " DPL ,Default privilege level" "0,1" bitfld.long 0x04 30. " DBMT ,Default bypass memory translation" "0,1" hexmask.long.word 0x04 0.--14. 1. " DICID ,Default isolation context ID" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" line.long 0x04 "LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" line.long 0x04 "LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" line.long 0x04 "LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" line.long 0x04 "LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" line.long 0x04 "LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" line.long 0x04 "LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" line.long 0x04 "LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" line.long 0x04 "LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" line.long 0x04 "LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" line.long 0x04 "LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" line.long 0x04 "LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" line.long 0x04 "LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" line.long 0x04 "LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" line.long 0x04 "LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" line.long 0x04 "LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" line.long 0x04 "LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" line.long 0x04 "LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" line.long 0x04 "LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" line.long 0x04 "LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" line.long 0x04 "LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" line.long 0x04 "LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" line.long 0x04 "LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" line.long 0x04 "LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" line.long 0x04 "LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" line.long 0x04 "LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" line.long 0x04 "LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" line.long 0x04 "LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" line.long 0x04 "LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" line.long 0x04 "LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" line.long 0x04 "LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" line.long 0x04 "LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" line.long 0x04 "LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" newline group.long 0x40014++0x03 line.long 0x00 "PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 0. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 15. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" bitfld.long 0x00 14. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0B line.long 0x00 "PF0_PME_MES_DR,PEX PF 0 PCIE PME And Message Detect Register" eventfld.long 0x00 15. " PTO ,Indicates that PME turn off was detected" "Not detected,Detected" eventfld.long 0x00 13. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 12. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" newline eventfld.long 0x00 10. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" eventfld.long 0x00 9. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 7. " LUD ,Indicates a link up was detected" "Not detected,Detected" line.long 0x04 "PF0_PME_MES_DISR,PEX PF 0 PCIE PME And Message Disable Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disabled" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disabled" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enabled" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enabled" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enabled" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enabled" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enabled" "Disabled,Enabled" if (((per.l.be(ad:0x1EE0000+0x120))&0x800000)==0x00) group.long 0x4002C++0x03 line.long 0x00 "PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x00 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" else group.long 0x4002C++0x03 line.long 0x00 "PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" endif group.long 0x40140++0x03 line.long 0x00 "PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 0x01 " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end endian.le width 0x0B tree.end tree.end elif cpuis("LS10?3A") tree.open "PCI-E (PCI Express)" tree "PCI_1" base ad:0x3400000 width 34. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,INTx interrupt message generation disable" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implemented,Implemented" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x04 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" line.byte 0x01 "CLASS_CODE_A,PCI Express Class Code Register" line.byte 0x02 "CLASS_CODE_B,PCI Express Class Code Register" line.byte 0x03 "CLASS_CODE_C,PCI Express Class Code Register" line.byte 0x04 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" ",RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "Memory,I/O" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not used,INTA,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" width 27. rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE_PORT_TYPE ,Device/Port type" ",,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "0,1" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,?..." group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "0,1" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Scale power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink support" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED[3] ,8.0 GT/s link speed supported" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed supported" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,3.5 GT/s link speed supported" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" newline width 41. rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x03 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" group.long 0x150++0x03 line.long 0x00 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x00 3. " LANE_ERR_STATUS[3] ,Lane 3 detected a lane-based error" "No error,Error" eventfld.long 0x00 2. " [2] ,Lane 2 detected a lane-based error" "No error,Error" eventfld.long 0x00 1. " [1] ,Lane 1 detected a lane-based error" "No error,Error" newline eventfld.long 0x00 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE0_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x4)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x6)++0x01 line.word 0x00 "LANE3_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3400000+0x900))&0x80000000)==0x80000000) group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" newline bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endian.be base ad:0x3400000+0x10000 width 22. tree "PEX1_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long 0x7FC++0x03 line.long 0x00 "PF0_DBG,PEX PFa Debug Register" rbitfld.long 0x00 26.--31. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." bitfld.long 0x00 1. " SR ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " WE ,Write enable" "Disabled,Enabled" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline tree.end endian.le width 0x0B tree.end tree "PCI_2" base ad:0x3500000 width 34. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,INTx interrupt message generation disable" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implemented,Implemented" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x04 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" line.byte 0x01 "CLASS_CODE_A,PCI Express Class Code Register" line.byte 0x02 "CLASS_CODE_B,PCI Express Class Code Register" line.byte 0x03 "CLASS_CODE_C,PCI Express Class Code Register" line.byte 0x04 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" ",RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "Memory,I/O" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not used,INTA,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" width 27. rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE_PORT_TYPE ,Device/Port type" ",,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "0,1" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,?..." group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "0,1" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Scale power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink support" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED[3] ,8.0 GT/s link speed supported" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed supported" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,3.5 GT/s link speed supported" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" newline width 41. rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x03 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" group.long 0x150++0x03 line.long 0x00 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x00 1. " LANE_ERR_STATUS[1] ,Lane 1 detected a lane-based error" "No error,Error" eventfld.long 0x00 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE0_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3500000+0x900))&0x80000000)==0x80000000) group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" newline bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endian.be base ad:0x3500000+0x10000 width 22. tree "PEX2_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long 0x7FC++0x03 line.long 0x00 "PF0_DBG,PEX PFa Debug Register" rbitfld.long 0x00 26.--31. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." bitfld.long 0x00 1. " SR ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " WE ,Write enable" "Disabled,Enabled" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline tree.end endian.le width 0x0B tree.end tree "PCI_3" base ad:0x3600000 width 34. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,INTx interrupt message generation disable" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implemented,Implemented" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x04 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" line.byte 0x01 "CLASS_CODE_A,PCI Express Class Code Register" line.byte 0x02 "CLASS_CODE_B,PCI Express Class Code Register" line.byte 0x03 "CLASS_CODE_C,PCI Express Class Code Register" line.byte 0x04 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" ",RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "Memory,I/O" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not used,INTA,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" width 27. rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE_PORT_TYPE ,Device/Port type" ",,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "0,1" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,?..." group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "0,1" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Scale power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink support" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED[3] ,8.0 GT/s link speed supported" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed supported" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,3.5 GT/s link speed supported" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" newline width 41. rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x03 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" group.long 0x150++0x03 line.long 0x00 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x00 1. " LANE_ERR_STATUS[1] ,Lane 1 detected a lane-based error" "No error,Error" eventfld.long 0x00 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE0_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3600000+0x900))&0x80000000)==0x80000000) group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" newline bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endian.be base ad:0x3600000+0x10000 width 22. tree "PEX3_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long 0x7FC++0x03 line.long 0x00 "PF0_DBG,PEX PFa Debug Register" rbitfld.long 0x00 26.--31. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." bitfld.long 0x00 1. " SR ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " WE ,Write enable" "Disabled,Enabled" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline tree.end endian.le width 0x0B tree.end tree.end elif cpuis("LS10?6A") tree.open "PCI-E (PCI Express)" tree "PCI_1" base ad:0x3400000 if (((per.l(ad:0x3400000+0x0E))&0x01)==0x01) width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signalled,Signalled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" else group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI Express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI Express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit," bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status and Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.l(ad:0x3400000+0x0E))&0x01)==0x00) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 28. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.l(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.l(ad:0x3400000+0x0E))&0x01)==0x01) group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" else group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware Autonomous Width Disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." bitfld.word 0x00 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" newline bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " LSPSUP[3] ,8.0 GT/s link speed support" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed support" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,2.5 GT/s link speed support" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities and Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.l(ad:0x3400000+0x0E))&0x01)==0x01) group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" else hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 3. " LANE_ERR_STATUS[3] ,Lane 4 detected a lane-based error" "No error,Error" eventfld.long 0x04 2. " [2] ,Lane 3 detected a lane-based error" "No error,Error" eventfld.long 0x04 1. " [1] ,Lane 2 detected a lane-based error" "No error,Error" newline eventfld.long 0x04 0. " [0] ,Lane 1 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x4)++0x01 line.word 0x00 "LANE3_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x6)++0x01 line.word 0x00 "LANE4_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 39. group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR , CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" newline hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3400000+0x900))&0x80000000)==0x80000000) if (((per.l(ad:0x3400000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." endif else if (((per.l(ad:0x3400000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.l(ad:0x3400000+0x0E))&0x01)==0x00) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif endian.be base ad:0x3400000+0x80000 tree "PEX1_LUT Memory Map/Registers" width 18. group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "PELUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "PELUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "PELUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "PELUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "PELUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "PELUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "PELUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "PELUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "PELUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "PELUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "PELUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "PELUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "PELUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "PELUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "PELUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "PELUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "PELUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "PELUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "PELUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "PELUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "PELUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "PELUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "PELUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "PELUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "PELUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "PELUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "PELUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "PELUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "PELUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "PELUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "PELUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "PELUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline group.long 0x40014++0x03 line.long 0x00 "PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 31. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 17. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" bitfld.long 0x00 16. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0F line.long 0x00 "PF0_PME_MES_DR,PEX PF 0 PCIE pme and Message Detect Register" eventfld.long 0x00 24. " LUD ,Indicates a link up was detected" "Not detected,Detected" eventfld.long 0x00 22. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 21. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 18. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 16. " PTO , Indicates that PME turn off was detected" "Not detected,Detected" line.long 0x04 "PF0_PME_MES_DISR,PEX PF 0 PCIE pme and Message Disable Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" line.long 0x0C "PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x0C 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x0C 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x0C 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x0C 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" group.long 0x40140++0x03 line.long 0x00 "PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 0x01 " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end endian.le width 0x0B tree.end tree "PCI_2" base ad:0x3500000 if (((per.l(ad:0x3500000+0x0E))&0x01)==0x01) width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signalled,Signalled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" else group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI Express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI Express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit," bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status and Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.l(ad:0x3500000+0x0E))&0x01)==0x00) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 28. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.l(ad:0x3500000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.l(ad:0x3500000+0x0E))&0x01)==0x01) group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" else group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware Autonomous Width Disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." bitfld.word 0x00 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" newline bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " LSPSUP[3] ,8.0 GT/s link speed support" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed support" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,2.5 GT/s link speed support" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities and Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.l(ad:0x3500000+0x0E))&0x01)==0x01) group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" else hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 1. " LANE_ERR_STATUS[1] ,Lane 1 detected a lane-based error" "No error,Error" eventfld.long 0x04 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 39. group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR , CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" newline hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3500000+0x900))&0x80000000)==0x80000000) if (((per.l(ad:0x3500000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." endif else if (((per.l(ad:0x3500000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.l(ad:0x3500000+0x0E))&0x01)==0x00) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif endian.be base ad:0x3500000+0x80000 tree "PEX2_LUT Memory Map/Registers" width 18. group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "PELUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "PELUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "PELUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "PELUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "PELUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "PELUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "PELUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "PELUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "PELUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "PELUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "PELUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "PELUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "PELUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "PELUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "PELUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "PELUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "PELUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "PELUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "PELUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "PELUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "PELUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "PELUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "PELUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "PELUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "PELUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "PELUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "PELUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "PELUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "PELUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "PELUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "PELUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "PELUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline group.long 0x40014++0x03 line.long 0x00 "PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 31. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 17. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" bitfld.long 0x00 16. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0F line.long 0x00 "PF0_PME_MES_DR,PEX PF 0 PCIE pme and Message Detect Register" eventfld.long 0x00 24. " LUD ,Indicates a link up was detected" "Not detected,Detected" eventfld.long 0x00 22. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 21. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 18. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 16. " PTO , Indicates that PME turn off was detected" "Not detected,Detected" line.long 0x04 "PF0_PME_MES_DISR,PEX PF 0 PCIE pme and Message Disable Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" line.long 0x0C "PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x0C 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x0C 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x0C 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x0C 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" group.long 0x40140++0x03 line.long 0x00 "PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 0x01 " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end endian.le width 0x0B tree.end tree "PCI_3" base ad:0x3600000 if (((per.l(ad:0x3600000+0x0E))&0x01)==0x01) width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signalled,Signalled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" else group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI Express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI Express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI Express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI Express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI Express devices are required to implement the PCI Express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit," bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA" line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status and Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.l(ad:0x3600000+0x0E))&0x01)==0x00) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 28. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.l(ad:0x3600000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Functional level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 9.--11. " EP_L1_LAT ,Endpoint L1 acceptable latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.l(ad:0x3600000+0x0E))&0x01)==0x01) group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." rbitfld.word 0x02 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 17. " EMIP ,Electromechanical interlock present" "Not present,Present" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" else group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware Autonomous Width Disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",x1,x2,,x4,?..." bitfld.word 0x00 0.--3. " LINK_SP ,Negotiated link speed" ",2.5GT/s,5.0GT/s,8.0GT/s,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding supported" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable supported" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 9. " IDO_CPL_EN ,IDO completion enable" "Disabled,Enabled" bitfld.word 0x00 8. " IDO_REQ_EN ,IDO request enable" "Disabled,Enabled" newline bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " LSPSUP[3] ,8.0 GT/s link speed support" "Not supported,Supported" newline bitfld.long 0x00 2. " [2] ,5.0 GT/s link speed support" "Not supported,Supported" bitfld.long 0x00 1. " [1] ,2.5 GT/s link speed support" "Not supported,Supported" group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities and Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.l(ad:0x3600000+0x0E))&0x01)==0x01) group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" else hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 1. " LANE_ERR_STATUS[1] ,Lane 1 detected a lane-based error" "No error,Error" eventfld.long 0x04 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 39. group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer and Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR , CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" newline hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3600000+0x900))&0x80000000)==0x80000000) if (((per.l(ad:0x3600000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." endif else if (((per.l(ad:0x3600000+0x0E))&0x01)==0x00) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x1B line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x04 0.--7. 1. " MSG_CODE ,Message code" line.long 0x08 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x0C "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x10 "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x10 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x14 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x14 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x14 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x18 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.l(ad:0x3600000+0x0E))&0x01)==0x00) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK_EP,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR Mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif endian.be base ad:0x3600000+0x80000 tree "PEX3_LUT Memory Map/Registers" width 18. group.long 0x20++0x07 line.long 0x00 "LUT_PEXLSR,PEX LUT Status Register" hexmask.long.word 0x00 16.--31. 1. " CREQID ,Captured REQID" eventfld.long 0x00 1. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" eventfld.long 0x00 0. " LUTM ,Lookup table miss" "Not missed,Missed" line.long 0x04 "LUT_PEXLCR,PEX LUT Control Register" hexmask.long.word 0x04 17.--31. 1. " DICID ,Default isolation context ID" bitfld.long 0x04 1. " DBMT ,Default bypass memory translation" "0,1" bitfld.long 0x04 0. " DPL ,Default privilege level" "0,1" group.long (0x800+0x0)++0x07 line.long 0x00 "LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" line.long 0x04 "PELUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x8)++0x07 line.long 0x00 "LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" line.long 0x04 "PELUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x10)++0x07 line.long 0x00 "LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" line.long 0x04 "PELUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x18)++0x07 line.long 0x00 "LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" line.long 0x04 "PELUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x20)++0x07 line.long 0x00 "LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" line.long 0x04 "PELUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x28)++0x07 line.long 0x00 "LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" line.long 0x04 "PELUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x30)++0x07 line.long 0x00 "LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" line.long 0x04 "PELUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x38)++0x07 line.long 0x00 "LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" line.long 0x04 "PELUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x40)++0x07 line.long 0x00 "LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" line.long 0x04 "PELUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x48)++0x07 line.long 0x00 "LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" line.long 0x04 "PELUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x50)++0x07 line.long 0x00 "LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" line.long 0x04 "PELUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x58)++0x07 line.long 0x00 "LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" line.long 0x04 "PELUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x60)++0x07 line.long 0x00 "LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" line.long 0x04 "PELUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x68)++0x07 line.long 0x00 "LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" line.long 0x04 "PELUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x70)++0x07 line.long 0x00 "LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" line.long 0x04 "PELUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x78)++0x07 line.long 0x00 "LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" line.long 0x04 "PELUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x80)++0x07 line.long 0x00 "LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" line.long 0x04 "PELUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x88)++0x07 line.long 0x00 "LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" line.long 0x04 "PELUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x90)++0x07 line.long 0x00 "LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" line.long 0x04 "PELUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0x98)++0x07 line.long 0x00 "LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" line.long 0x04 "PELUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA0)++0x07 line.long 0x00 "LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" line.long 0x04 "PELUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xA8)++0x07 line.long 0x00 "LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" line.long 0x04 "PELUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB0)++0x07 line.long 0x00 "LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" line.long 0x04 "PELUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xB8)++0x07 line.long 0x00 "LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" line.long 0x04 "PELUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC0)++0x07 line.long 0x00 "LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" line.long 0x04 "PELUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xC8)++0x07 line.long 0x00 "LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" line.long 0x04 "PELUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD0)++0x07 line.long 0x00 "LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" line.long 0x04 "PELUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xD8)++0x07 line.long 0x00 "LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" line.long 0x04 "PELUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE0)++0x07 line.long 0x00 "LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" line.long 0x04 "PELUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xE8)++0x07 line.long 0x00 "LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" line.long 0x04 "PELUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF0)++0x07 line.long 0x00 "LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" line.long 0x04 "PELUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" group.long (0x800+0xF8)++0x07 line.long 0x00 "LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" line.long 0x04 "PELUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" hexmask.long.word 0x04 17.--31. 1. " ICID ,Isolation context ID" bitfld.long 0x04 2. " BMT ,Bypass memory translation" "0,1" bitfld.long 0x04 1. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" newline bitfld.long 0x04 0. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" newline group.long 0x40014++0x03 line.long 0x00 "PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 31. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 17. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" bitfld.long 0x00 16. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0F line.long 0x00 "PF0_PME_MES_DR,PEX PF 0 PCIE pme and Message Detect Register" eventfld.long 0x00 24. " LUD ,Indicates a link up was detected" "Not detected,Detected" eventfld.long 0x00 22. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 21. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 18. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 16. " PTO , Indicates that PME turn off was detected" "Not detected,Detected" line.long 0x04 "PF0_PME_MES_DISR,PEX PF 0 PCIE pme and Message Disable Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" line.long 0x0C "PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x0C 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x0C 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x0C 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x0C 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" group.long 0x40140++0x03 line.long 0x00 "PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 0x01 " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end endian.le width 0x0B tree.end tree.end else tree.open "PCI-E (PCI Express)" tree "PCI_1" base ad:0x3400000 if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) width 22. group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" else width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB-CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." newline width 34. group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 15. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 28. newline rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Function level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" else group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding support" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED_VECTOR_8 ,Supported link speeds vector 8.0 GT/s" "0,1" newline bitfld.long 0x00 2. " SUPPORT_LINK_SPEED_VECTOR_5 ,Supported link speeds vector 5.0 GT/s" "0,1" bitfld.long 0x00 1. " SUPPORT_LINK_SPEED_VECTOR_2 ,Supported link speeds vector 2.5 GT/s" "0,1" newline group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 29. if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) rgroup.byte 0xB0++0x00 line.byte 0x00 "MSI_X_MESSAGE_CAPABILITY_ID,PCI Express MSI-X Message Capability ID Register" group.word 0xB2++0x01 line.word 0x00 "MSI_X_MESSAGE_CONTROL,PCI Express MSI-X Message Control Register" bitfld.word 0x00 15. " MSIXE ,MSI-X functionality enable" "Disabled,Enabled" bitfld.word 0x00 14. " FM ,Function mask" "Not masked,Masked" hexmask.word 0x00 0.--10. 1. " TS ,Table size" group.long 0xB4++0x07 line.long 0x00 "MSI_X_TABLE_OFFSET/BIR,PCI Express MSI-X Table Offset/BIR Register" hexmask.long 0x00 3.--31. 0x08 " TO ,Table offset" bitfld.long 0x00 0.--2. " TBIR ,Function's base address register used to map MSI-X table into memory space" "10h,14h,18h,1Ch,20h,24h,?..." line.long 0x04 "MSI_X_PBA_OFFSET_BIR,PCI Express MSI-X PBA Offset/BIR Register" hexmask.long 0x04 3.--31. 0x08 " PBA_OFFSET ,PBA offset" bitfld.long 0x04 0.--2. " PBIR ,Function's base address registers used to map MSI-X PBA into memory space" "10h,14h,18h,1Ch,20h,24h,?..." else hgroup.byte 0xB0++0x00 hide.byte 0x00 "MSI_X_MESSAGE_CAPABILITY_ID,PCI Express MSI-X Message Capability ID Register" hgroup.word 0xB2++0x01 hide.word 0x00 "MSI_X_MESSAGE_CONTROL,PCI Express MSI-X Message Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "MSI_X_TABLE_OFFSET/BIR,PCI Express MSI-X Table Offset/BIR Register" hgroup.long 0xB8++0x03 hide.long 0x00 "MSI_X_PBA_OFFSET/BIR,PCI Express MSI-X PBA Offset/BIR Register" endif width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" else group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "ARI_CAPABILITY_HEADER,ARI Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAPABILITY_ID ,ARI extended capability" rgroup.word 0x14C++0x03 line.word 0x00 "ARI_CAPABILITY,ARI Capability Register" hexmask.word.byte 0x00 8.--15. 1. " NFN ,Next function number" bitfld.word 0x00 1. " AFGC ,ARI device support of function group level granularity for ACS P2P egress control" "Not supported,Supported" bitfld.word 0x00 0. " MFGC ,ARI device support of function group level arbitration via MFVC" "Not supported,Supported" line.word 0x02 "ARI_CONTROL,ARI Control Register" bitfld.word 0x02 4.--6. " FG ,Function group number of this function" "0,1,2,3,4,5,6,7" bitfld.word 0x02 1. " AFGE ,ACS function groups enable" "Disabled,Enabled" bitfld.word 0x02 0. " MFGE ,MFVC function groups enable" "Disabled,Enabled" rgroup.long 0x158++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x15C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 3. " LANE_ERR_STATUS[3] ,Lane 4 detected a lane-based error" "Not detected,Detected" eventfld.long 0x04 2. " [2] ,Lane 3 detected a lane-based error" "Not detected,Detected" eventfld.long 0x04 1. " [1] ,Lane 2 detected a lane-based error" "Not detected,Detected" newline eventfld.long 0x04 0. " [0] ,Lane 1 detected a lane-based error" "Not detected,Detected" rgroup.word (0x164+0x0)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x164+0x2)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x164+0x4)++0x01 line.word 0x00 "LANE3_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x164+0x6)++0x01 line.word 0x00 "LANE4_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 38. rgroup.long 0x178++0x07 line.long 0x00 "SR_IOV_EXTENDED_CAPABILITY_ID,PCI Express SR-IOV Extended Capability ID Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_CAPABILITY_OFFSET ,Next capability offset" bitfld.long 0x00 16.--19. " CAPABILITY_VERSION ,Capability version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAPABILITY_ID ,PCI express extended capability ID" line.long 0x04 "SR_IOV_CAPABILITIES,PCI Express SR-IOV Capabilities Register" hexmask.long.word 0x04 21.--31. 1. " VFMIMN ,VF migration interrupt message number" bitfld.long 0x04 1. " ARICHR ,ARI capable hierarchy preserved" "Not preserved,Preserved" bitfld.long 0x04 0. " VFMC ,VF migration capable" "Not capable,Capable" rgroup.word 0x180++0x07 line.word 0x00 "SR_IOV_CONTROL,PCI Express SR-IOV Control Register" bitfld.word 0x00 4. " ARICH ,ARI capable hierarchy" "0,1" bitfld.word 0x00 3. " VFMSE ,Memory space enable for virtual functions" "Disabled,Enabled" bitfld.word 0x00 2. " VFMIE ,VF migration interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " VFME ,VF migration enable" "Disabled,Enabled" bitfld.word 0x00 0. " VFE ,VF enable" "Disabled,Enabled" line.word 0x02 "SR_IOV_STATUS,PCI Express SR-IOV Status Register" bitfld.word 0x02 0. " VFMS ,VF migration status" "In,Out" line.word 0x04 "SR_IOV_INITIAL_VF,PCI Express SR-IOV Initial VF Register" line.word 0x06 "SR_IOV_TOTAL_VF,PCI Express SR-IOV Total VF Register" group.word 0x188++0x01 line.word 0x00 "SR_IOV_NUMBER_VF,PCI Express SR-IOV Number VF Register" group.byte 0x18A++0x00 line.byte 0x00 "SR_IOV_FUNCTION_DEPENDENCY_LINK,PCI Express SR-IOV Function Dependency Link Register" rgroup.word 0x18C++0x03 line.word 0x00 "SR_IOV_FIRST_VF_OFFSET,PCI Express SR-IOV First VF Offset Register" line.word 0x02 "SR_IOV_VF_STRIDE,PCI Express SR-IOV VF Stride Register" rgroup.word 0x192++0x01 line.word 0x00 "SR_IOV_DEVICE_ID,PCI Express SR-IOV Device ID Register" rgroup.long 0x194++0x03 line.long 0x00 "SR_IOV_SUPPORTED_PAGE_SIZE,PCI Express SR-IOV Supported Page Size Register" group.long 0x198++0x1B line.long 0x00 "SR_IOV_SYSTEM_PAGE_SIZE,PCI Express SR-IOV System Page Size Register" line.long 0x04 "VFBAR0,PCI Express SR-IOV VF Base Address Register 0" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address where the inbound memory window begins" rbitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" rbitfld.long 0x04 1.--2. " TYPE ,Type" "Anywhere/32-bit,?..." line.long 0x08 "VFBAR1,PCI Express SR-IOV VF Base Address Register 1" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address where the inbound memory window begins" rbitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" rbitfld.long 0x08 1.--2. " TYPE ,Type" "Anywhere/32-bit,?..." line.long 0x0C "VFBAR2,PCI Express SR-IOV VF Base Address Register 2" hexmask.long.tbyte 0x0C 12.--31. 0x10 " ADDRESS ,Indicates the base address where the inbound memory window begins" rbitfld.long 0x0C 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" rbitfld.long 0x0C 1.--2. " TYPE ,Type" ",,Anywhere/64-bit,?..." line.long 0x10 "VFBAR3,PCI Express SR-IOV VF Base Address Register 3" line.long 0x14 "VFBAR4,PCI Express SR-IOV VF Base Address Register 4" hexmask.long.tbyte 0x14 12.--31. 0x10 " ADDRESS ,Indicates the base address where the inbound memory window begins" rbitfld.long 0x14 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" rbitfld.long 0x14 1.--2. " TYPE ,Type" ",,Anywhere/64-bit,?..." line.long 0x18 "VFBAR5,PCI Express SR-IOV VF Base Address Register 5" rgroup.long 0x1B4++0x03 line.long 0x00 "SR_IOV_MIGRATION_STATE_ARRAY_OFFSET,PCI Express SR-IOV Migration State Array Offset Register" hexmask.long 0x00 3.--31. 0x08 " MSAO ,VF migration state offset" bitfld.long 0x00 0.--2. " MSBIR ,VF migration state BIR" "0,1,2,3,4,5,6,7" width 39. newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3400000+0x900))&0x80000000)==0x80000000) if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" endif group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else if (((per.l(ad:0x01E00000+0x13C))&(0x10<<1))==(0x10<<1)) group.long 0x904++0x03 line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" newline bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x904++0x03 line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x908++0x17 line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x00 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x00 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE ,Message code" line.long 0x04 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x04 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x08 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x0C "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x0C 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x10 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x10 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x14 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif base ad:0x3400000+0x80000 tree "PEX1_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "PEX_LUT_PEXLSR,PEX LUT Status Register" eventfld.long 0x00 31. " LUTM ,Lookup table miss" "Not missed,Missed" eventfld.long 0x00 30. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" hexmask.long.word 0x00 0.--15. 1. " CREQID ,Captured REQID" line.long 0x04 "PEX_LUT_PEXLCR,PEX LUT Control Register" bitfld.long 0x04 31. " DPL ,Default privilege level" "0,1" bitfld.long 0x04 30. " DBMT ,Default bypass memory translation" "0,1" hexmask.long.word 0x04 0.--14. 1. " DICID ,Default isolation context ID" group.long (0x800+0x0)++0x07 line.long 0x00 "PEX_LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x8)++0x07 line.long 0x00 "PEX_LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x10)++0x07 line.long 0x00 "PEX_LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x18)++0x07 line.long 0x00 "PEX_LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x20)++0x07 line.long 0x00 "PEX_LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x28)++0x07 line.long 0x00 "PEX_LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x30)++0x07 line.long 0x00 "PEX_LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x38)++0x07 line.long 0x00 "PEX_LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x40)++0x07 line.long 0x00 "PEX_LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x48)++0x07 line.long 0x00 "PEX_LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x50)++0x07 line.long 0x00 "PEX_LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x58)++0x07 line.long 0x00 "PEX_LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x60)++0x07 line.long 0x00 "PEX_LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x68)++0x07 line.long 0x00 "PEX_LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x70)++0x07 line.long 0x00 "PEX_LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x78)++0x07 line.long 0x00 "PEX_LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x80)++0x07 line.long 0x00 "PEX_LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x88)++0x07 line.long 0x00 "PEX_LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x90)++0x07 line.long 0x00 "PEX_LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x98)++0x07 line.long 0x00 "PEX_LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA0)++0x07 line.long 0x00 "PEX_LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA8)++0x07 line.long 0x00 "PEX_LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB0)++0x07 line.long 0x00 "PEX_LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB8)++0x07 line.long 0x00 "PEX_LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC0)++0x07 line.long 0x00 "PEX_LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC8)++0x07 line.long 0x00 "PEX_LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD0)++0x07 line.long 0x00 "PEX_LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD8)++0x07 line.long 0x00 "PEX_LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE0)++0x07 line.long 0x00 "PEX_LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE8)++0x07 line.long 0x00 "PEX_LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF0)++0x07 line.long 0x00 "PEX_LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF8)++0x07 line.long 0x00 "PEX_LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" newline group.long 0x40014++0x03 line.long 0x00 "PEX_PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 0. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PEX_PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 15. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" bitfld.long 0x00 14. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0B line.long 0x00 "PEX_PF0_PME_MES_DR,PEX PF 0 PCIE PME And Message Detect Register" eventfld.long 0x00 15. " PTO ,Indicates that PME turn off was detected" "Not detected,Detected" eventfld.long 0x00 13. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 12. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" newline eventfld.long 0x00 10. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" eventfld.long 0x00 9. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 7. " LUD ,Indicates a link up was detected" "Not detected,Detected" line.long 0x04 "PEX_PF0_PME_MES_DISR,PEX PF 0 PCIE PME And Message Disabled Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PEX_PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" group.long 0x50014++0x03 line.long 0x00 "PEX_PF1_CONFIG,PEX PF 1 Config Register" bitfld.long 0x00 0. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x50018++0x03 line.long 0x00 "PEX_PF1_INT_STAT,PEX PF 1 Interrupt Status Register" bitfld.long 0x00 15. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" bitfld.long 0x00 14. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" group.long 0x50020++0x0B line.long 0x00 "PEX_PF1_PME_MES_DR,PEX PF 1 PCIE PME And Message Detect Register" eventfld.long 0x00 15. " PTO ,Indicates that PME turn off was detected" "Not detected,Detected" eventfld.long 0x00 13. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 12. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" newline eventfld.long 0x00 10. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" eventfld.long 0x00 9. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 7. " LUD ,Indicates a link up was detected" "Not detected,Detected" line.long 0x04 "PEX_PF1_PME_MES_DISR,PEX PF 1 PCIE PME And Message Disable Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PEX_PF1_PME_MES_IER,PEX PF 1 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" if (((per.b(ad:0x3400000+0x0E))&0x01)==0x01) group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" else group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x00 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" endif group.long 0x40140++0x03 line.long 0x00 "PEX_PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 1. " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PEX_PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PEX_PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407F8++0x03 line.long 0x00 "PEX_PF0_VF,PEX PF 0 VF Control Register" bitfld.long 0x00 22.--27. " VF ,Virtual function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " VF_ACT ,VF active" "Inactive,Active" group.long 0x50140++0x03 line.long 0x00 "PEX_PF1_RBP_ADDR_U,PEX PF 1 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 1. " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x50200++0x03 line.long 0x00 "PEX_PF1_ERR_DR,PEX PF 1 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x50208++0x03 line.long 0x00 "PEX_PF1_ERR_EN,PEX PF 1 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x50210++0x03 line.long 0x00 "PEX_PF1_ERR_DISR,PEX PF 1 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x507F8++0x03 line.long 0x00 "PEX_PF1_VF,PEX PF 1 VF Control Register" bitfld.long 0x00 22.--27. " VF ,Virtual function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " VF_ACT ,VF active" "Inactive,Active" group.long 0x407FC++0x03 line.long 0x00 "PEX_PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" newline rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." if (((per.l(ad:0x01E00000+0x13C))&(0x10<<1))==(0x10<<1)) group.long 0x5002C++0x03 line.long 0x00 "PEX_PF1_MCR,PEX PF 1 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" else group.long 0x5002C++0x03 line.long 0x00 "PEX_PF1_MCR,PEX PF 1 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x00 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" endif tree.end width 0x0B tree.end tree "PCI_2" base ad:0x3500000 if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) width 22. group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" else width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB-CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." newline width 34. group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 15. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 28. newline rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Function level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" else group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding support" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED_VECTOR_8 ,Supported link speeds vector 8.0 GT/s" "0,1" newline bitfld.long 0x00 2. " SUPPORT_LINK_SPEED_VECTOR_5 ,Supported link speeds vector 5.0 GT/s" "0,1" bitfld.long 0x00 1. " SUPPORT_LINK_SPEED_VECTOR_2 ,Supported link speeds vector 2.5 GT/s" "0,1" newline group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" else group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 0. " LANE_ERR_STATUS[0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word 0x154++0x01 line.word 0x00 "LANE0_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 38. width 39. newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3500000+0x900))&0x80000000)==0x80000000) if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" endif group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x03 line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x908++0x17 line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x00 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x00 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE ,Message code" line.long 0x04 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x04 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x08 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x0C "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x0C 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x10 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x10 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x14 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif base ad:0x3500000+0x80000 tree "PEX2_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "PEX_LUT_PEXLSR,PEX LUT Status Register" eventfld.long 0x00 31. " LUTM ,Lookup table miss" "Not missed,Missed" eventfld.long 0x00 30. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" hexmask.long.word 0x00 0.--15. 1. " CREQID ,Captured REQID" line.long 0x04 "PEX_LUT_PEXLCR,PEX LUT Control Register" bitfld.long 0x04 31. " DPL ,Default privilege level" "0,1" bitfld.long 0x04 30. " DBMT ,Default bypass memory translation" "0,1" hexmask.long.word 0x04 0.--14. 1. " DICID ,Default isolation context ID" group.long (0x800+0x0)++0x07 line.long 0x00 "PEX_LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x8)++0x07 line.long 0x00 "PEX_LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x10)++0x07 line.long 0x00 "PEX_LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x18)++0x07 line.long 0x00 "PEX_LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x20)++0x07 line.long 0x00 "PEX_LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x28)++0x07 line.long 0x00 "PEX_LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x30)++0x07 line.long 0x00 "PEX_LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x38)++0x07 line.long 0x00 "PEX_LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x40)++0x07 line.long 0x00 "PEX_LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x48)++0x07 line.long 0x00 "PEX_LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x50)++0x07 line.long 0x00 "PEX_LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x58)++0x07 line.long 0x00 "PEX_LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x60)++0x07 line.long 0x00 "PEX_LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x68)++0x07 line.long 0x00 "PEX_LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x70)++0x07 line.long 0x00 "PEX_LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x78)++0x07 line.long 0x00 "PEX_LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x80)++0x07 line.long 0x00 "PEX_LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x88)++0x07 line.long 0x00 "PEX_LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x90)++0x07 line.long 0x00 "PEX_LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x98)++0x07 line.long 0x00 "PEX_LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA0)++0x07 line.long 0x00 "PEX_LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA8)++0x07 line.long 0x00 "PEX_LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB0)++0x07 line.long 0x00 "PEX_LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB8)++0x07 line.long 0x00 "PEX_LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC0)++0x07 line.long 0x00 "PEX_LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC8)++0x07 line.long 0x00 "PEX_LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD0)++0x07 line.long 0x00 "PEX_LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD8)++0x07 line.long 0x00 "PEX_LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE0)++0x07 line.long 0x00 "PEX_LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE8)++0x07 line.long 0x00 "PEX_LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF0)++0x07 line.long 0x00 "PEX_LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF8)++0x07 line.long 0x00 "PEX_LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" newline group.long 0x40014++0x03 line.long 0x00 "PEX_PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 0. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PEX_PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 15. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" bitfld.long 0x00 14. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0B line.long 0x00 "PEX_PF0_PME_MES_DR,PEX PF 0 PCIE PME And Message Detect Register" eventfld.long 0x00 15. " PTO ,Indicates that PME turn off was detected" "Not detected,Detected" eventfld.long 0x00 13. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 12. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" newline eventfld.long 0x00 10. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" eventfld.long 0x00 9. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 7. " LUD ,Indicates a link up was detected" "Not detected,Detected" line.long 0x04 "PEX_PF0_PME_MES_DISR,PEX PF 0 PCIE PME And Message Disabled Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PEX_PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" if (((per.b(ad:0x3500000+0x0E))&0x01)==0x01) group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" else group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x00 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" endif group.long 0x40140++0x03 line.long 0x00 "PEX_PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 1. " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PEX_PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PEX_PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PEX_PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" newline rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end width 0x0B tree.end tree "PCI_3" base ad:0x3600000 if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) width 22. group.word 0x00++0x07 "Type 0 [EP mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" newline bitfld.word 0x04 1. " MEMORY_SPACE ,Controls whether this PCI express device (as a target) responds to memory accesses" "No response,Response" rbitfld.word 0x04 0. " I/O_SPACE ,Response behavior to PCI express I/O space accesses" "No response,Response" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requester receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requester when the requester receives a completion marked poisoned or the requester poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB_CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x17 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x04 "BAR1,PCI Express Base Address Register 1" hexmask.long.tbyte 0x04 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x04 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x04 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x04 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x08 "BAR2,PCI Express Base Address Register 2" hexmask.long.tbyte 0x08 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x08 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x08 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x08 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x0C "BAR3,PCI Express Base Address Register 3" line.long 0x10 "BAR4,PCI Express Base Address Register 4" hexmask.long.tbyte 0x10 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x10 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x10 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,,Locate anywhere/64-bit,?..." bitfld.long 0x10 0. " MEMSP ,Memory space indicator" "0,1" line.long 0x14 "BAR5,PCI Express Base Address Register 5" rgroup.word 0x2C++0x03 line.word 0x00 "SUBSYSTEM_VENDOR_ID,PCI Express Subsystem Vendor ID Register" line.word 0x02 "SUBSYSTEM_ID,PCI Express Subsystem ID Register" group.long 0x30++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x02 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." line.byte 0x01 "MINIMUM_GRANT,PCI Express Minimum Grant Register" line.byte 0x02 "MAXIMUM_LATENCY,PCI Express Maximum Latency Register" else width 27. group.word 0x00++0x07 "Type 1 [RC mode]" line.word 0x00 "VENDOR_ID,PCI Express Vendor ID Register" line.word 0x02 "DEVICE_ID,PCI Express Device ID Register" line.word 0x04 "COMMAND,PCI Express Command Register" bitfld.word 0x04 10. " INTERRUPT_DISABLE ,Controls the ability to generate INTx interrupt messages" "No,Yes" bitfld.word 0x04 8. " SERR ,Controls the reporting of fatal and non-fatal errors detected by the device to the root complex" "Disabled,Enabled" newline bitfld.word 0x04 6. " PARITY_ERROR_RESPONSE ,Controls whether this PCI express controller responds to parity errors" "No response,Response" bitfld.word 0x04 2. " BUS_MASTER ,Indicates whether this PCI express device is configured as a master" "Non master,Master" line.word 0x06 "STATUS,PCI Express Status Register" eventfld.word 0x06 15. " DETECTED_PARITY_ERROR ,Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command register" "No error,Error" eventfld.word 0x06 14. " SIGNALED_SYSTEM_ERROR ,Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set" "No error,Error" newline eventfld.word 0x06 13. " RECEIVED_MASTER_ABORT ,Set whenever a requestor receives a completion with unsupported request completion status" "Not received,Received" eventfld.word 0x06 12. " RECEIVED_TARGET_ABORT ,Set whenever a device receives a completion with completer abort completion status" "Not received,Received" newline eventfld.word 0x06 11. " SIGNALED_TARGET_ABORT ,Set whenever a device completes a request using completer abort completion status" "Not signaled,Signaled" eventfld.word 0x06 8. " MASTER_DATA_PARITY_ERROR_DETECTED ,Set by requestor when the requestor receives a completion marked poisoned or the requestor poisons a write request" "No error,Error" newline eventfld.word 0x06 4. " CAPABILITIES_LIST ,All PCI express devices are required to implement the PCI express capability structure" "Not implement,Implement" eventfld.word 0x06 3. " INTERRUPT_STATUS ,Set when an INTx interrupt message is pending internally to the device" "No interrupt,Interrupt" group.byte 0x08++0x00 line.byte 0x00 "REVISION_ID,PCI Express Revision ID Register" group.tbyte 0x09++0x02 line.tbyte 0x00 "CLASS_CODE,PCI Express Class Code Register" hexmask.tbyte.byte 0x00 16.--23. 1. " BASE_CLASS ,Base class" hexmask.tbyte.byte 0x00 8.--15. 1. " SUB-CLASS ,Sub-class" newline hexmask.tbyte.byte 0x00 0.--7. 1. " PROGRAMMING_INTERFACE ,Programming interface" group.byte 0x0C++0x00 line.byte 0x00 "CACHE_LINE_SIZE,PCI Express Cache Line Size Register" rgroup.byte 0x0D++0x01 line.byte 0x00 "LATENCY_TIMER,PCI Express Latency Timer Register" line.byte 0x01 "HEADER_TYPE,PCI Express Header Type Register" bitfld.byte 0x01 7. " MULTIFUNCTION ,Identifies whether a device supports multiple functions" "Single,Multiple" newline bitfld.byte 0x01 0. " HEADER_LAYOUT ,Header layout" "EP,RC" group.long 0x10++0x03 line.long 0x00 "BAR0,PCI Express Base Address Register 0" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDRESS ,Indicates the base address of the inbound memory window" bitfld.long 0x00 3. " PREF ,Prefetchable" "Not prefetchable,Prefetchable" newline bitfld.long 0x00 1.--2. " TYPE ,Type" "Locate anywhere/32-bit,?..." bitfld.long 0x00 0. " MEMSP ,Memory space indicator" "0,1" group.byte 0x18++0x02 line.byte 0x00 "PRIMARY_BUS_NUMBER,PCI Express Primary Bus Number Register" line.byte 0x01 "SECONDARY_BUS_NUMBER,PCI Express Secondary Bus Number Register" line.byte 0x02 "SUBORDINATE_BUS_NUMBER,PCI Express Subordinate Bus Number Register" group.byte 0x1C++0x01 line.byte 0x00 "IO_BASE,PCI Express I/O Base Register" hexmask.byte 0x00 4.--7. 0x10 " I/O_START_ADDRESS ,Specifies bits 15:12 of the I/O space start address" rbitfld.byte 0x00 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." line.byte 0x01 "IO_LIMIT,PCI Express I/O Limit Register" hexmask.byte 0x01 4.--7. 0x10 " I/O_LIMIT_ADDRESS ,Specifies bits 15:12 of the I/O space ending address" rbitfld.byte 0x01 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of I/O address bits" "16-bit,32-bit,?..." group.word 0x1E++0x09 line.word 0x00 "SECONDARY_STATUS,PCI Express Secondary Status Register" eventfld.word 0x00 15. " DPE ,Detected parity error" "Not detected,Detected" eventfld.word 0x00 14. " SSE ,Signaled system error" "Not signaled,Signaled" newline eventfld.word 0x00 13. " RMA ,Received master abort" "Not received,Received" eventfld.word 0x00 12. " RTA ,Received target abort" "Not received,Received" newline eventfld.word 0x00 11. " STA ,Signaled target abort" "Not signaled,Signaled" eventfld.word 0x00 8. " MDPE ,Master data parity error" "No error,Error" line.word 0x02 "MEMORY_BASE,PCI Express Memory Base Register" hexmask.word 0x02 4.--15. 0x10 " MEMORY_BASE ,Specifies bits 31:20 of the non-prefetchable memory space start address" line.word 0x04 "MEMORY_LIMIT,PCI Express Memory Limit Register" hexmask.word 0x04 4.--15. 0x10 " MEMORY_LIMIT ,Specifies bits 31:20 of the non-prefetchable memory space ending address" line.word 0x06 "PREFETCHABLE_MEMORY_BASE,PCI Express Prefetchable Memory Base Register" hexmask.word 0x06 4.--15. 0x10 " PF_MEMORY_BASE ,Specifies bits 31:20 of the prefetchable memory space start address" rbitfld.word 0x06 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." line.word 0x08 "PREFETCHABLE_MEMORY_LIMIT,PCI Express Prefetchable Memory Limit Register" hexmask.word 0x08 4.--15. 0x10 " PF_MEMORY_LIMIT ,Specifies bits 31:20 of the prefetchable memory space ending address" rbitfld.word 0x08 0.--3. " ADDRESS_DECODE_TYPE ,Specifies the number of prefetchable memory address bits" "32-bit,64-bit,?..." newline width 34. group.long 0x28++0x07 line.long 0x00 "PREFETCHABLE_BASE_UPPER_32_BITS,PCI Express Prefetchable Base Upper 32 Bits Register" line.long 0x04 "PREFETCHABLE_LIMIT_UPPER_32_BITS,PCI Express Prefetchable Limit Upper 32 Bits Register" newline width 27. rgroup.word 0x30++0x03 line.word 0x00 "I/O_BASE_UPPER_16_BITS,PCI Express I/O Base Upper 16 Bits Register" line.word 0x02 "I/O_LIMIT_UPPER_16_BITS,PCI Express I/O Limit Upper 16 Bits Register" rgroup.byte 0x34++0x00 line.byte 0x00 "CAPABILITIES_POINTER,Capabilities Pointer Register" group.long 0x38++0x03 line.long 0x00 "EXPANSION_ROM_BAR,PCI Express Expansion ROM Base Address Register" hexmask.long.tbyte 0x00 11.--31. 0x08 " ROM_BASE_ADDRESS ,Specifies bits 31:11 of the non-prefetchable expansion ROM space start address" bitfld.long 0x00 0. " ROMBAR_EN ,Address decode enable" "Disabled,Enabled" group.byte 0x3C++0x00 line.byte 0x00 "INTERRUPT_LINE,PCI Express Interrupt Line Register" rgroup.byte 0x3D++0x00 line.byte 0x00 "INTERRUPT_PIN,PCI Express Interrupt Pin Register" bitfld.byte 0x00 0.--2. " INTERRUPT_PIN ,Interrupt pin" "Not supported,INTA,INTB,INTC,INTD,?..." group.word 0x3E++0x01 line.word 0x00 "BRIDGE_CONTROL,PCI Express Bridge Control Register" bitfld.word 0x00 6. " SCND_RST ,Secondary bus reset" "No reset,Reset" bitfld.word 0x00 3. " VGA_EN ,VGA enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ISA_EN ,ISA enable" "Disabled,Enabled" bitfld.word 0x00 1. " SERR_EN ,SERR enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " PER ,Parity error response" "No response,Response" endif newline width 38. rgroup.byte 0x40++0x00 line.byte 0x00 "POWER_MANAGEMENT_CAPABILITY_ID,PCI Express Power Management Capability ID Register" rgroup.word 0x42++0x01 line.word 0x00 "POWER_MANAGEMENT_CAPABILITIES,PCI Express Power Management Capabilities Register" bitfld.word 0x00 15. " PME_SUPPORT[4] ,PME power state support bit 4" "Not supported,Supported" bitfld.word 0x00 14. " [3] ,PME power state support bit 3" "Not supported,Supported" bitfld.word 0x00 13. " [2] ,PME power state support bit 2" "Not supported,Supported" newline bitfld.word 0x00 12. " [1] ,PME power state support bit 1" "Not supported,Supported" bitfld.word 0x00 11. " [0] ,PME power state support bit 0" "Not supported,Supported" bitfld.word 0x00 10. " D2 ,D2 support" "Not supported,Supported" newline bitfld.word 0x00 9. " D1 ,D1 support" "Not supported,Supported" bitfld.word 0x00 6.--8. " AUX_CURR ,AUX current" "0,1,2,3,4,5,6,7" bitfld.word 0x00 5. " DSI ,Device specific initialization" "0,1" newline bitfld.word 0x00 3. " PME_CLK ,PME clock" "0,1" bitfld.word 0x00 0.--2. " VERSION ,Version of the specification" "0,1,2,3,4,5,6,7" group.word 0x44++0x01 line.word 0x00 "POWER_MANAGEMENT_STATUS_AND_CONTROL,PCI Express Power Management Status And Control Register" eventfld.word 0x00 15. " PME_STAT ,PME status" "0,1" bitfld.word 0x00 13.--14. " DATA_SCALE ,Data scale field" "0,1,2,3" bitfld.word 0x00 9.--12. " DATA_SELECT ,Data select field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 8. " PME_EN ,PME enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " POWER_STATE ,Indicates the current power state of the function" "D0,D1,D2,D3" rgroup.byte 0x47++0x00 line.byte 0x00 "POWER_MANAGEMENT_DATA,PCI Express Power Management Data Register" newline width 28. if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) rgroup.byte 0x50++0x00 line.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" group.word 0x52++0x01 line.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" rbitfld.word 0x00 7. " 64AC ,64-bit address capable" "Not capable,Capable" bitfld.word 0x00 4.--6. " MME ,Multiple message enable" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 1.--3. " MMC ,Multiple message capable" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0. " MSIE ,MSI enable" "Disabled,Enabled" group.long 0x54++0x07 line.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hexmask.long 0x00 2.--31. 0x04 " MESSAGE_ADDRESS ,System-specified message address" line.long 0x04 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" group.word 0x5C++0x01 line.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" else hgroup.byte 0x50++0x00 hide.byte 0x00 "MSI_MESSAGE_CAPABILITY_ID,PCI Express MSI Message Capability ID Register" hgroup.word 0x52++0x01 hide.word 0x00 "MSI_MESSAGE_CONTROL,PCI Express MSI Message Control Register" hgroup.long 0x54++0x03 hide.long 0x00 "MSI_MESSAGE_ADDRESS,PCI Express MSI Message Address Register" hgroup.long 0x58++0x03 hide.long 0x00 "MSI_MESSAGE_UPPER_ADDRESS,PCI Express MSI Message Upper Address Register" hgroup.word 0x5C++0x01 hide.word 0x00 "MSI_MESSAGE_DATA,PCI Express MSI Message Data Register" endif width 15. newline rgroup.byte 0x70++0x00 line.byte 0x00 "CAPABILITY_ID,PCI Express Capability ID Register" if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.word 0x72++0x01 line.word 0x00 "CAPABILITIES,PCI Express Capabilities Register" bitfld.word 0x00 9.--13. " INTERRUPT_MESSAGE_NUMBER ,Contains offset between base message data and the MSI message that is generated when any of the status bits are set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. " SLOT ,Slot implemented" "Not implemented,Implemented" bitfld.word 0x00 4.--7. " DEVICE/PORT_TYPE ,Device/Port type" "EP mode,,,,RC mode,?..." newline bitfld.word 0x00 0.--3. " CAPABILITY_VERSION ,Indicates the defined PCI express capability structure version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 28. newline rgroup.long 0x74++0x03 line.long 0x00 "DEVICE_CAPABILITIES,PCI Express Device Capabilities Register" bitfld.long 0x00 28. " FLRC ,Function level reset capability" "0,1" bitfld.long 0x00 26.--27. " CSPLS ,Captured slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 18.--25. 1. " CSPLV ,Captured slot power limit value" newline bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 15. " RBER ,Role based error reporting" "No error,Error" bitfld.long 0x00 6.--8. " EP_L0S_LAT ,Endpoint L0s acceptable latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " ET ,Extended tag field supported" "0,1" bitfld.long 0x00 3.--4. " PHAN_FCT ,Phantom functions supported" "0,1,2,3" bitfld.long 0x00 0.--2. " MAX_PL_SIZE_SUP ,Maximum payload size supported" ",256-bytes,?..." group.word 0x78++0x03 line.word 0x00 "DEVICE_CONTROL,PCI Express Device Control Register" bitfld.word 0x00 15. " IFLR ,Initiate functional level reset" "No reset,Reset" bitfld.word 0x00 12.--14. " MAX_READ_SIZE ,Maximum read request size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 11. " ENS ,No snoop enable" "Disabled,Enabled" newline bitfld.word 0x00 10. " APE ,AUX power PM enable" "Disabled,Enabled" bitfld.word 0x00 9. " PFE ,Phantom functions enable" "Disabled,Enabled" bitfld.word 0x00 8. " ETE ,Extended tag field enable" "Disabled,Enabled" newline bitfld.word 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum payload size" "0,1,2,3,4,5,6,7" bitfld.word 0x00 4. " RO ,Relaxed ordering enable" "Disabled,Enabled" bitfld.word 0x00 3. " URR ,Unsupported request reporting enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " FER ,Fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 1. " NFER ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.word 0x00 0. " CER ,Correctable error reporting enable" "Disabled,Enabled" line.word 0x02 "DEVICE_STATUS,PCI Express Device Status Register" rbitfld.word 0x02 5. " TP ,Transactions pending" "Not pending,Pending" rbitfld.word 0x02 4. " APD ,AUX power detected" "Not detected,Detected" eventfld.word 0x02 3. " URD ,Unsupported request detected" "Not detected,Detected" newline eventfld.word 0x02 2. " FED ,Fatal error detected" "Not detected,Detected" eventfld.word 0x02 1. " NFED ,Non-fatal error detected" "Not detected,Detected" eventfld.word 0x02 0. " CED ,Correctable error detected" "Not detected,Detected" rgroup.long 0x7C++0x03 line.long 0x00 "LINK_CAPABILITIES,PCI Express Link Capabilities Register" hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,Port number" bitfld.long 0x00 22. " AOC ,ASPM optionality compliance" "0,1" bitfld.long 0x00 21. " LBWN ,Link bandwidth notification capable" "Not capable,Capable" newline bitfld.long 0x00 20. " DLLARC ,Data link layer active reporting capable" "Not capable,Capable" bitfld.long 0x00 19. " SD_ERR_RPT_CAP ,Surprise down error reporting capable" "Not capable,Capable" bitfld.long 0x00 18. " CPM ,Clock power management" "0,1" newline bitfld.long 0x00 15.--17. " L1_EX_LAT ,L1 exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " L0S_EX_LAT ,L0s exit latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--11. " ASPM ,Active state power management (ASPM) support" "0,1,2,3" newline bitfld.long 0x00 4.--9. " MAX_LINK_W ,Maximum link width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " MAX_LINK_SP ,Maximum link speed" ",2.5 GT/s,5.0 GT/s,8.0 GT/s,?..." newline if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) group.word 0x80++0x01 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" rgroup.word 0x82++0x01 line.word 0x00 "LINK_STATUS,PCI Express Link Status Register" bitfld.word 0x00 15. " LABS ,Link autonomous bandwidth status" "0,1" bitfld.word 0x00 14. " LBMS ,Link bandwidth management status" "0,1" bitfld.word 0x00 12. " SCC ,Slot clock configuration" "0,1" newline bitfld.word 0x00 11. " LT ,Link training" "0,1" bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." bitfld.word 0x00 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." hgroup.long 0x84++0x03 hide.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hgroup.word 0x88++0x01 hide.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" hgroup.word 0x8A++0x01 hide.word 0x00 "SLOT_STATUS,PCI Express Slot Status Register" hgroup.word 0x8C++0x01 hide.word 0x00 "ROOT_CONTROL,PCI Express Root Control Register" hgroup.word 0x8E++0x01 hide.word 0x00 "ROOT_CAPABILITIES,PCI Express Root Capabilities" hgroup.long 0x90++0x03 hide.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" else group.word 0x80++0x03 line.word 0x00 "LINK_CONTROL,PCI Express Link Control Register" bitfld.word 0x00 11. " LABIE ,Link autonomous bandwidth interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " LBMIE ,Link bandwidth management interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " HW_AUTO_WIDTH_DIS ,Hardware autonomous width disable" "No,Yes" newline bitfld.word 0x00 8. " ECPM ,Enable clock power management" "Disabled,Enabled" bitfld.word 0x00 7. " EXT_SYNC ,Extended synch" "0,1" bitfld.word 0x00 6. " CCC ,Common clock configuration" "0,1" newline bitfld.word 0x00 5. " RL ,Retrain link" "No effect,Initiated" bitfld.word 0x00 4. " LD ,Link disable" "No,Yes" bitfld.word 0x00 3. " RCB ,Read completion boundary" "0,1" newline bitfld.word 0x00 0.--1. " ASPM_CTL ,Active state power management (ASPM) control" "0,1,2,3" line.word 0x02 "LINK_STATUS,PCI Express Link Status Register" eventfld.word 0x02 15. " LABS ,Link autonomous bandwidth status" "0,1" eventfld.word 0x02 14. " LBMS ,Link bandwidth management status" "0,1" rbitfld.word 0x02 12. " SCC ,Slot clock configuration" "0,1" newline rbitfld.word 0x02 11. " LT ,Link training" "0,1" rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rbitfld.word 0x02 4.--9. " NEG_LINK_W ,Negotiated link width" ",X1,X2,,X4,?..." rgroup.long 0x84++0x03 line.long 0x00 "SLOT_CAPABILITIES,PCI Express Slot Capabilities Register" hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Indicates the physical slot number attached to this port" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" bitfld.long 0x00 18. " NOCMDCPLSUP ,No command completed support" "Not supported,Supported" newline bitfld.long 0x00 15.--16. " SPLS ,Slot power limit scale" "0,1,2,3" hexmask.long.word 0x00 7.--14. 1. " SPLV ,Slot power limit value" bitfld.long 0x00 6. " HPD ,Hot plug capable" "Not capable,Capable" newline bitfld.long 0x00 5. " HPS ,Hot plug surprise" "0,1" bitfld.long 0x00 4. " PIP ,Power indicator present" "Not present,Present" bitfld.long 0x00 3. " AIP ,Attention indicator present" "Not present,Present" newline bitfld.long 0x00 2. " MRLSP ,MRL sensor present" "Not present,Present" bitfld.long 0x00 1. " PCP ,Power controller present" "Not present,Present" bitfld.long 0x00 0. " ABP ,Attention button present" "Not present,Present" group.word 0x88++0x07 line.word 0x00 "SLOT_CONTROL,PCI Express Slot Control Register" bitfld.word 0x00 12. " DLLSTCHGEN ,Data link layer state changed enable" "Disabled,Enabled" bitfld.word 0x00 11. " EMICTL ,Electromechanical interlock control" "0,1" bitfld.word 0x00 10. " PCC ,Power controller control" "0,1" newline bitfld.word 0x00 8.--9. " PIC ,Power indicator control" "0,1,2,3" bitfld.word 0x00 6.--7. " AIC ,Attention indicator control" "0,1,2,3" bitfld.word 0x00 5. " HPIE ,Hot plug interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " CCIE ,Command completed interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " PDCE ,Presence detect changed enable" "Disabled,Enabled" bitfld.word 0x00 2. " MRLSCE ,MRL sensor changed enable" "Disabled,Enabled" newline bitfld.word 0x00 1. " PFDE ,Power fault detected enable" "Disabled,Enabled" bitfld.word 0x00 0. " ABPE ,Attention button pressed enable" "Disabled,Enabled" line.word 0x02 "SLOT_STATUS,PCI Express Slot Status Register" eventfld.word 0x02 8. " DLLSTCHG ,Data link layer state changed" "Not changed,Changed" rbitfld.word 0x02 7. " EM_IL_ST ,Electromechanical interlock status" "0,1" rbitfld.word 0x02 6. " PDS ,Indicates presence of an adapter in the slot" "Not present,Present" newline rbitfld.word 0x02 5. " MRLSS ,MRL sensor state" "Closed,Open" eventfld.word 0x02 4. " CC ,Command completed" "Not completed,Completed" eventfld.word 0x02 3. " PDC ,Presence detect changed" "Not changed,Changed" newline eventfld.word 0x02 2. " MRLSC ,MRL sensor changed" "Not changed,Changed" eventfld.word 0x02 1. " PFD ,Power fault detected" "Not detected,Detected" eventfld.word 0x02 0. " ABP ,Attention button pressed" "Not pressed,Pressed" line.word 0x04 "ROOT_CONTROL,PCI Express Root Control Register" bitfld.word 0x04 4. " CRSSWVE ,CRS software visibility enable" "Disabled,Enabled" bitfld.word 0x04 3. " PMEIE ,PME interrupt enable" "Disabled,Enabled" bitfld.word 0x04 2. " SEFEE ,System error on fatal error enable" "Disabled,Enabled" newline bitfld.word 0x04 1. " SENFEE ,System error on non-fatal error enable" "Disabled,Enabled" bitfld.word 0x04 0. " SECEE ,System error on correctable error enable" "Disabled,Enabled" line.word 0x06 "ROOT_CAPABILITIES,PCI Express Root Capabilities" bitfld.word 0x06 0. " CRSSWV ,CRS software visibility" "Not visible,Visible" group.long 0x90++0x03 line.long 0x00 "ROOT_STATUS,PCI Express Root Status Register" bitfld.long 0x00 17. " PMEP ,PME pending" "Not pending,Pending" eventfld.long 0x00 16. " PMES ,PME status" "0,1" hexmask.long.word 0x00 0.--15. 1. " PME_REQUESTER_ID ,PME requester ID" endif newline rgroup.long 0x94++0x03 line.long 0x00 "DEVICE_CAPABILITIES_2,PCI Express Device Capabilities 2 Register" bitfld.long 0x00 5. " ARI_FWD ,ARI forwarding support" "Not supported,Supported" bitfld.long 0x00 4. " CPL_TO_DS ,Completion timeout disable support" "Not supported,Supported" bitfld.long 0x00 0.--3. " CPL_TO_RS ,Completion timeout ranges support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x98++0x01 line.word 0x00 "DEVICE_CONTROL_2,PCI Express Device Control 2 Register" bitfld.word 0x00 5. " ARIFE ,ARI forwarding enable" "Disabled,Enabled" bitfld.word 0x00 4. " CPL_TOD ,Completion timeout disable" "No,Yes" bitfld.word 0x00 0.--3. " CPL_TO_VAL ,Completion timeout value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0x9C++0x03 line.long 0x00 "LINK_CAPABILITIES_2,PCI Express Link Capabilities 2 Register" bitfld.long 0x00 8. " CROSSLINK_SUPPORTED ,Crosslink supported" "Not supported,Supported" bitfld.long 0x00 3. " SUPPORT_LINK_SPEED_VECTOR_8 ,Supported link speeds vector 8.0 GT/s" "0,1" newline bitfld.long 0x00 2. " SUPPORT_LINK_SPEED_VECTOR_5 ,Supported link speeds vector 5.0 GT/s" "0,1" bitfld.long 0x00 1. " SUPPORT_LINK_SPEED_VECTOR_2 ,Supported link speeds vector 2.5 GT/s" "0,1" newline group.word 0xA0++0x01 line.word 0x00 "LINK_CONTROL_2,PCI Express Link Control 2 Register" bitfld.word 0x00 12.--15. " CDE ,Compliance de-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 11. " CSOS ,Compliance SOS" "0,1" bitfld.word 0x00 10. " EMC ,Enter modified compliance" "0,1" newline bitfld.word 0x00 7.--9. " TXM ,Transmit margin" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. " SDE ,Selectable de-emphasis" "0,1" bitfld.word 0x00 5. " HWASD ,Hardware autonomous speed disable" "No,Yes" newline bitfld.word 0x00 4. " EC ,Enter compliance" "0,1" bitfld.word 0x00 0.--3. " T_LS ,Target link speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA2++0x01 line.word 0x00 "LINK_STATUS_2,PCI Express Link Status 2 Register" bitfld.word 0x00 5. " LER ,Link equalization request" "Not requested,Requested" newline bitfld.word 0x00 4. " EP3S ,Equalization phase 3 successful" "Not successful,Successful" bitfld.word 0x00 3. " EP2S ,Equalization phase 2 successful" "Not successful,Successful" bitfld.word 0x00 2. " EP1S ,Equalization phase 1 successful" "Not successful,Successful" newline bitfld.word 0x00 1. " EC ,Equalization complete" "Not completed,Completed" bitfld.word 0x00 0. " DE_LVL ,Current de-emphasis level" "0,1" width 41. newline rgroup.word 0x100++0x01 line.word 0x00 "ADVANCED_ERROR_REPORTING_CAPABILITY_ID,PCI Express Advanced Error Reporting Capability ID Register" group.long 0x104++0x17 line.long 0x00 "UNCORRECTABLE_ERROR_STATUS,PCI Express Uncorrectable Error Status Register" eventfld.long 0x00 20. " URE ,Unsupported request error status" "No error,Error" eventfld.long 0x00 19. " ECRCE ,ECRC error status" "No error,Error" eventfld.long 0x00 18. " MTLP ,Malformed TLP status" "No error,Error" newline eventfld.long 0x00 17. " RXO ,Receiver overflow status" "No error,Error" eventfld.long 0x00 16. " UC ,Unexpected completion status" "No error,Error" eventfld.long 0x00 15. " CA ,Completer abort status" "No error,Error" newline eventfld.long 0x00 14. " CTO ,Completion timeout status" "No error,Error" eventfld.long 0x00 13. " FCPE ,Flow control protocol error status" "No error,Error" eventfld.long 0x00 12. " PTLP ,Poisoned TLP status" "No error,Error" newline eventfld.long 0x00 4. " DLPE ,Data link protocol error status" "No error,Error" line.long 0x04 "UNCORRECTABLE_ERROR_MASK,PCI Express Uncorrectable Error Mask Register" bitfld.long 0x04 20. " UREM ,Unsupported request error mask" "Not masked,Masked" bitfld.long 0x04 19. " ECRCEM ,ECRC error mask" "Not masked,Masked" bitfld.long 0x04 18. " MTLPM ,Malformed TLP mask" "Not masked,Masked" newline bitfld.long 0x04 17. " RXOM ,Receiver overflow mask" "Not masked,Masked" bitfld.long 0x04 16. " UCM ,Unexpected completion mask" "Not masked,Masked" bitfld.long 0x04 15. " CAM ,Completer abort mask" "Not masked,Masked" newline bitfld.long 0x04 14. " CTOM ,Completion timeout mask" "Not masked,Masked" bitfld.long 0x04 13. " FCPEM ,Flow control protocol error mask" "Not masked,Masked" bitfld.long 0x04 12. " PTLPM ,Poisoned TLP mask" "Not masked,Masked" newline bitfld.long 0x04 4. " DLPEM ,Data link protocol error mask" "Not masked,Masked" line.long 0x08 "UNCORRECTABLE_ERROR_SEVERITY,PCI Express Uncorrectable Error Severity Register" bitfld.long 0x08 20. " URES ,Unsupported request error severity" "Not severe,Severe" bitfld.long 0x08 19. " ECRCES ,ECRC error severity" "Not severe,Severe" bitfld.long 0x08 18. " MTLPS ,Malformed TLP severity" "Not severe,Severe" newline bitfld.long 0x08 17. " RXOS ,Receiver overflow severity" "Not severe,Severe" bitfld.long 0x08 16. " UCS ,Unexpected completion severity" "Not severe,Severe" bitfld.long 0x08 15. " CAS ,Completer abort severity" "Not severe,Severe" newline bitfld.long 0x08 14. " CTOS ,Completion timeout severity" "Not severe,Severe" bitfld.long 0x08 13. " FCPES ,Flow control protocol error severity" "Not severe,Severe" bitfld.long 0x08 12. " PTLPS ,Poisoned TLP severity" "Not severe,Severe" newline bitfld.long 0x08 4. " DLPES ,Data link protocol error severity" "Not severe,Severe" line.long 0x0C "CORRECTABLE_ERROR_STATUS,PCI Express Correctable Error Status Register" eventfld.long 0x0C 13. " ADVNFE ,Advisory non-fatal error status" "No error,Error" eventfld.long 0x0C 12. " RTTO ,Replay timer timeout status" "No error,Error" eventfld.long 0x0C 8. " RNR ,REPLAY_NUM rollover status" "No error,Error" newline eventfld.long 0x0C 7. " BDLLP ,Bad DLLP status" "No error,Error" eventfld.long 0x0C 6. " BTLP ,Bad TLP status" "No error,Error" eventfld.long 0x0C 0. " RXE ,Receiver error status" "No error,Error" line.long 0x10 "CORRECTABLE_ERROR_MASK,PCI Express Correctable Error Mask Register" bitfld.long 0x10 13. " ADVNFEM ,Advisory non-fatal error mask" "Not masked,Masked" bitfld.long 0x10 12. " RTTOM ,Replay timer timeout mask" "Not masked,Masked" bitfld.long 0x10 8. " RNRM ,REPLAY_NUM rollover mask" "Not masked,Masked" newline bitfld.long 0x10 7. " BDLLPM ,Bad DLLP mask" "Not masked,Masked" bitfld.long 0x10 6. " BTLPM ,Bad TLP mask" "Not masked,Masked" bitfld.long 0x10 0. " RXEM ,Receiver error mask" "Not masked,Masked" line.long 0x14 "ADVANCED_ERROR_CAPABILITIES_AND_CONTROL,PCI Express Advanced Error Capabilities And Control Register" bitfld.long 0x14 8. " ECRCCE ,ECRC checking enable" "Disabled,Enabled" rbitfld.long 0x14 7. " ECRCCC ,ECRC checking capable" "Not capable,Capable" bitfld.long 0x14 6. " ECRCGE ,ECRC generation enable" "Disabled,Enabled" newline rbitfld.long 0x14 5. " ECRCGC ,ECRC generation capable" "Not capable,Capable" rbitfld.long 0x14 0.--4. " FIRST_ERROR_POINTER ,Identifies the bit position of the first error reported in the uncorrectable error status register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rgroup.long 0x11C++0x0F line.long 0x00 "HEADER_LOG_DWORD1,PCI Express Header Log Register 1" hexmask.long.byte 0x00 24.--31. 1. " BYTE_0 ,Byte 0 of the TLP header associated with the error" hexmask.long.byte 0x00 16.--23. 1. " BYTE_1 ,Byte 1 of the TLP header associated with the error" newline hexmask.long.byte 0x00 8.--15. 1. " BYTE_2 ,Byte 2 of the TLP header associated with the error" hexmask.long.byte 0x00 0.--7. 1. " BYTE_3 ,Byte 3 of the TLP header associated with the error" line.long 0x04 "HEADER_LOG_DWORD2,PCI Express Header Log Register 2" hexmask.long.byte 0x04 24.--31. 1. " BYTE_4 ,Byte 4 of the TLP header associated with the error" hexmask.long.byte 0x04 16.--23. 1. " BYTE_5 ,Byte 5 of the TLP header associated with the error" newline hexmask.long.byte 0x04 8.--15. 1. " BYTE_6 ,Byte 6 of the TLP header associated with the error" hexmask.long.byte 0x04 0.--7. 1. " BYTE_7 ,Byte 7 of the TLP header associated with the error" line.long 0x08 "HEADER_LOG_DWORD3,PCI Express Header Log Register 3" hexmask.long.byte 0x08 24.--31. 1. " BYTE_8 ,Byte 8 of the TLP header associated with the error" hexmask.long.byte 0x08 16.--23. 1. " BYTE_9 ,Byte 9 of the TLP header associated with the error" newline hexmask.long.byte 0x08 8.--15. 1. " BYTE_A ,Byte 10 of the TLP header associated with the error" hexmask.long.byte 0x08 0.--7. 1. " BYTE_B ,Byte 11 of the TLP header associated with the error" line.long 0x0C "HEADER_LOG_DWORD4,PCI Express Header Log Register 4" hexmask.long.byte 0x0C 24.--31. 1. " BYTE_C ,Byte 12 of the TLP header associated with the error" hexmask.long.byte 0x0C 16.--23. 1. " BYTE_D ,Byte 13 of the TLP header associated with the error" newline hexmask.long.byte 0x0C 8.--15. 1. " BYTE_E ,Byte 14 of the TLP header associated with the error" hexmask.long.byte 0x0C 0.--7. 1. " BYTE_F ,Byte 15 of the TLP header associated with the error" newline if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) hgroup.long 0x12C++0x03 hide.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" hgroup.long 0x130++0x03 hide.long 0x00 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" else group.long 0x12C++0x07 line.long 0x00 "ROOT_ERROR_COMMAND,PCI Express Root Error Command Register" bitfld.long 0x00 2. " FERE ,Fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 1. " NFERE ,Non-fatal error reporting enable" "Disabled,Enabled" bitfld.long 0x00 0. " CERE ,Correctable error reporting enable" "Disabled,Enabled" line.long 0x04 "ROOT_ERROR_STATUS,PCI Express Root Error Status Register" rbitfld.long 0x04 27.--31. " AEIMN ,Advanced error interrupt message number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" eventfld.long 0x04 6. " FEMR ,Fatal error messages received" "Not received,Received" eventfld.long 0x04 5. " NFEMR ,Non-fatal error messages received" "Not received,Received" newline eventfld.long 0x04 4. " FUF ,First uncorrectable fatal" "0,1" eventfld.long 0x04 3. " MEFNFR ,Multiple ERR_FATAL/NONFATAL received" "Not received,Received" eventfld.long 0x04 2. " EFNFR ,ERR_FATAL/NONFATAL received" "Not received,Received" newline eventfld.long 0x04 1. " MECR ,Multiple ERR_COR received" "Not received,Received" eventfld.long 0x04 0. " ECR ,ERR_COR received" "Not received,Received" endif rgroup.word 0x134++0x03 line.word 0x00 "CORRECTABLE_ERROR_SOURCE_ID,PCI Express Correctable Error Source ID Register" line.word 0x02 "ERROR_SOURCE_ID,PCI Express Error Source ID Register" newline width 28. newline rgroup.long 0x148++0x03 line.long 0x00 "SPCIE_CAP_HEADER_REG,Secondary PCIE Capability Header Register" hexmask.long.word 0x00 20.--31. 0x10 " NEXT_OFFSET ,Pointer to the next capability structure" bitfld.long 0x00 16.--19. " CAP_VERSION ,Indicates the version of the capability structure present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " EXTENDED_CAP_ID ,Secondary PCI express capability" group.long 0x14C++0x07 line.long 0x00 "LINK_CONTROL3_REG,Link Control 3 Register" bitfld.long 0x00 1. " EQ_REQ_INT_EN ,Link equalization request interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " PERFORM_EQ ,Perform equalization" "Not performed,Performed" line.long 0x04 "LANE_ERR_STATUS_REG,Lane Error Status Register" eventfld.long 0x04 1. " LANE_ERR_STATUS[1] ,Lane 1 detected a lane-based error" "No error,Error" eventfld.long 0x04 0. " [0] ,Lane 0 detected a lane-based error" "No error,Error" rgroup.word (0x154+0x0)++0x01 line.word 0x00 "LANE1_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word (0x154+0x2)++0x01 line.word 0x00 "LANE2_EQUALIZATION_CONTROL,Lane Equalization Control Register" bitfld.word 0x00 12.--14. " USP_RX_PRESET_HINT ,Upstream port receiver preset hint" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--11. " USP_TX_PRESET ,Upstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--6. " DSP_RX_PRESET_HINT ,Downstream port receiver preset hint" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 0.--3. " DSP_TX_PRESET ,Downstream port transmitter preset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline width 38. width 39. newline group.long 0x71C++0x03 line.long 0x00 "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer And Filter Mask 1 Register" bitfld.long 0x00 31. " CX_FLT_MASK_RC_CFG_DISCARD ,CX_FLT_MASK_RC_CFG_DISCARD" "Not masked,Masked" bitfld.long 0x00 30. " CX_FLT_MASK_RC_IO_DISCARD ,CX_FLT_MASK_RC_IO_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 29. " CX_FLT_MASK_MSG_DROP ,CX_FLT_MASK_MSG_DROP" "Not masked,Masked" bitfld.long 0x00 28. " CX_FLT_MASK_CPL_ECRC_DISCARD ,CX_FLT_MASK_CPL_ECRC_DISCARD" "Not masked,Masked" newline bitfld.long 0x00 27. " CX_FLT_MASK_ECRC_DISCARD ,CX_FLT_MASK_ECRC_DISCARD" "Not masked,Masked" bitfld.long 0x00 26. " CX_FLT_MASK_CPL_LEN_MATCH ,CX_FLT_MASK_CPL_LEN_MATCH" "Not masked,Masked" newline bitfld.long 0x00 25. " CX_FLT_MASK_CPL_ATTR_MATCH ,CX_FLT_MASK_CPL_ATTR_MATCH" "Not masked,Masked" bitfld.long 0x00 24. " CX_FLT_MASK_CPL_TC_MATCH ,CX_FLT_MASK_CPL_TC_MATCH" "Not masked,Masked" newline bitfld.long 0x00 23. " CX_FLT_MASK_CPL_FUNC_MATCH ,CX_FLT_MASK_CPL_FUNC_MATCH" "Not masked,Masked" bitfld.long 0x00 22. " CX_FLT_MASK_CPL_REQID_MATCH ,CX_FLT_MASK_CPL_REQID_MATCH" "Not masked,Masked" newline bitfld.long 0x00 21. " CX_FLT_MASK_CPL_TAGERR_MATCH ,CX_FLT_MASK_CPL_TAGERR_MATCH" "Not masked,Masked" bitfld.long 0x00 20. " CX_FLT_MASK_LOCKED_RD_AS_UR ,CX_FLT_MASK_LOCKED_RD_AS_UR" "Not masked,Masked" newline bitfld.long 0x00 19. " CX_FLT_MASK_CFG_TYPE1_RE_AS_UR ,CX_FLT_MASK_CFG_TYPE1_RE_AS_UR" "Not masked,Masked" bitfld.long 0x00 18. " CX_FLT_MASK_UR_OUTSIDE_BAR ,CX_FLT_MASK_UR_OUTSIDE_BAR" "Not masked,Masked" newline bitfld.long 0x00 17. " CX_FLT_MASK_UR_POIS ,CX_FLT_MASK_UR_POIS" "Not masked,Masked" bitfld.long 0x00 16. " CX_FLT_MASK_UR_FUNC_MISMATCH ,CX_FLT_MASK_UR_FUNC_MISMATCH" "Not masked,Masked" newline bitfld.long 0x00 15. " DISABLE_FC_WD_TIMER ,Disables FC watchdog timer" "No,Yes" hexmask.long.word 0x00 0.--10. 1. " SKP_INT_VAL ,SKP interval value" newline group.long 0x890++0x03 line.long 0x00 "GEN3_RELATED_OFF,Gen3 Control Register" bitfld.long 0x00 16. " GEN3_EQUALIZATION_DISABLE ,Equalization disable" "No,Yes" bitfld.long 0x00 12. " RXEQ_PH01_EN ,Rx equalization phase 0/phase 1 hold enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " EQ_EIEOS_CNT ,Equalization EIEOS count reset disable" "No,Yes" group.long 0x8BC++0x03 line.long 0x00 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register" bitfld.long 0x00 0. " RO_WR_EN ,Read-only write enable" "Disabled,Enabled" newline group.long 0x8E0++0x07 line.long 0x00 "COHERENCY_CONTROL_1_OFF,Coherency Control 1" hexmask.long 0x00 2.--31. 0x04 " CFG_MEMTYPE_BOUNDARY_LOW_ADDR ,Boundary lower address for memory type" bitfld.long 0x00 0. " CFG_MEMTYPE_VALUE ,Memory type" "CCSR/Memory,?..." line.long 0x04 "COHERENCY_CONTROL_2_OFF,Coherency Control 2" group.long 0x900++0x03 line.long 0x00 "IATU_VIEWPORT_OFF,IATU Index Register" bitfld.long 0x00 31. " REGION_DIR ,Region direction" "Outbound,Inbound" hexmask.long.byte 0x00 0.--7. 1. " REGION_INDEX ,Region index" newline if (((per.l(ad:0x3600000+0x900))&0x80000000)==0x80000000) if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 20.--24. " CTRL_1_FUNC_NUM ,Function number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" newline bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 19. " FUNC_NUM_MATCH_EN ,Function number match enable" "Disabled,Enabled" bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--10. " BAR_NUM ,BAR number" "BAR 0,BAR 1,BAR 2,BAR 3,BAR 4,BAR 5,ROM,?..." else group.long 0x904++0x07 line.long 0x00 "IATU_REGION_CTRL_1_OFF_INBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3" bitfld.long 0x00 0.--4. " TYPE ,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IATU_REGION_CTRL_2_OFF_INBOUND_0,IATU Region Control 2 Register" bitfld.long 0x04 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x04 30. " MATCH_MODE ,Match mode" "Address/Routing ID/Address,BAR/Accept/Vendor ID" newline bitfld.long 0x04 18. " AT_MATCH_EN ,AT match enable" "Disabled,Enabled" endif group.long 0x90C++0x13 line.long 0x00 "IATU_LWR_BASE_ADDR_OFF_INBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x00 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x04 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_0,IATU Upper Base Address Register" line.long 0x08 "IATU_LIMIT_ADDR_OFF_INBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x08 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x08 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x0C "IATU_LWR_TARGET_ADDR_OFF_INBOUND_0,IATU Region#N Lower Offset Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x0C 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x10 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0,IATU Upper Target Address Register" else group.long 0x904++0x03 line.long 0x00 "IATU_REGION_CTRL_1_OFF_OUTBOUND_0,IATU Region Control 1 Register" bitfld.long 0x00 16.--17. " AT ,When the address of an outbound TLP is matched to this region then the AT field of the TLP is changed to the value in this register" "0,1,2,3" bitfld.long 0x00 9.--10. " ATTR ,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register" "0,1,2,3" newline bitfld.long 0x00 8. " TD ,When the address of an outbound TLP is matched to this region then the TD field of the TLP is changed to the value in this register" "0,1" bitfld.long 0x00 5.--7. " TC ,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. " TYPE ,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x908++0x17 line.long 0x00 "IATU_REGION_CTRL_2_OFF_OUTBOUND_0,IATU Region Control 2 Register" bitfld.long 0x00 31. " REGION_EN ,Region enable" "Disabled,Enabled" bitfld.long 0x00 28. " CFG_SHIFT_MODE ,CFG shift mode" "Not shifted,Shifted" newline hexmask.long.byte 0x00 0.--7. 1. " MSG_CODE ,Message code" line.long 0x04 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,IATU Lower Base Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " LWR_BASE_RW ,Forms bits [31:12] of the start address of the address region to be translated" hexmask.long.word 0x04 0.--11. 0x01 " LWR_BASE_HW ,Forms bits [11:0] of the start address of the address region to be translated" line.long 0x08 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,IATU Upper Base Address Register" line.long 0x0C "IATU_LIMIT_ADDR_OFF_OUTBOUND_0,IATU Limit Address Register" hexmask.long.tbyte 0x0C 12.--31. 0x10 " LIMIT_ADDR_RW ,Forms bits [31:12] of the end address of the address region to be translated" hexmask.long.word 0x0C 0.--11. 0x01 " LIMIT_ADDR_HW ,Forms bits [11:0] of the end address of the address region to be translated" line.long 0x10 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,IATU Outbound Region#N Lower Offset Address Register" hexmask.long.tbyte 0x10 12.--31. 0x10 " LWR_TARGET_RW ,Forms bits [31:12] of the of the new address of the translated region" hexmask.long.word 0x10 0.--11. 0x01 " LWR_TARGET_HW ,Forms bits [11:0] of the start address of the new address of the translated region" line.long 0x14 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,IATU Upper Target Address Register" endif wgroup.long 0x1010++0x07 line.long 0x00 "BAR0_MASK,Base Address 0 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR1_MASK,Base Address 1 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) wgroup.long 0x1018++0x0F line.long 0x00 "BAR2_MASK,Base Address 2 Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Mask" bitfld.long 0x00 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x04 "BAR3_MASK,Base Address 3 Mask Register" hexmask.long 0x04 1.--31. 1. " MASK ,Mask" bitfld.long 0x04 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x08 "BAR4_MASK,Base Address 4 Mask Register" hexmask.long 0x08 1.--31. 1. " MASK ,Mask" bitfld.long 0x08 0. " BAR_EN ,Invert mode" "Disabled,Enabled" line.long 0x0C "BAR5_MASK,Base Address 5 Mask Register" hexmask.long 0x0C 1.--31. 1. " MASK ,Mask" bitfld.long 0x0C 0. " BAR_EN ,Invert mode" "Disabled,Enabled" wgroup.long 0x1030++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long 0x00 1.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" else newline newline newline newline wgroup.long 0x1038++0x03 line.long 0x00 "EXP_ROM_BAR_MASK,Expansion ROM Base Address Mask Register" hexmask.long.tbyte 0x00 11.--31. 1. " MASK ,Expansion ROM BAR mask" bitfld.long 0x00 0. " BAR_EN ,Expansion ROM BAR enable" "Disabled,Enabled" endif base ad:0x3600000+0x80000 tree "PEX3_LUT Memory Map/Registers" group.long 0x20++0x07 line.long 0x00 "PEX_LUT_PEXLSR,PEX LUT Status Register" eventfld.long 0x00 31. " LUTM ,Lookup table miss" "Not missed,Missed" eventfld.long 0x00 30. " MLUTM ,Multiple lookup table miss" "Not missed,Missed" hexmask.long.word 0x00 0.--15. 1. " CREQID ,Captured REQID" line.long 0x04 "PEX_LUT_PEXLCR,PEX LUT Control Register" bitfld.long 0x04 31. " DPL ,Default privilege level" "0,1" bitfld.long 0x04 30. " DBMT ,Default bypass memory translation" "0,1" hexmask.long.word 0x04 0.--14. 1. " DICID ,Default isolation context ID" group.long (0x800+0x0)++0x07 line.long 0x00 "PEX_LUT_PEXL0UDR,PEX LUT Entry 0 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 0 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 0 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL0LDR,PEX LUT Entry 0 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 0 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 0 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x8)++0x07 line.long 0x00 "PEX_LUT_PEXL1UDR,PEX LUT Entry 1 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 1 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 1 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL1LDR,PEX LUT Entry 1 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 1 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 1 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x10)++0x07 line.long 0x00 "PEX_LUT_PEXL2UDR,PEX LUT Entry 2 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 2 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 2 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL2LDR,PEX LUT Entry 2 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 2 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 2 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x18)++0x07 line.long 0x00 "PEX_LUT_PEXL3UDR,PEX LUT Entry 3 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 3 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 3 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL3LDR,PEX LUT Entry 3 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 3 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 3 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x20)++0x07 line.long 0x00 "PEX_LUT_PEXL4UDR,PEX LUT Entry 4 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 4 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 4 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL4LDR,PEX LUT Entry 4 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 4 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 4 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x28)++0x07 line.long 0x00 "PEX_LUT_PEXL5UDR,PEX LUT Entry 5 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 5 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 5 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL5LDR,PEX LUT Entry 5 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 5 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 5 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x30)++0x07 line.long 0x00 "PEX_LUT_PEXL6UDR,PEX LUT Entry 6 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 6 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 6 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL6LDR,PEX LUT Entry 6 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 6 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 6 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x38)++0x07 line.long 0x00 "PEX_LUT_PEXL7UDR,PEX LUT Entry 7 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 7 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 7 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL7LDR,PEX LUT Entry 7 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 7 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 7 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x40)++0x07 line.long 0x00 "PEX_LUT_PEXL8UDR,PEX LUT Entry 8 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 8 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 8 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL8LDR,PEX LUT Entry 8 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 8 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 8 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x48)++0x07 line.long 0x00 "PEX_LUT_PEXL9UDR,PEX LUT Entry 9 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 9 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 9 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL9LDR,PEX LUT Entry 9 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 9 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 9 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x50)++0x07 line.long 0x00 "PEX_LUT_PEXL10UDR,PEX LUT Entry 10 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 10 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 10 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL10LDR,PEX LUT Entry 10 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 10 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 10 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x58)++0x07 line.long 0x00 "PEX_LUT_PEXL11UDR,PEX LUT Entry 11 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 11 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 11 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL11LDR,PEX LUT Entry 11 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 11 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 11 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x60)++0x07 line.long 0x00 "PEX_LUT_PEXL12UDR,PEX LUT Entry 12 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 12 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 12 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL12LDR,PEX LUT Entry 12 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 12 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 12 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x68)++0x07 line.long 0x00 "PEX_LUT_PEXL13UDR,PEX LUT Entry 13 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 13 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 13 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL13LDR,PEX LUT Entry 13 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 13 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 13 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x70)++0x07 line.long 0x00 "PEX_LUT_PEXL14UDR,PEX LUT Entry 14 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 14 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 14 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL14LDR,PEX LUT Entry 14 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 14 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 14 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x78)++0x07 line.long 0x00 "PEX_LUT_PEXL15UDR,PEX LUT Entry 15 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 15 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 15 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL15LDR,PEX LUT Entry 15 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 15 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 15 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x80)++0x07 line.long 0x00 "PEX_LUT_PEXL16UDR,PEX LUT Entry 16 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 16 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 16 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL16LDR,PEX LUT Entry 16 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 16 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 16 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x88)++0x07 line.long 0x00 "PEX_LUT_PEXL17UDR,PEX LUT Entry 17 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 17 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 17 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL17LDR,PEX LUT Entry 17 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 17 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 17 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x90)++0x07 line.long 0x00 "PEX_LUT_PEXL18UDR,PEX LUT Entry 18 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 18 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 18 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL18LDR,PEX LUT Entry 18 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 18 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 18 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0x98)++0x07 line.long 0x00 "PEX_LUT_PEXL19UDR,PEX LUT Entry 19 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 19 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 19 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL19LDR,PEX LUT Entry 19 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 19 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 19 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA0)++0x07 line.long 0x00 "PEX_LUT_PEXL20UDR,PEX LUT Entry 20 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 20 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 20 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL20LDR,PEX LUT Entry 20 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 20 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 20 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xA8)++0x07 line.long 0x00 "PEX_LUT_PEXL21UDR,PEX LUT Entry 21 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 21 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 21 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL21LDR,PEX LUT Entry 21 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 21 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 21 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB0)++0x07 line.long 0x00 "PEX_LUT_PEXL22UDR,PEX LUT Entry 22 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 22 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 22 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL22LDR,PEX LUT Entry 22 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 22 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 22 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xB8)++0x07 line.long 0x00 "PEX_LUT_PEXL23UDR,PEX LUT Entry 23 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 23 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 23 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL23LDR,PEX LUT Entry 23 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 23 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 23 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC0)++0x07 line.long 0x00 "PEX_LUT_PEXL24UDR,PEX LUT Entry 24 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 24 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 24 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL24LDR,PEX LUT Entry 24 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 24 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 24 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xC8)++0x07 line.long 0x00 "PEX_LUT_PEXL25UDR,PEX LUT Entry 25 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 25 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 25 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL25LDR,PEX LUT Entry 25 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 25 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 25 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD0)++0x07 line.long 0x00 "PEX_LUT_PEXL26UDR,PEX LUT Entry 26 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 26 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 26 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL26LDR,PEX LUT Entry 26 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 26 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 26 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xD8)++0x07 line.long 0x00 "PEX_LUT_PEXL27UDR,PEX LUT Entry 27 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 27 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 27 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL27LDR,PEX LUT Entry 27 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 27 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 27 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE0)++0x07 line.long 0x00 "PEX_LUT_PEXL28UDR,PEX LUT Entry 28 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 28 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 28 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL28LDR,PEX LUT Entry 28 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 28 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 28 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xE8)++0x07 line.long 0x00 "PEX_LUT_PEXL29UDR,PEX LUT Entry 29 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 29 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 29 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL29LDR,PEX LUT Entry 29 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 29 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 29 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF0)++0x07 line.long 0x00 "PEX_LUT_PEXL30UDR,PEX LUT Entry 30 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 30 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 30 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL30LDR,PEX LUT Entry 30 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 30 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 30 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" group.long (0x800+0xF8)++0x07 line.long 0x00 "PEX_LUT_PEXL31UDR,PEX LUT Entry 31 Upper Data Register" hexmask.long.word 0x00 16.--31. 1. " REQID ,The request ID of entry 31 of the PEX lookup table" hexmask.long.word 0x00 0.--15. 1. " MASK ,The mask field of entry 31 of the PEX lookup table" line.long 0x04 "PEX_LUT_PEXL31LDR,PEX LUT Entry 31 Lower Data Register" bitfld.long 0x04 31. " EN ,The enable field of entry 31 within the PEX lookup table" "Disabled,Enabled" bitfld.long 0x04 30. " PL ,The privilege level field of entry 31 within the PEX lookup table" "0,1" bitfld.long 0x04 29. " BMT ,Bypass memory translation" "0,1" newline hexmask.long.word 0x04 0.--14. 1. " ICID ,Isolation context ID" newline group.long 0x40014++0x03 line.long 0x00 "PEX_PF0_CONFIG,PEX PF 0 Config Register" bitfld.long 0x00 0. " CFG_READY ,Config ready" "Not ready,Ready" rgroup.long 0x40018++0x03 line.long 0x00 "PEX_PF0_INT_STAT,PEX PF 0 Interrupt Status Register" bitfld.long 0x00 15. " INTM ,Per PF dependent message interrupt is pending" "Not pending,Pending" bitfld.long 0x00 14. " INTE ,Per PF dependent error interrupt is pending" "Not pending,Pending" group.long 0x40020++0x0B line.long 0x00 "PEX_PF0_PME_MES_DR,PEX PF 0 PCIE PME And Message Detect Register" eventfld.long 0x00 15. " PTO ,Indicates that PME turn off was detected" "Not detected,Detected" eventfld.long 0x00 13. " ENL23 ,Indicates that PCIe core entered L2/L3 ready state" "Not detected,Detected" eventfld.long 0x00 12. " EXL23 ,Indicates that PCIe core exited L2/L3 ready state" "Not detected,Detected" newline eventfld.long 0x00 10. " HRD ,Indicates a hot reset was detected" "Not detected,Detected" eventfld.long 0x00 9. " LDD ,Indicates a link down was detected" "Not detected,Detected" eventfld.long 0x00 7. " LUD ,Indicates a link up was detected" "Not detected,Detected" line.long 0x04 "PEX_PF0_PME_MES_DISR,PEX PF 0 PCIE PME And Message Disabled Register" bitfld.long 0x04 15. " PTOD ,PME turn off detect disable" "No,Yes" bitfld.long 0x04 13. " ENL23D ,Entered L2/L3 ready state detect disable" "No,Yes" bitfld.long 0x04 12. " EXL23D ,Exited L2/L3 ready state detect disable" "No,Yes" newline bitfld.long 0x04 10. " HRDD ,Hot reset detect disable" "No,Yes" bitfld.long 0x04 9. " LDDD ,Link down detect disable" "No,Yes" bitfld.long 0x04 7. " LUDD ,Link up detect disable" "No,Yes" line.long 0x08 "PEX_PF0_PME_MES_IER,PEX PF 0 PCIE PME And Message Interrupt Enable Register" bitfld.long 0x08 15. " PTOIE ,PME turn off interrupt enable" "Disabled,Enabled" bitfld.long 0x08 13. " ENL23IE ,Entered L2/L3 ready state detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 12. " EXL23IE ,Exited L2/L3 ready state detect interrupt enable" "Disabled,Enabled" newline bitfld.long 0x08 10. " HRDIE ,Hot reset detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 9. " LDDIE ,Link down detect interrupt enable" "Disabled,Enabled" bitfld.long 0x08 7. " LUDIE ,Link up detect interrupt enable" "Disabled,Enabled" if (((per.b(ad:0x3600000+0x0E))&0x01)==0x01) group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" else group.long 0x4002C++0x03 line.long 0x00 "PEX_PF0_MCR,PEX PF 0 PCIE Message Command Register" bitfld.long 0x00 4. " INTX ,Assert/de-assert intx command" "Not asserted,Asserted" bitfld.long 0x00 2. " SPMES ,Send PM_PME command" "No effect,Send" bitfld.long 0x00 1. " EXL2S ,Exit L2 state command" "No effect,Generate" newline bitfld.long 0x00 0. " PTOMR ,Generate PME turn off message" "No effect,Generate" endif group.long 0x40140++0x03 line.long 0x00 "PEX_PF0_RBP_ADDR_U,PEX PF 0 Route By Port Address Upper Register" hexmask.long.word 0x00 16.--31. 1. " ADDR_U ,Upper 16 bit of the PCIE slave device used for the outbound transactions" group.long 0x40200++0x03 line.long 0x00 "PEX_PF0_ERR_DR,PEX PF 0 PCIE Error Detect Register" eventfld.long 0x00 31. " ME ,Indicates multiple errors of same type" "Not detected,Detected" eventfld.long 0x00 23. " PCT ,Indicates completion timeout" "Not detected,Detected" eventfld.long 0x00 21. " PCAC ,Completer abort was detected" "Not detected,Detected" newline eventfld.long 0x00 19. " CDNSC ,Completion with data not successful was detected" "Not detected,Detected" eventfld.long 0x00 2. " UREP ,Indicates an unsupported request completion was detected" "Not detected,Detected" group.long 0x40208++0x03 line.long 0x00 "PEX_PF0_ERR_EN,PEX PF 0 PCIE Error Interrupt Enable Register" bitfld.long 0x00 23. " PCTIE ,Completion timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " PCACIE ,Completer abort interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CDNSCIE ,Completion with data not successful interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " UREPIE ,Unsupported request in EP mode interrupt enable" "Disabled,Enabled" group.long 0x40210++0x03 line.long 0x00 "PEX_PF0_ERR_DISR,PEX PF 0 PCIE Error Disable Register" eventfld.long 0x00 31. " MED ,Multiple errors of same type detection disable" "No,Yes" newline bitfld.long 0x00 23. " PCTD ,Completion detection disable" "No,Yes" bitfld.long 0x00 21. " PCACD ,Completer abort detection disable" "No,Yes" bitfld.long 0x00 19. " CDNSCD ,Completion with data not successful detection disable" "No,Yes" newline bitfld.long 0x00 2. " UREPD ,Unsupported request in EP mode detection disable" "No,Yes" group.long 0x407FC++0x03 line.long 0x00 "PEX_PF0_DBG,PEX PF0 Debug Register" bitfld.long 0x00 31. " WE ,Write enable" "Disabled,Enabled" bitfld.long 0x00 30. " SR ,Soft reset" "No reset,Reset" newline rbitfld.long 0x00 0.--5. " LTSSM ,Link training status state machine (LTSSM) status" "DETECT_QUIET,DETECT_ACTIVE,POLL_ACTIVE,POLL_COMPLIANCE,POLL_CONFIG,PRE_DETECT_QUIET,DETECT_WAIT,CFG_LINKWD_START,CFG_LINKWD_ACEPT,CFG_LANENUM_WAIT,CFG_LANENUM_ACEPT,CFG_COMPLETE,CFG_IDLE,RCVRY_LOCK,RCVRY_SPEED,RCVRY_RCVRCFG,RCVRY_IDLE,L0,L0S,L123_SEND_EIDLE,L1_IDLE,L2_IDLE,L2_WAKE,DISABLED_ENTRY,DISABLED_IDLE,DISABLED,LPBK_ENTRY,LPBK_ACTIVE,LPBK_EXIT,LPBK_EXIT_TIMEOUT,HOT_RESET_ENTRY,HOT_RESET,RCVRY_EQ0,RCVRY_EQ1,RCVRY_EQ2,RCVRY_EQ3,?..." tree.end width 0x0B tree.end tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree.open "PMU (Power Management Unit)" tree "PMU_ARM" base ad:0x1E30000 width 11. tree "Threads Registers" rgroup.long 0x40++0x03 line.long 0x00 "TWAITSR0,Core Wait Status Register" bitfld.long 0x00 7. " T_WAITING7 ,Core wait status bit 7" "Not in wait state,In wait state" bitfld.long 0x00 6. " [6] ,Core wait status bit 6" "Not in wait state,In wait state" bitfld.long 0x00 5. " [5] ,Core wait status bit 5" "Not in wait state,In wait state" bitfld.long 0x00 4. " [4] ,Core wait status bit 4" "Not in wait state,In wait state" newline bitfld.long 0x00 3. " [3] ,Core wait status bit 3" "Not in wait state,In wait state" bitfld.long 0x00 2. " [2] ,Core wait status bit 2" "Not in wait state,In wait state" bitfld.long 0x00 1. " [1] ,Core wait status bit 1" "Not in wait state,In wait state" bitfld.long 0x00 0. " [0] ,Core wait status bit 0" "Not in wait state,In wait state" rgroup.long 0x50++0x03 line.long 0x00 "TWDTDSR0,Core Watchdog Detect Status Register" bitfld.long 0x00 7. " TWDT_DET7 ,Core WDT detect status bit 7" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 6. " [6] ,Core WDT detect status bit 6" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 5. " [5] ,Core WDT detect status bit 5" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 4. " [4] ,Core WDT detect status bit 4" "Not signalled WRS,Signalled WRS" newline bitfld.long 0x00 3. " [3] ,Core WDT detect status bit 3" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 2. " [2] ,Core WDT detect status bit 2" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 1. " [1] ,Core WDT detect status bit 1" "Not signalled WRS,Signalled WRS" bitfld.long 0x00 0. " [0] ,Core WDT detect status bit 0" "Not signalled WRS,Signalled WRS" group.long 0x1B0++0x03 line.long 0x00 "TTBHLTCR0,Core Time Base Halt Control Register" bitfld.long 0x00 7. " TTBHLT7 ,Core timebase behavior during core halted bit 7" "Stopped,Not stopped" bitfld.long 0x00 6. " [6] ,Core timebase behavior during core halted bit 6" "Stopped,Not stopped" bitfld.long 0x00 5. " [5] ,Core timebase behavior during core halted bit 5" "Stopped,Not stopped" bitfld.long 0x00 4. " [4] ,Core timebase behavior during core halted bit 4" "Stopped,Not stopped" newline bitfld.long 0x00 3. " [3] ,Core timebase behavior during core halted bit 3" "Stopped,Not stopped" bitfld.long 0x00 2. " [2] ,Core timebase behavior during core halted bit 2" "Stopped,Not stopped" bitfld.long 0x00 1. " [1] ,Core timebase behavior during core halted bit 1" "Stopped,Not stopped" bitfld.long 0x00 0. " [0] ,Core timebase behavior during core halted bit 0" "Stopped,Not stopped" tree.end width 12. tree "Physical Cores Registers" group.long 0x810++0x03 line.long 0x00 "PCWFESR,Physical Core WFE Status Register" bitfld.long 0x00 7. " PC7 ,Physical core WFE status bit 7" "Not in WFE,In WFE" bitfld.long 0x00 6. " [6] ,Physical core WFE status bit 6" "Not in WFE,In WFE" bitfld.long 0x00 5. " [5] ,Physical core WFE status bit 5" "Not in WFE,In WFE" bitfld.long 0x00 4. " [4] ,Physical core WFE status bit 4" "Not in WFE,In WFE" newline bitfld.long 0x00 3. " [3] ,Physical core WFE status bit 3" "Not in WFE,In WFE" bitfld.long 0x00 2. " [2] ,Physical core WFE status bit 2" "Not in WFE,In WFE" bitfld.long 0x00 1. " [1] ,Physical core WFE status bit 1" "Not in WFE,In WFE" bitfld.long 0x00 0. " [0] ,Physical core WFE status bit 0" "Not in WFE,In WFE" group.long 0x830++0x03 line.long 0x00 "PCPW20SR,Physical Core PW20 Status Register" bitfld.long 0x00 7. " PC7 ,Physical core PW20 status bit 7" "Not in PW20,In PW20" bitfld.long 0x00 6. " [6] ,Physical core PW20 status bit 6" "Not in PW20,In PW20" bitfld.long 0x00 5. " [5] ,Physical core PW20 status bit 5" "Not in PW20,In PW20" bitfld.long 0x00 4. " [4] ,Physical core PW20 status bit 4" "Not in PW20,In PW20" newline bitfld.long 0x00 3. " [3] ,Physical core PW20 status bit 3" "Not in PW20,In PW20" bitfld.long 0x00 2. " [2] ,Physical core PW20 status bit 2" "Not in PW20,In PW20" bitfld.long 0x00 1. " [1] ,Physical core PW20 status bit 1" "Not in PW20,In PW20" bitfld.long 0x00 0. " [0] ,Physical core PW20 status bit 0" "Not in PW20,In PW20" group.long 0x840++0x03 line.long 0x00 "PCPH30SR,Physical Core PH30 Status Register" bitfld.long 0x00 7. " PC7 ,Physical core PH30 status bit 7" "Not in PH30,In PH30" bitfld.long 0x00 6. " [6] ,Physical core PH30 status bit 6" "Not in PH30,In PH30" bitfld.long 0x00 5. " [5] ,Physical core PH30 status bit 5" "Not in PH30,In PH30" bitfld.long 0x00 4. " [4] ,Physical core PH30 status bit 4" "Not in PH30,In PH30" newline bitfld.long 0x00 3. " [3] ,Physical core PH30 status bit 3" "Not in PH30,In PH30" bitfld.long 0x00 2. " [2] ,Physical core PH30 status bit 2" "Not in PH30,In PH30" bitfld.long 0x00 1. " [1] ,Physical core PH30 status bit 1" "Not in PH30,In PH30" bitfld.long 0x00 0. " [0] ,Physical core PH30 status bit 0" "Not in PH30,In PH30" group.long 0x8A0++0x07 line.long 0x00 "PCTBENR,Physical Core Time Base Enable Register" bitfld.long 0x00 7. " PCTBEN7 ,Core timebase enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Core timebase enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Core timebase enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Core timebase enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Core timebase enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Core timebase enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Core timebase enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Core timebase enable bit 0" "Disabled,Enabled" line.long 0x04 "PCTBCKSELR,Physical Core Time Base Clock Select Register" bitfld.long 0x04 7. " PCTBCKSEL7 ,Core timebase input clock select bit 7" "Clock/16,RTC" bitfld.long 0x04 6. " [6] ,Core timebase input clock select bit 6" "Clock/16,RTC" bitfld.long 0x04 5. " [5] ,Core timebase input clock select bit 5" "Clock/16,RTC" bitfld.long 0x04 4. " [4] ,Core timebase input clock select bit 4" "Clock/16,RTC" newline bitfld.long 0x04 3. " [3] ,Core timebase input clock select bit 3" "Clock/16,RTC" bitfld.long 0x04 2. " [2] ,Core timebase input clock select bit 2" "Clock/16,RTC" bitfld.long 0x04 1. " [1] ,Core timebase input clock select bit 1" "Clock/16,RTC" bitfld.long 0x04 0. " [0] ,Core timebase input clock select bit 0" "Clock/16,RTC" tree.end width 20. tree "Cluster Registers" group.long 0x1000++0x03 line.long 0x00 "CLPCL10SR,Cluster PCL10 (Stop) Status Register" bitfld.long 0x00 1. " CL1 ,Cluster 0 PCL10 status bit 1" "Not in PLC10,In PLC10" bitfld.long 0x00 0. " [0] ,Cluster 0 PCL10 status bit 0" "Not in PLC10,In PLC10" group.long 0x100C++0x03 line.long 0x00 "CLPCL10PSR,Cluster PCL10 (Stop) Previous Status Register" eventfld.long 0x00 1. " CL_P_PCL10_1 ,Cluster PCL10 previous status bit 1" "Not in PCL10,In PCL10" eventfld.long 0x00 0. " [0] ,Cluster PCL10 previous status bit 0" "Not in PCL10,In PCL10" group.long 0x1060++0x03 line.long 0x00 "CLWAKEEVENTDLYR,Cluster Wakeup Event Delay Register" bitfld.long 0x00 16.--19. " EVENTI_DLY ,EVENTI delay" "None,1 cycle,4 cycles,16 cycles,64 cycles,256 cycles,1024 cycles,4096 cycles,16384 cycles,?..." bitfld.long 0x00 0.--3. " CLREXMONREQ_DLY ,CLREXMONREQ delay" "None,1 cycle,4 cycles,16 cycles,64 cycles,256 cycles,1024 cycles,4096 cycles,16384 cycles,?..." group.long 0x1100++0x03 line.long 0x00 "CLAINACTR_SET/CLR,Cluster ACP AINACTS Set/Clear Control Register" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " CLAINACT1 ,Cluster ACP inactive bit 1" "Active,Inactive" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Cluster ACP inactive bit 0" "Active,Inactive" group.long 0x1108++0x03 line.long 0x00 "CLSINACTR_SET/CLR,Cluster Skyros SINACT Set/Clear Control Register" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " CLSINACT1 ,Cluster Skyros inactive bit 1" "Active,Inactive" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Cluster Skyros inactive bit 0" "Active,Inactive" group.long 0x1118++0x03 line.long 0x00 "CLL2FLUSHR_SET/CLR,Cluster L2FLUSH Status Set/Clear Control Register" setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CLL2FLUSH1 ,Cluster 1 L2 flush status bit 1" "Not in L2,In L2" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Cluster 1 L2 flush status bit 0" "Not in L2,In L2" group.long 0x18A0++0x03 line.long 0x00 "CLTBENR,Cluster Time Base Enable Register" bitfld.long 0x00 1. " CLTBEN1 ,Cluster timebase enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Cluster timebase enable bit 0" "Disabled,Enabled" tree.end newline width 9. rgroup.long 0xFBF8++0x07 line.long 0x00 "IPREV1R,IP Revision 1 Register" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP_ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,IP_MJ" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,IP_MN" line.long 0x04 "IPREV2R,IP Revision 2 Register" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,IP_INT" hexmask.long.byte 0x04 0.--7. 1. " IP_CFG ,IP_CFG" width 0x0B tree.end tree "PMU_SOC" base ad:0x1E30000 width 11. tree "Threads Registers" rgroup.long 0x40++0x03 line.long 0x00 "TWAITSR0,Core Wait Status Register" bitfld.long 0x00 7. " T_WAITING7 ,Core wait status bit 7" "Not in wait state,In wait state" bitfld.long 0x00 6. " [6] ,Core wait status bit 6" "Not in wait state,In wait state" bitfld.long 0x00 5. " [5] ,Core wait status bit 5" "Not in wait state,In wait state" bitfld.long 0x00 4. " [4] ,Core wait status bit 4" "Not in wait state,In wait state" newline bitfld.long 0x00 3. " [3] ,Core wait status bit 3" "Not in wait state,In wait state" bitfld.long 0x00 2. " [2] ,Core wait status bit 2" "Not in wait state,In wait state" bitfld.long 0x00 1. " [1] ,Core wait status bit 1" "Not in wait state,In wait state" bitfld.long 0x00 0. " [0] ,Core wait status bit 0" "Not in wait state,In wait state" group.long 0x1B0++0x03 line.long 0x00 "TTBHLTCR0,Core Time Base Halt Control Register" bitfld.long 0x00 7. " TTBHLT7 ,Core timebase behavior during core halted bit 7" "Stopped,Not stopped" bitfld.long 0x00 6. " [6] ,Core timebase behavior during core halted bit 6" "Stopped,Not stopped" bitfld.long 0x00 5. " [5] ,Core timebase behavior during core halted bit 5" "Stopped,Not stopped" bitfld.long 0x00 4. " [4] ,Core timebase behavior during core halted bit 4" "Stopped,Not stopped" newline bitfld.long 0x00 3. " [3] ,Core timebase behavior during core halted bit 3" "Stopped,Not stopped" bitfld.long 0x00 2. " [2] ,Core timebase behavior during core halted bit 2" "Stopped,Not stopped" bitfld.long 0x00 1. " [1] ,Core timebase behavior during core halted bit 1" "Stopped,Not stopped" bitfld.long 0x00 0. " [0] ,Core timebase behavior during core halted bit 0" "Stopped,Not stopped" tree.end width 17. tree "Physical Cores Registers" group.long 0x824++0x03 line.long 0x00 "PCPH20R_SET/CLR,Physical Core PH20 Set/Clear Control Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " PC_PH20_RQ7 ,Trigger core PH20 request bit 7" "Not requested,Requested" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Trigger core PH20 request bit 6" "Not requested,Requested" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Trigger core PH20 request bit 5" "Not requested,Requested" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Trigger core PH20 request bit 4" "Not requested,Requested" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Trigger core PH20 request bit 3" "Not requested,Requested" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Trigger core PH20 request bit 2" "Not requested,Requested" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Trigger core PH20 request bit 1" "Not requested,Requested" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Trigger core PH20 request bit 0" "Not requested,Requested" group.long 0x840++0x03 line.long 0x00 "PCPH30SR,Physical Core PH30 Status Register" bitfld.long 0x00 7. " PC7 ,Physical core PH30 status bit 7" "Not in PH30,In PH30" bitfld.long 0x00 6. " [6] ,Physical core PH30 status bit 6" "Not in PH30,In PH30" bitfld.long 0x00 5. " [5] ,Physical core PH30 status bit 5" "Not in PH30,In PH30" bitfld.long 0x00 4. " [4] ,Physical core PH30 status bit 4" "Not in PH30,In PH30" newline bitfld.long 0x00 3. " [3] ,Physical core PH30 status bit 3" "Not in PH30,In PH30" bitfld.long 0x00 2. " [2] ,Physical core PH30 status bit 2" "Not in PH30,In PH30" bitfld.long 0x00 1. " [1] ,Physical core PH30 status bit 1" "Not in PH30,In PH30" bitfld.long 0x00 0. " [0] ,Physical core PH30 status bit 0" "Not in PH30,In PH30" group.long 0x8A0++0x03 line.long 0x00 "PCTBENR,Physical Core Time Base Enable Register" bitfld.long 0x00 7. " PCTBEN7 ,Core timebase enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Core timebase enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Core timebase enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Core timebase enable bit 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Core timebase enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Core timebase enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Core timebase enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Core timebase enable bit 0" "Disabled,Enabled" group.long 0x8A8++0x03 line.long 0x00 "TBCLKDIVR,Time Base Clock Divider Register" bitfld.long 0x00 0.--4. " TBCLKDIV ,Timebase clock divider configuration" "1/16,,1/8,,,,1/24,,1/32,?..." tree.end width 12. tree "Cluster Registers" group.long 0x1000++0x03 line.long 0x00 "CLPCL10SR,Cluster PCL10 (Stop) Status Register" bitfld.long 0x00 1. " CL1 ,Cluster 0 PCL10 status bit 1" "Not in PLC10,In PLC10" bitfld.long 0x00 0. " [0] ,Cluster 0 PCL10 status bit 0" "Not in PLC10,In PLC10" group.long 0x100C++0x03 line.long 0x00 "CLPCL10PSR,Cluster PCL10 (Stop) Previous Status Register" eventfld.long 0x00 1. " CL_P_PCL10_1 ,Cluster PCL10 previous status bit 1" "Not in PCL10,In PCL10" eventfld.long 0x00 0. " [0] ,Cluster PCL10 previous status bit 0" "Not in PCL10,In PCL10" tree.end newline width 12. group.long 0x4000++0x03 line.long 0x00 "POWMGTCSR,Power Management Control And Status Register" bitfld.long 0x00 31. " LYNX_PD ,Lynx and protocol converter powerdown control" "Not in LPM,In LPM" bitfld.long 0x00 20. " LPM20_RQ ,LPM20 state request" "Not requested,Requested" bitfld.long 0x00 17. " LPM35_RQ ,LPM35 state request" "Not requested,Requested" bitfld.long 0x00 16. " LPM40_RQ ,LPM40 state request" "Not requested,Requested" newline rbitfld.long 0x00 9. " LPM20_ST ,LPM20 status" "Not attempted,Attempted" bitfld.long 0x00 8. " P_LPM20_ST ,Previous LPM20 status" "Not in LPM20,In LPM20" rbitfld.long 0x00 2. " LPM35_ST ,LPM35 status" "Not attempted,Attempted" rbitfld.long 0x00 1. " LPM40_ST ,LPM40 status" "Not attempted,Attempted" group.long 0x4040++0x17 line.long 0x00 "IPPDEXPCR0,IP Powerdown Exception Control Register 0" bitfld.long 0x00 22. " SEC ,SEC" "0,1" bitfld.long 0x00 16. " SATA1 ,SATA1" "0,1" bitfld.long 0x00 13. " USB2 ,USB2" "0,1" bitfld.long 0x00 12. " USB1 ,USB1" "0,1" newline bitfld.long 0x00 8. " QDMA ,qDMA" "0,1" bitfld.long 0x00 2. " ESDHC ,eSDHC" "0,1" line.long 0x04 "IPPDEXPCR1,IP Powerdown Exception Control Register 1" bitfld.long 0x04 9. " MAC_10 ,MAC_10" "0,1" bitfld.long 0x04 8. " [9] ,MAC_9" "0,1" bitfld.long 0x04 7. " [8] ,MAC_8" "0,1" bitfld.long 0x04 6. " [7] ,MAC_7" "0,1" newline bitfld.long 0x04 5. " [6] ,MAC_6" "0,1" bitfld.long 0x04 4. " [5] ,MAC_5" "0,1" bitfld.long 0x04 3. " [4] ,MAC_4" "0,1" bitfld.long 0x04 2. " [3] ,MAC_3" "0,1" newline bitfld.long 0x04 1. " [2] ,MAC_2" "0,1" bitfld.long 0x04 0. " [1] ,MAC_1" "0,1" line.long 0x08 "IPPDEXPCR2,IP Powerdown Exception Control Register 2" bitfld.long 0x08 16. " AIOP ,AIOP" "0,1" bitfld.long 0x08 13. " MC ,MC" "0,1" bitfld.long 0x08 12. " QBMAN ,QBMAN" "0,1" bitfld.long 0x08 2. " PCIE3 ,PCIe3" "0,1" newline bitfld.long 0x08 1. " PCIE2 ,PCIe2" "0,1" bitfld.long 0x08 0. " PCIE1 ,PCIe1" "0,1" line.long 0x0C "IPPDEXPCR3,IP Powerdown Exception Control Register 3" bitfld.long 0x0C 9. " I2C4 ,I2C4" "0,1" bitfld.long 0x0C 8. " I2C3 ,I2C3" "0,1" bitfld.long 0x0C 5. " SPI ,SPI" "0,1" bitfld.long 0x0C 4. " QSPI ,QSPI" "0,1" newline bitfld.long 0x0C 3. " DUART2 ,DUART2" "0,1" bitfld.long 0x0C 2. " DUART1 ,DUART1" "0,1" bitfld.long 0x0C 1. " I2C2 ,I2C2" "0,1" bitfld.long 0x0C 0. " I2C1 ,I2C1" "0,1" line.long 0x10 "IPPDEXPCR4,IP Powerdown Exception Control Register 4" bitfld.long 0x10 20. " PEBM ,PEBM" "0,1" bitfld.long 0x10 14. " FLEXTIMERS1_4 ,FlexTImers1_4" "0,1" bitfld.long 0x10 13. " TMU ,TMU" "0,1" bitfld.long 0x10 12. " OCRAM ,OCRAM" "0,1" newline bitfld.long 0x10 10. " DBG ,DBG" "0,1" bitfld.long 0x10 9. " GPIO ,GPIO" "0,1" bitfld.long 0x10 8. " IFC ,IFC" "0,1" bitfld.long 0x10 0. " DDR1 ,DDR1" "0,1" line.long 0x14 "IPPDEXPCR5,IP Powerdown Exception Control Register 5" bitfld.long 0x14 0. " WRIOP ,WRIOP" "0,1" width 0x0B tree.end tree "DP_PMU_PPC" base ad:0x8290000 width 21. tree "Threads Registers" group.long 0x00++0x03 line.long 0x00 "TPH10R_SET/CLR,Core PH10 Status Set/Clear Control Register" setclrfld.long 0x00 17. 0x10 17. 0x20 17. " T_PH10_REQ17 ,Core 17 PH10 status bit 17" "Not in PH10,In PH10" setclrfld.long 0x00 16. 0x10 16. 0x20 16. " [16] ,Core 16 PH10 status bit 16" "Not in PH10,In PH10" setclrfld.long 0x00 15. 0x10 15. 0x20 15. " [15] ,Core 15 PH10 status bit 15" "Not in PH10,In PH10" newline setclrfld.long 0x00 14. 0x10 14. 0x20 14. " [14] ,Core 14 PH10 status bit 14" "Not in PH10,In PH10" setclrfld.long 0x00 13. 0x10 13. 0x20 13. " [13] ,Core 13 PH10 status bit 13" "Not in PH10,In PH10" setclrfld.long 0x00 12. 0x10 12. 0x20 12. " [12] ,Core 12 PH10 status bit 12" "Not in PH10,In PH10" newline setclrfld.long 0x00 11. 0x10 11. 0x20 11. " [11] ,Core 11 PH10 status bit 11" "Not in PH10,In PH10" setclrfld.long 0x00 10. 0x10 10. 0x20 10. " [10] ,Core 10 PH10 status bit 10" "Not in PH10,In PH10" setclrfld.long 0x00 9. 0x10 9. 0x20 9. " [9] ,Core 9 PH10 status bit 9" "Not in PH10,In PH10" newline setclrfld.long 0x00 8. 0x10 8. 0x20 8. " [8] ,Core 8 PH10 status bit 8" "Not in PH10,In PH10" setclrfld.long 0x00 7. 0x10 7. 0x20 7. " [7] ,Core 7 PH10 status bit 7" "Not in PH10,In PH10" setclrfld.long 0x00 6. 0x10 6. 0x20 6. " [6] ,Core 6 PH10 status bit 6" "Not in PH10,In PH10" newline setclrfld.long 0x00 5. 0x10 5. 0x20 5. " [5] ,Core 5 PH10 status bit 5" "Not in PH10,In PH10" setclrfld.long 0x00 4. 0x10 4. 0x20 4. " [4] ,Core 4 PH10 status bit 4" "Not in PH10,In PH10" setclrfld.long 0x00 3. 0x10 3. 0x20 3. " [3] ,Core 3 PH10 status bit 3" "Not in PH10,In PH10" newline setclrfld.long 0x00 2. 0x10 2. 0x20 2. " [2] ,Core 2 PH10 status bit 2" "Not in PH10,In PH10" setclrfld.long 0x00 1. 0x10 1. 0x20 1. " [1] ,Core 1 PH10 status bit 1" "Not in PH10,In PH10" setclrfld.long 0x00 0. 0x10 0. 0x20 0. " [0] ,Core 0 PH10 status bit 0" "Not in PH10,In PH10" group.long 0x30++0x03 line.long 0x00 "TPH10PSR0,Core PH10 Previous Status Register" eventfld.long 0x00 17. " T_P_PH10_17 ,Core PH10 previous status bit 17" "Not in PH10,In PH10" eventfld.long 0x00 16. " [16] ,Core PH10 previous status bit 16" "Not in PH10,In PH10" eventfld.long 0x00 15. " [15] ,Core PH10 previous status bit 15" "Not in PH10,In PH10" newline eventfld.long 0x00 14. " [14] ,Core PH10 previous status bit 14" "Not in PH10,In PH10" eventfld.long 0x00 13. " [13] ,Core PH10 previous status bit 13" "Not in PH10,In PH10" eventfld.long 0x00 12. " [12] ,Core PH10 previous status bit 12" "Not in PH10,In PH10" newline eventfld.long 0x00 11. " [11] ,Core PH10 previous status bit 11" "Not in PH10,In PH10" eventfld.long 0x00 10. " [10] ,Core PH10 previous status bit 10" "Not in PH10,In PH10" eventfld.long 0x00 9. " [9] ,Core PH10 previous status bit 9" "Not in PH10,In PH10" newline eventfld.long 0x00 8. " [8] ,Core PH10 previous status bit 8" "Not in PH10,In PH10" eventfld.long 0x00 7. " [7] ,Core PH10 previous status bit 7" "Not in PH10,In PH10" eventfld.long 0x00 6. " [6] ,Core PH10 previous status bit 6" "Not in PH10,In PH10" newline eventfld.long 0x00 5. " [5] ,Core PH10 previous status bit 5" "Not in PH10,In PH10" eventfld.long 0x00 4. " [4] ,Core PH10 previous status bit 4" "Not in PH10,In PH10" eventfld.long 0x00 3. " [3] ,Core PH10 previous status bit 3" "Not in PH10,In PH10" newline eventfld.long 0x00 2. " [2] ,Core PH10 previous status bit 2" "Not in PH10,In PH10" eventfld.long 0x00 1. " [1] ,Core PH10 previous status bit 1" "Not in PH10,In PH10" eventfld.long 0x00 0. " [0] ,Core PH10 previous status bit 0" "Not in PH10,In PH10" rgroup.long 0x40++0x03 line.long 0x00 "TWAITSR0,Core Wait Status Register" bitfld.long 0x00 17. " T_WAITING17 ,Core wait status bit 17" "Not in wait state,In wait state" bitfld.long 0x00 16. " [16] ,Core wait status bit 16" "Not in wait state,In wait state" bitfld.long 0x00 15. " [15] ,Core wait status bit 15" "Not in wait state,In wait state" newline bitfld.long 0x00 14. " [14] ,Core wait status bit 14" "Not in wait state,In wait state" bitfld.long 0x00 13. " [13] ,Core wait status bit 13" "Not in wait state,In wait state" bitfld.long 0x00 12. " [12] ,Core wait status bit 12" "Not in wait state,In wait state" newline bitfld.long 0x00 11. " [11] ,Core wait status bit 11" "Not in wait state,In wait state" bitfld.long 0x00 10. " [10] ,Core wait status bit 10" "Not in wait state,In wait state" bitfld.long 0x00 9. " [9] ,Core wait status bit 9" "Not in wait state,In wait state" newline bitfld.long 0x00 8. " [8] ,Core wait status bit 8" "Not in wait state,In wait state" bitfld.long 0x00 7. " [7] ,Core wait status bit 7" "Not in wait state,In wait state" bitfld.long 0x00 6. " [6] ,Core wait status bit 6" "Not in wait state,In wait state" newline bitfld.long 0x00 5. " [5] ,Core wait status bit 5" "Not in wait state,In wait state" bitfld.long 0x00 4. " [4] ,Core wait status bit 4" "Not in wait state,In wait state" bitfld.long 0x00 3. " [3] ,Core wait status bit 3" "Not in wait state,In wait state" newline bitfld.long 0x00 2. " [2] ,Core wait status bit 2" "Not in wait state,In wait state" bitfld.long 0x00 1. " [1] ,Core wait status bit 1" "Not in wait state,In wait state" bitfld.long 0x00 0. " [0] ,Core wait status bit 0" "Not in wait state,In wait state" group.long 0x1B0++0x03 line.long 0x00 "TTBHLTCR0,Core Time Base Halt Control Register" bitfld.long 0x00 17. " TTBHLT17 ,Core timebase behavior during core halted bit 17" "Stopped,Not stopped" bitfld.long 0x00 16. " [16] ,Core timebase behavior during core halted bit 16" "Stopped,Not stopped" bitfld.long 0x00 15. " [15] ,Core timebase behavior during core halted bit 15" "Stopped,Not stopped" newline bitfld.long 0x00 14. " [14] ,Core timebase behavior during core halted bit 14" "Stopped,Not stopped" bitfld.long 0x00 13. " [13] ,Core timebase behavior during core halted bit 13" "Stopped,Not stopped" bitfld.long 0x00 12. " [12] ,Core timebase behavior during core halted bit 12" "Stopped,Not stopped" newline bitfld.long 0x00 11. " [11] ,Core timebase behavior during core halted bit 11" "Stopped,Not stopped" bitfld.long 0x00 10. " [10] ,Core timebase behavior during core halted bit 10" "Stopped,Not stopped" bitfld.long 0x00 9. " [9] ,Core timebase behavior during core halted bit 9" "Stopped,Not stopped" newline bitfld.long 0x00 8. " [8] ,Core timebase behavior during core halted bit 8" "Stopped,Not stopped" bitfld.long 0x00 7. " [7] ,Core timebase behavior during core halted bit 7" "Stopped,Not stopped" bitfld.long 0x00 6. " [6] ,Core timebase behavior during core halted bit 6" "Stopped,Not stopped" newline bitfld.long 0x00 5. " [5] ,Core timebase behavior during core halted bit 5" "Stopped,Not stopped" bitfld.long 0x00 4. " [4] ,Core timebase behavior during core halted bit 4" "Stopped,Not stopped" bitfld.long 0x00 3. " [3] ,Core timebase behavior during core halted bit 3" "Stopped,Not stopped" newline bitfld.long 0x00 2. " [2] ,Core timebase behavior during core halted bit 2" "Stopped,Not stopped" bitfld.long 0x00 1. " [1] ,Core timebase behavior during core halted bit 1" "Stopped,Not stopped" bitfld.long 0x00 0. " [0] ,Core timebase behavior during core halted bit 0" "Stopped,Not stopped" tree.end width 21. tree "Physical Cores Registers" group.long 0x800++0x03 line.long 0x00 "PCPH15R_SET/CLR,Physical Core PH15 Set/Clear Control Register" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PC_PH15_RQ17 ,Physical core PH15 status bit 17" "Not in PH15,In PH15" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Physical core PH15 status bit 16" "Not in PH15,In PH15" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Physical core PH15 status bit 15" "Not in PH15,In PH15" newline setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Physical core PH15 status bit 14" "Not in PH15,In PH15" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Physical core PH15 status bit 13" "Not in PH15,In PH15" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Physical core PH15 status bit 12" "Not in PH15,In PH15" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Physical core PH15 status bit 11" "Not in PH15,In PH15" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Physical core PH15 status bit 10" "Not in PH15,In PH15" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,Physical core PH15 status bit 9" "Not in PH15,In PH15" newline setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,Physical core PH15 status bit 8" "Not in PH15,In PH15" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,Physical core PH15 status bit 7" "Not in PH15,In PH15" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Physical core PH15 status bit 6" "Not in PH15,In PH15" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Physical core PH15 status bit 5" "Not in PH15,In PH15" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Physical core PH15 status bit 4" "Not in PH15,In PH15" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Physical core PH15 status bit 3" "Not in PH15,In PH15" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Physical core PH15 status bit 2" "Not in PH15,In PH15" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Physical core PH15 status bit 1" "Not in PH15,In PH15" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Physical core PH15 status bit 0" "Not in PH15,In PH15" group.long 0x80C++0x03 line.long 0x00 "PCPH15PSR,Physical Core PH15 Previous Status Register" eventfld.long 0x00 17. " PC_P_PH15_17 ,Physical core PH15 previous status bit 17" "Not in PH15,In PH15" eventfld.long 0x00 16. " [16] ,Physical core PH15 previous status bit 16" "Not in PH15,In PH15" eventfld.long 0x00 15. " [15] ,Physical core PH15 previous status bit 15" "Not in PH15,In PH15" newline eventfld.long 0x00 14. " [14] ,Physical core PH15 previous status bit 14" "Not in PH15,In PH15" eventfld.long 0x00 13. " [13] ,Physical core PH15 previous status bit 13" "Not in PH15,In PH15" eventfld.long 0x00 12. " [12] ,Physical core PH15 previous status bit 12" "Not in PH15,In PH15" newline eventfld.long 0x00 11. " [11] ,Physical core PH15 previous status bit 11" "Not in PH15,In PH15" eventfld.long 0x00 10. " [10] ,Physical core PH15 previous status bit 10" "Not in PH15,In PH15" eventfld.long 0x00 9. " [9] ,Physical core PH15 previous status bit 9" "Not in PH15,In PH15" newline eventfld.long 0x00 8. " [8] ,Physical core PH15 previous status bit 8" "Not in PH15,In PH15" eventfld.long 0x00 7. " [7] ,Physical core PH15 previous status bit 7" "Not in PH15,In PH15" eventfld.long 0x00 6. " [6] ,Physical core PH15 previous status bit 6" "Not in PH15,In PH15" newline eventfld.long 0x00 5. " [5] ,Physical core PH15 previous status bit 5" "Not in PH15,In PH15" eventfld.long 0x00 4. " [4] ,Physical core PH15 previous status bit 4" "Not in PH15,In PH15" eventfld.long 0x00 3. " [3] ,Physical core PH15 previous status bit 3" "Not in PH15,In PH15" newline eventfld.long 0x00 2. " [2] ,Physical core PH15 previous status bit 2" "Not in PH15,In PH15" eventfld.long 0x00 1. " [1] ,Physical core PH15 previous status bit 1" "Not in PH15,In PH15" eventfld.long 0x00 0. " [0] ,Physical core PH15 previous status bit 0" "Not in PH15,In PH15" group.long 0x820++0x03 line.long 0x00 "PCPH20SR,Physical Core PH20 Status Register" bitfld.long 0x00 17. " PC17 ,Physical core PH20 status bit 17" "Not in PH20,In PH20" bitfld.long 0x00 16. " [16] ,Physical core PH20 status bit 16" "Not in PH20,In PH20" bitfld.long 0x00 15. " [15] ,Physical core PH20 status bit 15" "Not in PH20,In PH20" newline bitfld.long 0x00 14. " [14] ,Physical core PH20 status bit 14" "Not in PH20,In PH20" bitfld.long 0x00 13. " [13] ,Physical core PH20 status bit 13" "Not in PH20,In PH20" bitfld.long 0x00 12. " [12] ,Physical core PH20 status bit 12" "Not in PH20,In PH20" newline bitfld.long 0x00 11. " [11] ,Physical core PH20 status bit 11" "Not in PH20,In PH20" bitfld.long 0x00 10. " [10] ,Physical core PH20 status bit 10" "Not in PH20,In PH20" bitfld.long 0x00 9. " [9] ,Physical core PH20 status bit 9" "Not in PH20,In PH20" newline bitfld.long 0x00 8. " [8] ,Physical core PH20 status bit 8" "Not in PH20,In PH20" bitfld.long 0x00 7. " [7] ,Physical core PH20 status bit 7" "Not in PH20,In PH20" bitfld.long 0x00 6. " [6] ,Physical core PH20 status bit 6" "Not in PH20,In PH20" newline bitfld.long 0x00 5. " [5] ,Physical core PH20 status bit 5" "Not in PH20,In PH20" bitfld.long 0x00 4. " [4] ,Physical core PH20 status bit 4" "Not in PH20,In PH20" bitfld.long 0x00 3. " [3] ,Physical core PH20 status bit 3" "Not in PH20,In PH20" newline bitfld.long 0x00 2. " [2] ,Physical core PH20 status bit 2" "Not in PH20,In PH20" bitfld.long 0x00 1. " [1] ,Physical core PH20 status bit 1" "Not in PH20,In PH20" bitfld.long 0x00 0. " [0] ,Physical core PH20 status bit 0" "Not in PH20,In PH20" group.long 0x82C++0x03 line.long 0x00 "PCPH20PSR,Physical Core PH20 Previous Status Register" eventfld.long 0x00 17. " PC_P_PH20_17 ,Physical core PH20 previous status bit 17" "Not in PH20,In PH20" eventfld.long 0x00 16. " [16] ,Physical core PH20 previous status bit 16" "Not in PH20,In PH20" eventfld.long 0x00 15. " [15] ,Physical core PH20 previous status bit 15" "Not in PH20,In PH20" newline eventfld.long 0x00 14. " [14] ,Physical core PH20 previous status bit 14" "Not in PH20,In PH20" eventfld.long 0x00 13. " [13] ,Physical core PH20 previous status bit 13" "Not in PH20,In PH20" eventfld.long 0x00 12. " [12] ,Physical core PH20 previous status bit 12" "Not in PH20,In PH20" newline eventfld.long 0x00 11. " [11] ,Physical core PH20 previous status bit 11" "Not in PH20,In PH20" eventfld.long 0x00 10. " [10] ,Physical core PH20 previous status bit 10" "Not in PH20,In PH20" eventfld.long 0x00 9. " [9] ,Physical core PH20 previous status bit 9" "Not in PH20,In PH20" newline eventfld.long 0x00 8. " [8] ,Physical core PH20 previous status bit 8" "Not in PH20,In PH20" eventfld.long 0x00 7. " [7] ,Physical core PH20 previous status bit 7" "Not in PH20,In PH20" eventfld.long 0x00 6. " [6] ,Physical core PH20 previous status bit 6" "Not in PH20,In PH20" newline eventfld.long 0x00 5. " [5] ,Physical core PH20 previous status bit 5" "Not in PH20,In PH20" eventfld.long 0x00 4. " [4] ,Physical core PH20 previous status bit 4" "Not in PH20,In PH20" eventfld.long 0x00 3. " [3] ,Physical core PH20 previous status bit 3" "Not in PH20,In PH20" newline eventfld.long 0x00 2. " [2] ,Physical core PH20 previous status bit 2" "Not in PH20,In PH20" eventfld.long 0x00 1. " [1] ,Physical core PH20 previous status bit 1" "Not in PH20,In PH20" eventfld.long 0x00 0. " [0] ,Physical core PH20 previous status bit 0" "Not in PH20,In PH20" group.long 0x83C++0x07 line.long 0x00 "PCRETCR,Physical Core PW20 State Retention Configuration Register" bitfld.long 0x00 17. " PC_RET_EN17 ,Physical core PW20 state retention bit 17 enable" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Physical core PW20 state retention bit 16 enable" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Physical core PW20 state retention bit 15 enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Physical core PW20 state retention bit 14 enable" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Physical core PW20 state retention bit 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Physical core PW20 state retention bit 12 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Physical core PW20 state retention bit 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Physical core PW20 state retention bit 10 enable" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Physical core PW20 state retention bit 9 enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Physical core PW20 state retention bit 8 enable" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Physical core PW20 state retention bit 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Physical core PW20 state retention bit 6 enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Physical core PW20 state retention bit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Physical core PW20 state retention bit 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Physical core PW20 state retention bit 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Physical core PW20 state retention bit 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Physical core PW20 state retention bit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Physical core PW20 state retention bit 0 enable" "Disabled,Enabled" line.long 0x04 "PCPH30SR,Physical Core PH30 Status Register" bitfld.long 0x04 17. " PC17 ,Physical core PH30 status bit 17" "Not in PH30,In PH30" bitfld.long 0x04 16. " [16] ,Physical core PH30 status bit 16" "Not in PH30,In PH30" bitfld.long 0x04 15. " [15] ,Physical core PH30 status bit 15" "Not in PH30,In PH30" newline bitfld.long 0x04 14. " [14] ,Physical core PH30 status bit 14" "Not in PH30,In PH30" bitfld.long 0x04 13. " [13] ,Physical core PH30 status bit 13" "Not in PH30,In PH30" bitfld.long 0x04 12. " [12] ,Physical core PH30 status bit 12" "Not in PH30,In PH30" newline bitfld.long 0x04 11. " [11] ,Physical core PH30 status bit 11" "Not in PH30,In PH30" bitfld.long 0x04 10. " [10] ,Physical core PH30 status bit 10" "Not in PH30,In PH30" bitfld.long 0x04 9. " [9] ,Physical core PH30 status bit 9" "Not in PH30,In PH30" newline bitfld.long 0x04 8. " [8] ,Physical core PH30 status bit 9" "Not in PH30,In PH30" bitfld.long 0x04 7. " [7] ,Physical core PH30 status bit 7" "Not in PH30,In PH30" bitfld.long 0x04 6. " [6] ,Physical core PH30 status bit 6" "Not in PH30,In PH30" newline bitfld.long 0x04 5. " [5] ,Physical core PH30 status bit 5" "Not in PH30,In PH30" bitfld.long 0x04 4. " [4] ,Physical core PH30 status bit 4" "Not in PH30,In PH30" bitfld.long 0x04 3. " [3] ,Physical core PH30 status bit 3" "Not in PH30,In PH30" newline bitfld.long 0x04 2. " [2] ,Physical core PH30 status bit 2" "Not in PH30,In PH30" bitfld.long 0x04 1. " [1] ,Physical core PH30 status bit 1" "Not in PH30,In PH30" bitfld.long 0x04 0. " [0] ,Physical core PH30 status bit 0" "Not in PH30,In PH30" group.long 0x8A0++0x03 line.long 0x00 "PCTBENR,Physical Core Time Base Enable Register" bitfld.long 0x00 17. " PCTBEN17 ,Core timebase enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Core timebase enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Core timebase enable bit 15" "Disabled,Enabled" newline bitfld.long 0x00 14. " [14] ,Core timebase enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Core timebase enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Core timebase enable bit 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Core timebase enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Core timebase enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Core timebase enable bit 9" "Disabled,Enabled" newline bitfld.long 0x00 8. " [8] ,Core timebase enable bit 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Core timebase enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Core timebase enable bit 6" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Core timebase enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Core timebase enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Core timebase enable bit 3" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Core timebase enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Core timebase enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Core timebase enable bit 0" "Disabled,Enabled" tree.end width 20. tree "Cluster Registers" group.long 0x1000++0x03 line.long 0x00 "CLPCL10SR_SET/CLR,Cluster PCL10 (Stop) Status Set/Clear Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CL4 ,Cluster 0 PCL10 status bit 4" "Not in PCL10,In PCL10" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Cluster 0 PCL10 status bit 3" "Not in PCL10,In PCL10" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Cluster 0 PCL10 status bit 2" "Not in PCL10,In PCL10" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Cluster 0 PCL10 status bit 1" "Not in PCL10,In PCL10" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Cluster 0 PCL10 status bit 0" "Not in PCL10,In PCL10" group.long 0x100C++0x03 line.long 0x00 "CLPCL10PSR,Cluster PCL10 (Stop) Previous Status Register" eventfld.long 0x00 4. " CL_P_PCL10_4 ,Cluster PCL10 previous status bit 4" "Not in PCL10,In PCL10" eventfld.long 0x00 3. " [3] ,Cluster PCL10 previous status bit 3" "Not in PCL10,In PCL10" eventfld.long 0x00 2. " [2] ,Cluster PCL10 previous status bit 2" "Not in PCL10,In PCL10" newline eventfld.long 0x00 1. " [1] ,Cluster PCL10 previous status bit 1" "Not in PCL10,In PCL10" eventfld.long 0x00 0. " [0] ,Cluster PCL10 previous status bit 0" "Not in PCL10,In PCL10" group.long 0x1020++0x03 line.long 0x00 "CLPCL20SR_SET/CLR,Cluster PCL20 (Retain) Status Set/Clear Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CL_P_PCL10_4 ,Cluster PCL20 status bit 4" "Not in PCL20,In PCL20" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Cluster PCL20 status bit 3" "Not in PCL20,In PCL20" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Cluster PCL20 status bit 2" "Not in PCL20,In PCL20" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Cluster PCL20 status bit 1" "Not in PCL20,In PCL20" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Cluster PCL20 status bit 0" "Not in PCL20,In PCL20" group.long 0x102C++0x03 line.long 0x00 "CLPCL20PSR,Cluster PCL20 (Retain) Previous Status Register" eventfld.long 0x00 4. " CL_P_PCL20_4 ,Cluster PCL20 previous status bit 4" "Not in PCL20,In PCL20" eventfld.long 0x00 3. " [3] ,Cluster PCL20 previous status bit 3" "Not in PCL20,In PCL20" eventfld.long 0x00 2. " [2] ,Cluster PCL20 previous status bit 2" "Not in PCL20,In PCL20" newline eventfld.long 0x00 1. " [1] ,Cluster PCL20 previous status bit 1" "Not in PCL20,In PCL20" eventfld.long 0x00 0. " [0] ,Cluster PCL20 previous status bit 0" "Not in PCL20,In PCL20" group.long 0x2000++0x03 line.long 0x00 "DMPDM10SR_SET/CLR,Cluster Domain DM10 (Halt) Status Set/Clear Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CL4 ,Cluster domain 0 DM10 status bit 4" "Not in DM10,In DM10" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Cluster domain 0 DM10 status bit 3" "Not in DM10,In DM10" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Cluster domain 0 DM10 status bit 2" "Not in DM10,In DM10" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Cluster domain 0 DM10 status bit 1" "Not in DM10,In DM10" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Cluster domain 0 DM10 status bit 0" "Not in DM10,In DM10" group.long 0x200C++0x03 line.long 0x00 "DMPDM10PSR,Cluster Domain DM10 (Halt) Previous Status Register" eventfld.long 0x00 4. " CL_P_DM10_4 ,Cluster DM10 previous status bit 4" "Not in DM10,In DM10" eventfld.long 0x00 3. " [3] ,Cluster DM10 previous status bit 3" "Not in DM10,In DM10" eventfld.long 0x00 2. " [2] ,Cluster DM10 previous status bit 2" "Not in DM10,In DM10" newline eventfld.long 0x00 1. " [1] ,Cluster DM10 previous status bit 1" "Not in DM10,In DM10" eventfld.long 0x00 0. " [0] ,Cluster DM10 previous status bit 0" "Not in DM10,In DM10" group.long 0x2020++0x03 line.long 0x00 "DMPDM15SR_SET/CLR,Cluster Domain DM15 (Stop) Status Set/Clear Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CL4 ,Cluster domain 4 DM15 status bit 4" "Not in DM15,In DM15" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Cluster domain 3 DM15 status bit 3" "Not in DM15,In DM15" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Cluster domain 2 DM15 status bit 2" "Not in DM15,In DM15" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Cluster domain 1 DM15 status bit 1" "Not in DM15,In DM15" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Cluster domain 0 DM15 status bit 0" "Not in DM15,In DM15" group.long 0x202C++0x03 line.long 0x00 "DMPDM15PSR,Cluster Domain DM15 (Stop) Previous Status Register" eventfld.long 0x00 4. " CL_P_DM15_4 ,Cluster DM15 previous status bit 4" "Not in DM15,In DM15" eventfld.long 0x00 3. " [3] ,Cluster DM15 previous status bit 3" "Not in DM15,In DM15" eventfld.long 0x00 2. " [2] ,Cluster DM15 previous status bit 2" "Not in DM15,In DM15" newline eventfld.long 0x00 1. " [1] ,Cluster DM15 previous status bit 1" "Not in DM15,In DM15" eventfld.long 0x00 0. " [0] ,Cluster DM15 previous status bit 0" "Not in DM15,In DM15" group.long 0x2040++0x03 line.long 0x00 "DMPDM20SR_SET/CLR,Cluster Domain DM20 (Retain) Status Set/Clear Register" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CL4 ,Cluster domain 4 DM20 status bit 4" "Not in DM20,In DM20" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Cluster domain 3 DM20 status bit 3" "Not in DM20,In DM20" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Cluster domain 2 DM20 status bit 2" "Not in DM20,In DM20" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Cluster domain 1 DM20 status bit 1" "Not in DM20,In DM20" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Cluster domain 0 DM20 status bit 0" "Not in DM20,In DM20" group.long 0x204C++0x03 line.long 0x00 "DMPDM20PSR,Cluster Domain DM20 (Retain) Previous Status Register" eventfld.long 0x00 4. " CL_P_DM20_4 ,Cluster DM20 previous status bit 4" "Not in DM20,In DM20" eventfld.long 0x00 3. " [3] ,Cluster DM20 previous status bit 3" "Not in DM20,In DM20" eventfld.long 0x00 2. " [2] ,Cluster DM20 previous status bit 2" "Not in DM20,In DM20" newline eventfld.long 0x00 1. " [1] ,Cluster DM20 previous status bit 1" "Not in DM20,In DM20" eventfld.long 0x00 0. " [0] ,Cluster DM20 previous status bit 0" "Not in DM20,In DM20" group.long 0xC000++0x03 line.long 0x00 "RSTCR,Cluster Domain Warm Reset Control Register" bitfld.long 0x00 0. " REQ ,AIOP tile reset" "No reset,Reset" group.long 0xC020++0x03 line.long 0x00 "RSTEXPCR,Cluster Domain Warm Reset Disable Control Register" bitfld.long 0x00 4. " DM_RST_DIS4 ,Cluster domain warm reset disable bit 4" "No,Yes" bitfld.long 0x00 3. " [3] ,Cluster domain warm reset disable bit 3" "No,Yes" bitfld.long 0x00 2. " [2] ,Cluster domain warm reset disable bit 2" "No,Yes" bitfld.long 0x00 1. " [1] ,Cluster domain warm reset disable bit 1" "No,Yes" bitfld.long 0x00 0. " [0] ,Cluster domain warm reset disable bit 0" "No,Yes" tree.end width 0x0B tree.end tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "QuadSPI (Quad Serial Peripheral Interface)" base ad:0x20C0000 width 9. endian.be group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 19. " ISD3FB ,Idle signal drive IOFB[3] flash B" "Logic L,Logic H" bitfld.long 0x00 18. " ISD2FB ,Idle signal drive IOFB[2] flash B" "Logic L,Logic H" bitfld.long 0x00 17. " ISD3FA ,Idle signal drive IOFA[3] flash A" "Logic L,Logic H" newline bitfld.long 0x00 16. " ISD2FA ,Idle signal drive IOFA[2] flash A" "Logic L,Logic H" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 7. " DDR_EN ,DDR mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " DQS_EN ,DQS enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " END_CFG ,Defines the endianness of the QSPI module" "64bit BE,32bit LE,32bit BE,64bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No effect,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No effect,Reset" if (((per.l.be(ad:0x20C0000+0x15C))&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " SEQID ,Points to a sequence in the look-up-table" bitfld.long 0x00 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " SEQID ,Points to a sequence in the look-up-table" bitfld.long 0x00 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" endif if ((per.l.be(ad:0x20C0000+0x15C))&0x06)==0x00 group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 14.--15. " TDH ,Serial flash data in hold time" "Aligned with the posedge of internal,Aligned with 2x,Aligned with 4x,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 14.--15. " TDH ,Serial flash data in hold time" "Aligned with the posedge of internal,Aligned with 2x,Aligned with 4x,?..." bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l.be(ad:0x20C0000+0x15C))&0x04)==0x00) group.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer 0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.byte 0x10 12.--15. 1. " SEQID ,Points to a sequence in the look-up-table" line.long 0x14 "SOCCR,SOC Configuration Register" group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer 0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer 1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer 2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x17 line.long 0x00 "BUF0CR,Buffer 0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.byte 0x10 12.--15. 1. " SEQID ,Points to a sequence in the look-up-table" line.long 0x14 "SOCCR,SOC Configuration Register" rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer 0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer 1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer 2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l.be(ad:0x20C0000+0x15C))&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif if (((per.l.be(ad:0x20C0000))&0x4000)==0x4000) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 16.--18. " DDRSMP ,DDR sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" newline bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Read counter indicates how many entries of 4 bytes have been removed from the RX Buffer" bitfld.long 0x00 8.--13. " RDBFL ,RX buffer fill level" "0 bytes,4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes,132 bytes,136 bytes,140 bytes,144 bytes,148 bytes,152 bytes,156 bytes,160 bytes,164 bytes,168 bytes,172 bytes,176 bytes,180 bytes,184 bytes,188 bytes,192 bytes,196 bytes,200 bytes,204 bytes,208 bytes,212 bytes,216 bytes,220 bytes,224 bytes,228 bytes,232 bytes,236 bytes,240 bytes,244 bytes,248 bytes,252 bytes" if (((per.l.be(ad:0x20C0000+0x15C))&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB Bus registers,IP Bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB Bus registers,IP Bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Transmit counter" bitfld.long 0x00 8.--13. " TRBFL ,TX buffer fill level" "0 bytes,4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes,132 bytes,136 bytes,140 bytes,144 bytes,148 bytes,152 bytes,156 bytes,160 bytes,164 bytes,168 bytes,172 bytes,176 bytes,180 bytes,184 bytes,188 bytes,192 bytes,196 bytes,200 bytes,204 bytes,208 bytes,212 bytes,216 bytes,220 bytes,224 bytes,228 bytes,232 bytes,236 bytes,240 bytes,244 bytes,248 bytes,252 bytes" if (((per.l.be(ad:0x20C0000+0x15C))&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 29.--31. " DLPSMP ,Data learning pattern sampling point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" bitfld.long 0x00 24. " TXEDA ,TX buffer enough data available" "Not enough,Enough" bitfld.long 0x00 23. " RXDMA ,RX buffer DMA" "Not active,Active" newline bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" newline bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "Empty,Not empty" newline bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "Empty,Not empty" bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "Empty,Not empty" bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "No pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" newline bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not initiated,Initiated" bitfld.long 0x00 1. " IP_ACC ,IP access" "Not initiated,Initiated" bitfld.long 0x00 0. " BUSY ,Module busy" "Idle,Busy" if (((per.l.be(ad:0x20C0000))&0x4000)==0x0) group.long 0x160++0x03 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 31. " DLPFF ,Data learning pattern failure flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Not full,Full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Not empty,Empty" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" newline eventfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not asserted,Asserted" eventfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 11. " IUEF ,IP command usage error flag" "No error,Error" eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" newline eventfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" else rgroup.long 0x160++0x03 line.long 0x00 "FR,Flag Register" bitfld.long 0x00 31. " DLPFF ,Data learning pattern failure flag" "Not occurred,Occurred" bitfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Not full,Full" bitfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Not empty,Empty" bitfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" newline bitfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not asserted,Asserted" bitfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" bitfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" newline bitfld.long 0x00 11. " IUEF ,IP command usage error flag" "No error,Error" bitfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" bitfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" bitfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" newline bitfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" endif group.long 0x164++0x03 line.long 0x00 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x00 31. " DLPFIE ,Data learning pattern failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " TBFDE ,TX buffer fill DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " IUEIE ,IP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l.be(ad:0x20C0000+0x168))&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,When set it signifies that a sequence is in suspended state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" bitfld.long 0x00 0. " SUSPND ,When set it signifies that a sequence is in suspended state" "Not suspended,Suspended" endif wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" if ((per.l.be(ad:0x20C0000+0x15C))&0x06)==0x00 group.long 0x180++0x13 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" line.long 0x10 "DLPR,Data Learn Pattern Register" else rgroup.long 0x180++0x13 line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" line.long 0x10 "DLPR,Data Learn Pattern Register" endif tree "RX Buffer Data Registers" hgroup.long 0x200++0x03 hide.long 0x00 "RBDR0,RX Buffer Data Register 0" in hgroup.long 0x204++0x03 hide.long 0x00 "RBDR1,RX Buffer Data Register 1" in hgroup.long 0x208++0x03 hide.long 0x00 "RBDR2,RX Buffer Data Register 2" in hgroup.long 0x20C++0x03 hide.long 0x00 "RBDR3,RX Buffer Data Register 3" in hgroup.long 0x210++0x03 hide.long 0x00 "RBDR4,RX Buffer Data Register 4" in hgroup.long 0x214++0x03 hide.long 0x00 "RBDR5,RX Buffer Data Register 5" in hgroup.long 0x218++0x03 hide.long 0x00 "RBDR6,RX Buffer Data Register 6" in hgroup.long 0x21C++0x03 hide.long 0x00 "RBDR7,RX Buffer Data Register 7" in hgroup.long 0x220++0x03 hide.long 0x00 "RBDR8,RX Buffer Data Register 8" in hgroup.long 0x224++0x03 hide.long 0x00 "RBDR9,RX Buffer Data Register 9" in hgroup.long 0x228++0x03 hide.long 0x00 "RBDR10,RX Buffer Data Register 10" in hgroup.long 0x22C++0x03 hide.long 0x00 "RBDR11,RX Buffer Data Register 11" in hgroup.long 0x230++0x03 hide.long 0x00 "RBDR12,RX Buffer Data Register 12" in hgroup.long 0x234++0x03 hide.long 0x00 "RBDR13,RX Buffer Data Register 13" in hgroup.long 0x238++0x03 hide.long 0x00 "RBDR14,RX Buffer Data Register 14" in hgroup.long 0x23C++0x03 hide.long 0x00 "RBDR15,RX Buffer Data Register 15" in hgroup.long 0x240++0x03 hide.long 0x00 "RBDR16,RX Buffer Data Register 16" in hgroup.long 0x244++0x03 hide.long 0x00 "RBDR17,RX Buffer Data Register 17" in hgroup.long 0x248++0x03 hide.long 0x00 "RBDR18,RX Buffer Data Register 18" in hgroup.long 0x24C++0x03 hide.long 0x00 "RBDR19,RX Buffer Data Register 19" in hgroup.long 0x250++0x03 hide.long 0x00 "RBDR20,RX Buffer Data Register 20" in hgroup.long 0x254++0x03 hide.long 0x00 "RBDR21,RX Buffer Data Register 21" in hgroup.long 0x258++0x03 hide.long 0x00 "RBDR22,RX Buffer Data Register 22" in hgroup.long 0x25C++0x03 hide.long 0x00 "RBDR23,RX Buffer Data Register 23" in hgroup.long 0x260++0x03 hide.long 0x00 "RBDR24,RX Buffer Data Register 24" in hgroup.long 0x264++0x03 hide.long 0x00 "RBDR25,RX Buffer Data Register 25" in hgroup.long 0x268++0x03 hide.long 0x00 "RBDR26,RX Buffer Data Register 26" in hgroup.long 0x26C++0x03 hide.long 0x00 "RBDR27,RX Buffer Data Register 27" in hgroup.long 0x270++0x03 hide.long 0x00 "RBDR28,RX Buffer Data Register 28" in hgroup.long 0x274++0x03 hide.long 0x00 "RBDR29,RX Buffer Data Register 29" in hgroup.long 0x278++0x03 hide.long 0x00 "RBDR30,RX Buffer Data Register 30" in hgroup.long 0x27C++0x03 hide.long 0x00 "RBDR31,RX Buffer Data Register 31" in tree.end newline group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 0.--1. " LOCK_UNLOCK ,Locks/Unlocks the LUT" ",Locked,Unlocked,?..." tree "Look-up Table Registers(0..63)" if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l.be(ad:0x20C0000+0x304))&0x02)==0x02) group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,ADDR_DDR,MODE_DDR,MODE2_DDR,MODE4_DDR,READ_DDR,WRITE_DDR,DATA_LEARN,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,8 pads" hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif tree.end newline tree "AHB RX Data Buffer" hgroup.long 0x60000000++0x03 hide.long 0x00 "ARDB_0,AHB RX Data Buffer Register 0" in hgroup.long 0x60000004++0x03 hide.long 0x00 "ARDB_1,AHB RX Data Buffer Register 1" in hgroup.long 0x60000008++0x03 hide.long 0x00 "ARDB_2,AHB RX Data Buffer Register 2" in hgroup.long 0x6000000C++0x03 hide.long 0x00 "ARDB_3,AHB RX Data Buffer Register 3" in hgroup.long 0x60000010++0x03 hide.long 0x00 "ARDB_4,AHB RX Data Buffer Register 4" in hgroup.long 0x60000014++0x03 hide.long 0x00 "ARDB_5,AHB RX Data Buffer Register 5" in hgroup.long 0x60000018++0x03 hide.long 0x00 "ARDB_6,AHB RX Data Buffer Register 6" in hgroup.long 0x6000001C++0x03 hide.long 0x00 "ARDB_7,AHB RX Data Buffer Register 7" in hgroup.long 0x60000020++0x03 hide.long 0x00 "ARDB_8,AHB RX Data Buffer Register 8" in hgroup.long 0x60000024++0x03 hide.long 0x00 "ARDB_9,AHB RX Data Buffer Register 9" in hgroup.long 0x60000028++0x03 hide.long 0x00 "ARDB_10,AHB RX Data Buffer Register 10" in hgroup.long 0x6000002C++0x03 hide.long 0x00 "ARDB_11,AHB RX Data Buffer Register 11" in hgroup.long 0x60000030++0x03 hide.long 0x00 "ARDB_12,AHB RX Data Buffer Register 12" in hgroup.long 0x60000034++0x03 hide.long 0x00 "ARDB_13,AHB RX Data Buffer Register 13" in hgroup.long 0x60000038++0x03 hide.long 0x00 "ARDB_14,AHB RX Data Buffer Register 14" in hgroup.long 0x6000003C++0x03 hide.long 0x00 "ARDB_15,AHB RX Data Buffer Register 15" in hgroup.long 0x60000040++0x03 hide.long 0x00 "ARDB_16,AHB RX Data Buffer Register 16" in hgroup.long 0x60000044++0x03 hide.long 0x00 "ARDB_17,AHB RX Data Buffer Register 17" in hgroup.long 0x60000048++0x03 hide.long 0x00 "ARDB_18,AHB RX Data Buffer Register 18" in hgroup.long 0x6000004C++0x03 hide.long 0x00 "ARDB_19,AHB RX Data Buffer Register 19" in hgroup.long 0x60000050++0x03 hide.long 0x00 "ARDB_20,AHB RX Data Buffer Register 20" in hgroup.long 0x60000054++0x03 hide.long 0x00 "ARDB_21,AHB RX Data Buffer Register 21" in hgroup.long 0x60000058++0x03 hide.long 0x00 "ARDB_22,AHB RX Data Buffer Register 22" in hgroup.long 0x6000005C++0x03 hide.long 0x00 "ARDB_23,AHB RX Data Buffer Register 23" in hgroup.long 0x60000060++0x03 hide.long 0x00 "ARDB_24,AHB RX Data Buffer Register 24" in hgroup.long 0x60000064++0x03 hide.long 0x00 "ARDB_25,AHB RX Data Buffer Register 25" in hgroup.long 0x60000068++0x03 hide.long 0x00 "ARDB_26,AHB RX Data Buffer Register 26" in hgroup.long 0x6000006C++0x03 hide.long 0x00 "ARDB_27,AHB RX Data Buffer Register 27" in hgroup.long 0x60000070++0x03 hide.long 0x00 "ARDB_28,AHB RX Data Buffer Register 28" in hgroup.long 0x60000074++0x03 hide.long 0x00 "ARDB_29,AHB RX Data Buffer Register 29" in hgroup.long 0x60000078++0x03 hide.long 0x00 "ARDB_30,AHB RX Data Buffer Register 30" in hgroup.long 0x6000007C++0x03 hide.long 0x00 "ARDB_31,AHB RX Data Buffer Register 31" in tree.end endian.le width 0x0B tree.end else tree "QuadSPI (Quad Serial Peripheral Interface)" base ad:0x1550000 width 9. group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " SCLKCFG ,Serial clock configuration" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO/Buffer" "No effect,Clear" newline bitfld.long 0x00 2.--3. " END_CFG ,Defines the endianness of the QSPI module" "64bit BE,32bit LE,32bit BE,64bit LE" bitfld.long 0x00 1. " SWRSTHD ,Software reset for AHB domain" "No effect,Reset" bitfld.long 0x00 0. " SWRSTSD ,Software reset for serial flash domain" "No effect,Reset" if (((per.l(ad:0x1550000+0x15C))&0x02)==0x00) group.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " SEQID ,Points to a sequence in the look-up-table" bitfld.long 0x00 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" else rgroup.long 0x08++0x03 line.long 0x00 "IPCR,IP Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " SEQID ,Points to a sequence in the look-up-table" bitfld.long 0x00 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " IDATSZ ,IP data transfer size" endif if ((per.l(ad:0x1550000+0x15C))&0x06)==0x00 group.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0x0C++0x03 line.long 0x00 "FLSHCR,Flash Configuration Register" bitfld.long 0x00 8.--11. " TCSH ,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TCSS ,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.l(ad:0x1550000+0x15C))&0x04)==0x00) group.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer 0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.byte 0x10 12.--15. 1. " SEQID ,Points to a sequence in the look-up-table" group.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer 0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer 1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer 2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" else rgroup.long 0x10++0x13 line.long 0x00 "BUF0CR,Buffer 0 Configuration Register" bitfld.long 0x00 31. " HP_EN ,High priority enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x00 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "BUF1CR,Buffer 1 Configuration Register" hexmask.long.byte 0x04 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x04 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "BUF2CR,Buffer 2 Configuration Register" hexmask.long.byte 0x08 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x08 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "BUF3CR,Buffer 3 Configuration Register" bitfld.long 0x0C 31. " ALLMST ,All master enable" "Disabled,Enabled" hexmask.long.byte 0x0C 8.--15. 1. " ADATSZ ,AHB data transfer size" bitfld.long 0x0C 0.--3. " MSTRID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "BFGENCR,Buffer Generic Configuration Register" bitfld.long 0x10 16. " PAR_EN ,Parallel flash mode enable" "Disabled,Enabled" hexmask.long.byte 0x10 12.--15. 1. " SEQID ,Points to a sequence in the look-up-table" rgroup.long 0x30++0x0B line.long 0x00 "BUF0IND,Buffer 0 Top Index Register" hexmask.long 0x00 3.--31. 1. " TPINDX0 ,Top index of buffer 0" line.long 0x04 "BUF1IND,Buffer 1 Top Index Register" hexmask.long 0x04 3.--31. 1. " TPINDX1 ,Top index of buffer 1" line.long 0x08 "BUF2IND,Buffer 2 Top Index Register" hexmask.long 0x08 3.--31. 1. " TPINDX2 ,Top index of buffer 2" endif if (((per.l(ad:0x1550000+0x15C))&0x02)==0x00) group.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" else rgroup.long 0x100++0x03 line.long 0x00 "SFAR,Serial Flash Address Register" endif if (((per.l(ad:0x1550000))&0x4000)==0x4000) group.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" else rgroup.long 0x108++0x03 line.long 0x00 "SMPR,Sampling Register" bitfld.long 0x00 6. " FSDLY ,Full speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 5. " FSPHS ,Full speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" bitfld.long 0x00 2. " HSDLY ,Half speed delay selection for SDR instructions" "One cycle,Two cycles" bitfld.long 0x00 1. " HSPHS ,Half speed phase selection for SDR instructions" "Non-inverted clock,Inverted clock" newline bitfld.long 0x00 0. " HSENA ,Half speed serial flash clock enable" "Disabled,Enabled" endif rgroup.long 0x10C++0x03 line.long 0x00 "RBSR,RX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " RDCTR ,Read counter indicates how many entries of 4 bytes have been removed from the RX Buffer" bitfld.long 0x00 8.--13. " RDBFL ,RX buffer fill level" "0 bytes,4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes,132 bytes,136 bytes,140 bytes,144 bytes,148 bytes,152 bytes,156 bytes,160 bytes,164 bytes,168 bytes,172 bytes,176 bytes,180 bytes,184 bytes,188 bytes,192 bytes,196 bytes,200 bytes,204 bytes,208 bytes,212 bytes,216 bytes,220 bytes,224 bytes,228 bytes,232 bytes,236 bytes,240 bytes,244 bytes,248 bytes,252 bytes" if (((per.l.be(ad:0x1550000+0x15C))&0x02)==0x00) group.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB Bus registers,IP Bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" else rgroup.long 0x110++0x03 line.long 0x00 "RBCT,RX Buffer Control Register" bitfld.long 0x00 8. " RXBRD ,RX buffer readout" "AHB Bus registers,IP Bus registers" bitfld.long 0x00 0.--4. " WMRK ,RX buffer watermark" "4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes,128 bytes" endif rgroup.long 0x150++0x03 line.long 0x00 "TBSR,TX Buffer Status Register" hexmask.long.word 0x00 16.--31. 1. " TRCTR ,Transmit counter" bitfld.long 0x00 8.--12. " TRBFL ,TX buffer fill level" "0 bytes,4 bytes,8 bytes,12 bytes,16 bytes,20 bytes,24 bytes,28 bytes,32 bytes,36 bytes,40 bytes,44 bytes,48 bytes,52 bytes,56 bytes,60 bytes,64 bytes,68 bytes,72 bytes,76 bytes,80 bytes,84 bytes,88 bytes,92 bytes,96 bytes,100 bytes,104 bytes,108 bytes,112 bytes,116 bytes,120 bytes,124 bytes" if (((per.l(ad:0x1550000+0x15C))&0x8000000)==0x00) group.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" else rgroup.long 0x154++0x03 line.long 0x00 "TBDR,TX Buffer Data Register" endif rgroup.long 0x15C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 27. " TXFULL ,TX buffer full" "Not full,Full" bitfld.long 0x00 24. " TXNE ,TX buffer not empty" "Empty,Not empty" bitfld.long 0x00 23. " RXDMA ,RX buffer DMA" "Not active,Active" bitfld.long 0x00 19. " RXFULL ,RX buffer full" "Not full,Full" newline bitfld.long 0x00 16. " RXWE ,RX buffer watermark exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 14. " AHB3FUL ,AHB 3 buffer full" "Not full,Full" bitfld.long 0x00 13. " AHB2FUL ,AHB 2 buffer full" "Not full,Full" bitfld.long 0x00 12. " AHB1FUL ,AHB 1 buffer full" "Not full,Full" newline bitfld.long 0x00 11. " AHB0FUL ,AHB 0 buffer full" "Not full,Full" bitfld.long 0x00 10. " AHB3NE ,AHB 3 buffer not empty" "Empty,Not empty" bitfld.long 0x00 9. " AHB2NE ,AHB 2 buffer not empty" "Empty,Not empty" bitfld.long 0x00 8. " AHB1NE ,AHB 1 buffer not empty" "Empty,Not empty" newline bitfld.long 0x00 7. " AHB0NE ,AHB 0 buffer not empty" "Empty,Not empty" bitfld.long 0x00 6. " AHBTRN ,AHB access transaction pending" "No pending,Pending" bitfld.long 0x00 5. " AHBGNT ,AHB command priority granted" "Not granted,Granted" bitfld.long 0x00 2. " AHB_ACC ,AHB access" "Not initiated,Initiated" newline bitfld.long 0x00 1. " IP_ACC ,IP access" "Not initiated,Initiated" bitfld.long 0x00 0. " BUSY ,Module busy" "Idle,Busy" if (((per.l(ad:0x1550000))&0x4000)==0x0) group.long 0x160++0x03 line.long 0x00 "FR,Flag Register" eventfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Not full,Full" eventfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Not empty,Empty" eventfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" eventfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not asserted,Asserted" eventfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" eventfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" eventfld.long 0x00 11. " IUEF ,IP command usage error flag" "No error,Error" newline eventfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" eventfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" eventfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" eventfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" else rgroup.long 0x160++0x03 line.long 0x00 "FR,Flag Register" bitfld.long 0x00 27. " TBFF ,TX buffer fill flag" "Not full,Full" bitfld.long 0x00 26. " TBUF ,TX buffer underrun flag" "Not empty,Empty" bitfld.long 0x00 23. " ILLINE ,Illegal instruction error flag" "No error,Error" bitfld.long 0x00 17. " RBOF ,RX buffer overflow flag" "No overflow,Overflow" newline bitfld.long 0x00 16. " RBDF ,RX buffer drain flag" "Not asserted,Asserted" bitfld.long 0x00 15. " ABSEF ,AHB sequence error flag" "No error,Error" bitfld.long 0x00 12. " ABOF ,AHB buffer overflow flag" "No overflow,Overflow" bitfld.long 0x00 11. " IUEF ,IP command usage error flag" "No error,Error" newline bitfld.long 0x00 7. " IPAEF ,IP command trigger during AHB access error flag" "No error,Error" bitfld.long 0x00 6. " IPIEF ,IP command trigger could not be executed error flag" "No error,Error" bitfld.long 0x00 4. " IPGEF ,IP command trigger during AHB grant error flag" "No error,Error" bitfld.long 0x00 0. " TFF ,IP command transaction finished flag" "Not finished,Finished" endif group.long 0x164++0x03 line.long 0x00 "RSER,Interrupt and DMA Request Select and Enable Register" bitfld.long 0x00 27. " TBFIE ,TX buffer fill interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " TBUIE ,TX buffer underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " ILLINIE ,Illegal instruction error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 21. " RBDDE ,RX buffer drain DMA enable" "Disabled,Enabled" bitfld.long 0x00 17. " RBOIE ,RX buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " RBDIE ,RX buffer drain interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " ABSEIE ,AHB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 12. " ABOIE ,AHB buffer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " IUEIE ,IP command usage error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " IPAEIE ,IP command trigger during AHB access error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " IPIEIE ,IP command trigger during IP access error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " IPGEIE ,IP command trigger during AHB grant error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TFIE ,Transaction finished interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x1550000+0x168))&0x01)==0x01) rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" hexmask.long.byte 0x00 9.--15. 1. " DATLFT ,Data left" bitfld.long 0x00 6.--7. " SPDBUF ,Suspended buffer" "0,1,2,3" newline bitfld.long 0x00 0. " SUSPND ,When set it signifies that a sequence is in suspended state" "Not suspended,Suspended" else rgroup.long 0x168++0x03 line.long 0x00 "SPNDST,Sequence Suspend Status Register" bitfld.long 0x00 0. " SUSPND ,When set it signifies that a sequence is in suspended state" "Not suspended,Suspended" endif wgroup.long 0x16C++0x03 line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register" bitfld.long 0x00 8. " IPPTRC ,IP pointer clear" "No effect,Clear" bitfld.long 0x00 0. " BFPTRC ,Buffer pointer clear" "No effect,Clear" if ((per.l(ad:0x1550000+0x15C))&0x06)==0x00 group.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" else rgroup.long 0x180++0x0F line.long 0x00 "SFA1AD,Serial Flash A1 Top Address" hexmask.long.tbyte 0x00 10.--31. 0x04 " TPADA1 ,Top address for serial flash A1" line.long 0x04 "SFA2AD,Serial Flash A2 Top Address" hexmask.long.tbyte 0x04 10.--31. 0x04 " TPADA2 ,Top address for serial flash A2" line.long 0x08 "SFB1AD,Serial Flash B1 Top Address" hexmask.long.tbyte 0x08 10.--31. 0x04 " TPADB1 ,Top address for serial flash B1" line.long 0x0C "SFB2AD,Serial Flash B2 Top Address" hexmask.long.tbyte 0x0C 10.--31. 0x04 " TPADB2 ,Top address for serial flash B2" endif tree "RX Buffer Data Registers" hgroup.long 0x200++0x03 hide.long 0x00 "RBDR0,RX Buffer Data Register 0" in hgroup.long 0x204++0x03 hide.long 0x00 "RBDR1,RX Buffer Data Register 1" in hgroup.long 0x208++0x03 hide.long 0x00 "RBDR2,RX Buffer Data Register 2" in hgroup.long 0x20C++0x03 hide.long 0x00 "RBDR3,RX Buffer Data Register 3" in hgroup.long 0x210++0x03 hide.long 0x00 "RBDR4,RX Buffer Data Register 4" in hgroup.long 0x214++0x03 hide.long 0x00 "RBDR5,RX Buffer Data Register 5" in hgroup.long 0x218++0x03 hide.long 0x00 "RBDR6,RX Buffer Data Register 6" in hgroup.long 0x21C++0x03 hide.long 0x00 "RBDR7,RX Buffer Data Register 7" in hgroup.long 0x220++0x03 hide.long 0x00 "RBDR8,RX Buffer Data Register 8" in hgroup.long 0x224++0x03 hide.long 0x00 "RBDR9,RX Buffer Data Register 9" in hgroup.long 0x228++0x03 hide.long 0x00 "RBDR10,RX Buffer Data Register 10" in hgroup.long 0x22C++0x03 hide.long 0x00 "RBDR11,RX Buffer Data Register 11" in hgroup.long 0x230++0x03 hide.long 0x00 "RBDR12,RX Buffer Data Register 12" in hgroup.long 0x234++0x03 hide.long 0x00 "RBDR13,RX Buffer Data Register 13" in hgroup.long 0x238++0x03 hide.long 0x00 "RBDR14,RX Buffer Data Register 14" in hgroup.long 0x23C++0x03 hide.long 0x00 "RBDR15,RX Buffer Data Register 15" in hgroup.long 0x240++0x03 hide.long 0x00 "RBDR16,RX Buffer Data Register 16" in hgroup.long 0x244++0x03 hide.long 0x00 "RBDR17,RX Buffer Data Register 17" in hgroup.long 0x248++0x03 hide.long 0x00 "RBDR18,RX Buffer Data Register 18" in hgroup.long 0x24C++0x03 hide.long 0x00 "RBDR19,RX Buffer Data Register 19" in hgroup.long 0x250++0x03 hide.long 0x00 "RBDR20,RX Buffer Data Register 20" in hgroup.long 0x254++0x03 hide.long 0x00 "RBDR21,RX Buffer Data Register 21" in hgroup.long 0x258++0x03 hide.long 0x00 "RBDR22,RX Buffer Data Register 22" in hgroup.long 0x25C++0x03 hide.long 0x00 "RBDR23,RX Buffer Data Register 23" in hgroup.long 0x260++0x03 hide.long 0x00 "RBDR24,RX Buffer Data Register 24" in hgroup.long 0x264++0x03 hide.long 0x00 "RBDR25,RX Buffer Data Register 25" in hgroup.long 0x268++0x03 hide.long 0x00 "RBDR26,RX Buffer Data Register 26" in hgroup.long 0x26C++0x03 hide.long 0x00 "RBDR27,RX Buffer Data Register 27" in hgroup.long 0x270++0x03 hide.long 0x00 "RBDR28,RX Buffer Data Register 28" in hgroup.long 0x274++0x03 hide.long 0x00 "RBDR29,RX Buffer Data Register 29" in hgroup.long 0x278++0x03 hide.long 0x00 "RBDR30,RX Buffer Data Register 30" in hgroup.long 0x27C++0x03 hide.long 0x00 "RBDR31,RX Buffer Data Register 31" in tree.end newline group.long 0x300++0x07 line.long 0x00 "LUTKEY,LUT Key Register" line.long 0x04 "LCKCR,LUT Lock Configuration Register" bitfld.long 0x04 0.--1. " LOCK_UNLOCK ,Locks/Unlocks the LUT" ",Locked,Unlocked,?..." tree "Look-up Table Registers(0..63)" if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x310++0x03 line.long 0x00 "LUT0,Look-up Table Register 0" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x314++0x03 line.long 0x00 "LUT1,Look-up Table Register 1" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x318++0x03 line.long 0x00 "LUT2,Look-up Table Register 2" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x31C++0x03 line.long 0x00 "LUT3,Look-up Table Register 3" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x320++0x03 line.long 0x00 "LUT4,Look-up Table Register 4" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x324++0x03 line.long 0x00 "LUT5,Look-up Table Register 5" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x328++0x03 line.long 0x00 "LUT6,Look-up Table Register 6" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x32C++0x03 line.long 0x00 "LUT7,Look-up Table Register 7" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x330++0x03 line.long 0x00 "LUT8,Look-up Table Register 8" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x334++0x03 line.long 0x00 "LUT9,Look-up Table Register 9" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x338++0x03 line.long 0x00 "LUT10,Look-up Table Register 10" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x33C++0x03 line.long 0x00 "LUT11,Look-up Table Register 11" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x340++0x03 line.long 0x00 "LUT12,Look-up Table Register 12" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x344++0x03 line.long 0x00 "LUT13,Look-up Table Register 13" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x348++0x03 line.long 0x00 "LUT14,Look-up Table Register 14" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x34C++0x03 line.long 0x00 "LUT15,Look-up Table Register 15" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x350++0x03 line.long 0x00 "LUT16,Look-up Table Register 16" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x354++0x03 line.long 0x00 "LUT17,Look-up Table Register 17" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x358++0x03 line.long 0x00 "LUT18,Look-up Table Register 18" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x35C++0x03 line.long 0x00 "LUT19,Look-up Table Register 19" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x360++0x03 line.long 0x00 "LUT20,Look-up Table Register 20" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x364++0x03 line.long 0x00 "LUT21,Look-up Table Register 21" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x368++0x03 line.long 0x00 "LUT22,Look-up Table Register 22" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x36C++0x03 line.long 0x00 "LUT23,Look-up Table Register 23" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x370++0x03 line.long 0x00 "LUT24,Look-up Table Register 24" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x374++0x03 line.long 0x00 "LUT25,Look-up Table Register 25" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x378++0x03 line.long 0x00 "LUT26,Look-up Table Register 26" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x37C++0x03 line.long 0x00 "LUT27,Look-up Table Register 27" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x380++0x03 line.long 0x00 "LUT28,Look-up Table Register 28" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x384++0x03 line.long 0x00 "LUT29,Look-up Table Register 29" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x388++0x03 line.long 0x00 "LUT30,Look-up Table Register 30" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x38C++0x03 line.long 0x00 "LUT31,Look-up Table Register 31" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x390++0x03 line.long 0x00 "LUT32,Look-up Table Register 32" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x394++0x03 line.long 0x00 "LUT33,Look-up Table Register 33" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x398++0x03 line.long 0x00 "LUT34,Look-up Table Register 34" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x39C++0x03 line.long 0x00 "LUT35,Look-up Table Register 35" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A0++0x03 line.long 0x00 "LUT36,Look-up Table Register 36" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A4++0x03 line.long 0x00 "LUT37,Look-up Table Register 37" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3A8++0x03 line.long 0x00 "LUT38,Look-up Table Register 38" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3AC++0x03 line.long 0x00 "LUT39,Look-up Table Register 39" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B0++0x03 line.long 0x00 "LUT40,Look-up Table Register 40" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B4++0x03 line.long 0x00 "LUT41,Look-up Table Register 41" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3B8++0x03 line.long 0x00 "LUT42,Look-up Table Register 42" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3BC++0x03 line.long 0x00 "LUT43,Look-up Table Register 43" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C0++0x03 line.long 0x00 "LUT44,Look-up Table Register 44" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C4++0x03 line.long 0x00 "LUT45,Look-up Table Register 45" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3C8++0x03 line.long 0x00 "LUT46,Look-up Table Register 46" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3CC++0x03 line.long 0x00 "LUT47,Look-up Table Register 47" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D0++0x03 line.long 0x00 "LUT48,Look-up Table Register 48" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D4++0x03 line.long 0x00 "LUT49,Look-up Table Register 49" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3D8++0x03 line.long 0x00 "LUT50,Look-up Table Register 50" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3DC++0x03 line.long 0x00 "LUT51,Look-up Table Register 51" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E0++0x03 line.long 0x00 "LUT52,Look-up Table Register 52" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E4++0x03 line.long 0x00 "LUT53,Look-up Table Register 53" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3E8++0x03 line.long 0x00 "LUT54,Look-up Table Register 54" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3EC++0x03 line.long 0x00 "LUT55,Look-up Table Register 55" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F0++0x03 line.long 0x00 "LUT56,Look-up Table Register 56" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F4++0x03 line.long 0x00 "LUT57,Look-up Table Register 57" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3F8++0x03 line.long 0x00 "LUT58,Look-up Table Register 58" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x3FC++0x03 line.long 0x00 "LUT59,Look-up Table Register 59" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x400++0x03 line.long 0x00 "LUT60,Look-up Table Register 60" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x404++0x03 line.long 0x00 "LUT61,Look-up Table Register 61" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x408++0x03 line.long 0x00 "LUT62,Look-up Table Register 62" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif if (((per.l(ad:0x1550000+0x304))&0x02)==0x02) group.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" else rgroup.long 0x40C++0x03 line.long 0x00 "LUT63,Look-up Table Register 63" bitfld.long 0x00 26.--31. " INSTR1 ,Instruction 1" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 24.--25. " PAD1 ,Pad information for INSTR1" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 16.--23. 1. " OPRND1 ,Operand for INSTR1" newline bitfld.long 0x00 10.--15. " INSTR0 ,Instruction 0" "STOP,CMD,ADDR,DUMMY,MODE,MODE2,MODE4,READ,WRITE,JMP_ON_CS,?..." bitfld.long 0x00 8.--9. " PAD0 ,Pad information for INSTR0" "1 pad,2 pads,4 pads,?..." hexmask.long.byte 0x00 0.--7. 1. " OPRND0 ,Operand for INSTR0" endif tree.end newline tree "AHB RX Data Buffer" hgroup.long 0x60000000++0x03 hide.long 0x00 "ARDB_0,AHB RX Data Buffer Register 0" in hgroup.long 0x60000004++0x03 hide.long 0x00 "ARDB_1,AHB RX Data Buffer Register 1" in hgroup.long 0x60000008++0x03 hide.long 0x00 "ARDB_2,AHB RX Data Buffer Register 2" in hgroup.long 0x6000000C++0x03 hide.long 0x00 "ARDB_3,AHB RX Data Buffer Register 3" in hgroup.long 0x60000010++0x03 hide.long 0x00 "ARDB_4,AHB RX Data Buffer Register 4" in hgroup.long 0x60000014++0x03 hide.long 0x00 "ARDB_5,AHB RX Data Buffer Register 5" in hgroup.long 0x60000018++0x03 hide.long 0x00 "ARDB_6,AHB RX Data Buffer Register 6" in hgroup.long 0x6000001C++0x03 hide.long 0x00 "ARDB_7,AHB RX Data Buffer Register 7" in hgroup.long 0x60000020++0x03 hide.long 0x00 "ARDB_8,AHB RX Data Buffer Register 8" in hgroup.long 0x60000024++0x03 hide.long 0x00 "ARDB_9,AHB RX Data Buffer Register 9" in hgroup.long 0x60000028++0x03 hide.long 0x00 "ARDB_10,AHB RX Data Buffer Register 10" in hgroup.long 0x6000002C++0x03 hide.long 0x00 "ARDB_11,AHB RX Data Buffer Register 11" in hgroup.long 0x60000030++0x03 hide.long 0x00 "ARDB_12,AHB RX Data Buffer Register 12" in hgroup.long 0x60000034++0x03 hide.long 0x00 "ARDB_13,AHB RX Data Buffer Register 13" in hgroup.long 0x60000038++0x03 hide.long 0x00 "ARDB_14,AHB RX Data Buffer Register 14" in hgroup.long 0x6000003C++0x03 hide.long 0x00 "ARDB_15,AHB RX Data Buffer Register 15" in hgroup.long 0x60000040++0x03 hide.long 0x00 "ARDB_16,AHB RX Data Buffer Register 16" in hgroup.long 0x60000044++0x03 hide.long 0x00 "ARDB_17,AHB RX Data Buffer Register 17" in hgroup.long 0x60000048++0x03 hide.long 0x00 "ARDB_18,AHB RX Data Buffer Register 18" in hgroup.long 0x6000004C++0x03 hide.long 0x00 "ARDB_19,AHB RX Data Buffer Register 19" in hgroup.long 0x60000050++0x03 hide.long 0x00 "ARDB_20,AHB RX Data Buffer Register 20" in hgroup.long 0x60000054++0x03 hide.long 0x00 "ARDB_21,AHB RX Data Buffer Register 21" in hgroup.long 0x60000058++0x03 hide.long 0x00 "ARDB_22,AHB RX Data Buffer Register 22" in hgroup.long 0x6000005C++0x03 hide.long 0x00 "ARDB_23,AHB RX Data Buffer Register 23" in hgroup.long 0x60000060++0x03 hide.long 0x00 "ARDB_24,AHB RX Data Buffer Register 24" in hgroup.long 0x60000064++0x03 hide.long 0x00 "ARDB_25,AHB RX Data Buffer Register 25" in hgroup.long 0x60000068++0x03 hide.long 0x00 "ARDB_26,AHB RX Data Buffer Register 26" in hgroup.long 0x6000006C++0x03 hide.long 0x00 "ARDB_27,AHB RX Data Buffer Register 27" in hgroup.long 0x60000070++0x03 hide.long 0x00 "ARDB_28,AHB RX Data Buffer Register 28" in hgroup.long 0x60000074++0x03 hide.long 0x00 "ARDB_29,AHB RX Data Buffer Register 29" in hgroup.long 0x60000078++0x03 hide.long 0x00 "ARDB_30,AHB RX Data Buffer Register 30" in hgroup.long 0x6000007C++0x03 hide.long 0x00 "ARDB_31,AHB RX Data Buffer Register 31" in tree.end width 0x0B tree.end endif sif cpuis("LS10?3*")||cpuis("LS10?6*") tree "qDMA (Queue Direct Memory Access)" base ad:0x8380000 width 10. group.long 0x00++0x03 line.long 0x00 "DMR,DMA Mode Register" bitfld.long 0x00 31. " SR ,Soft reset" "No effect,Reset" bitfld.long 0x00 30. " DQD ,Dequeue disable" "No,Yes" bitfld.long 0x00 29. " GBT ,Global bandwidth throttle enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " SD ,Snoop disable for memory data access" "No,Yes" bitfld.long 0x00 20. " DSD ,Snoop disable for memory descriptor access" "No,Yes" bitfld.long 0x00 16. " TCD ,Throttle control disable" "No,Yes" sif cpuis("LS10?6*") bitfld.long 0x00 15. " LRM ,Legacy repeat mode" "Disabled,Enabled" endif newline bitfld.long 0x00 8.--10. " DQOS ,QoS for memory descriptor access" "0,1,2,3,4,5,6,7" rgroup.long 0x04++0x03 line.long 0x00 "DSR_P,DMA Status Register" bitfld.long 0x00 31. " DB ,DMA busy" "Idle,Busy" sif cpuis("LS10?6*") group.long 0x14++0x03 line.long 0x00 "DLSIDR,DMA Legacy Stream ID Register" hexmask.long.byte 0x00 0.--7. 1. " STREAM_ID ,Stream ID for data transactions issued in legacy mode" endif group.long 0x40++0x03 line.long 0x00 "DSIDFR,DMA Stream ID Flush Register" bitfld.long 0x00 30.--31. " FM ,Flush mode enable" "Disabled,Stream ID match only,?..." hexmask.long.byte 0x00 0.--7. 1. " STREAM_ID ,Stream ID for data transactions issued in legacy mode" rgroup.long 0x10004++0x03 line.long 0x00 "DSR_M,DMA Status Register" bitfld.long 0x00 31. " DB ,DMA busy" "Idle,Busy" group.long 0x10040++0x03 line.long 0x00 "DGBTR,DMA Global Bandwidth Throttle Register" bitfld.long 0x00 16.--19. " TBC ,Token bucket capacity (in bytes) defined by 2TBC" ",,,,,,,,256B,512B,1KB,2KB,4KB,?..." bitfld.long 0x00 8.--10. " MULT ,The token addition rate multiplier is 2MULT" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " SCALE ,The token addition rate scaler is 2SCALE" "0,1,2,3,4,5,6,7" sif cpuis("LS10?6*") if ((per.l(ad:0x8380000+0x10100)&0x40000)==0x40000) group.long 0x10100++0x03 line.long 0x00 "DLMR,DMA Legacy Mode Register" bitfld.long 0x00 24.--27. " PC ,Pause control" "1 bytes,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,?..." bitfld.long 0x00 21. " EMP ,External master pause mode" "Disabled,Enabled" bitfld.long 0x00 18. " EMC ,External master control" "Disabled,Enabled" bitfld.long 0x00 16.--17. " DAHTS ,Destination address hold transfer size" "1 byte,2 bytes,4 bytes,8 bytes" newline bitfld.long 0x00 14.--15. " SAHTS ,Source address hold transfer size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination address hold enable" "Disabled,Enabled" bitfld.long 0x00 12. " SAHE ,Source address hold enable" "Disabled,Enabled" bitfld.long 0x00 11. " PF ,Prefetchable" "Non prefetchable,Prefetchable" newline bitfld.long 0x00 10. " SRW ,Single register write" "Normal,Enabled" bitfld.long 0x00 9. " EOSIE ,End-of-segments interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " EIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SWSM ,Single write start mode" "Disabled,Enabled" newline bitfld.long 0x00 0. " CS ,Channel start" "Halt,Start" else group.long 0x10100++0x03 line.long 0x00 "DLMR,DMA Legacy Mode Register" bitfld.long 0x00 21. " EMP ,External master pause mode" "Disabled,Enabled" bitfld.long 0x00 18. " EMC ,External master control" "Disabled,Enabled" bitfld.long 0x00 16.--17. " DAHTS ,Destination address hold transfer size" "1 byte,2 bytes,4 bytes,8 bytes" newline bitfld.long 0x00 14.--15. " SAHTS ,Source address hold transfer size" "1 byte,2 bytes,4 bytes,8 bytes" bitfld.long 0x00 13. " DAHE ,Destination address hold enable" "Disabled,Enabled" bitfld.long 0x00 12. " SAHE ,Source address hold enable" "Disabled,Enabled" bitfld.long 0x00 11. " PF ,Prefetchable" "Non prefetchable,Prefetchable" newline bitfld.long 0x00 10. " SRW ,Single register write" "Normal,Enabled" bitfld.long 0x00 9. " EOSIE ,End-of-segments interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. " EIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " SWSM ,Single write start mode" "Disabled,Enabled" newline bitfld.long 0x00 0. " CS ,Channel start" "Halt,Start" endif group.long 0x10104++0x03 line.long 0x00 "DLSR,DMA Legacy Status Register" eventfld.long 0x00 7. " TE ,Transfer error" "No error,Error" bitfld.long 0x00 5. " CH ,Channel halted" "Not halted,Halted" eventfld.long 0x00 4. " PE ,Programming error" "No error,Error" bitfld.long 0x00 2. " CB ,Programming error" "No error,Error" newline eventfld.long 0x00 1. " EOSI ,End-of-segment interrupt" "No interrupt,Interrupt" group.long 0x10110++0x13 line.long 0x00 "DLSATR,DMA Legacy Source Attributes Register" bitfld.long 0x00 16.--19. " SRTTYPE ,DMA source transaction type" "Read - do not snoop,Read - snoop,Enhanced read - do not snoop,Enhanced read - snoop,?..." hexmask.long.byte 0x00 0.--7. 0x01 0x01 " ESAD_0_7 ,Extended source address" line.long 0x04 "DLSAR,DMA Legacy Source Address Register" line.long 0x08 "DLDATR,DMA Legacy Destination Attributes Register" bitfld.long 0x08 30. " NLWR ,No last write with response" "Write-with-response,Write-without-response" bitfld.long 0x08 16.--19. " DWTTYPE ,DMA destination transaction type" "Write - do not snoop,Write - snoop,Enhanced write - do not snoop,Enhanced write - snoop,?..." hexmask.long.byte 0x08 0.--7. 0x01 0x01 " EDAD_0_7 ,Extended destination address" line.long 0x0C "DLDAR,DMA Legacy Destination Address Register" line.long 0x10 "DLBCR,DMA Legacy Byte Count Register" hexmask.long 0x10 0.--29. 1. " BC ,Byte count" endif rgroup.long 0x10BF8++0x07 line.long 0x00 "IPBRR0,IP Block Revision Register 0" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" line.long 0x04 "IPBRR1,IP Block Revision Register 1" hexmask.long.byte 0x04 16.--23. 1. " IP_INT ,IP block integration options" hexmask.long.byte 0x04 8.--15. 1. " IP_MNT ,IP block maintenance version" bitfld.long 0x04 6.--7. " IP_CFG[7:6] ,DMA engines" "1 engine,2 engines,4 engines,8 engines" sif cpuis("LS10?6*") bitfld.long 0x04 4.--5. " IP_CFG[4:5] ,Legacy mode capable DMA engines" "1 engine,2 engines,4 engines,?..." endif group.long 0x10E00++0x07 line.long 0x00 "DEIER,DMA Error Interrupt Enable Register" bitfld.long 0x00 31. " MEIE ,Multiple error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " RTEIE ,Read transaction error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " WTEIE ,Write transaction error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CDEIE ,Command descriptor error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " SDEIE ,Source descriptor error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " DDEIE ,Destination descriptor error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " EREIE ,Enqueue rejection error interrupt enable" "Disabled,Enabled" line.long 0x04 "DEDR,DMA Error Detect Register" eventfld.long 0x04 31. " ME ,Multiple error" "No error,Error" eventfld.long 0x04 29. " RTE ,Read transaction error" "No error,Error" eventfld.long 0x04 28. " WTE ,Write transaction error" "No error,Error" newline eventfld.long 0x04 27. " CDE ,Command descriptor error" "No error,Error" eventfld.long 0x04 26. " SDE ,Source descriptor error" "No error,Error" eventfld.long 0x04 25. " DDE ,Destination descriptor error" "No error,Error" newline eventfld.long 0x04 24. " ERE ,Enqueue rejection error" "No error,Error" rgroup.long 0x10E10++0x0F line.long 0x00 "DECFDW0R,DMA Error Capture Frame Descriptor Word 0 Register. Bits 0-31" line.long 0x04 "DECFDW1R,DMA Error Capture Frame Descriptor Word 1 Register. Bits 32-63" line.long 0x08 "DECFDW2R,DMA Error Capture Frame Descriptor Word 2 Register. Bits 64-95" line.long 0x0C "DECFDW3R,DMA Error Capture Frame Descriptor Word 3 Register. Bits 96-127" rgroup.long 0x10E30++0x07 line.long 0x00 "DECCQIDR,DMA Error Capture Command Queue ID Register" bitfld.long 0x00 0.--4. " CQID ,Command queue ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "DECBR,DMA Error Capture Byte Count Register" tree.open "Block 0 Specific Registers" base ad:0x8380000 width 12. tree "qDMA Command Queue" if (((per.l(ad:0x8380000+0x200C0))&0x80000000)==0x80000000) group.long 0x200C0++0x03 line.long 0x00 "B0CQ0MR,Block 0 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x200C0+0x04)++0x03 line.long 0x00 "B0CQ0SR,Block 0 Command Queue 0 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x200C0+0x08)++0x07 line.long 0x00 "B0CQ0EDPAR,Block 0 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ0DPAR,Block 0 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x200C0++0x03 line.long 0x00 "B0CQ0MR,Block 0 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x200C0+0x04)++0x03 hide.long 0x00 "B0CQ0SR,Block 0 Command Queue 0 Status Register" rgroup.long (0x200C0+0x08)++0x07 line.long 0x00 "B0CQ0EDPAR,Block 0 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ0DPAR,Block 0 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x200C0+0x10)++0x07 line.long 0x00 "B0CQ0EEPAR,Block 0 Command Queue 0 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ0EPAR,Block 0 Command Queue 0 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x201C0))&0x80000000)==0x80000000) group.long 0x201C0++0x03 line.long 0x00 "B0CQ1MR,Block 0 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x201C0+0x04)++0x03 line.long 0x00 "B0CQ1SR,Block 0 Command Queue 1 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x201C0+0x08)++0x07 line.long 0x00 "B0CQ1EDPAR,Block 0 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ1DPAR,Block 0 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x201C0++0x03 line.long 0x00 "B0CQ1MR,Block 0 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x201C0+0x04)++0x03 hide.long 0x00 "B0CQ1SR,Block 0 Command Queue 1 Status Register" rgroup.long (0x201C0+0x08)++0x07 line.long 0x00 "B0CQ1EDPAR,Block 0 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ1DPAR,Block 0 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x201C0+0x10)++0x07 line.long 0x00 "B0CQ1EEPAR,Block 0 Command Queue 1 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ1EPAR,Block 0 Command Queue 1 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x202C0))&0x80000000)==0x80000000) group.long 0x202C0++0x03 line.long 0x00 "B0CQ2MR,Block 0 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x202C0+0x04)++0x03 line.long 0x00 "B0CQ2SR,Block 0 Command Queue 2 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x202C0+0x08)++0x07 line.long 0x00 "B0CQ2EDPAR,Block 0 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ2DPAR,Block 0 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x202C0++0x03 line.long 0x00 "B0CQ2MR,Block 0 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x202C0+0x04)++0x03 hide.long 0x00 "B0CQ2SR,Block 0 Command Queue 2 Status Register" rgroup.long (0x202C0+0x08)++0x07 line.long 0x00 "B0CQ2EDPAR,Block 0 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ2DPAR,Block 0 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x202C0+0x10)++0x07 line.long 0x00 "B0CQ2EEPAR,Block 0 Command Queue 2 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ2EPAR,Block 0 Command Queue 2 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x203C0))&0x80000000)==0x80000000) group.long 0x203C0++0x03 line.long 0x00 "B0CQ3MR,Block 0 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x203C0+0x04)++0x03 line.long 0x00 "B0CQ3SR,Block 0 Command Queue 3 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x203C0+0x08)++0x07 line.long 0x00 "B0CQ3EDPAR,Block 0 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ3DPAR,Block 0 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x203C0++0x03 line.long 0x00 "B0CQ3MR,Block 0 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x203C0+0x04)++0x03 hide.long 0x00 "B0CQ3SR,Block 0 Command Queue 3 Status Register" rgroup.long (0x203C0+0x08)++0x07 line.long 0x00 "B0CQ3EDPAR,Block 0 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ3DPAR,Block 0 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x203C0+0x10)++0x07 line.long 0x00 "B0CQ3EEPAR,Block 0 Command Queue 3 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ3EPAR,Block 0 Command Queue 3 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x204C0))&0x80000000)==0x80000000) group.long 0x204C0++0x03 line.long 0x00 "B0CQ4MR,Block 0 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x204C0+0x04)++0x03 line.long 0x00 "B0CQ4SR,Block 0 Command Queue 4 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x204C0+0x08)++0x07 line.long 0x00 "B0CQ4EDPAR,Block 0 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ4DPAR,Block 0 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x204C0++0x03 line.long 0x00 "B0CQ4MR,Block 0 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x204C0+0x04)++0x03 hide.long 0x00 "B0CQ4SR,Block 0 Command Queue 4 Status Register" rgroup.long (0x204C0+0x08)++0x07 line.long 0x00 "B0CQ4EDPAR,Block 0 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ4DPAR,Block 0 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x204C0+0x10)++0x07 line.long 0x00 "B0CQ4EEPAR,Block 0 Command Queue 4 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ4EPAR,Block 0 Command Queue 4 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x205C0))&0x80000000)==0x80000000) group.long 0x205C0++0x03 line.long 0x00 "B0CQ5MR,Block 0 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x205C0+0x04)++0x03 line.long 0x00 "B0CQ5SR,Block 0 Command Queue 5 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x205C0+0x08)++0x07 line.long 0x00 "B0CQ5EDPAR,Block 0 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ5DPAR,Block 0 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x205C0++0x03 line.long 0x00 "B0CQ5MR,Block 0 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x205C0+0x04)++0x03 hide.long 0x00 "B0CQ5SR,Block 0 Command Queue 5 Status Register" rgroup.long (0x205C0+0x08)++0x07 line.long 0x00 "B0CQ5EDPAR,Block 0 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ5DPAR,Block 0 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x205C0+0x10)++0x07 line.long 0x00 "B0CQ5EEPAR,Block 0 Command Queue 5 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ5EPAR,Block 0 Command Queue 5 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x206C0))&0x80000000)==0x80000000) group.long 0x206C0++0x03 line.long 0x00 "B0CQ6MR,Block 0 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x206C0+0x04)++0x03 line.long 0x00 "B0CQ6SR,Block 0 Command Queue 6 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x206C0+0x08)++0x07 line.long 0x00 "B0CQ6EDPAR,Block 0 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ6DPAR,Block 0 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x206C0++0x03 line.long 0x00 "B0CQ6MR,Block 0 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x206C0+0x04)++0x03 hide.long 0x00 "B0CQ6SR,Block 0 Command Queue 6 Status Register" rgroup.long (0x206C0+0x08)++0x07 line.long 0x00 "B0CQ6EDPAR,Block 0 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ6DPAR,Block 0 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x206C0+0x10)++0x07 line.long 0x00 "B0CQ6EEPAR,Block 0 Command Queue 6 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ6EPAR,Block 0 Command Queue 6 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8380000+0x207C0))&0x80000000)==0x80000000) group.long 0x207C0++0x03 line.long 0x00 "B0CQ7MR,Block 0 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x207C0+0x04)++0x03 line.long 0x00 "B0CQ7SR,Block 0 Command Queue 7 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x207C0+0x08)++0x07 line.long 0x00 "B0CQ7EDPAR,Block 0 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ7DPAR,Block 0 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x207C0++0x03 line.long 0x00 "B0CQ7MR,Block 0 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x207C0+0x04)++0x03 hide.long 0x00 "B0CQ7SR,Block 0 Command Queue 7 Status Register" rgroup.long (0x207C0+0x08)++0x07 line.long 0x00 "B0CQ7EDPAR,Block 0 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B0CQ7DPAR,Block 0 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x207C0+0x10)++0x07 line.long 0x00 "B0CQ7EEPAR,Block 0 Command Queue 7 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B0CQ7EPAR,Block 0 Command Queue 7 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" group.long 0x200E0++0x07 line.long 0x00 "B0CQIER,Block 0 Command Queue Interrupt Enable Register" bitfld.long 0x00 31. " CQ0TIE ,Command queue 0 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " CQ1TIE ,Command queue 1 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " CQ2TIE ,Command queue 2 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CQ3TIE ,Command queue 3 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CQ4TIE ,Command queue 4 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " CQ5TIE ,Command queue 5 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CQ6TIE ,Command queue 6 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " CQ7TIE ,Command queue 7 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " SQPEIE ,Status queue programming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SQTIE ,Status queue threshold interrupt enable" "Disabled,Enabled" line.long 0x04 "B0CQIDR,Block 0 Command Queue Interrupt Detect Register" eventfld.long 0x04 31. " CQ0T ,Command queue 0 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 30. " CQ1T ,Command queue 1 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 29. " CQ2T ,Command queue 2 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 28. " CQ3T ,Command queue 3 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " CQ4T ,Command queue 4 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 26. " CQ5T ,Command queue 5 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 25. " CQ6T ,Command queue 6 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 24. " CQ7T ,Command queue 7 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " SQPE ,Status queue programming error interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 15. " SQT ,Status queue threshold interrupt detected" "No interrupt,Interrupt" tree.end tree "qDMA Status Queue" if (((per.l(ad:0x8380000+0x20800))&0x80000000)==0x80000000) group.long 0x20800++0x03 line.long 0x00 "B0SQMR,Block 0 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long 0x20804++0x03 line.long 0x00 "B0SQSR,Block 0 Status Queue Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" else group.long 0x20800++0x03 line.long 0x00 "B0SQMR,Block 0 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long 0x20804++0x03 hide.long 0x00 "B0SQSR,Block 0 Status Queue Status Register" endif group.long 0x20808++0x0F line.long 0x00 "B0SQEDPAR,Block 0 Status Queue Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " SQDPA ,Upper status queue dequeue pointer address bits" line.long 0x04 "B0SQDPAR,Block 0 Status Queue Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " SQDPA ,Status queue dequeue pointer address" line.long 0x08 "B0SQEEPAR,Block 0 Status Queue Extended Enqueue Pointer Address Register" hexmask.long.byte 0x08 0.--7. 0x01 " SQEPA ,Extended status queue enqueue pointer address bits" line.long 0x0C "B0SQEPAR,Block 0 Status Queue Enqueue Pointer Address Register" hexmask.long 0x0C 4.--31. 0x10 " SQEPA ,Status queue enqueue pointer address" if (((per.l(ad:0x8380000+0x20800))&0x80000000)==0x80000000) group.long 0x20828++0x03 line.long 0x00 "B0SQICR,Block 0 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" rbitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" else group.long 0x20828++0x03 line.long 0x00 "B0SQICR,Block 0 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing Status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" endif tree.end width 0x0B tree.end tree.open "Block 1 Specific Registers" base ad:0x8390000 width 12. tree "qDMA Command Queue" if (((per.l(ad:0x8390000+0x200C0))&0x80000000)==0x80000000) group.long 0x200C0++0x03 line.long 0x00 "B1CQ0MR,Block 1 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x200C0+0x04)++0x03 line.long 0x00 "B1CQ0SR,Block 1 Command Queue 0 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x200C0+0x08)++0x07 line.long 0x00 "B1CQ0EDPAR,Block 1 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ0DPAR,Block 1 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x200C0++0x03 line.long 0x00 "B1CQ0MR,Block 1 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x200C0+0x04)++0x03 hide.long 0x00 "B1CQ0SR,Block 1 Command Queue 0 Status Register" rgroup.long (0x200C0+0x08)++0x07 line.long 0x00 "B1CQ0EDPAR,Block 1 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ0DPAR,Block 1 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x200C0+0x10)++0x07 line.long 0x00 "B1CQ0EEPAR,Block 1 Command Queue 0 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ0EPAR,Block 1 Command Queue 0 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x201C0))&0x80000000)==0x80000000) group.long 0x201C0++0x03 line.long 0x00 "B1CQ1MR,Block 1 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x201C0+0x04)++0x03 line.long 0x00 "B1CQ1SR,Block 1 Command Queue 1 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x201C0+0x08)++0x07 line.long 0x00 "B1CQ1EDPAR,Block 1 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ1DPAR,Block 1 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x201C0++0x03 line.long 0x00 "B1CQ1MR,Block 1 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x201C0+0x04)++0x03 hide.long 0x00 "B1CQ1SR,Block 1 Command Queue 1 Status Register" rgroup.long (0x201C0+0x08)++0x07 line.long 0x00 "B1CQ1EDPAR,Block 1 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ1DPAR,Block 1 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x201C0+0x10)++0x07 line.long 0x00 "B1CQ1EEPAR,Block 1 Command Queue 1 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ1EPAR,Block 1 Command Queue 1 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x202C0))&0x80000000)==0x80000000) group.long 0x202C0++0x03 line.long 0x00 "B1CQ2MR,Block 1 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x202C0+0x04)++0x03 line.long 0x00 "B1CQ2SR,Block 1 Command Queue 2 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x202C0+0x08)++0x07 line.long 0x00 "B1CQ2EDPAR,Block 1 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ2DPAR,Block 1 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x202C0++0x03 line.long 0x00 "B1CQ2MR,Block 1 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x202C0+0x04)++0x03 hide.long 0x00 "B1CQ2SR,Block 1 Command Queue 2 Status Register" rgroup.long (0x202C0+0x08)++0x07 line.long 0x00 "B1CQ2EDPAR,Block 1 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ2DPAR,Block 1 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x202C0+0x10)++0x07 line.long 0x00 "B1CQ2EEPAR,Block 1 Command Queue 2 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ2EPAR,Block 1 Command Queue 2 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x203C0))&0x80000000)==0x80000000) group.long 0x203C0++0x03 line.long 0x00 "B1CQ3MR,Block 1 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x203C0+0x04)++0x03 line.long 0x00 "B1CQ3SR,Block 1 Command Queue 3 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x203C0+0x08)++0x07 line.long 0x00 "B1CQ3EDPAR,Block 1 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ3DPAR,Block 1 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x203C0++0x03 line.long 0x00 "B1CQ3MR,Block 1 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x203C0+0x04)++0x03 hide.long 0x00 "B1CQ3SR,Block 1 Command Queue 3 Status Register" rgroup.long (0x203C0+0x08)++0x07 line.long 0x00 "B1CQ3EDPAR,Block 1 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ3DPAR,Block 1 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x203C0+0x10)++0x07 line.long 0x00 "B1CQ3EEPAR,Block 1 Command Queue 3 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ3EPAR,Block 1 Command Queue 3 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x204C0))&0x80000000)==0x80000000) group.long 0x204C0++0x03 line.long 0x00 "B1CQ4MR,Block 1 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x204C0+0x04)++0x03 line.long 0x00 "B1CQ4SR,Block 1 Command Queue 4 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x204C0+0x08)++0x07 line.long 0x00 "B1CQ4EDPAR,Block 1 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ4DPAR,Block 1 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x204C0++0x03 line.long 0x00 "B1CQ4MR,Block 1 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x204C0+0x04)++0x03 hide.long 0x00 "B1CQ4SR,Block 1 Command Queue 4 Status Register" rgroup.long (0x204C0+0x08)++0x07 line.long 0x00 "B1CQ4EDPAR,Block 1 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ4DPAR,Block 1 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x204C0+0x10)++0x07 line.long 0x00 "B1CQ4EEPAR,Block 1 Command Queue 4 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ4EPAR,Block 1 Command Queue 4 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x205C0))&0x80000000)==0x80000000) group.long 0x205C0++0x03 line.long 0x00 "B1CQ5MR,Block 1 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x205C0+0x04)++0x03 line.long 0x00 "B1CQ5SR,Block 1 Command Queue 5 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x205C0+0x08)++0x07 line.long 0x00 "B1CQ5EDPAR,Block 1 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ5DPAR,Block 1 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x205C0++0x03 line.long 0x00 "B1CQ5MR,Block 1 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x205C0+0x04)++0x03 hide.long 0x00 "B1CQ5SR,Block 1 Command Queue 5 Status Register" rgroup.long (0x205C0+0x08)++0x07 line.long 0x00 "B1CQ5EDPAR,Block 1 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ5DPAR,Block 1 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x205C0+0x10)++0x07 line.long 0x00 "B1CQ5EEPAR,Block 1 Command Queue 5 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ5EPAR,Block 1 Command Queue 5 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x206C0))&0x80000000)==0x80000000) group.long 0x206C0++0x03 line.long 0x00 "B1CQ6MR,Block 1 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x206C0+0x04)++0x03 line.long 0x00 "B1CQ6SR,Block 1 Command Queue 6 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x206C0+0x08)++0x07 line.long 0x00 "B1CQ6EDPAR,Block 1 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ6DPAR,Block 1 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x206C0++0x03 line.long 0x00 "B1CQ6MR,Block 1 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x206C0+0x04)++0x03 hide.long 0x00 "B1CQ6SR,Block 1 Command Queue 6 Status Register" rgroup.long (0x206C0+0x08)++0x07 line.long 0x00 "B1CQ6EDPAR,Block 1 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ6DPAR,Block 1 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x206C0+0x10)++0x07 line.long 0x00 "B1CQ6EEPAR,Block 1 Command Queue 6 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ6EPAR,Block 1 Command Queue 6 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x8390000+0x207C0))&0x80000000)==0x80000000) group.long 0x207C0++0x03 line.long 0x00 "B1CQ7MR,Block 1 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x207C0+0x04)++0x03 line.long 0x00 "B1CQ7SR,Block 1 Command Queue 7 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x207C0+0x08)++0x07 line.long 0x00 "B1CQ7EDPAR,Block 1 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ7DPAR,Block 1 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x207C0++0x03 line.long 0x00 "B1CQ7MR,Block 1 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x207C0+0x04)++0x03 hide.long 0x00 "B1CQ7SR,Block 1 Command Queue 7 Status Register" rgroup.long (0x207C0+0x08)++0x07 line.long 0x00 "B1CQ7EDPAR,Block 1 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B1CQ7DPAR,Block 1 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x207C0+0x10)++0x07 line.long 0x00 "B1CQ7EEPAR,Block 1 Command Queue 7 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B1CQ7EPAR,Block 1 Command Queue 7 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" group.long 0x200E0++0x07 line.long 0x00 "B1CQIER,Block 1 Command Queue Interrupt Enable Register" bitfld.long 0x00 31. " CQ0TIE ,Command queue 0 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " CQ1TIE ,Command queue 1 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " CQ2TIE ,Command queue 2 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CQ3TIE ,Command queue 3 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CQ4TIE ,Command queue 4 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " CQ5TIE ,Command queue 5 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CQ6TIE ,Command queue 6 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " CQ7TIE ,Command queue 7 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " SQPEIE ,Status queue programming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SQTIE ,Status queue threshold interrupt enable" "Disabled,Enabled" line.long 0x04 "B1CQIDR,Block 1 Command Queue Interrupt Detect Register" eventfld.long 0x04 31. " CQ0T ,Command queue 0 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 30. " CQ1T ,Command queue 1 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 29. " CQ2T ,Command queue 2 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 28. " CQ3T ,Command queue 3 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " CQ4T ,Command queue 4 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 26. " CQ5T ,Command queue 5 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 25. " CQ6T ,Command queue 6 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 24. " CQ7T ,Command queue 7 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " SQPE ,Status queue programming error interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 15. " SQT ,Status queue threshold interrupt detected" "No interrupt,Interrupt" tree.end tree "qDMA Status Queue" if (((per.l(ad:0x8390000+0x20800))&0x80000000)==0x80000000) group.long 0x20800++0x03 line.long 0x00 "B1SQMR,Block 1 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long 0x20804++0x03 line.long 0x00 "B1SQSR,Block 1 Status Queue Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" else group.long 0x20800++0x03 line.long 0x00 "B1SQMR,Block 1 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long 0x20804++0x03 hide.long 0x00 "B1SQSR,Block 1 Status Queue Status Register" endif group.long 0x20808++0x0F line.long 0x00 "B1SQEDPAR,Block 1 Status Queue Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " SQDPA ,Upper status queue dequeue pointer address bits" line.long 0x04 "B1SQDPAR,Block 1 Status Queue Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " SQDPA ,Status queue dequeue pointer address" line.long 0x08 "B1SQEEPAR,Block 1 Status Queue Extended Enqueue Pointer Address Register" hexmask.long.byte 0x08 0.--7. 0x01 " SQEPA ,Extended status queue enqueue pointer address bits" line.long 0x0C "B1SQEPAR,Block 1 Status Queue Enqueue Pointer Address Register" hexmask.long 0x0C 4.--31. 0x10 " SQEPA ,Status queue enqueue pointer address" if (((per.l(ad:0x8390000+0x20800))&0x80000000)==0x80000000) group.long 0x20828++0x03 line.long 0x00 "B1SQICR,Block 1 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" rbitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" else group.long 0x20828++0x03 line.long 0x00 "B1SQICR,Block 1 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing Status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" endif tree.end width 0x0B tree.end tree.open "Block 2 Specific Registers" base ad:0x83A0000 width 12. tree "qDMA Command Queue" if (((per.l(ad:0x83A0000+0x200C0))&0x80000000)==0x80000000) group.long 0x200C0++0x03 line.long 0x00 "B2CQ0MR,Block 2 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x200C0+0x04)++0x03 line.long 0x00 "B2CQ0SR,Block 2 Command Queue 0 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x200C0+0x08)++0x07 line.long 0x00 "B2CQ0EDPAR,Block 2 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ0DPAR,Block 2 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x200C0++0x03 line.long 0x00 "B2CQ0MR,Block 2 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x200C0+0x04)++0x03 hide.long 0x00 "B2CQ0SR,Block 2 Command Queue 0 Status Register" rgroup.long (0x200C0+0x08)++0x07 line.long 0x00 "B2CQ0EDPAR,Block 2 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ0DPAR,Block 2 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x200C0+0x10)++0x07 line.long 0x00 "B2CQ0EEPAR,Block 2 Command Queue 0 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ0EPAR,Block 2 Command Queue 0 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x201C0))&0x80000000)==0x80000000) group.long 0x201C0++0x03 line.long 0x00 "B2CQ1MR,Block 2 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x201C0+0x04)++0x03 line.long 0x00 "B2CQ1SR,Block 2 Command Queue 1 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x201C0+0x08)++0x07 line.long 0x00 "B2CQ1EDPAR,Block 2 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ1DPAR,Block 2 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x201C0++0x03 line.long 0x00 "B2CQ1MR,Block 2 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x201C0+0x04)++0x03 hide.long 0x00 "B2CQ1SR,Block 2 Command Queue 1 Status Register" rgroup.long (0x201C0+0x08)++0x07 line.long 0x00 "B2CQ1EDPAR,Block 2 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ1DPAR,Block 2 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x201C0+0x10)++0x07 line.long 0x00 "B2CQ1EEPAR,Block 2 Command Queue 1 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ1EPAR,Block 2 Command Queue 1 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x202C0))&0x80000000)==0x80000000) group.long 0x202C0++0x03 line.long 0x00 "B2CQ2MR,Block 2 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x202C0+0x04)++0x03 line.long 0x00 "B2CQ2SR,Block 2 Command Queue 2 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x202C0+0x08)++0x07 line.long 0x00 "B2CQ2EDPAR,Block 2 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ2DPAR,Block 2 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x202C0++0x03 line.long 0x00 "B2CQ2MR,Block 2 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x202C0+0x04)++0x03 hide.long 0x00 "B2CQ2SR,Block 2 Command Queue 2 Status Register" rgroup.long (0x202C0+0x08)++0x07 line.long 0x00 "B2CQ2EDPAR,Block 2 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ2DPAR,Block 2 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x202C0+0x10)++0x07 line.long 0x00 "B2CQ2EEPAR,Block 2 Command Queue 2 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ2EPAR,Block 2 Command Queue 2 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x203C0))&0x80000000)==0x80000000) group.long 0x203C0++0x03 line.long 0x00 "B2CQ3MR,Block 2 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x203C0+0x04)++0x03 line.long 0x00 "B2CQ3SR,Block 2 Command Queue 3 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x203C0+0x08)++0x07 line.long 0x00 "B2CQ3EDPAR,Block 2 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ3DPAR,Block 2 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x203C0++0x03 line.long 0x00 "B2CQ3MR,Block 2 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x203C0+0x04)++0x03 hide.long 0x00 "B2CQ3SR,Block 2 Command Queue 3 Status Register" rgroup.long (0x203C0+0x08)++0x07 line.long 0x00 "B2CQ3EDPAR,Block 2 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ3DPAR,Block 2 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x203C0+0x10)++0x07 line.long 0x00 "B2CQ3EEPAR,Block 2 Command Queue 3 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ3EPAR,Block 2 Command Queue 3 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x204C0))&0x80000000)==0x80000000) group.long 0x204C0++0x03 line.long 0x00 "B2CQ4MR,Block 2 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x204C0+0x04)++0x03 line.long 0x00 "B2CQ4SR,Block 2 Command Queue 4 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x204C0+0x08)++0x07 line.long 0x00 "B2CQ4EDPAR,Block 2 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ4DPAR,Block 2 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x204C0++0x03 line.long 0x00 "B2CQ4MR,Block 2 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x204C0+0x04)++0x03 hide.long 0x00 "B2CQ4SR,Block 2 Command Queue 4 Status Register" rgroup.long (0x204C0+0x08)++0x07 line.long 0x00 "B2CQ4EDPAR,Block 2 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ4DPAR,Block 2 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x204C0+0x10)++0x07 line.long 0x00 "B2CQ4EEPAR,Block 2 Command Queue 4 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ4EPAR,Block 2 Command Queue 4 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x205C0))&0x80000000)==0x80000000) group.long 0x205C0++0x03 line.long 0x00 "B2CQ5MR,Block 2 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x205C0+0x04)++0x03 line.long 0x00 "B2CQ5SR,Block 2 Command Queue 5 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x205C0+0x08)++0x07 line.long 0x00 "B2CQ5EDPAR,Block 2 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ5DPAR,Block 2 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x205C0++0x03 line.long 0x00 "B2CQ5MR,Block 2 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x205C0+0x04)++0x03 hide.long 0x00 "B2CQ5SR,Block 2 Command Queue 5 Status Register" rgroup.long (0x205C0+0x08)++0x07 line.long 0x00 "B2CQ5EDPAR,Block 2 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ5DPAR,Block 2 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x205C0+0x10)++0x07 line.long 0x00 "B2CQ5EEPAR,Block 2 Command Queue 5 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ5EPAR,Block 2 Command Queue 5 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x206C0))&0x80000000)==0x80000000) group.long 0x206C0++0x03 line.long 0x00 "B2CQ6MR,Block 2 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x206C0+0x04)++0x03 line.long 0x00 "B2CQ6SR,Block 2 Command Queue 6 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x206C0+0x08)++0x07 line.long 0x00 "B2CQ6EDPAR,Block 2 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ6DPAR,Block 2 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x206C0++0x03 line.long 0x00 "B2CQ6MR,Block 2 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x206C0+0x04)++0x03 hide.long 0x00 "B2CQ6SR,Block 2 Command Queue 6 Status Register" rgroup.long (0x206C0+0x08)++0x07 line.long 0x00 "B2CQ6EDPAR,Block 2 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ6DPAR,Block 2 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x206C0+0x10)++0x07 line.long 0x00 "B2CQ6EEPAR,Block 2 Command Queue 6 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ6EPAR,Block 2 Command Queue 6 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x207C0))&0x80000000)==0x80000000) group.long 0x207C0++0x03 line.long 0x00 "B2CQ7MR,Block 2 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x207C0+0x04)++0x03 line.long 0x00 "B2CQ7SR,Block 2 Command Queue 7 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x207C0+0x08)++0x07 line.long 0x00 "B2CQ7EDPAR,Block 2 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ7DPAR,Block 2 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x207C0++0x03 line.long 0x00 "B2CQ7MR,Block 2 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x207C0+0x04)++0x03 hide.long 0x00 "B2CQ7SR,Block 2 Command Queue 7 Status Register" rgroup.long (0x207C0+0x08)++0x07 line.long 0x00 "B2CQ7EDPAR,Block 2 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B2CQ7DPAR,Block 2 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x207C0+0x10)++0x07 line.long 0x00 "B2CQ7EEPAR,Block 2 Command Queue 7 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B2CQ7EPAR,Block 2 Command Queue 7 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" group.long 0x200E0++0x07 line.long 0x00 "B2CQIER,Block 2 Command Queue Interrupt Enable Register" bitfld.long 0x00 31. " CQ0TIE ,Command queue 0 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " CQ1TIE ,Command queue 1 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " CQ2TIE ,Command queue 2 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CQ3TIE ,Command queue 3 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CQ4TIE ,Command queue 4 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " CQ5TIE ,Command queue 5 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CQ6TIE ,Command queue 6 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " CQ7TIE ,Command queue 7 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " SQPEIE ,Status queue programming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SQTIE ,Status queue threshold interrupt enable" "Disabled,Enabled" line.long 0x04 "B2CQIDR,Block 2 Command Queue Interrupt Detect Register" eventfld.long 0x04 31. " CQ0T ,Command queue 0 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 30. " CQ1T ,Command queue 1 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 29. " CQ2T ,Command queue 2 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 28. " CQ3T ,Command queue 3 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " CQ4T ,Command queue 4 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 26. " CQ5T ,Command queue 5 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 25. " CQ6T ,Command queue 6 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 24. " CQ7T ,Command queue 7 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " SQPE ,Status queue programming error interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 15. " SQT ,Status queue threshold interrupt detected" "No interrupt,Interrupt" tree.end tree "qDMA Status Queue" if (((per.l(ad:0x83A0000+0x20800))&0x80000000)==0x80000000) group.long 0x20800++0x03 line.long 0x00 "B2SQMR,Block 2 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long 0x20804++0x03 line.long 0x00 "B2SQSR,Block 2 Status Queue Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" else group.long 0x20800++0x03 line.long 0x00 "B2SQMR,Block 2 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long 0x20804++0x03 hide.long 0x00 "B2SQSR,Block 2 Status Queue Status Register" endif group.long 0x20808++0x0F line.long 0x00 "B2SQEDPAR,Block 2 Status Queue Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " SQDPA ,Upper status queue dequeue pointer address bits" line.long 0x04 "B2SQDPAR,Block 2 Status Queue Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " SQDPA ,Status queue dequeue pointer address" line.long 0x08 "B2SQEEPAR,Block 2 Status Queue Extended Enqueue Pointer Address Register" hexmask.long.byte 0x08 0.--7. 0x01 " SQEPA ,Extended status queue enqueue pointer address bits" line.long 0x0C "B2SQEPAR,Block 2 Status Queue Enqueue Pointer Address Register" hexmask.long 0x0C 4.--31. 0x10 " SQEPA ,Status queue enqueue pointer address" if (((per.l(ad:0x83A0000+0x20800))&0x80000000)==0x80000000) group.long 0x20828++0x03 line.long 0x00 "B2SQICR,Block 2 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" rbitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" else group.long 0x20828++0x03 line.long 0x00 "B2SQICR,Block 2 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing Status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" endif tree.end width 0x0B tree.end tree.open "Block 3 Specific Registers" base ad:0x83B0000 width 12. tree "qDMA Command Queue" if (((per.l(ad:0x83B0000+0x200C0))&0x80000000)==0x80000000) group.long 0x200C0++0x03 line.long 0x00 "B3CQ0MR,Block 3 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x200C0+0x04)++0x03 line.long 0x00 "B3CQ0SR,Block 3 Command Queue 0 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x200C0+0x08)++0x07 line.long 0x00 "B3CQ0EDPAR,Block 3 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ0DPAR,Block 3 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x200C0++0x03 line.long 0x00 "B3CQ0MR,Block 3 Command Queue 0 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x200C0+0x04)++0x03 hide.long 0x00 "B3CQ0SR,Block 3 Command Queue 0 Status Register" rgroup.long (0x200C0+0x08)++0x07 line.long 0x00 "B3CQ0EDPAR,Block 3 Command Queue 0 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ0DPAR,Block 3 Command Queue 0 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x200C0+0x10)++0x07 line.long 0x00 "B3CQ0EEPAR,Block 3 Command Queue 0 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ0EPAR,Block 3 Command Queue 0 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x201C0))&0x80000000)==0x80000000) group.long 0x201C0++0x03 line.long 0x00 "B3CQ1MR,Block 3 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x201C0+0x04)++0x03 line.long 0x00 "B3CQ1SR,Block 3 Command Queue 1 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x201C0+0x08)++0x07 line.long 0x00 "B3CQ1EDPAR,Block 3 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ1DPAR,Block 3 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x201C0++0x03 line.long 0x00 "B3CQ1MR,Block 3 Command Queue 1 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x201C0+0x04)++0x03 hide.long 0x00 "B3CQ1SR,Block 3 Command Queue 1 Status Register" rgroup.long (0x201C0+0x08)++0x07 line.long 0x00 "B3CQ1EDPAR,Block 3 Command Queue 1 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ1DPAR,Block 3 Command Queue 1 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x201C0+0x10)++0x07 line.long 0x00 "B3CQ1EEPAR,Block 3 Command Queue 1 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ1EPAR,Block 3 Command Queue 1 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x202C0))&0x80000000)==0x80000000) group.long 0x202C0++0x03 line.long 0x00 "B3CQ2MR,Block 3 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x202C0+0x04)++0x03 line.long 0x00 "B3CQ2SR,Block 3 Command Queue 2 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x202C0+0x08)++0x07 line.long 0x00 "B3CQ2EDPAR,Block 3 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ2DPAR,Block 3 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x202C0++0x03 line.long 0x00 "B3CQ2MR,Block 3 Command Queue 2 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x202C0+0x04)++0x03 hide.long 0x00 "B3CQ2SR,Block 3 Command Queue 2 Status Register" rgroup.long (0x202C0+0x08)++0x07 line.long 0x00 "B3CQ2EDPAR,Block 3 Command Queue 2 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ2DPAR,Block 3 Command Queue 2 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x202C0+0x10)++0x07 line.long 0x00 "B3CQ2EEPAR,Block 3 Command Queue 2 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ2EPAR,Block 3 Command Queue 2 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x203C0))&0x80000000)==0x80000000) group.long 0x203C0++0x03 line.long 0x00 "B3CQ3MR,Block 3 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x203C0+0x04)++0x03 line.long 0x00 "B3CQ3SR,Block 3 Command Queue 3 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x203C0+0x08)++0x07 line.long 0x00 "B3CQ3EDPAR,Block 3 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ3DPAR,Block 3 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x203C0++0x03 line.long 0x00 "B3CQ3MR,Block 3 Command Queue 3 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x203C0+0x04)++0x03 hide.long 0x00 "B3CQ3SR,Block 3 Command Queue 3 Status Register" rgroup.long (0x203C0+0x08)++0x07 line.long 0x00 "B3CQ3EDPAR,Block 3 Command Queue 3 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ3DPAR,Block 3 Command Queue 3 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x203C0+0x10)++0x07 line.long 0x00 "B3CQ3EEPAR,Block 3 Command Queue 3 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ3EPAR,Block 3 Command Queue 3 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x204C0))&0x80000000)==0x80000000) group.long 0x204C0++0x03 line.long 0x00 "B3CQ4MR,Block 3 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x204C0+0x04)++0x03 line.long 0x00 "B3CQ4SR,Block 3 Command Queue 4 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x204C0+0x08)++0x07 line.long 0x00 "B3CQ4EDPAR,Block 3 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ4DPAR,Block 3 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x204C0++0x03 line.long 0x00 "B3CQ4MR,Block 3 Command Queue 4 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x204C0+0x04)++0x03 hide.long 0x00 "B3CQ4SR,Block 3 Command Queue 4 Status Register" rgroup.long (0x204C0+0x08)++0x07 line.long 0x00 "B3CQ4EDPAR,Block 3 Command Queue 4 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ4DPAR,Block 3 Command Queue 4 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x204C0+0x10)++0x07 line.long 0x00 "B3CQ4EEPAR,Block 3 Command Queue 4 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ4EPAR,Block 3 Command Queue 4 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x205C0))&0x80000000)==0x80000000) group.long 0x205C0++0x03 line.long 0x00 "B3CQ5MR,Block 3 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x205C0+0x04)++0x03 line.long 0x00 "B3CQ5SR,Block 3 Command Queue 5 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x205C0+0x08)++0x07 line.long 0x00 "B3CQ5EDPAR,Block 3 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ5DPAR,Block 3 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x205C0++0x03 line.long 0x00 "B3CQ5MR,Block 3 Command Queue 5 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x205C0+0x04)++0x03 hide.long 0x00 "B3CQ5SR,Block 3 Command Queue 5 Status Register" rgroup.long (0x205C0+0x08)++0x07 line.long 0x00 "B3CQ5EDPAR,Block 3 Command Queue 5 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ5DPAR,Block 3 Command Queue 5 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x205C0+0x10)++0x07 line.long 0x00 "B3CQ5EEPAR,Block 3 Command Queue 5 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ5EPAR,Block 3 Command Queue 5 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x206C0))&0x80000000)==0x80000000) group.long 0x206C0++0x03 line.long 0x00 "B3CQ6MR,Block 3 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x206C0+0x04)++0x03 line.long 0x00 "B3CQ6SR,Block 3 Command Queue 6 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x206C0+0x08)++0x07 line.long 0x00 "B3CQ6EDPAR,Block 3 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ6DPAR,Block 3 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x206C0++0x03 line.long 0x00 "B3CQ6MR,Block 3 Command Queue 6 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x206C0+0x04)++0x03 hide.long 0x00 "B3CQ6SR,Block 3 Command Queue 6 Status Register" rgroup.long (0x206C0+0x08)++0x07 line.long 0x00 "B3CQ6EDPAR,Block 3 Command Queue 6 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ6DPAR,Block 3 Command Queue 6 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x206C0+0x10)++0x07 line.long 0x00 "B3CQ6EEPAR,Block 3 Command Queue 6 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ6EPAR,Block 3 Command Queue 6 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x207C0))&0x80000000)==0x80000000) group.long 0x207C0++0x03 line.long 0x00 "B3CQ7MR,Block 3 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long (0x207C0+0x04)++0x03 line.long 0x00 "B3CQ7SR,Block 3 Command Queue 7 Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" bitfld.long 0x00 0. " XOFF ,Command queue has entered congestion management (XOFF)" "Not XOFF,XOFF" group.long (0x207C0+0x08)++0x07 line.long 0x00 "B3CQ7EDPAR,Block 3 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ7DPAR,Block 3 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" else group.long 0x207C0++0x03 line.long 0x00 "B3CQ7MR,Block 3 Command Queue 7 Mode Register" bitfld.long 0x00 31. " EN ,Command queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " EI ,Enqueue pointer increment" "Not incremented,Incremented" bitfld.long 0x00 20.--23. " CD_THLD ,Interrupt threshold" "16,32,64,128,256,512,1024,2048,4096,8192,?..." bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long (0x207C0+0x04)++0x03 hide.long 0x00 "B3CQ7SR,Block 3 Command Queue 7 Status Register" rgroup.long (0x207C0+0x08)++0x07 line.long 0x00 "B3CQ7EDPAR,Block 3 Command Queue 7 Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQDPA ,Extended command queue dequeue pointer address bits" line.long 0x04 "B3CQ7DPAR,Block 3 Command Queue 7 Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQDPA ,Command queue dequeue pointer address" endif group.long (0x207C0+0x10)++0x07 line.long 0x00 "B3CQ7EEPAR,Block 3 Command Queue 7 Extended Enqueue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ECQEPA ,Extended command queue enqueue pointer address" line.long 0x04 "B3CQ7EPAR,Block 3 Command Queue 7 Enqueue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " CQEPA ,Command queue enqueue pointer address" group.long 0x200E0++0x07 line.long 0x00 "B3CQIER,Block 3 Command Queue Interrupt Enable Register" bitfld.long 0x00 31. " CQ0TIE ,Command queue 0 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " CQ1TIE ,Command queue 1 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " CQ2TIE ,Command queue 2 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CQ3TIE ,Command queue 3 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " CQ4TIE ,Command queue 4 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " CQ5TIE ,Command queue 5 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CQ6TIE ,Command queue 6 threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " CQ7TIE ,Command queue 7 threshold interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " SQPEIE ,Status queue programming error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 15. " SQTIE ,Status queue threshold interrupt enable" "Disabled,Enabled" line.long 0x04 "B3CQIDR,Block 3 Command Queue Interrupt Detect Register" eventfld.long 0x04 31. " CQ0T ,Command queue 0 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 30. " CQ1T ,Command queue 1 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 29. " CQ2T ,Command queue 2 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 28. " CQ3T ,Command queue 3 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 27. " CQ4T ,Command queue 4 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 26. " CQ5T ,Command queue 5 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 25. " CQ6T ,Command queue 6 threshold interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 24. " CQ7T ,Command queue 7 threshold interrupt detected" "No interrupt,Interrupt" newline eventfld.long 0x04 23. " SQPE ,Status queue programming error interrupt detected" "No interrupt,Interrupt" eventfld.long 0x04 15. " SQT ,Status queue threshold interrupt detected" "No interrupt,Interrupt" tree.end tree "qDMA Status Queue" if (((per.l(ad:0x83B0000+0x20800))&0x80000000)==0x80000000) group.long 0x20800++0x03 line.long 0x00 "B3SQMR,Block 3 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" rbitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." rgroup.long 0x20804++0x03 line.long 0x00 "B3SQSR,Block 3 Status Queue Status Register" bitfld.long 0x00 17. " QE ,Queue empty" "Not empty,Empty" bitfld.long 0x00 16. " QF ,Queue full" "Not full,Full" else group.long 0x20800++0x03 line.long 0x00 "B3SQMR,Block 3 Status Queue Mode Register" bitfld.long 0x00 31. " EN ,Status queue enable" "Disabled,Enabled" bitfld.long 0x00 30. " DI ,Dequeue pointer increment" "No effect,Increment" bitfld.long 0x00 16.--19. " CQ_SIZE ,Circular descriptor queue size" "64,128,256,512,1024,2048,4096,8192,16384,?..." hgroup.long 0x20804++0x03 hide.long 0x00 "B3SQSR,Block 3 Status Queue Status Register" endif group.long 0x20808++0x0F line.long 0x00 "B3SQEDPAR,Block 3 Status Queue Extended Dequeue Pointer Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " SQDPA ,Upper status queue dequeue pointer address bits" line.long 0x04 "B3SQDPAR,Block 3 Status Queue Dequeue Pointer Address Register" hexmask.long 0x04 4.--31. 0x10 " SQDPA ,Status queue dequeue pointer address" line.long 0x08 "B3SQEEPAR,Block 3 Status Queue Extended Enqueue Pointer Address Register" hexmask.long.byte 0x08 0.--7. 0x01 " SQEPA ,Extended status queue enqueue pointer address bits" line.long 0x0C "B3SQEPAR,Block 3 Status Queue Enqueue Pointer Address Register" hexmask.long 0x0C 4.--31. 0x10 " SQEPA ,Status queue enqueue pointer address" if (((per.l(ad:0x83B0000+0x20800))&0x80000000)==0x80000000) group.long 0x20828++0x03 line.long 0x00 "B3SQICR,Block 3 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" rbitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" else group.long 0x20828++0x03 line.long 0x00 "B3SQICR,Block 3 Status Queue Interrupt Coalescing Register" bitfld.long 0x00 31. " ICEN ,Interrupt coalescing enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " ICST ,Interrupt coalescing Status threshold" "Disabled,1 notification,2 notifications,4 notifications,8 notifications,16 notifications,32 notifications,64 notifications,128 notifications,256 notifications,512 notifications,1024 notifications,2048 notifications,?..." hexmask.long.word 0x00 0.--15. 1. " ICTT ,Interrupt coalescing timer threshold" endif tree.end width 0x0B tree.end width 10. newline group.long 0x20A00++0x03 line.long 0x00 "CQMR,Command Queue Mode Register" bitfld.long 0x00 28.--29. " QOS ,QoS used for memory access (0-7)" "0,2,4,6" hexmask.long.word 0x00 0.--9. 1. " AG_DLA ,Arbitration group deadlock avoidance" group.long 0x20A08++0x0F line.long 0x00 "CQDSCR1,Command Queue Dequeue Scheduler Configuration Register 1" bitfld.long 0x00 28.--30. " AGQ0 ,Arbitration group number for command queue 0" "0,?..." bitfld.long 0x00 24.--26. " AGQ1 ,Arbitration group number for command queue 1" "0,1,?..." bitfld.long 0x00 20.--22. " AGQ2 ,Arbitration group number for command queue 2" "0,1,2,?..." bitfld.long 0x00 16.--18. " AGQ3 ,Arbitration group number for command queue 3" "0,1,2,3,?..." newline bitfld.long 0x00 12.--14. " AGQ4 ,Arbitration group number for command queue 4" "0,1,2,3,4,?..." bitfld.long 0x00 8.--10. " AGQ5 ,Arbitration group number for command queue 5" "0,1,2,3,4,5,?..." bitfld.long 0x00 4.--6. " AGQ6 ,Arbitration group number for command queue 6" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 0.--2. " AGQ7 ,Arbitration group number for command queue 7" "0,1,2,3,4,5,6,7" line.long 0x04 "CQDSCR2,Command Queue Dequeue Scheduler Configuration Register 2" bitfld.long 0x04 28.--30. " AWQ0 ,Arbitration weight for command queue 0" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. " AWQ1 ,Arbitration weight for command queue 1" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " AWQ2 ,Arbitration weight for command queue 2" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " AWQ3 ,Arbitration weight for command queue 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. " AWQ4 ,Arbitration weight for command queue 4" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " AWQ5 ,Arbitration weight for command queue 5" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. " AWQ6 ,Arbitration weight for command queue 6" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " AWQ7 ,Arbitration weight for command queue 7" "0,1,2,3,4,5,6,7" line.long 0x08 "CQIER,Command Queue Interrupt Enable Register" bitfld.long 0x08 31. " MEIE ,Multiple error interrupt enable" "Disabled,Enabled" bitfld.long 0x08 0. " TEIE ,Transaction error interrupt enable" "Disabled,Enabled" line.long 0x0C "CQEDR,Command Queue Error Detect Register" eventfld.long 0x0C 31. " ME ,Multiple error" "No error,Error" eventfld.long 0x0C 0. " TE ,Transaction error" "No error,Error" rgroup.long 0x20A18++0x07 line.long 0x00 "CQECEAR,Command Queue Error Capture Extended Address Register" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Address" line.long 0x04 "CQECAR,Command Queue Error Capture Address Register" group.long 0x20A20++0x03 line.long 0x00 "SQCCMR,Status Queue Critical Congestion Management Register" bitfld.long 0x00 16.--21. " ENTER_WM ,Critical congestion enter watermark level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,4,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20A80++0x0F line.long 0x00 "CQB0SIDR,Command Queue Block 0 Stream ID Register" eventfld.long 0x00 31. " V ,Prohibit stream ID modification" "Permitted,Prohibited" hexmask.long.byte 0x00 0.--7. 1. " STREAM_ID ,Stream ID for data and descriptor accesses when using the command queues" line.long 0x04 "CQB1SIDR,Command Queue Block 1 Stream ID Register" eventfld.long 0x04 31. " V ,Prohibit stream ID modification" "Permitted,Prohibited" hexmask.long.byte 0x04 0.--7. 1. " STREAM_ID ,Stream ID for data and descriptor accesses when using the command queues" line.long 0x08 "CQB2SIDR,Command Queue Block 2 Stream ID Register" eventfld.long 0x08 31. " V ,Prohibit stream ID modification" "Permitted,Prohibited" hexmask.long.byte 0x08 0.--7. 1. " STREAM_ID ,Stream ID for data and descriptor accesses when using the command queues" line.long 0x0C "CQB3SIDR,Command Queue Block 3 Stream ID Register" eventfld.long 0x0C 31. " V ,Prohibit stream ID modification" "Permitted,Prohibited" hexmask.long.byte 0x0C 0.--7. 1. " STREAM_ID ,Stream ID for data and descriptor accesses when using the command queues" width 0x0B tree.end endif sif !cpuis("LS1088*")&&!cpuis("LS1084*")&&!cpuis("LS1048*")&&!cpuis("LS1044*") tree "SATA 3.0 AHCI (Advanced Host Controller Interface for Serial Advanced Technology Attachment 3.0)" base ad:0x3200000 width 9. rgroup.long 0x00++0x03 "HBA Registers" line.long 0x00 "CAP,HBA Capabilities Register" bitfld.long 0x00 31. " S64A ,64-bit addressing support" "Not supported,Supported" bitfld.long 0x00 30. " SNCQ ,Native command queuing support" "Not supported,Supported" bitfld.long 0x00 29. " SSNTF ,SNotification register support" "Not supported,Supported" newline bitfld.long 0x00 28. " SMPS ,Mechanical presence switch support" "Not supported,Supported" bitfld.long 0x00 27. " SSS ,Staggered spin-up support" "Not supported,Supported" bitfld.long 0x00 26. " SALP ,Aggressive link power management support" "Not supported,Supported" newline bitfld.long 0x00 25. " SAL ,Activity LED support" "Not supported,Supported" bitfld.long 0x00 24. " SCLO ,Command list override support" "Not supported,Supported" bitfld.long 0x00 20.--23. " ISS ,Interface speed support" ",Gen 1,Gen 2,Gen 3,?..." newline bitfld.long 0x00 18. " SAM ,AHCI mode only support" "Not supported,Supported" bitfld.long 0x00 17. " SPM ,Port multiplier support" "Not supported,Supported" bitfld.long 0x00 16. " FBSS ,FIS-based switching support" "Not supported,Supported" newline bitfld.long 0x00 15. " PMD ,PIO multiple DRQ block support" "Not supported,Supported" bitfld.long 0x00 14. " SSC ,Slumber state capable support" "Not supported,Supported" bitfld.long 0x00 13. " PSC ,Partial state capable support" "Not supported,Supported" newline bitfld.long 0x00 8.--12. " NCS ,Number of command slots" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 7. " CCCS ,Command completion coalescing support" "Not supported,Supported" bitfld.long 0x00 6. " EMS ,Enclosure management support" "Not supported,Supported" newline bitfld.long 0x00 5. " SXS ,External SATA support" "Not supported,Supported" bitfld.long 0x00 0.--4. " NP ,Number of ports" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" if (((per.l(ad:0x3200000+0x00))&0x40000)==0x00) group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" bitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" else group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" rbitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" endif rgroup.long 0x10++0x03 line.long 0x00 "VS,AHCI Version Register" hexmask.long.word 0x00 16.--31. 1. " MJR ,Major version number" hexmask.long.word 0x00 0.--15. 1. " MNR ,Minor version number" group.long 0x14++0x03 line.long 0x00 "CCC_CTL,Command Completion Coalescing Control Register" hexmask.long.word 0x00 16.--31. 1. " TV ,Timeout value" hexmask.long.byte 0x00 8.--15. 1. " CC ,Command completions" rbitfld.long 0x00 3.--7. " INT ,Specifies the interrupt used by the CCC feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. " EN ,Command completion coalescing feature enable" "Disabled,Enabled" rgroup.long 0x24++0x03 line.long 0x00 "CAP2,HBA Capabilities Extended Register" bitfld.long 0x00 2. " APST ,Automatic partial to slumber transitions support" "Not supported,Supported" bitfld.long 0x00 1. " NVMP ,NVMHCI support" "Not supported,Supported" bitfld.long 0x00 0. " BOH ,BIOS/OS handoff support" "Not supported,Supported" group.long 0xA4++0x1F line.long 0x00 "PCFG,Port Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " TPSS ,Microsecond timer post scaler" bitfld.long 0x00 12.--14. " TPRS ,Microsecond timer pre scaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--5. " PAD ,Port address" ",,Addr cfg/status set,?..." line.long 0x04 "PPCFG,Port Phy1Cfg Register" bitfld.long 0x04 31. " ESDF ,Enable signal detect filter" "Disabled,Enabled" bitfld.long 0x04 30. " ERSN ,Enable reset speed negotiation" "Disabled,Enabled" bitfld.long 0x04 29. " PSS ,PhyControl select SerDes slumber CMU during link slumber" "No slumber,Slumber" bitfld.long 0x04 28. " PSSO ,PhyControl select SerDes OOB or internally decoded OOB signaling as inputs" "SerDes,Internal" newline rbitfld.long 0x04 27. " STB ,Status of the gen fixed clocks parameter" "Fixed freq clock,Variable clock" bitfld.long 0x04 26. " PBPNA ,PhyControl BIST pattern no aligns" "Not continuously,Continuously" bitfld.long 0x04 25. " PBCE ,PhyControl BIST clear error" "No effect,Clear" bitfld.long 0x04 24. " PBPE ,PhyControl BIST pattern enable" "Disabled,Enabled" newline bitfld.long 0x04 21.--23. " PBPS ,PhyControl BIST pattern select" "LBP,LFTP,MFTP,HFTP,PRBS,BIST,?..." bitfld.long 0x04 20. " FPR ,Force PHY ready" "Not forced,Forced" bitfld.long 0x04 18. " SNR ,Speed negotiation rate" "Normal,SPD" newline bitfld.long 0x04 17. " SNM ,Speed negotiation method" "Fastest speed to Gen 1,Gen 1 to fastest speed" hexmask.long.tbyte 0x04 0.--16. 1. " TTA ,This value determines the time period the controller transmits and waits for ALIGNp during speed negotiation" line.long 0x08 "PP2C,Port Phy2Cfg Register" hexmask.long.byte 0x08 24.--31. 1. " CINMP ,COMINIT negate minimum period" hexmask.long.byte 0x08 16.--23. 1. " CIBGN ,COMINIT burst gap nominal" hexmask.long.byte 0x08 8.--15. 1. " CIBGMX ,COMINIT burst gap maximum" hexmask.long.byte 0x08 0.--7. 1. " CIBGMN ,COMINIT burst gap minimum" line.long 0x0C "PP3C,Port Phy3Cfg Register" hexmask.long.byte 0x0C 24.--31. 1. " CWNMP ,COMWAKE negate minimum period" hexmask.long.byte 0x0C 16.--23. 1. " CWBGN ,COMWAKE burst gap nominal" hexmask.long.byte 0x0C 8.--15. 1. " CWBGMX ,COMWAKE burst gap maximum" hexmask.long.byte 0x0C 0.--7. 1. " CWBGMN ,COMWAKE burst gap minimum" line.long 0x10 "PP4C,Port Phy4Cfg Register" hexmask.long.byte 0x10 24.--31. 1. " PTST ,Partial to slumber timer value" hexmask.long.byte 0x10 16.--23. 1. " SFD ,Signal failure detection" hexmask.long.byte 0x10 8.--15. 1. " BNM ,COM burst nominal" hexmask.long.byte 0x10 0.--7. 1. " BMX ,COM burst maximum" line.long 0x14 "PP5C,Port Phy5Cfg Register" hexmask.long.word 0x14 20.--31. 1. " RCT ,Rate change timer" hexmask.long.tbyte 0x14 0.--19. 1. " RIT ,Retry interval timer" line.long 0x18 "AXICC,AXI CACHE Control Register" bitfld.long 0x18 29. " EARC ,Enable the ARCACHE" "Disabled,Enabled" bitfld.long 0x18 28. " EAWC ,Enable the AWCACHE" "Disabled,Enabled" bitfld.long 0x18 24.--27. " AWCF ,Address write cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 20.--23. " AWCD ,Address write cache data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 16.--19. " AWCFD ,Address write cache final data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 12.--15. " ARCP ,Address read cache PRD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. " ARCH ,Address read cache header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 4.--7. " ARCF ,Address read cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. " ARCA ,Address read cache ATAPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "PAXIC,Port AXICfg Register" bitfld.long 0x1C 28. " ENPE ,Enable non zero 4MB PRD entries" "Disabled,Enabled" bitfld.long 0x1C 25. " AAO ,Allow address overwrite" "Not allowed,Allowed" bitfld.long 0x1C 24. " ECM ,Enable the context management" "Disabled,Enabled" bitfld.long 0x1C 20.--23. " OTL ,Outstanding transfer limit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x1C 16.--19. " MARIDD ,Memory address read ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " MARID ,Memory address read ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " MAWIDD ,Memory address write ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. " MAWID ,Memory address write ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("LS1012*")&&!cpuis("LS10?3*") group.long 0xC4++0x03 line.long 0x00 "AXIPC,AXI PROT Control" bitfld.long 0x00 29. " EARP ,Enable the ARPROT" "Disabled,Enabled" bitfld.long 0x00 28. " EAWP ,Enable the AWPROT" "Disabled,Enabled" bitfld.long 0x00 24.--26. " AWPF ,Address write PROT FIS" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " AWPD ,Address write PROT Data" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " AWPFD ,Address write PROT final data" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " ARPP ,Address read PROT PRD" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " ARPH ,Address read PROT header" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ARPF ,Address read PROT FIS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " ARPD ,Address read PROT data" "0,1,2,3,4,5,6,7" endif group.long 0xC8++0x03 line.long 0x00 "PTC,Port TransCfg Register" bitfld.long 0x00 9. " ITM ,Initialize transport memories" "Not initialized,Initialized" bitfld.long 0x00 8. " ENBD ,Enable back down" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " RXWM ,RxWaterMark" group.long 0xD0++0x0B line.long 0x00 "PLC,Port LinkCfg Register" bitfld.long 0x00 27.--31. " PMPRA ,Power management primitive rate acknowledge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " POE ,Primitive override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " PRT ,PHY ready timer" hexmask.long.byte 0x00 8.--15. 1. " AIR ,Align insertion rate" newline bitfld.long 0x00 7. " EPNRT ,Enable PHY not ready timer" "Disabled,Enabled" bitfld.long 0x00 6. " S4A ,Send 4 aligns" "Sent 2,Sent 4" bitfld.long 0x00 5. " RXSE ,Rx scramble enable" "Disabled,Enabled" bitfld.long 0x00 4. " TXSE ,TX scramble enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TXPJ ,TX prim junk" "Junk data,DEADBEEF" bitfld.long 0x00 2. " TXC ,TX cont enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXBC ,RX bad CRC enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXBC ,TX bad CRC enable" "Disabled,Enabled" line.long 0x04 "PLC1,Port LinkCfg1 Register" bitfld.long 0x04 6. " CD ,Data character or primitive" "Data char,Primitive" bitfld.long 0x04 0.--5. " POS ,Primitive override state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,4,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PLC2,Port LinkCfg2 Register" group.long 0xE0++0x0B line.long 0x00 "PLS1,Port LinkStatus1 Register" hexmask.long.byte 0x00 24.--31. 1. " KCEC ,Kchar error count" hexmask.long.byte 0x00 16.--23. 1. " PIEC ,PHY internal error count" hexmask.long.byte 0x00 8.--15. 1. " CEC ,Code error count" hexmask.long.byte 0x00 0.--7. 1. " DEC ,Disparity error count" line.long 0x04 "PCMDC,Port CmdConfig Register" bitfld.long 0x04 29. " TSVIE ,Trustzone slave ID violation interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " TSVI ,Trustzone slave ID violation interrupt" "No interrupt,Interrupt" hexmask.long.word 0x04 12.--27. 1. " TSVT ,Trustzone slave ID of violating transaction" bitfld.long 0x04 1. " ETLL ,Enable transport layer loopback" "Disabled,Enabled" newline bitfld.long 0x04 0. " ETLLB ,Enable transport layer loopback in the BIST L mode" "Disabled,Enabled" line.long 0x08 "PPCS,Port PhyControlStatus Register" rbitfld.long 0x08 30.--31. " PHYCE ,Current 2 bit code error" "00,01,10,11" rbitfld.long 0x08 28.--29. " PHYDE ,Current 2 bit disparity error" "00,01,10,11" rbitfld.long 0x08 27. " PHYKC ,Current 1 bit K character" "0,1" newline hexmask.long.tbyte 0x08 11.--26. 1. " PHYD ,Current 16 bit data" bitfld.long 0x08 10. " CCAC ,Comma alignment has changed" "Not changed,Changed" rbitfld.long 0x08 5.--9. " CCA ,Current comma alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x08 0.--4. " PCTRLS ,PHY control state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "TCR,Timer Control Register" hexmask.long.word 0x00 0.--12. 1. " TPS ,Timer PreScalar value" group.long 0x100++0x0F "Port Registers" line.long 0x00 "PXCLB,Port X Command List Base Address Register" hexmask.long.tbyte 0x00 10.--31. 0x04 " CLB ,Command list base address register" line.long 0x04 "PXCLBU,Port X Command List Base Address Upper 32-bit Register" line.long 0x08 "PXFB,Port X FIS Base Address Register" hexmask.long.tbyte 0x08 8.--31. 0x01 " FB ,FIS base address" line.long 0x0C "PXFBU,Port X FIS Base Address Upper 32-bit Register" newline if (((per.l(ad:0x3200000+0x118))&0x100000)==0x100000) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" newline rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" newline bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif endif if (((per.l(ad:0x3200000))&0x4000000)==0x4000000) if (((per.l(ad:0x3200000+0x24))&0x04)==0x04) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif else if (((per.l(ad:0x3200000+0x24))&0x04)==0x04) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif endif rgroup.long 0x128++0x03 line.long 0x00 "PXSSTS,Port X SATA Status Register" bitfld.long 0x00 8.--11. " IPM ,Interface power management" "Device not present,Active,Partial power management,,,,Slumber power management,?..." bitfld.long 0x00 4.--7. " SPD ,Current interface speed" "Device not present,Gen 1,Gen 2,Gen 3,?..." bitfld.long 0x00 0.--3. " DET ,Device detection" "Not detected/Not established,Detected/Not established,,Detected/Established,Offline mode,?..." group.long 0x12C++0x07 line.long 0x00 "PXSCTL,Port X Serial ATA Control Register" bitfld.long 0x00 8.--11. " IPM ,Indicates which power states the HBA is not allowed to transition to" "No restrictions,Partial state disabled,Slumber state disabled,Partial/Slumber state disabled,?..." bitfld.long 0x00 4.--7. " SPD ,Indicates the highest allowable speed of the interface" "No restrictions,Generation 1 comm rate,Generation 2 comm rate,Generation 3 comm rate,?..." bitfld.long 0x00 0.--3. " DET ,Device detection initialization" "Not detected/initialized,Perform interface comm init,,,Disable SATA,?..." line.long 0x04 "PXSERR,Port X SATA Error Register" bitfld.long 0x04 26. " DIAG[10] ,Diagnostic error information : Change in device presence has been detected" "Not detected,Detected" bitfld.long 0x04 25. " [9] ,Diagnostic error information : Unknown FIS Type" "Not occurred,Occurred" bitfld.long 0x04 24. " [8] ,Diagnostic error information : Transport state transition error" "Not occurred,Occurred" newline bitfld.long 0x04 23. " [7] ,Diagnostic error information : Link sequence error" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,Diagnostic error information : Handshake error" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,Diagnostic error information : CRC error" "Not occurred,Occurred" newline bitfld.long 0x04 20. " [4] ,Diagnostic error information : Disparity error" "Not occurred,Occurred" bitfld.long 0x04 19. " [3] ,Diagnostic error information : 10B to 8B decode error" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,Diagnostic error information : Comm wake" "Not detected,Detected" newline bitfld.long 0x04 17. " [1] ,Diagnostic error information : PHY internal error" "Not detected,Detected" bitfld.long 0x04 16. " [0] ,Diagnostic error information : PhyRdy change" "Not detected,Detected" newline bitfld.long 0x04 11. " ERR[5] ,Error information : Internal error" "No error,Error" bitfld.long 0x04 10. " [4] ,Error information : Protocol error" "No error,Error" bitfld.long 0x04 9. " [3] ,Error information : Persistent communication or data integrity error" "No error,Error" newline bitfld.long 0x04 8. " [2] ,Error information : Transient data integrity error" "No error,Error" bitfld.long 0x04 1. " [1] ,Error information : Recovered communications error" "No error,Error" bitfld.long 0x04 0. " [0] ,Error information : Recovered data integrity error" "No error,Error" group.long 0x138++0x03 line.long 0x00 "PXCI,Port X Command Issue Register" if (((per.l(ad:0x3200000+0x140))&0x04)==0x04) group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 16.--19. " DWE ,Device with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" endif group.long 0x170++0x03 line.long 0x00 "PBERR,Port 0/1 BIST Error" bitfld.long 0x00 1. " BEOS ,BIST error one shot bit" "No error,Error" rbitfld.long 0x00 0. " BERR ,BIST error" "No error,Error" width 0x0B tree.end else tree.open "SATA 3.0 AHCI (Advanced Host Controller Interface for Serial Advanced Technology Attachment 3.0)" tree "SATA 1" base ad:0x3200000 width 9. rgroup.long 0x00++0x03 "HBA Registers" line.long 0x00 "CAP,HBA Capabilities Register" bitfld.long 0x00 31. " S64A ,64-bit addressing support" "Not supported,Supported" bitfld.long 0x00 30. " SNCQ ,Native command queuing support" "Not supported,Supported" bitfld.long 0x00 29. " SSNTF ,SNotification register support" "Not supported,Supported" newline bitfld.long 0x00 28. " SMPS ,Mechanical presence switch support" "Not supported,Supported" bitfld.long 0x00 27. " SSS ,Staggered spin-up support" "Not supported,Supported" bitfld.long 0x00 26. " SALP ,Aggressive link power management support" "Not supported,Supported" newline bitfld.long 0x00 25. " SAL ,Activity LED support" "Not supported,Supported" bitfld.long 0x00 24. " SCLO ,Command list override support" "Not supported,Supported" bitfld.long 0x00 20.--23. " ISS ,Interface speed support" ",Gen 1,Gen 2,Gen 3,?..." newline bitfld.long 0x00 18. " SAM ,AHCI mode only support" "Not supported,Supported" bitfld.long 0x00 17. " SPM ,Port multiplier support" "Not supported,Supported" bitfld.long 0x00 16. " FBSS ,FIS-based switching support" "Not supported,Supported" newline bitfld.long 0x00 15. " PMD ,PIO multiple DRQ block support" "Not supported,Supported" bitfld.long 0x00 14. " SSC ,Slumber state capable support" "Not supported,Supported" bitfld.long 0x00 13. " PSC ,Partial state capable support" "Not supported,Supported" newline bitfld.long 0x00 8.--12. " NCS ,Number of command slots" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 7. " CCCS ,Command completion coalescing support" "Not supported,Supported" bitfld.long 0x00 6. " EMS ,Enclosure management support" "Not supported,Supported" newline bitfld.long 0x00 5. " SXS ,External SATA support" "Not supported,Supported" bitfld.long 0x00 0.--4. " NP ,Number of ports" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" if (((per.l(ad:0x3200000+0x00))&0x40000)==0x00) group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" bitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" else group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" rbitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" endif rgroup.long 0x10++0x03 line.long 0x00 "VS,AHCI Version Register" hexmask.long.word 0x00 16.--31. 1. " MJR ,Major version number" hexmask.long.word 0x00 0.--15. 1. " MNR ,Minor version number" group.long 0x14++0x03 line.long 0x00 "CCC_CTL,Command Completion Coalescing Control Register" hexmask.long.word 0x00 16.--31. 1. " TV ,Timeout value" hexmask.long.byte 0x00 8.--15. 1. " CC ,Command completions" rbitfld.long 0x00 3.--7. " INT ,Specifies the interrupt used by the CCC feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. " EN ,Command completion coalescing feature enable" "Disabled,Enabled" rgroup.long 0x24++0x03 line.long 0x00 "CAP2,HBA Capabilities Extended Register" bitfld.long 0x00 2. " APST ,Automatic partial to slumber transitions support" "Not supported,Supported" bitfld.long 0x00 1. " NVMP ,NVMHCI support" "Not supported,Supported" bitfld.long 0x00 0. " BOH ,BIOS/OS handoff support" "Not supported,Supported" group.long 0xA4++0x1F line.long 0x00 "PCFG,Port Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " TPSS ,Microsecond timer post scaler" bitfld.long 0x00 12.--14. " TPRS ,Microsecond timer pre scaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--5. " PAD ,Port address" ",,Addr cfg/status set,?..." line.long 0x04 "PPCFG,Port Phy1Cfg Register" bitfld.long 0x04 31. " ESDF ,Enable signal detect filter" "Disabled,Enabled" bitfld.long 0x04 30. " ERSN ,Enable reset speed negotiation" "Disabled,Enabled" bitfld.long 0x04 29. " PSS ,PhyControl select SerDes slumber CMU during link slumber" "No slumber,Slumber" bitfld.long 0x04 28. " PSSO ,PhyControl select SerDes OOB or internally decoded OOB signaling as inputs" "SerDes,Internal" newline rbitfld.long 0x04 27. " STB ,Status of the gen fixed clocks parameter" "Fixed freq clock,Variable clock" bitfld.long 0x04 26. " PBPNA ,PhyControl BIST pattern no aligns" "Not continuously,Continuously" bitfld.long 0x04 25. " PBCE ,PhyControl BIST clear error" "No effect,Clear" bitfld.long 0x04 24. " PBPE ,PhyControl BIST pattern enable" "Disabled,Enabled" newline bitfld.long 0x04 21.--23. " PBPS ,PhyControl BIST pattern select" "LBP,LFTP,MFTP,HFTP,PRBS,BIST,?..." bitfld.long 0x04 20. " FPR ,Force PHY ready" "Not forced,Forced" bitfld.long 0x04 18. " SNR ,Speed negotiation rate" "Normal,SPD" newline bitfld.long 0x04 17. " SNM ,Speed negotiation method" "Fastest speed to Gen 1,Gen 1 to fastest speed" hexmask.long.tbyte 0x04 0.--16. 1. " TTA ,This value determines the time period the controller transmits and waits for ALIGNp during speed negotiation" line.long 0x08 "PP2C,Port Phy2Cfg Register" hexmask.long.byte 0x08 24.--31. 1. " CINMP ,COMINIT negate minimum period" hexmask.long.byte 0x08 16.--23. 1. " CIBGN ,COMINIT burst gap nominal" hexmask.long.byte 0x08 8.--15. 1. " CIBGMX ,COMINIT burst gap maximum" hexmask.long.byte 0x08 0.--7. 1. " CIBGMN ,COMINIT burst gap minimum" line.long 0x0C "PP3C,Port Phy3Cfg Register" hexmask.long.byte 0x0C 24.--31. 1. " CWNMP ,COMWAKE negate minimum period" hexmask.long.byte 0x0C 16.--23. 1. " CWBGN ,COMWAKE burst gap nominal" hexmask.long.byte 0x0C 8.--15. 1. " CWBGMX ,COMWAKE burst gap maximum" hexmask.long.byte 0x0C 0.--7. 1. " CWBGMN ,COMWAKE burst gap minimum" line.long 0x10 "PP4C,Port Phy4Cfg Register" hexmask.long.byte 0x10 24.--31. 1. " PTST ,Partial to slumber timer value" hexmask.long.byte 0x10 16.--23. 1. " SFD ,Signal failure detection" hexmask.long.byte 0x10 8.--15. 1. " BNM ,COM burst nominal" hexmask.long.byte 0x10 0.--7. 1. " BMX ,COM burst maximum" line.long 0x14 "PP5C,Port Phy5Cfg Register" hexmask.long.word 0x14 20.--31. 1. " RCT ,Rate change timer" hexmask.long.tbyte 0x14 0.--19. 1. " RIT ,Retry interval timer" line.long 0x18 "AXICC,AXI CACHE Control Register" bitfld.long 0x18 29. " EARC ,Enable the ARCACHE" "Disabled,Enabled" bitfld.long 0x18 28. " EAWC ,Enable the AWCACHE" "Disabled,Enabled" bitfld.long 0x18 24.--27. " AWCF ,Address write cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 20.--23. " AWCD ,Address write cache data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 16.--19. " AWCFD ,Address write cache final data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 12.--15. " ARCP ,Address read cache PRD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. " ARCH ,Address read cache header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 4.--7. " ARCF ,Address read cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. " ARCA ,Address read cache ATAPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "PAXIC,Port AXICfg Register" bitfld.long 0x1C 28. " ENPE ,Enable non zero 4MB PRD entries" "Disabled,Enabled" bitfld.long 0x1C 25. " AAO ,Allow address overwrite" "Not allowed,Allowed" bitfld.long 0x1C 24. " ECM ,Enable the context management" "Disabled,Enabled" bitfld.long 0x1C 20.--23. " OTL ,Outstanding transfer limit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x1C 16.--19. " MARIDD ,Memory address read ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " MARID ,Memory address read ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " MAWIDD ,Memory address write ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. " MAWID ,Memory address write ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("LS1012*")&&!cpuis("LS10?3*") group.long 0xC4++0x03 line.long 0x00 "AXIPC,AXI PROT Control" bitfld.long 0x00 29. " EARP ,Enable the ARPROT" "Disabled,Enabled" bitfld.long 0x00 28. " EAWP ,Enable the AWPROT" "Disabled,Enabled" bitfld.long 0x00 24.--26. " AWPF ,Address write PROT FIS" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " AWPD ,Address write PROT Data" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " AWPFD ,Address write PROT final data" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " ARPP ,Address read PROT PRD" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " ARPH ,Address read PROT header" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ARPF ,Address read PROT FIS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " ARPD ,Address read PROT data" "0,1,2,3,4,5,6,7" endif group.long 0xC8++0x03 line.long 0x00 "PTC,Port TransCfg Register" bitfld.long 0x00 9. " ITM ,Initialize transport memories" "Not initialized,Initialized" bitfld.long 0x00 8. " ENBD ,Enable back down" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " RXWM ,RxWaterMark" group.long 0xD0++0x0B line.long 0x00 "PLC,Port LinkCfg Register" bitfld.long 0x00 27.--31. " PMPRA ,Power management primitive rate acknowledge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " POE ,Primitive override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " PRT ,PHY ready timer" hexmask.long.byte 0x00 8.--15. 1. " AIR ,Align insertion rate" newline bitfld.long 0x00 7. " EPNRT ,Enable PHY not ready timer" "Disabled,Enabled" bitfld.long 0x00 6. " S4A ,Send 4 aligns" "Sent 2,Sent 4" bitfld.long 0x00 5. " RXSE ,Rx scramble enable" "Disabled,Enabled" bitfld.long 0x00 4. " TXSE ,TX scramble enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TXPJ ,TX prim junk" "Junk data,DEADBEEF" bitfld.long 0x00 2. " TXC ,TX cont enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXBC ,RX bad CRC enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXBC ,TX bad CRC enable" "Disabled,Enabled" line.long 0x04 "PLC1,Port LinkCfg1 Register" bitfld.long 0x04 6. " CD ,Data character or primitive" "Data char,Primitive" bitfld.long 0x04 0.--5. " POS ,Primitive override state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,4,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PLC2,Port LinkCfg2 Register" group.long 0xE0++0x0B line.long 0x00 "PLS1,Port LinkStatus1 Register" hexmask.long.byte 0x00 24.--31. 1. " KCEC ,Kchar error count" hexmask.long.byte 0x00 16.--23. 1. " PIEC ,PHY internal error count" hexmask.long.byte 0x00 8.--15. 1. " CEC ,Code error count" hexmask.long.byte 0x00 0.--7. 1. " DEC ,Disparity error count" line.long 0x04 "PCMDC,Port CmdConfig Register" bitfld.long 0x04 29. " TSVIE ,Trustzone slave ID violation interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " TSVI ,Trustzone slave ID violation interrupt" "No interrupt,Interrupt" hexmask.long.word 0x04 12.--27. 1. " TSVT ,Trustzone slave ID of violating transaction" bitfld.long 0x04 1. " ETLL ,Enable transport layer loopback" "Disabled,Enabled" newline bitfld.long 0x04 0. " ETLLB ,Enable transport layer loopback in the BIST L mode" "Disabled,Enabled" line.long 0x08 "PPCS,Port PhyControlStatus Register" rbitfld.long 0x08 30.--31. " PHYCE ,Current 2 bit code error" "00,01,10,11" rbitfld.long 0x08 28.--29. " PHYDE ,Current 2 bit disparity error" "00,01,10,11" rbitfld.long 0x08 27. " PHYKC ,Current 1 bit K character" "0,1" newline hexmask.long.tbyte 0x08 11.--26. 1. " PHYD ,Current 16 bit data" bitfld.long 0x08 10. " CCAC ,Comma alignment has changed" "Not changed,Changed" rbitfld.long 0x08 5.--9. " CCA ,Current comma alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x08 0.--4. " PCTRLS ,PHY control state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "TCR,Timer Control Register" hexmask.long.word 0x00 0.--12. 1. " TPS ,Timer PreScalar value" group.long 0x100++0x0F "Port Registers" line.long 0x00 "PXCLB,Port X Command List Base Address Register" hexmask.long.tbyte 0x00 10.--31. 0x04 " CLB ,Command list base address register" line.long 0x04 "PXCLBU,Port X Command List Base Address Upper 32-bit Register" line.long 0x08 "PXFB,Port X FIS Base Address Register" hexmask.long.tbyte 0x08 8.--31. 0x01 " FB ,FIS base address" line.long 0x0C "PXFBU,Port X FIS Base Address Upper 32-bit Register" newline if (((per.l(ad:0x3200000+0x118))&0x100000)==0x100000) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" newline rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" newline bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif endif if (((per.l(ad:0x3200000))&0x4000000)==0x4000000) if (((per.l(ad:0x3200000+0x24))&0x04)==0x04) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif else if (((per.l(ad:0x3200000+0x24))&0x04)==0x04) if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3200000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3200000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3200000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif endif rgroup.long 0x128++0x03 line.long 0x00 "PXSSTS,Port X SATA Status Register" bitfld.long 0x00 8.--11. " IPM ,Interface power management" "Device not present,Active,Partial power management,,,,Slumber power management,?..." bitfld.long 0x00 4.--7. " SPD ,Current interface speed" "Device not present,Gen 1,Gen 2,Gen 3,?..." bitfld.long 0x00 0.--3. " DET ,Device detection" "Not detected/Not established,Detected/Not established,,Detected/Established,Offline mode,?..." group.long 0x12C++0x07 line.long 0x00 "PXSCTL,Port X Serial ATA Control Register" bitfld.long 0x00 8.--11. " IPM ,Indicates which power states the HBA is not allowed to transition to" "No restrictions,Partial state disabled,Slumber state disabled,Partial/Slumber state disabled,?..." bitfld.long 0x00 4.--7. " SPD ,Indicates the highest allowable speed of the interface" "No restrictions,Generation 1 comm rate,Generation 2 comm rate,Generation 3 comm rate,?..." bitfld.long 0x00 0.--3. " DET ,Device detection initialization" "Not detected/initialized,Perform interface comm init,,,Disable SATA,?..." line.long 0x04 "PXSERR,Port X SATA Error Register" bitfld.long 0x04 26. " DIAG[10] ,Diagnostic error information : Change in device presence has been detected" "Not detected,Detected" bitfld.long 0x04 25. " [9] ,Diagnostic error information : Unknown FIS Type" "Not occurred,Occurred" bitfld.long 0x04 24. " [8] ,Diagnostic error information : Transport state transition error" "Not occurred,Occurred" newline bitfld.long 0x04 23. " [7] ,Diagnostic error information : Link sequence error" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,Diagnostic error information : Handshake error" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,Diagnostic error information : CRC error" "Not occurred,Occurred" newline bitfld.long 0x04 20. " [4] ,Diagnostic error information : Disparity error" "Not occurred,Occurred" bitfld.long 0x04 19. " [3] ,Diagnostic error information : 10B to 8B decode error" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,Diagnostic error information : Comm wake" "Not detected,Detected" newline bitfld.long 0x04 17. " [1] ,Diagnostic error information : PHY internal error" "Not detected,Detected" bitfld.long 0x04 16. " [0] ,Diagnostic error information : PhyRdy change" "Not detected,Detected" newline bitfld.long 0x04 11. " ERR[5] ,Error information : Internal error" "No error,Error" bitfld.long 0x04 10. " [4] ,Error information : Protocol error" "No error,Error" bitfld.long 0x04 9. " [3] ,Error information : Persistent communication or data integrity error" "No error,Error" newline bitfld.long 0x04 8. " [2] ,Error information : Transient data integrity error" "No error,Error" bitfld.long 0x04 1. " [1] ,Error information : Recovered communications error" "No error,Error" bitfld.long 0x04 0. " [0] ,Error information : Recovered data integrity error" "No error,Error" group.long 0x138++0x03 line.long 0x00 "PXCI,Port X Command Issue Register" if (((per.l(ad:0x3200000+0x140))&0x04)==0x04) group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 16.--19. " DWE ,Device with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" endif group.long 0x170++0x03 line.long 0x00 "PBERR,Port 0/1 BIST Error" bitfld.long 0x00 1. " BEOS ,BIST error one shot bit" "No error,Error" rbitfld.long 0x00 0. " BERR ,BIST error" "No error,Error" width 0x0B tree.end tree "SATA 2" base ad:0x3210000 width 9. rgroup.long 0x00++0x03 "HBA Registers" line.long 0x00 "CAP,HBA Capabilities Register" bitfld.long 0x00 31. " S64A ,64-bit addressing support" "Not supported,Supported" bitfld.long 0x00 30. " SNCQ ,Native command queuing support" "Not supported,Supported" bitfld.long 0x00 29. " SSNTF ,SNotification register support" "Not supported,Supported" newline bitfld.long 0x00 28. " SMPS ,Mechanical presence switch support" "Not supported,Supported" bitfld.long 0x00 27. " SSS ,Staggered spin-up support" "Not supported,Supported" bitfld.long 0x00 26. " SALP ,Aggressive link power management support" "Not supported,Supported" newline bitfld.long 0x00 25. " SAL ,Activity LED support" "Not supported,Supported" bitfld.long 0x00 24. " SCLO ,Command list override support" "Not supported,Supported" bitfld.long 0x00 20.--23. " ISS ,Interface speed support" ",Gen 1,Gen 2,Gen 3,?..." newline bitfld.long 0x00 18. " SAM ,AHCI mode only support" "Not supported,Supported" bitfld.long 0x00 17. " SPM ,Port multiplier support" "Not supported,Supported" bitfld.long 0x00 16. " FBSS ,FIS-based switching support" "Not supported,Supported" newline bitfld.long 0x00 15. " PMD ,PIO multiple DRQ block support" "Not supported,Supported" bitfld.long 0x00 14. " SSC ,Slumber state capable support" "Not supported,Supported" bitfld.long 0x00 13. " PSC ,Partial state capable support" "Not supported,Supported" newline bitfld.long 0x00 8.--12. " NCS ,Number of command slots" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 7. " CCCS ,Command completion coalescing support" "Not supported,Supported" bitfld.long 0x00 6. " EMS ,Enclosure management support" "Not supported,Supported" newline bitfld.long 0x00 5. " SXS ,External SATA support" "Not supported,Supported" bitfld.long 0x00 0.--4. " NP ,Number of ports" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" if (((per.l(ad:0x3210000+0x00))&0x40000)==0x00) group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" bitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" else group.long 0x04++0x03 line.long 0x00 "GHC,Global HBA Control Register" rbitfld.long 0x00 31. " AE ,AHCI enable" "Disabled,Enabled" rbitfld.long 0x00 2. " MRSM ,MSI revert to single message" "Not reverted,Reverted" bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HR ,HBA reset" "No reset,Reset" endif rgroup.long 0x10++0x03 line.long 0x00 "VS,AHCI Version Register" hexmask.long.word 0x00 16.--31. 1. " MJR ,Major version number" hexmask.long.word 0x00 0.--15. 1. " MNR ,Minor version number" group.long 0x14++0x03 line.long 0x00 "CCC_CTL,Command Completion Coalescing Control Register" hexmask.long.word 0x00 16.--31. 1. " TV ,Timeout value" hexmask.long.byte 0x00 8.--15. 1. " CC ,Command completions" rbitfld.long 0x00 3.--7. " INT ,Specifies the interrupt used by the CCC feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. " EN ,Command completion coalescing feature enable" "Disabled,Enabled" rgroup.long 0x24++0x03 line.long 0x00 "CAP2,HBA Capabilities Extended Register" bitfld.long 0x00 2. " APST ,Automatic partial to slumber transitions support" "Not supported,Supported" bitfld.long 0x00 1. " NVMP ,NVMHCI support" "Not supported,Supported" bitfld.long 0x00 0. " BOH ,BIOS/OS handoff support" "Not supported,Supported" group.long 0xA4++0x1F line.long 0x00 "PCFG,Port Configuration Register" hexmask.long.byte 0x00 16.--22. 1. " TPSS ,Microsecond timer post scaler" bitfld.long 0x00 12.--14. " TPRS ,Microsecond timer pre scaler" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--5. " PAD ,Port address" ",,Addr cfg/status set,?..." line.long 0x04 "PPCFG,Port Phy1Cfg Register" bitfld.long 0x04 31. " ESDF ,Enable signal detect filter" "Disabled,Enabled" bitfld.long 0x04 30. " ERSN ,Enable reset speed negotiation" "Disabled,Enabled" bitfld.long 0x04 29. " PSS ,PhyControl select SerDes slumber CMU during link slumber" "No slumber,Slumber" bitfld.long 0x04 28. " PSSO ,PhyControl select SerDes OOB or internally decoded OOB signaling as inputs" "SerDes,Internal" newline rbitfld.long 0x04 27. " STB ,Status of the gen fixed clocks parameter" "Fixed freq clock,Variable clock" bitfld.long 0x04 26. " PBPNA ,PhyControl BIST pattern no aligns" "Not continuously,Continuously" bitfld.long 0x04 25. " PBCE ,PhyControl BIST clear error" "No effect,Clear" bitfld.long 0x04 24. " PBPE ,PhyControl BIST pattern enable" "Disabled,Enabled" newline bitfld.long 0x04 21.--23. " PBPS ,PhyControl BIST pattern select" "LBP,LFTP,MFTP,HFTP,PRBS,BIST,?..." bitfld.long 0x04 20. " FPR ,Force PHY ready" "Not forced,Forced" bitfld.long 0x04 18. " SNR ,Speed negotiation rate" "Normal,SPD" newline bitfld.long 0x04 17. " SNM ,Speed negotiation method" "Fastest speed to Gen 1,Gen 1 to fastest speed" hexmask.long.tbyte 0x04 0.--16. 1. " TTA ,This value determines the time period the controller transmits and waits for ALIGNp during speed negotiation" line.long 0x08 "PP2C,Port Phy2Cfg Register" hexmask.long.byte 0x08 24.--31. 1. " CINMP ,COMINIT negate minimum period" hexmask.long.byte 0x08 16.--23. 1. " CIBGN ,COMINIT burst gap nominal" hexmask.long.byte 0x08 8.--15. 1. " CIBGMX ,COMINIT burst gap maximum" hexmask.long.byte 0x08 0.--7. 1. " CIBGMN ,COMINIT burst gap minimum" line.long 0x0C "PP3C,Port Phy3Cfg Register" hexmask.long.byte 0x0C 24.--31. 1. " CWNMP ,COMWAKE negate minimum period" hexmask.long.byte 0x0C 16.--23. 1. " CWBGN ,COMWAKE burst gap nominal" hexmask.long.byte 0x0C 8.--15. 1. " CWBGMX ,COMWAKE burst gap maximum" hexmask.long.byte 0x0C 0.--7. 1. " CWBGMN ,COMWAKE burst gap minimum" line.long 0x10 "PP4C,Port Phy4Cfg Register" hexmask.long.byte 0x10 24.--31. 1. " PTST ,Partial to slumber timer value" hexmask.long.byte 0x10 16.--23. 1. " SFD ,Signal failure detection" hexmask.long.byte 0x10 8.--15. 1. " BNM ,COM burst nominal" hexmask.long.byte 0x10 0.--7. 1. " BMX ,COM burst maximum" line.long 0x14 "PP5C,Port Phy5Cfg Register" hexmask.long.word 0x14 20.--31. 1. " RCT ,Rate change timer" hexmask.long.tbyte 0x14 0.--19. 1. " RIT ,Retry interval timer" line.long 0x18 "AXICC,AXI CACHE Control Register" bitfld.long 0x18 29. " EARC ,Enable the ARCACHE" "Disabled,Enabled" bitfld.long 0x18 28. " EAWC ,Enable the AWCACHE" "Disabled,Enabled" bitfld.long 0x18 24.--27. " AWCF ,Address write cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 20.--23. " AWCD ,Address write cache data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 16.--19. " AWCFD ,Address write cache final data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 12.--15. " ARCP ,Address read cache PRD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. " ARCH ,Address read cache header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 4.--7. " ARCF ,Address read cache FIS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. " ARCA ,Address read cache ATAPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "PAXIC,Port AXICfg Register" bitfld.long 0x1C 28. " ENPE ,Enable non zero 4MB PRD entries" "Disabled,Enabled" bitfld.long 0x1C 25. " AAO ,Allow address overwrite" "Not allowed,Allowed" bitfld.long 0x1C 24. " ECM ,Enable the context management" "Disabled,Enabled" bitfld.long 0x1C 20.--23. " OTL ,Outstanding transfer limit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x1C 16.--19. " MARIDD ,Memory address read ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 12.--15. " MARID ,Memory address read ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 8.--11. " MAWIDD ,Memory address write ID for data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 4.--7. " MAWID ,Memory address write ID for non data transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif !cpuis("LS1012*")&&!cpuis("LS10?3*") group.long 0xC4++0x03 line.long 0x00 "AXIPC,AXI PROT Control" bitfld.long 0x00 29. " EARP ,Enable the ARPROT" "Disabled,Enabled" bitfld.long 0x00 28. " EAWP ,Enable the AWPROT" "Disabled,Enabled" bitfld.long 0x00 24.--26. " AWPF ,Address write PROT FIS" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " AWPD ,Address write PROT Data" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " AWPFD ,Address write PROT final data" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " ARPP ,Address read PROT PRD" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " ARPH ,Address read PROT header" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ARPF ,Address read PROT FIS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " ARPD ,Address read PROT data" "0,1,2,3,4,5,6,7" endif group.long 0xC8++0x03 line.long 0x00 "PTC,Port TransCfg Register" bitfld.long 0x00 9. " ITM ,Initialize transport memories" "Not initialized,Initialized" bitfld.long 0x00 8. " ENBD ,Enable back down" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " RXWM ,RxWaterMark" group.long 0xD0++0x0B line.long 0x00 "PLC,Port LinkCfg Register" bitfld.long 0x00 27.--31. " PMPRA ,Power management primitive rate acknowledge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 26. " POE ,Primitive override enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " PRT ,PHY ready timer" hexmask.long.byte 0x00 8.--15. 1. " AIR ,Align insertion rate" newline bitfld.long 0x00 7. " EPNRT ,Enable PHY not ready timer" "Disabled,Enabled" bitfld.long 0x00 6. " S4A ,Send 4 aligns" "Sent 2,Sent 4" bitfld.long 0x00 5. " RXSE ,Rx scramble enable" "Disabled,Enabled" bitfld.long 0x00 4. " TXSE ,TX scramble enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " TXPJ ,TX prim junk" "Junk data,DEADBEEF" bitfld.long 0x00 2. " TXC ,TX cont enable" "Disabled,Enabled" bitfld.long 0x00 1. " RXBC ,RX bad CRC enable" "Disabled,Enabled" bitfld.long 0x00 0. " TXBC ,TX bad CRC enable" "Disabled,Enabled" line.long 0x04 "PLC1,Port LinkCfg1 Register" bitfld.long 0x04 6. " CD ,Data character or primitive" "Data char,Primitive" bitfld.long 0x04 0.--5. " POS ,Primitive override state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,4,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PLC2,Port LinkCfg2 Register" group.long 0xE0++0x0B line.long 0x00 "PLS1,Port LinkStatus1 Register" hexmask.long.byte 0x00 24.--31. 1. " KCEC ,Kchar error count" hexmask.long.byte 0x00 16.--23. 1. " PIEC ,PHY internal error count" hexmask.long.byte 0x00 8.--15. 1. " CEC ,Code error count" hexmask.long.byte 0x00 0.--7. 1. " DEC ,Disparity error count" line.long 0x04 "PCMDC,Port CmdConfig Register" bitfld.long 0x04 29. " TSVIE ,Trustzone slave ID violation interrupt enable" "Disabled,Enabled" bitfld.long 0x04 28. " TSVI ,Trustzone slave ID violation interrupt" "No interrupt,Interrupt" hexmask.long.word 0x04 12.--27. 1. " TSVT ,Trustzone slave ID of violating transaction" bitfld.long 0x04 1. " ETLL ,Enable transport layer loopback" "Disabled,Enabled" newline bitfld.long 0x04 0. " ETLLB ,Enable transport layer loopback in the BIST L mode" "Disabled,Enabled" line.long 0x08 "PPCS,Port PhyControlStatus Register" rbitfld.long 0x08 30.--31. " PHYCE ,Current 2 bit code error" "00,01,10,11" rbitfld.long 0x08 28.--29. " PHYDE ,Current 2 bit disparity error" "00,01,10,11" rbitfld.long 0x08 27. " PHYKC ,Current 1 bit K character" "0,1" newline hexmask.long.tbyte 0x08 11.--26. 1. " PHYD ,Current 16 bit data" bitfld.long 0x08 10. " CCAC ,Comma alignment has changed" "Not changed,Changed" rbitfld.long 0x08 5.--9. " CCA ,Current comma alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x08 0.--4. " PCTRLS ,PHY control state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xF0++0x03 line.long 0x00 "TCR,Timer Control Register" hexmask.long.word 0x00 0.--12. 1. " TPS ,Timer PreScalar value" group.long 0x100++0x0F "Port Registers" line.long 0x00 "PXCLB,Port X Command List Base Address Register" hexmask.long.tbyte 0x00 10.--31. 0x04 " CLB ,Command list base address register" line.long 0x04 "PXCLBU,Port X Command List Base Address Upper 32-bit Register" line.long 0x08 "PXFB,Port X FIS Base Address Register" hexmask.long.tbyte 0x08 8.--31. 0x01 " FB ,FIS base address" line.long 0x0C "PXFBU,Port X FIS Base Address Upper 32-bit Register" newline if (((per.l(ad:0x3210000+0x118))&0x100000)==0x100000) if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" newline rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 31. " CPDS ,Cold port detect status" "Not detected,Detected" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" newline bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" newline bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif else if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000))&0x80000)==0x80000) group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" bitfld.long 0x00 7. " DMPS ,Device mechanical presence status" "0,1" newline rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" else group.long 0x110++0x03 line.long 0x00 "PXIS,Port X Interrupt Status Register" bitfld.long 0x00 30. " TFES ,Task file error status" "No error,Error" bitfld.long 0x00 29. " HBFS ,Host bus fatal error status" "No error,Error" bitfld.long 0x00 28. " HBDS ,Host bus data error status" "No error,Error" newline bitfld.long 0x00 27. " IFS ,Interface fatal error status" "No error,Error" bitfld.long 0x00 26. " NTFS ,Interface non-fatal error status" "No error,Error" bitfld.long 0x00 24. " OFS ,Overflow status" "No overflow,Overflow" newline bitfld.long 0x00 23. " IPMS ,Incorrect port multiplier status" "0,1" rbitfld.long 0x00 22. " PRCS ,PhyRdy change status" "Not changed,Changed" rbitfld.long 0x00 6. " PCS ,Port connect change status" "Not changed,Changed" newline bitfld.long 0x00 5. " DPS ,Descriptor processed" "Not processed,Processed" rbitfld.long 0x00 4. " UFS ,Unknown FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " SDBS ,Set device bits interrupt" "No interrupt,Interrupt" newline bitfld.long 0x00 2. " DSS ,DMA setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " PSS ,PIO setup FIS interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " DHRS ,Device to host register FIS interrupt" "No interrupt,Interrupt" endif endif if (((per.l(ad:0x3210000))&0x4000000)==0x4000000) if (((per.l(ad:0x3210000+0x24))&0x04)==0x04) if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 27. " ASP ,Aggressive slumber / partial" "Partial,Slumber" bitfld.long 0x00 26. " ALPE ,Aggressive link power management enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" newline rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" newline rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" newline rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif else if (((per.l(ad:0x3210000+0x24))&0x04)==0x04) if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" newline rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline bitfld.long 0x00 23. " APSTE ,Automatic partial to slumber transitions enabled" "Disabled,Enabled" rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" newline rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" newline rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" newline rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif else if (((per.l(ad:0x3210000))&0x10000000)==0x10000000)&&(((per.l(ad:0x3210000+0x118))&0x80000)==0x80000) if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 13. " MPSS ,Mechanical presence switch state" "Closed,Open" rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" newline bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif else if (((per.l(ad:0x3210000))&0x20000)==0x20000) group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" bitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" else group.long 0x118++0x03 line.long 0x00 "PXCMD,Port X Command And Status Register" bitfld.long 0x00 28.--31. " ICC ,Interface communication control" "Idle,Active,Partial,,,,Slumber,?..." bitfld.long 0x00 25. " DLAE ,Drive LED on ATAPI enable" "Disabled,Enabled" bitfld.long 0x00 24. " ATAPI ,Device is ATAPI" "Not ATAPI,ATAPI" newline rbitfld.long 0x00 22. " FBSCP ,FIS-based switching capable port" "Not capable,Capable" rbitfld.long 0x00 21. " ESP ,Indicates that this port's signal connector is externally accessible on a signal only connector" "Not accessible,Accessible" rbitfld.long 0x00 20. " CPD ,Cold presence detection support" "Not supported,Supported" newline rbitfld.long 0x00 19. " MPSP ,Mechanical presence switch attached to port support" "Not supported,Supported" rbitfld.long 0x00 18. " HPCP ,Hot plug capable port" "Not capable,Capable" rbitfld.long 0x00 17. " PMA ,Port multiplier attached" "Not attached,Attached" newline rbitfld.long 0x00 16. " CPS ,Cold presence state" "Not detected,Detected" rbitfld.long 0x00 15. " CR ,Command list running" "Not running,Running" rbitfld.long 0x00 14. " FR ,FIS receive running" "Not running,Running" newline rbitfld.long 0x00 8.--12. " CCS ,Current command slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. " FRE ,FIS receive enable" "Disabled,Enabled" bitfld.long 0x00 3. " CLO ,Command list override" "Not overridden,Overridden" newline rbitfld.long 0x00 2. " POD ,Power on device" "Powered off,Powered on" rbitfld.long 0x00 1. " SUD ,Spin-up device" "0,1" bitfld.long 0x00 0. " ST ,When set the HBA starts processing the command list" "Not started,Started" endif endif endif endif rgroup.long 0x128++0x03 line.long 0x00 "PXSSTS,Port X SATA Status Register" bitfld.long 0x00 8.--11. " IPM ,Interface power management" "Device not present,Active,Partial power management,,,,Slumber power management,?..." bitfld.long 0x00 4.--7. " SPD ,Current interface speed" "Device not present,Gen 1,Gen 2,Gen 3,?..." bitfld.long 0x00 0.--3. " DET ,Device detection" "Not detected/Not established,Detected/Not established,,Detected/Established,Offline mode,?..." group.long 0x12C++0x07 line.long 0x00 "PXSCTL,Port X Serial ATA Control Register" bitfld.long 0x00 8.--11. " IPM ,Indicates which power states the HBA is not allowed to transition to" "No restrictions,Partial state disabled,Slumber state disabled,Partial/Slumber state disabled,?..." bitfld.long 0x00 4.--7. " SPD ,Indicates the highest allowable speed of the interface" "No restrictions,Generation 1 comm rate,Generation 2 comm rate,Generation 3 comm rate,?..." bitfld.long 0x00 0.--3. " DET ,Device detection initialization" "Not detected/initialized,Perform interface comm init,,,Disable SATA,?..." line.long 0x04 "PXSERR,Port X SATA Error Register" bitfld.long 0x04 26. " DIAG[10] ,Diagnostic error information : Change in device presence has been detected" "Not detected,Detected" bitfld.long 0x04 25. " [9] ,Diagnostic error information : Unknown FIS Type" "Not occurred,Occurred" bitfld.long 0x04 24. " [8] ,Diagnostic error information : Transport state transition error" "Not occurred,Occurred" newline bitfld.long 0x04 23. " [7] ,Diagnostic error information : Link sequence error" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,Diagnostic error information : Handshake error" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,Diagnostic error information : CRC error" "Not occurred,Occurred" newline bitfld.long 0x04 20. " [4] ,Diagnostic error information : Disparity error" "Not occurred,Occurred" bitfld.long 0x04 19. " [3] ,Diagnostic error information : 10B to 8B decode error" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,Diagnostic error information : Comm wake" "Not detected,Detected" newline bitfld.long 0x04 17. " [1] ,Diagnostic error information : PHY internal error" "Not detected,Detected" bitfld.long 0x04 16. " [0] ,Diagnostic error information : PhyRdy change" "Not detected,Detected" newline bitfld.long 0x04 11. " ERR[5] ,Error information : Internal error" "No error,Error" bitfld.long 0x04 10. " [4] ,Error information : Protocol error" "No error,Error" bitfld.long 0x04 9. " [3] ,Error information : Persistent communication or data integrity error" "No error,Error" newline bitfld.long 0x04 8. " [2] ,Error information : Transient data integrity error" "No error,Error" bitfld.long 0x04 1. " [1] ,Error information : Recovered communications error" "No error,Error" bitfld.long 0x04 0. " [0] ,Error information : Recovered data integrity error" "No error,Error" group.long 0x138++0x03 line.long 0x00 "PXCI,Port X Command Issue Register" if (((per.l(ad:0x3210000+0x140))&0x04)==0x04) group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 16.--19. " DWE ,Device with error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "PXFBS,Port X FIS-Based Switching Control" rbitfld.long 0x00 12.--15. " ADO ,Active device optimization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " DEV ,Device to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 2. " SDE ,Single device error" "No error,Error" bitfld.long 0x00 1. " DEC ,Device error clear" "No effect,Clear" bitfld.long 0x00 0. " EN ,FIS-based switching enable" "Disabled,Enabled" endif group.long 0x170++0x03 line.long 0x00 "PBERR,Port 0/1 BIST Error" bitfld.long 0x00 1. " BEOS ,BIST error one shot bit" "No error,Error" rbitfld.long 0x00 0. " BERR ,BIST error" "No error,Error" width 0x0B tree.end tree.end endif tree "SerDes" sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "SerDes 1" base ad:0x1EA0000 width 12. tree "Group/PLL Configuration Control and Status Registers" if (((per.l(ad:0x1EA0000)&0x60000000))==0x00) rgroup.long 0x00++0x03 line.long 0x00 "PLL1RSTCTL,SerDes Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "PLL1RSTCTL,SerDes Reset Control Register" eventfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes Reset Control Register" eventfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif newline group.long 0x04++0x07 line.long 0x00 "PLL1CR0,SerDes PLL 1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100MHz,125MHz,150MHz,?..." rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" newline bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5GHz,,,,,,,,,,3GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." line.long 0x04 "PLL1CR1,SerDes PLL 1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" bitfld.long 0x04 21. " VCO_EN ,Select VCO for use in PLL1" "LC VCO,Ring VCO" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL 2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100MHz,125MHz,150MHz,?..." rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" newline bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5GHz,,,,,,,,,,3GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." line.long 0x04 "PLL2CR1,SerDes PLL 2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" bitfld.long 0x04 21. " VCO_EN ,Select VCO for use in PLL1" "LC VCO,Ring VCO" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL 1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL 2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control 1 Register" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control 1 Register" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,SerDes General Register 0" bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" rgroup.long 0x100++0x03 line.long 0x00 "LN0PSSR0,SerDes Lane 0 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LN1PSSR0,SerDes Lane 1 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LN2PSSR0,SerDes Lane 2 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LN3PSSR0,SerDes Lane 3 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." newline group.long 0x200++0x03 line.long 0x00 "PCCR0,SerDes Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 0,?..." group.long 0x220++0x03 line.long 0x00 "PCCR8,SerDes Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on Lane 0 to GMIIa,?..." newline bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIa configuration" "Disabled,x1 on Lane 1 to GMIIb,?..." newline bitfld.long 0x00 23. " SGMIIC_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIa configuration" "Disabled,x1 on Lane 2 to GMIIc,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIIa configuration" "Disabled,x1 on Lane 3 to GMIId,?..." group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled,x1 on Lane 0,?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on Lane 1,x1 on Lane 3,?..." group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 2 to XGMIIa,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,x1 on Lane 3 to XGMIIb,?..." group.long 0x300++0x03 line.long 0x00 "PEXEQCR,SerDes PCI Express Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,SerDes PCI Express Equalization Preset 0 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,SerDes PCI Express Equalization Preset 1 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,SerDes PCI Express Equalization Preset 2 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,SerDes PCI Express Equalization Preset 3 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,SerDes PCI Express Equalization Preset 4 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,SerDes PCI Express Equalization Preset 5 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,SerDes PCI Express Equalization Preset 6 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,SerDes PCI Express Equalization Preset 7 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,SerDes PCI Express Equalization Preset 8 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,SerDes PCI Express Equalization Preset 9 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,SerDes PCI Express Equalization Preset 10 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." tree.end tree "Per-lane SerDes Control/Status Registers" group.long 0x800++0x07 line.long 0x00 "LNAGCR0,SerDes Lane A General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNAGCR1,SerDes Lane A General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x840++0x07 line.long 0x00 "LNBGCR0,SerDes Lane B General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNBGCR1,SerDes Lane B General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x880++0x07 line.long 0x00 "LNCGCR0,SerDes Lane C General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNCGCR1,SerDes Lane C General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,SerDes Lane D General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,SerDes Lane D General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,SerDes Lane A Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,SerDes Lane A Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,SerDes Lane A Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,SerDes Lane B Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,SerDes Lane B Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,SerDes Lane B Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNCSSCR0,SerDes Lane C Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCRECR0,SerDes Lane C Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,SerDes Lane C Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x88C+0x0C)++0x0B line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8CC++0x07 line.long 0x00 "LNDSSCR0,SerDes Lane D Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,SerDes Lane D Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,SerDes Lane D Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x8CC+0x0C)++0x0B line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,SRDS x Lane A Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,SRDS x Lane B Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,SRDS x Lane C Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,SRDS x Lane D Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" tree.end tree "Protocol Control and Status Registers" group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" rgroup.long 0x1984++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x1994++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" tree.end width 0x0B tree.end tree "SerDes 2" base ad:0x1EB0000 width 12. tree "Group/PLL Configuration Control and Status Registers" if (((per.l(ad:0x1EB0000)&0x60000000))==0x00) rgroup.long 0x00++0x03 line.long 0x00 "PLL1RSTCTL,SerDes Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "PLL1RSTCTL,SerDes Reset Control Register" eventfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes Reset Control Register" eventfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif newline group.long 0x04++0x07 line.long 0x00 "PLL1CR0,SerDes PLL 1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100MHz,125MHz,150MHz,?..." rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" newline bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5GHz,,,,,,,,,,3GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." line.long 0x04 "PLL1CR1,SerDes PLL 1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" bitfld.long 0x04 21. " VCO_EN ,Select VCO for use in PLL1" "LC VCO,Ring VCO" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL 2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100MHz,125MHz,150MHz,?..." rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" newline bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5GHz,,,,,,,,,,3GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." line.long 0x04 "PLL2CR1,SerDes PLL 2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" bitfld.long 0x04 21. " VCO_EN ,Select VCO for use in PLL1" "LC VCO,Ring VCO" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL 1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL 2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control 1 Register" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control 1 Register" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,SerDes General Register 0" bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" rgroup.long 0x100++0x03 line.long 0x00 "LN0PSSR0,SerDes Lane 0 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LN1PSSR0,SerDes Lane 1 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LN2PSSR0,SerDes Lane 2 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LN3PSSR0,SerDes Lane 3 Protocol Select Status Register 0" bitfld.long 0x00 24.--28. " TYPE ,Protocol type" "PCI EXP,SGMII-1G,SATA,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." newline group.long 0x200++0x03 line.long 0x00 "PCCR0,SerDes Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x4 [3:0] on lanes [0:3],x1 on lane 0,x2 [1:0] on lanes [0:1],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 2,x1 on lane 1,?..." newline bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 3,x1 on Lane 2,x2 [1:0] on Lanes [2:3],?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,SerDes Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 3,?..." group.long 0x220++0x03 line.long 0x00 "PCCR8,SerDes Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 23. " SGMIIC_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" group.long 0x300++0x03 line.long 0x00 "PEXEQCR,SerDes PCI Express Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,SerDes PCI Express Equalization Preset 0 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,SerDes PCI Express Equalization Preset 1 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,SerDes PCI Express Equalization Preset 2 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,SerDes PCI Express Equalization Preset 3 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,SerDes PCI Express Equalization Preset 4 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,SerDes PCI Express Equalization Preset 5 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,SerDes PCI Express Equalization Preset 6 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,SerDes PCI Express Equalization Preset 7 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,SerDes PCI Express Equalization Preset 8 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,SerDes PCI Express Equalization Preset 9 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,SerDes PCI Express Equalization Preset 10 Control Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." tree.end tree "Per-lane SerDes Control/Status Registers" group.long 0x800++0x07 line.long 0x00 "LNAGCR0,SerDes Lane A General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNAGCR1,SerDes Lane A General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x840++0x07 line.long 0x00 "LNBGCR0,SerDes Lane B General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNBGCR1,SerDes Lane B General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x880++0x07 line.long 0x00 "LNCGCR0,SerDes Lane C General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNCGCR1,SerDes Lane C General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,SerDes Lane D General Control Register 0" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,SerDes Lane D General Control Register 1" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" newline bitfld.long 0x04 5.--6. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,SerDes Lane A Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,SerDes Lane A Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,SerDes Lane A Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,SerDes Lane B Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,SerDes Lane B Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,SerDes Lane B Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNCSSCR0,SerDes Lane C Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCRECR0,SerDes Lane C Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,SerDes Lane C Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x88C+0x0C)++0x0B line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8CC++0x07 line.long 0x00 "LNDSSCR0,SerDes Lane D Speed Switch Control Register 0" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" newline bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" newline bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,SerDes Lane D Receive Equalization Control Register 0" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,SerDes Lane D Receiver Equalization Control Register 1" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x8CC+0x0C)++0x0B line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,SRDS x Lane A Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,SRDS x Lane B Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,SRDS x Lane C Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,SRDS x Lane D Test Control/Status Register 3" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" tree.end tree "Protocol Control and Status Registers" group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control 1" hexmask.long.byte 0x00 27.--31. 0x08 " MDEV_PORT ,MDIO bus port address" rgroup.long 0x1984++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x1994++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" tree.end width 0x0B tree.end elif cpuis("LS1012*") tree "SerDes 1" base ad:0x1EA0000 width 12. endian.be tree "Group/PLL Configuration Control and Status Registers" if (((per.l.be(ad:0x1EA0000)&0x60000000))==0x00) rgroup.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif group.long 0x4++0x07 line.long 0x00 "PLL1CR0,SerDes PLL1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL1CR1,SerDes PLL1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL2CR1,SerDes PLL2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control Register 1" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control Register 1" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,General Control Register 0 " bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" sif cpuis("LS10?3*") rgroup.long 0x100++0x03 line.long 0x00 "LNAPSSR0,Lane A Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LNBPSSR0,Lane B Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LNCPSSR0,Lane C Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LNDPSSR0,Lane D Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." endif sif cpuis("LS10?6*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 0,x4 [3:0] on lanes [0:3],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 1,?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 2,x2 on lanes [2:3],x1 on lane 3,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 3,?..." elif cpuis("LS10?3*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x4 [3:0] on lanes [0:3],x1 on lane 0,x2 [1:0] on lanes [0:1],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 2,x1 on lane 1?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 3,,x2 [1:0] on lanes [2:3],?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,Enabled on lane 3,?..." else group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x1 on lane 2,Disabled,Disabled,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 2,?..." bitfld.long 0x00 12.--14. " TXCLKA_CFG ,TXCLKa configuration" "Disabled,Enabled on lane 0,Enabled on lane 1,?..." endif sif cpuis("LS10?6*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to GMIIa,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on Lane 1 to GMIIb,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 2 to GMIIc,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to GMIId,?..." elif cpuis("LS10?3*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to FMan Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 2 to FMan Mac 2,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 3 to FMan Mac 5,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to FMan Mac 6,?..." else group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to WRIOP Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 1 to WRIOP Mac 5,?..." endif sif cpuis("LS10?6*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on lane 1 to GMIIa,b,c,e,?..." elif cpuis("LS10?3*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled, x1 on Lane 0 connected to FMan MACs 1 2 5 6?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on Lane 1 connected to FMan MACs 1 2 5 6,?..." endif sif cpuis("LS10?6*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 1 to XGMIIa,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,x1 on Lane 0 to XGMIIb,?..." elif cpuis("LS10?3*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 0 to FMan MAC 9,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,?..." endif sif cpuis("LS10?6*") group.long 0x300++0x03 line.long 0x00 "PEXEQCR,PCIe Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,PCIe Equalization Preset 0 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,PCIe Equalization Preset 1 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,PCIe Equalization Preset 2 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,PCIe Equalization Preset 3 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,PCIe Equalization Preset 4 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,PCIe Equalization Preset 5 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,PCIe Equalization Preset 6 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,PCIe Equalization Preset 7 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,PCIe Equalization Preset 8 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,PCIe Equalization Preset 9 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,PCIe Equalization Preset 10 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." endif tree.end tree "Per-lane SerDes Control/Status Registers" sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x880+0x04)++0x03 line.long 0x00 "LNCGCR1,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x8C0+0x04)++0x03 line.long 0x00 "LNDGCR1,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" else if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane $2 to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane $2" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane $2" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane $2" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane $2" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,General Control Register 1 - Lane D" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x04 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x04 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x04)++0x03 line.long 0x00 "LNARECR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x08)++0x03 line.long 0x00 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x04)++0x03 line.long 0x00 "LNBRECR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x08)++0x03 line.long 0x00 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x04)++0x03 line.long 0x00 "LNCRECR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,Speed Switch Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x08)++0x03 line.long 0x00 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x04)++0x03 line.long 0x00 "LNDRECR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,Test Control/Status Register 3 - Lane C" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" else group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,Receive Equalization Control Register 0 - Lane A" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Receive Equalization Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,Transmit Equalization Control Register 0 - Lane A" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,TTL Control Register 0 - Lane A" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,Receive Equalization Control Register 0 - Lane B" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Receive Equalization Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,Transmit Equalization Control Register 0 - Lane B" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,TTL Control Register 0 - Lane B" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,Receive Equalization Control Register 0 - Lane C" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long 0x894++0x03 line.long 0x00 "LNDRECR1,Receive Equalization Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long 0x898++0x0B line.long 0x00 "LNDTECR0,Transmit Equalization Control Register 0 - Lane D" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,TTL Control Register 0 - Lane D" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" endif tree.end tree "Protocol Control and Status Registers" sif cpuis("LS10?6*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" elif cpuis("LS10?3*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" else group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEX$2 Protocol Control Register 0" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" else group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" else rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1994++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x19A4++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" endif tree.end endian.le width 0x0B tree.end elif cpuis("LS10?3*") tree "SerDes 1" base ad:0x1EA0000 width 12. endian.be tree "Group/PLL Configuration Control and Status Registers" if (((per.l.be(ad:0x1EA0000)&0x60000000))==0x00) rgroup.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif group.long 0x4++0x07 line.long 0x00 "PLL1CR0,SerDes PLL1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL1CR1,SerDes PLL1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL2CR1,SerDes PLL2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control Register 1" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control Register 1" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,General Control Register 0 " bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" sif cpuis("LS10?3*") rgroup.long 0x100++0x03 line.long 0x00 "LNAPSSR0,Lane A Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LNBPSSR0,Lane B Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LNCPSSR0,Lane C Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LNDPSSR0,Lane D Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." endif sif cpuis("LS10?6*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 0,x4 [3:0] on lanes [0:3],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 1,?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 2,x2 on lanes [2:3],x1 on lane 3,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 3,?..." elif cpuis("LS10?3*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x4 [3:0] on lanes [0:3],x1 on lane 0,x2 [1:0] on lanes [0:1],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 2,x1 on lane 1?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 3,,x2 [1:0] on lanes [2:3],?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,Enabled on lane 3,?..." else group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x1 on lane 2,Disabled,Disabled,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 2,?..." bitfld.long 0x00 12.--14. " TXCLKA_CFG ,TXCLKa configuration" "Disabled,Enabled on lane 0,Enabled on lane 1,?..." endif sif cpuis("LS10?6*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to GMIIa,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on Lane 1 to GMIIb,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 2 to GMIIc,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to GMIId,?..." elif cpuis("LS10?3*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to FMan Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 2 to FMan Mac 2,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 3 to FMan Mac 5,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to FMan Mac 6,?..." else group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to WRIOP Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 1 to WRIOP Mac 5,?..." endif sif cpuis("LS10?6*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on lane 1 to GMIIa,b,c,e,?..." elif cpuis("LS10?3*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled, x1 on Lane 0 connected to FMan MACs 1 2 5 6?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on Lane 1 connected to FMan MACs 1 2 5 6,?..." endif sif cpuis("LS10?6*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 1 to XGMIIa,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,x1 on Lane 0 to XGMIIb,?..." elif cpuis("LS10?3*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 0 to FMan MAC 9,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,?..." endif sif cpuis("LS10?6*") group.long 0x300++0x03 line.long 0x00 "PEXEQCR,PCIe Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,PCIe Equalization Preset 0 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,PCIe Equalization Preset 1 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,PCIe Equalization Preset 2 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,PCIe Equalization Preset 3 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,PCIe Equalization Preset 4 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,PCIe Equalization Preset 5 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,PCIe Equalization Preset 6 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,PCIe Equalization Preset 7 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,PCIe Equalization Preset 8 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,PCIe Equalization Preset 9 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,PCIe Equalization Preset 10 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." endif tree.end tree "Per-lane SerDes Control/Status Registers" sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x880+0x04)++0x03 line.long 0x00 "LNCGCR1,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x8C0+0x04)++0x03 line.long 0x00 "LNDGCR1,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" else if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane $2 to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane $2" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane $2" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane $2" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane $2" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,General Control Register 1 - Lane D" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x04 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x04 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x04)++0x03 line.long 0x00 "LNARECR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x08)++0x03 line.long 0x00 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x04)++0x03 line.long 0x00 "LNBRECR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x08)++0x03 line.long 0x00 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x04)++0x03 line.long 0x00 "LNCRECR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,Speed Switch Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x08)++0x03 line.long 0x00 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x04)++0x03 line.long 0x00 "LNDRECR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,Test Control/Status Register 3 - Lane C" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" else group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,Receive Equalization Control Register 0 - Lane A" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Receive Equalization Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,Transmit Equalization Control Register 0 - Lane A" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,TTL Control Register 0 - Lane A" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,Receive Equalization Control Register 0 - Lane B" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Receive Equalization Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,Transmit Equalization Control Register 0 - Lane B" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,TTL Control Register 0 - Lane B" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,Receive Equalization Control Register 0 - Lane C" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long 0x894++0x03 line.long 0x00 "LNDRECR1,Receive Equalization Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long 0x898++0x0B line.long 0x00 "LNDTECR0,Transmit Equalization Control Register 0 - Lane D" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,TTL Control Register 0 - Lane D" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" endif tree.end tree "Protocol Control and Status Registers" sif cpuis("LS10?6*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" elif cpuis("LS10?3*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" else group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEX$2 Protocol Control Register 0" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" else group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" else rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1994++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x19A4++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" endif tree.end endian.le width 0x0B tree.end else tree "SerDes 1" base ad:0x1EA0000 width 12. endian.be tree "Group/PLL Configuration Control and Status Registers" if (((per.l.be(ad:0x1EA0000)&0x60000000))==0x00) rgroup.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif group.long 0x4++0x07 line.long 0x00 "PLL1CR0,SerDes PLL1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL1CR1,SerDes PLL1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL2CR1,SerDes PLL2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control Register 1" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control Register 1" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,General Control Register 0 " bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" sif cpuis("LS10?3*") rgroup.long 0x100++0x03 line.long 0x00 "LNAPSSR0,Lane A Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LNBPSSR0,Lane B Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LNCPSSR0,Lane C Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LNDPSSR0,Lane D Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." endif sif cpuis("LS10?6*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 0,x4 [3:0] on lanes [0:3],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 1,?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 2,x2 on lanes [2:3],x1 on lane 3,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 3,?..." elif cpuis("LS10?3*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x4 [3:0] on lanes [0:3],x1 on lane 0,x2 [1:0] on lanes [0:1],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 2,x1 on lane 1?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 3,,x2 [1:0] on lanes [2:3],?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,Enabled on lane 3,?..." else group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x1 on lane 2,Disabled,Disabled,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 2,?..." bitfld.long 0x00 12.--14. " TXCLKA_CFG ,TXCLKa configuration" "Disabled,Enabled on lane 0,Enabled on lane 1,?..." endif sif cpuis("LS10?6*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to GMIIa,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on Lane 1 to GMIIb,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 2 to GMIIc,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to GMIId,?..." elif cpuis("LS10?3*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to FMan Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 2 to FMan Mac 2,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 3 to FMan Mac 5,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to FMan Mac 6,?..." else group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to WRIOP Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 1 to WRIOP Mac 5,?..." endif sif cpuis("LS10?6*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on lane 1 to GMIIa,b,c,e,?..." elif cpuis("LS10?3*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled, x1 on Lane 0 connected to FMan MACs 1 2 5 6?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on Lane 1 connected to FMan MACs 1 2 5 6,?..." endif sif cpuis("LS10?6*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 1 to XGMIIa,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,x1 on Lane 0 to XGMIIb,?..." elif cpuis("LS10?3*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 0 to FMan MAC 9,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,?..." endif sif cpuis("LS10?6*") group.long 0x300++0x03 line.long 0x00 "PEXEQCR,PCIe Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,PCIe Equalization Preset 0 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,PCIe Equalization Preset 1 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,PCIe Equalization Preset 2 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,PCIe Equalization Preset 3 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,PCIe Equalization Preset 4 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,PCIe Equalization Preset 5 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,PCIe Equalization Preset 6 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,PCIe Equalization Preset 7 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,PCIe Equalization Preset 8 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,PCIe Equalization Preset 9 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,PCIe Equalization Preset 10 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." endif tree.end tree "Per-lane SerDes Control/Status Registers" sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x880+0x04)++0x03 line.long 0x00 "LNCGCR1,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x8C0+0x04)++0x03 line.long 0x00 "LNDGCR1,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" else if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EA0000)&0x80000000))==0x00) group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane $2 to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane $2" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane $2" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane $2" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane $2" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,General Control Register 1 - Lane D" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x04 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x04 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x04)++0x03 line.long 0x00 "LNARECR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x80C-0x0C))&0xF80)==0x00) group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x08)++0x03 line.long 0x00 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x04)++0x03 line.long 0x00 "LNBRECR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x84C-0x0C))&0xF80)==0x00) group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x08)++0x03 line.long 0x00 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x04)++0x03 line.long 0x00 "LNCRECR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,Speed Switch Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x88C-0x0C))&0xF80)==0x00) group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x08)++0x03 line.long 0x00 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x04)++0x03 line.long 0x00 "LNDRECR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EA0000+0x8CC-0x0C))&0xF80)==0x00) group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,Test Control/Status Register 3 - Lane C" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" else group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,Receive Equalization Control Register 0 - Lane A" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Receive Equalization Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,Transmit Equalization Control Register 0 - Lane A" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,TTL Control Register 0 - Lane A" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,Receive Equalization Control Register 0 - Lane B" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Receive Equalization Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,Transmit Equalization Control Register 0 - Lane B" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,TTL Control Register 0 - Lane B" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,Receive Equalization Control Register 0 - Lane C" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long 0x894++0x03 line.long 0x00 "LNDRECR1,Receive Equalization Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long 0x898++0x0B line.long 0x00 "LNDTECR0,Transmit Equalization Control Register 0 - Lane D" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,TTL Control Register 0 - Lane D" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" endif tree.end tree "Protocol Control and Status Registers" sif cpuis("LS10?6*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" elif cpuis("LS10?3*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" else group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEX$2 Protocol Control Register 0" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" else group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" else rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1994++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x19A4++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" endif tree.end endian.le width 0x0B tree.end tree "SerDes 2" base ad:0x1EB0000 width 12. endian.be tree "Group/PLL Configuration Control and Status Registers" if (((per.l.be(ad:0x1EB0000)&0x60000000))==0x00) rgroup.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" else group.long 0x0++0x03 line.long 0x00 "PLL1RSTCTL,SerDes PLL1 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "PLL2RSTCTL,SerDes PLL2 Reset Control Register" bitfld.long 0x00 31. " RSTREQ ,PLL reset request" "Not requested,Requested" bitfld.long 0x00 30. " RST_DONE ,PLL reset done from control block state machine" "In progress,Done" bitfld.long 0x00 29. " RST_ERR ,No PLL lock before counter time_out" "No error,Error" newline bitfld.long 0x00 7. " PLLRST_B ,PLL1 reset" "Reset,App mode" bitfld.long 0x00 6. " SDRST_B ,SRDS group reset" "Reset,App mode" bitfld.long 0x00 5. " SDEN ,SerDes enable" "Disabled,Enabled" endif group.long 0x4++0x07 line.long 0x00 "PLL1CR0,SerDes PLL1 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL1CR1,SerDes PLL1 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x24++0x07 line.long 0x00 "PLL2CR0,SerDes PLL2 Control Register 0" bitfld.long 0x00 31. " POFF ,Power down an unused PLL" "On,Off" bitfld.long 0x00 28.--30. " RFCLK_SEL ,Reference clock frequency select" "100 MHz,125 MHz,156.25 MHz,150 MHz,?..." bitfld.long 0x00 27. " RFCLK_EN ,Reference clock observe enable" "Disabled,Enabled" newline rbitfld.long 0x00 23. " PLL_LCK ,Indicates PLL1 has calibrated and locked" "Not locked,Locked" sif cpuis("LS10?6*")||cpuis("LS10?3*") bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,5.15625 GHz,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." else bitfld.long 0x00 16.--19. " FRATE_SEL ,Select frequency of PLL VCO" "5.00 GHz,,,,,,,4.00 GHz,,3.125 GHz,3.00 GHz,?..." bitfld.long 0x00 0.--1. " DLYDIV_SEL ,Select PLLN_ex_dly_clk divider value" "PLLN_ex_dly_clk off,FRATE_SEL/16,?..." endif line.long 0x04 "PLL2CR1,SerDes PLL2 Control Register 1" bitfld.long 0x04 27. " PLLBW_SEL ,Select higher PLL1 bandwidth" "Nominal,PLL" group.long 0x18++0x03 line.long 0x00 "PLL1CR5,SerDes PLL1 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PLL2CR5,SerDes PLL2 Control Register 5" bitfld.long 0x00 31. " SEL_REFCLK_AMP_DIS ,Disables the reference clock amplifier" "No,Yes" bitfld.long 0x00 27. " LEFT_REF_BUF_EN ,Enable for left directed reference clock buffer" "Disabled,Enabled" bitfld.long 0x00 24. " RIGHT_REF_BUF_EN ,Enable for right directed reference clock buffer" "Disabled,Enabled" tree.end tree "General Control and Status Registers" group.long 0x90++0x07 line.long 0x00 "TCALCR,SerDes Transmit Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the transmit calibration" "Reset,App mode" line.long 0x04 "TCALCR1,SerDes Transmit Calibration Control Register 1" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the right" "Disabled,Enabled" bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" group.long 0xA0++0x07 line.long 0x00 "RCALCR,SerDes Receive Calibration Control Register" bitfld.long 0x00 27. " CALRST_B ,Reset the receive calibration" "Reset,App mode" line.long 0x04 "RCALCR1,SerDes Receive Calibration Control Register 1" bitfld.long 0x04 31. " ANA_IN_REFCLK_BUF_EN ,Enable CML analog buffer used to transition SoC reference clock to 10G serdes" "Disabled,Enabled" bitfld.long 0x04 27. " DIG_OUT_REFCLK_EN ,Enable CMOS digital buffered version of selected ref_clk to the left" "Disabled,Enabled" newline bitfld.long 0x04 24. " ANA_OUT_REFCLK_EN ,Enable CML analog buffered version of selected ref_clk to the left" "Disabled,Enabled" rbitfld.long 0x04 0.--1. " BI_REFCTL_OUT ,Output COP DFT/BurnIn/JTAG reference clock controls to wrapper" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "GR0,General Control Register 0 " bitfld.long 0x00 14. " XPAD_SEL ,Describes to SerDes module the value of the power supply being used by the Serdes I/Os" "High xpadvdd,Low xpadvdd" tree.end tree "Protocol Configuration Control and Status Registers" sif cpuis("LS10?3*") rgroup.long 0x100++0x03 line.long 0x00 "LNAPSSR0,Lane A Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x120++0x03 line.long 0x00 "LNBPSSR0,Lane B Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x140++0x03 line.long 0x00 "LNCPSSR0,Lane C Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." rgroup.long 0x160++0x03 line.long 0x00 "LNDPSSR0,Lane D Protocol Select Status Register 0" bitfld.long 0x00 24.--31. " TYPE ,Protocol type" "PCIe,SGMII-1G,SATA,,,,,,,,XFI,?..." bitfld.long 0x00 16.--19. " MAC ,MAC instance" "MAC1,MAC2,MAC3,MAC4,MAC5,MAC6,MAC7,MAC8,MAC9,MAC10,?..." bitfld.long 0x00 8.--10. " PCS ,PCS instance of TYPE within PHY" "PCSa/1,PCSb/2,PCSc/3,PCSd/4,?..." newline bitfld.long 0x00 0.--3. " LANE ,Lane number within PCS" "0,1,2,3,?..." endif sif cpuis("LS10?6*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" elif cpuis("LS10?3*") group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x4 [3:0] on lanes [0:3],x1 on lane 0,x2 [1:0] on lanes [0:1],?..." bitfld.long 0x00 24.--26. " PEXB_CFG ,PEXb configuration" "Disabled,x1 on lane 2,x1 on lane 1?..." bitfld.long 0x00 20.--22. " PEXC_CFG ,PEXc configuration" "Disabled,x1 on lane 3,,x2 [1:0] on lanes [2:3],?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,Enabled on lane 3,?..." else group.long 0x200++0x03 line.long 0x00 "PCCR0,Protocol Configuration Register 0" bitfld.long 0x00 28.--30. " PEXA_CFG ,PEXa configuration" "Disabled,x1 on lane 1,x1 on lane 2,Disabled,Disabled,?..." group.long 0x208++0x03 line.long 0x00 "PCCR2,Protocol Configuration Register 2" bitfld.long 0x00 28.--30. " SATAA_CFG ,SATAa configuration" "Disabled,x1 on lane 2,?..." bitfld.long 0x00 12.--14. " TXCLKA_CFG ,TXCLKa configuration" "Disabled,Enabled on lane 0,Enabled on lane 1,?..." endif sif cpuis("LS10?6*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 1 to GMIIb,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,?..." elif cpuis("LS10?3*") group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to FMan Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 2 to FMan Mac 2,?..." bitfld.long 0x00 23. " SGMIIC_KX ,SGMIId 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 20.--22. " SGMIIC_CFG ,SGMIIc configuration" "Disabled,x1 on lane 3 to FMan Mac 5,?..." newline bitfld.long 0x00 19. " SGMIID_KX ,SGMIIe 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 16.--18. " SGMIID_CFG ,SGMIId configuration" "Disabled,x1 on lane 3 to FMan Mac 6,?..." else group.long 0x220++0x03 line.long 0x00 "PCCR8,Protocol Configuration Register 8" bitfld.long 0x00 31. " SGMIIA_KX ,SGMIIb 1000Base-KX configuration" "SGMII,1000Base-KX" bitfld.long 0x00 28.--30. " SGMIIA_CFG ,SGMIIa configuration" "Disabled,x1 on lane 0 to WRIOP Mac 9,?..." bitfld.long 0x00 27. " SGMIIB_KX ,SGMIIc 1000Base-KX configuration" "SGMII,1000Base-KX" newline bitfld.long 0x00 24.--26. " SGMIIB_CFG ,SGMIIb configuration" "Disabled,x1 on lane 1 to WRIOP Mac 5,?..." endif sif cpuis("LS10?6*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled,?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,?..." elif cpuis("LS10?3*") group.long 0x224++0x03 line.long 0x00 "PCCR9,Protocol Configuration Register 9" bitfld.long 0x00 28.--30. " QSGMIIA_CFG ,QSGMIIa configuration" "Disabled, x1 on Lane 0 connected to FMan MACs 1 2 5 6?..." bitfld.long 0x00 24.--26. " QSGMIIB_CFG ,QSGMIIb configuration" "Disabled,x1 on Lane 1 connected to FMan MACs 1 2 5 6,?..." endif sif cpuis("LS10?6*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,?..." elif cpuis("LS10?3*") group.long 0x22C++0x03 line.long 0x00 "PCCRB,Protocol Configuration Register B" bitfld.long 0x00 28.--30. " XFIA_CFG ,XFIa configuration" "Disabled,x1 on Lane 0 to FMan MAC 9,?..." bitfld.long 0x00 24.--26. " XFIB_CFG ,XFIb configuration" "Disabled,?..." endif sif cpuis("LS10?6*") group.long 0x300++0x03 line.long 0x00 "PEXEQCR,PCIe Equalization Configuration Register" bitfld.long 0x00 6.--11. " FS ,PCI express FS value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " LF ,PCI express LF value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x304++0x03 line.long 0x00 "PEXEQP0CR,PCIe Equalization Preset 0 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x308++0x03 line.long 0x00 "PEXEQP1CR,PCIe Equalization Preset 1 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x30C++0x03 line.long 0x00 "PEXEQP2CR,PCIe Equalization Preset 2 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x310++0x03 line.long 0x00 "PEXEQP3CR,PCIe Equalization Preset 3 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x314++0x03 line.long 0x00 "PEXEQP4CR,PCIe Equalization Preset 4 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x318++0x03 line.long 0x00 "PEXEQP5CR,PCIe Equalization Preset 5 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x31C++0x03 line.long 0x00 "PEXEQP6CR,PCIe Equalization Preset 6 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x320++0x03 line.long 0x00 "PEXEQP7CR,PCIe Equalization Preset 7 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x324++0x03 line.long 0x00 "PEXEQP8CR,PCIe Equalization Preset 8 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x328++0x03 line.long 0x00 "PEXEQP9CR,PCIe Equalization Preset 9 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." group.long 0x32C++0x03 line.long 0x00 "PEXEQP10CR,PCIe Equalization Preset 10 Register" bitfld.long 0x00 12.--17. " CP1 ,C(+1) preset value" "12,8,10,6,0,0,0,9,6,0,10,?..." bitfld.long 0x00 0.--5. " CM1 ,C(-1) preset value" "0,0,0,0,0,5,6,5,6,8,6,?..." endif tree.end tree "Per-lane SerDes Control/Status Registers" sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x03 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x03 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x880++0x03 line.long 0x00 "LNCGCR0,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane C to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane C" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane C" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane C" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane C" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane C" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x880+0x04)++0x03 line.long 0x00 "LNCGCR1,General Control Register 0 - Lane C" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x8C0++0x03 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane D to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane D" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane D" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane D" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane D" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane D" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x8C0+0x04)++0x03 line.long 0x00 "LNDGCR1,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" else if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x800++0x07 line.long 0x00 "LNAGCR0,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane A to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane A" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane A" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane A" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane A" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane A" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x800+0x04)++0x03 line.long 0x00 "LNAGCR1,General Control Register 0 - Lane A" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" if (((per.l.be(ad:0x1EB0000)&0x80000000))==0x00) group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" rbitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" rbitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline rbitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" rbitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." else group.long 0x840++0x07 line.long 0x00 "LNBGCR0,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane B to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane B" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane B" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane B" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane B" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane B" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." endif group.long (0x840+0x04)++0x03 line.long 0x00 "LNBGCR1,General Control Register 0 - Lane B" bitfld.long 0x00 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x00 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x00 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x00 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x00 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x00 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x00 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x00 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x00 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x00 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" group.long 0x8C0++0x07 line.long 0x00 "LNDGCR0,General Control Register 0 - Lane D" bitfld.long 0x00 31. " RPLL_LES ,Directs the RX portion of lane $2 to use the corresponding PLL" "Use PLL2,Use PLL1" bitfld.long 0x00 28.--29. " RRAT_SEL ,Receiver speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 27. " TPLL_LES ,Used to direct the TX portion of lane to use the corresponding PLL" "Use PLL2,Use PLL1" newline bitfld.long 0x00 24.--25. " TRAT_SEL ,Transmitter speed selection for lane $2" "FRATE_SEL,FRATE_SEL/2,FRATE_SEL/4,FRATE_SEL*2" bitfld.long 0x00 22. " RRST_B ,Resets receiver for lane $2" "Reset,App mode" bitfld.long 0x00 21. " TRST_B ,Resets transmitter for lane $2" "Reset,App mode" newline bitfld.long 0x00 20. " RX_PD ,Lane powerdown for receiver on lane $2" "Active,Powered down" bitfld.long 0x00 19. " TX_PD ,Lane powerdown for transmitter on lane $2" "Active,Powered down" bitfld.long 0x00 18. " IF20BIT_EN ,20-bit interface enable" "10-bit,20-bit" newline bitfld.long 0x00 16. " FIRST_LANE ,Indicates this lane is the first (lane 0) of a group of lanes" "Not first,First" bitfld.long 0x00 7.--11. " PROTS ,Lane protocol select" "PCI EXP,SGMII-1G,SATA,,,,,,,,XFI/10GBase-KR,?..." line.long 0x04 "LNDGCR1,General Control Register 1 - Lane D" bitfld.long 0x04 31. " RDAT_INV ,Invert Rx data" "Not inverted,Inverted" bitfld.long 0x04 30. " TDAT_INV ,Invert Tx data" "Not inverted,Inverted" bitfld.long 0x04 26. " OPAD_CTL ,TX output pad control signal for common mode" "Transmitter enabled,Common mode" newline bitfld.long 0x04 20.--22. " REIDL_TH ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 18.--19. " REIDL_EX_SEL ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 16.--17. " REIDL_ET_SEL ,Exit idle filter select MSB" "0,1,2,3" newline bitfld.long 0x04 15. " REIDL_EX_MSB ,Exit idle filter select MSB" "0,1" bitfld.long 0x04 14. " REIDL_ET_MSB ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 13. " REQ_CTL_SNP ,Initiate snapshot of RX equalization control Gaink2/Gaink3 and offset registers" "Not initiated,Initiated" newline bitfld.long 0x04 12. " REQ_CDR_SNP ,Initiate snapshot of RX clock/data recovery (CDR) registers" "Not initiated,Initiated" bitfld.long 0x04 7. " TRSTDIR ,Multi-lane protocol Tx clock synchronization control" "0,1" bitfld.long 0x04 6. " REQ_BIN_SNP ,Initiate snapshot of RX equalization control binning registers" "0,1" newline bitfld.long 0x04 4.--5. " ISLEW_RCTL ,Slew control for quadrature generator" "0,1,2,3" bitfld.long 0x04 0.--1. " OSLEW_RCTL ,Phase interpolator output clock edge rate control" "0,1,2,3" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") if (((per.l.be(ad:0x1EB0000+0x80C-0x0C))&0xF80)==0x00) group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x80C++0x03 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x04)++0x03 line.long 0x00 "LNARECR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EB0000+0x80C-0x0C))&0xF80)==0x00) group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x80C+0x0C)++0x07 line.long 0x00 "LNATECR0,SerDes Lane A Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,SerDes Lane A Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x80C+0x08)++0x03 line.long 0x00 "LNATTLCR0,A Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EB0000+0x84C-0x0C))&0xF80)==0x00) group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x84C++0x03 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x04)++0x03 line.long 0x00 "LNBRECR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EB0000+0x84C-0x0C))&0xF80)==0x00) group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x84C+0x0C)++0x07 line.long 0x00 "LNBTECR0,SerDes Lane B Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,SerDes Lane B Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x84C+0x08)++0x03 line.long 0x00 "LNBTTLCR0,B Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EB0000+0x88C-0x0C))&0xF80)==0x00) group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x88C++0x03 line.long 0x00 "LNCSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x04)++0x03 line.long 0x00 "LNCRECR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x88C+0x08)++0x03 line.long 0x00 "LNCRECR1,Speed Switch Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EB0000+0x88C-0x0C))&0xF80)==0x00) group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x88C+0x0C)++0x07 line.long 0x00 "LNCTECR0,SerDes Lane C Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNCSSCR1,SerDes Lane C Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x88C+0x08)++0x03 line.long 0x00 "LNCTTLCR0,C Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.l.be(ad:0x1EB0000+0x8CC-0x0C))&0xF80)==0x00) group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" rbitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long 0x8CC++0x03 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x04)++0x03 line.long 0x00 "LNDRECR0,Speed Switch Control Register 0 - Lane D" bitfld.long 0x00 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x00 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x00 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x00 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x00 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x00 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDRECR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" if (((per.l.be(ad:0x1EB0000+0x8CC-0x0C))&0xF80)==0x00) group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" rbitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." rbitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" rbitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" rbitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" rbitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.long (0x8CC+0x0C)++0x07 line.long 0x00 "LNDTECR0,SerDes Lane D Transmit Equalization Control Register 0" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,SerDes Lane D Speed Switch Control Register 1" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long (0x8CC+0x08)++0x03 line.long 0x00 "LNDTTLCR0,D Transition Tracking Loop Control Register 0" bitfld.long 0x00 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8BC++0x03 line.long 0x00 "LNCTCSR3,Test Control/Status Register 3 - Lane C" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" else group.long 0x80C++0x07 line.long 0x00 "LNASSCR0,Speed Switch Control Register 0 - Lane A" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNARECR0,Receive Equalization Control Register 0 - Lane A" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x80C+0x08)++0x03 line.long 0x00 "LNARECR1,Receive Equalization Control Register 1 - Lane A" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x80C+0x0C)++0x0B line.long 0x00 "LNATECR0,Transmit Equalization Control Register 0 - Lane A" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNASSCR1,Speed Switch Control Register 1 - Lane A" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNATTLCR0,TTL Control Register 0 - Lane A" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x84C++0x07 line.long 0x00 "LNBSSCR0,Speed Switch Control Register 0 - Lane B" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBRECR0,Receive Equalization Control Register 0 - Lane B" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long (0x84C+0x08)++0x03 line.long 0x00 "LNBRECR1,Receive Equalization Control Register 1 - Lane B" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long (0x84C+0x0C)++0x0B line.long 0x00 "LNBTECR0,Transmit Equalization Control Register 0 - Lane B" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNBSSCR1,Speed Switch Control Register 1 - Lane B" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNBTTLCR0,TTL Control Register 0 - Lane B" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x88C++0x07 line.long 0x00 "LNDSSCR0,Speed Switch Control Register 0 - Lane C" bitfld.long 0x00 29.--31. " REIDL_TH_0 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27.--28. " REIDL_EX_SEL_0 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x00 25.--26. " REIDL_ET_SEL_0 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x00 24. " REIDL_EX_MSB_0 ,Exit idle filter select MSB" "0,1" bitfld.long 0x00 23. " REIDL_ET_MSB_0 ,Enter idle filter select MSB" "0,1" bitfld.long 0x00 18. " RXEQ_BST_0 ,Rx equalization boost" "No boost,Boost" newline bitfld.long 0x00 16.--17. " BASE_WAND_0 ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" bitfld.long 0x00 15. " OSETOVD6_0 ,Binary decode of lane adaptive equalization offset initialization or override value" "0,1" bitfld.long 0x00 13.--14. " TEQ_TYPE_0 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." newline bitfld.long 0x00 12. " SGN_PREQ_0 ,Precursor sign" "Negative,Positive" bitfld.long 0x00 11. " SGN_POST1Q_0 ,Post1q sign" "Negative,Positive" bitfld.long 0x00 6.--10. " RATIO_PST1Q_0 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. " AMP_RED_0 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDRECR0,Receive Equalization Control Register 0 - Lane C" bitfld.long 0x04 28. " RXEQ_BST ,Rx equalization boost" "0,1" bitfld.long 0x04 24.--27. " GK2OVD ,Binary decode of lane adaptive equalization gaink2 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " GK3OVD ,Binary decode of lane adaptive equalization gaink3 initialization or override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15. " GK2OVD_EN ,Controls source of rx equalization gaink2 setting" "Use rxeq,Fix gaink2" bitfld.long 0x04 14. " GK3OVD_EN ,Controls source of rx equalization gaink3 setting" "Use rxeq,Fix gaink3" bitfld.long 0x04 13. " OSETOVD_EN ,Controls source of rx equalization offset setting" "On release,Fixed" newline bitfld.long 0x04 10.--11. " BASE_WAND ,Baseline wander control select" "Off(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset as GainBLW override" hexmask.long.byte 0x04 0.--6. 0x01 " OSETOVD ,Binary decode of lane adaptive equalization offset" rgroup.long 0x894++0x03 line.long 0x00 "LNDRECR1,Receive Equalization Control Register 1 - Lane C" bitfld.long 0x00 2. " EQ_BSNP_DN ,Snapshot of RX EQ bin complete" "Not completed,Completed" bitfld.long 0x00 1. " EQ_CSNP_DN ,Snapshot of RX EQ ctrl complete" "Not completed,Completed" bitfld.long 0x00 0. " CDR_SNP_DN ,Snapshot of CDR loop complete" "Not completed,Completed" group.long 0x898++0x0B line.long 0x00 "LNDTECR0,Transmit Equalization Control Register 0 - Lane D" bitfld.long 0x00 28.--29. " TEQ_TYPE ,Selects amount/type of transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x00 26. " SGN_PREQ ,Precursor sign" "Negative,Positive" bitfld.long 0x00 22.--25. " RATIO_PREQ ,Ratio of full swing transition bit to pre-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 21. " SGN_POST1Q ,Post q sign" "Negative,Positive" bitfld.long 0x00 16.--20. " RATIO_PST1Q ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " ADPT_EQ ,Transmitter adjustments for 8G/10G" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " AMP_RED ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "LNDSSCR1,Speed Switch Control Register 1 - Lane D" bitfld.long 0x04 29.--31. " REIDL_TH_1 ,Receiver electrical idle detection threshold control" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27.--28. " REIDL_EX_SEL_1 ,Exit electrical idle filter select" "0,1,2,3" bitfld.long 0x04 25.--26. " REIDL_ET_SEL_1 ,Enter idle filter select" "0,1,2,3" newline bitfld.long 0x04 24. " REIDL_EX_MSB_1 ,Exit idle filter select MSB see REIDL_EX_SEL_1 for settings" "0,1" bitfld.long 0x04 23. " REIDL_ET_MSB_1 ,Enter idle filter select MSB" "0,1" bitfld.long 0x04 21.--22. " ISLEW_RCTL_1 ,Slew control for quadrature generator" "0,1,2,3" newline bitfld.long 0x04 18. " RXEQ_BST_1 ,Rx equalization boost" "0,1" bitfld.long 0x04 16.--17. " BASE_WAND_1 ,Baseline wander control select" "OFF(8b10b data),Default BinBLW threshold,Alternate BinBLW sign,Rx EQ offset" bitfld.long 0x04 15. " OSETOVD6_1 ,Binary decode of lane adaptive equalization offset initialization or override value" "Initialize,Override" newline bitfld.long 0x04 13.--14. " TEQ_TYPE_1 ,Lane transmit equalization" "No equalization,2 levels,3 levels,?..." bitfld.long 0x04 12. " SGN_PREQ_1 ,Precursor sign" "Negative,Positive" bitfld.long 0x04 11. " SGN_POST1Q_1 ,Post1q sign" "Negative,Positive" newline bitfld.long 0x04 6.--10. " RATIO_PST1Q_1 ,Ratio of full swing transition bit to first post-cursor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--5. " AMP_RED_1 ,Overall TX amplitude reduction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "LNDTTLCR0,TTL Control Register 0 - Lane D" bitfld.long 0x08 24.--29. " FLT_SEL ,Selects the gain Kfr/Kph and TTL edge counting window widths in the CDR loop for the lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x83C++0x03 line.long 0x00 "LNATCSR3,Test Control/Status Register 3 - Lane A" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x87C++0x03 line.long 0x00 "LNBTCSR3,Test Control/Status Register 3 - Lane B" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" group.long 0x8FC++0x03 line.long 0x00 "LNDTCSR3,Test Control/Status Register 3 - Lane D" bitfld.long 0x00 28.--29. " LPBK_EN ,Loopback data from TX to RX" "App mode,Loopback mode,?..." rbitfld.long 0x00 27. " CDR_LCK ,When asserted CDR loop has acquired a valid Rx clock" "Not acquired,Acquired" endif tree.end tree "Protocol Control and Status Registers" sif cpuis("LS10?6*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" bitfld.long 0x00 27. " RD_SW ,Reduced swing operation for 8 GT/s" "Full,Reduced" elif cpuis("LS10?3*") group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEXA Protocol Control Register 0" group.long 0x1040++0x03 line.long 0x00 "PEXBCR0,PEXB Protocol Control Register 0" group.long 0x1080++0x03 line.long 0x00 "PEXCCR0,PEXC Protocol Control Register 0" else group.long 0x1000++0x03 line.long 0x00 "PEXACR0,PEX$2 Protocol Control Register 0" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1824++0x03 line.long 0x00 "SGMIICCR1,SGMIIC Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1834++0x03 line.long 0x00 "SGMIIDCR1,SGMIID Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" else group.long 0x1804++0x03 line.long 0x00 "SGMIIACR1,SGMIIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" group.long 0x1814++0x03 line.long 0x00 "SGMIIBCR1,SGMIIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 11. " SGPCS_EN ,SGMII PCS enable" "Disabled,Enabled" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x182C++0x03 line.long 0x00 "SGMIICCR3,SGMIIC Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x183C++0x03 line.long 0x00 "SGMIIDCR3,SGMIID Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" else rgroup.long 0x180C++0x03 line.long 0x00 "SGMIIACR3,SGMIIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" rgroup.long 0x181C++0x03 line.long 0x00 "SGMIIBCR3,SGMIIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,Error on LPI wake" "No error,Error" endif sif cpuis("LS10?6*")||cpuis("LS10?3*") group.long 0x1884++0x03 line.long 0x00 "QSGMIIACR1,QSGMIIA Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x1894++0x03 line.long 0x00 "QSGMIIBCR1,QSGMIIB Protocol Control Register 1" bitfld.long 0x00 29.--31. " MDEV_PORT ,Device port ID" "0,1,2,3,4,5,6,7" group.long 0x188C++0x03 line.long 0x00 "QSGMIIACR3,QSGMIIA Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x189C++0x03 line.long 0x00 "QSGMIIBCR3,QSGMIIB Protocol Control Register 3" bitfld.long 0x00 19. " WK_ERR0 ,Port 0 error on LPI wake" "No error,Error" bitfld.long 0x00 18. " WK_ERR1 ,Port 1 error on LPI wake" "No error,Error" bitfld.long 0x00 17. " WK_ERR2 ,Port 2 error on LPI wake" "No error,Error" newline bitfld.long 0x00 16. " WK_ERR3 ,Port 3 error on LPI wake" "No error,Error" bitfld.long 0x00 15. " RX_QU0 ,Port 0 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 14. " RX_QU1 ,Port 1 Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 13. " RX_QU2 ,Port 2 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 12. " RX_QU3 ,Port 3 Rx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 11. " RX_ACT0 ,Port 0 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 10. " RX_ACT1 ,Port 1 Rx active LPI state" "Not active,Active" bitfld.long 0x00 9. " RX_ACT2 ,Port 2 Rx active LPI state" "Not active,Active" bitfld.long 0x00 8. " RX_ACT3 ,Port 3 Rx active LPI state" "Not active,Active" newline bitfld.long 0x00 7. " TX_QU0 ,Port 0 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 6. " TX_QU1 ,Port 1 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 5. " TX_QU2 ,Port 2 Tx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 4. " TX_QU3 ,Port 3 Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 3. " TX_ACT0 ,Port 0 Tx active LPI state" "Not active,Active" bitfld.long 0x00 2. " TX_ACT1 ,Port 1 Tx active LPI state" "Not active,Active" newline bitfld.long 0x00 1. " TX_ACT2 ,Port 2 Tx active LPI state" "Not active,Active" bitfld.long 0x00 0. " TX_ACT3 ,Port 3 Tx active LPI state" "Not active,Active" group.long 0x1984++0x03 line.long 0x00 "XFIACR1,XFIA Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1994++0x03 line.long 0x00 "XFIBCR1,XFIB Protocol Control Register 1" bitfld.long 0x00 27.--31. " MDEV_PORT ,MDIO bus port address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1994++0x03 line.long 0x00 "XFIACR3,XFIA Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" rgroup.long 0x19A4++0x03 line.long 0x00 "XFIBCR3,XFIB Protocol Control Register 3" bitfld.long 0x00 31. " TX_QU ,Tx quiet LPI state" "Not quiet,Quiet" bitfld.long 0x00 30. " TX_ACT ,Tx active LPI state" "Not active,Active" bitfld.long 0x00 27. " RX_QU ,Rx quiet LPI state" "Not quiet,Quiet" newline bitfld.long 0x00 26. " RX_ACT ,Rx active LPI state" "Not active,Active" bitfld.long 0x00 23. " WK_ERR ,LPI wake error" "No error,Error" bitfld.long 0x00 22. " TX_ALRT ,LPI Tx alert" "No alert,Alert" endif tree.end endian.le width 0x0B tree.end endif tree.end ; sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*")||cpuis("LS10?3*")||cpuis("LS10?6*") ; tree "MDIO" ; %include ls10xx/mdio.ph 19848B8008 18048B8008 18848B8008 ; tree.end ; else ; tree "MDIO" ; %include ls10xx/mdio_big.ph 19848B8008 18048B8008 18848B8008 ; tree.end ; endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "SPI (Serial Peripheral Interface)" base ad:0x2100000 width 13. if (((per.l(ad:0x2100000+0x2C))&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" ",Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." newline rbitfld.long 0x00 27. " FRZ ,Enables transfers to be stopped on the next frame boundary when the device enters debug mode" "Not halted,Halted" rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Ignored,Overwritten" newline rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 14. " MDIS ,Allows clock to be stopped to non-memory mapped logic in module" "Not allowed,Allowed" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" rbitfld.long 0x00 11. " CLR_TXF ,Flushes the TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Flushes the RX FIFO" "No effect,Clear" newline rbitfld.long 0x00 3. " XSPI ,Extended SPI mode" "Normal,Extended" rbitfld.long 0x00 2. " FCPCS ,Fast continuous PCS mode" "Normal/Slow,Fast" newline rbitfld.long 0x00 1. " PES ,Parity error stop" "Continued,Stopped" bitfld.long 0x00 0. " HALT ,Start and stop frame transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" ",Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." newline bitfld.long 0x00 27. " FRZ ,Enables transfers to be stopped on the next frame boundary when the device enters debug mode" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 14. " MDIS ,Allows clock to be stopped to non-memory mapped logic in module" "Not allowed,Allowed" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Flushes the TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Flushes the RX FIFO" "No effect,Clear" newline bitfld.long 0x00 3. " XSPI ,Extended SPI mode" "Normal,Extended" bitfld.long 0x00 2. " FCPCS ,Fast continuous PCS mode" "Normal/Slow,Fast" newline bitfld.long 0x00 1. " PES ,Parity error stop" "Continued,Stopped" bitfld.long 0x00 0. " HALT ,Start and stop frame transfers" "Started,Stopped" endif if (((per.l(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " TCNT ,SPI transfer counter" endif if (((per.l(ad:0x2100000+0x00))&0x80000000)==0x80000000) if (((per.l(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x0C++0x07 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x04 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x04 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x04 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x04 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x04 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x04 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x04 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x04 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x04 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x04 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x07 line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x04 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x04 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x04 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x04 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x04 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x04 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x04 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x04 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x04 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x04 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else if (((per.l(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Active low,Active high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow." newline bitfld.long 0x00 24. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 23. " PP ,Parity polarity" "Even,Odd" else hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register" endif endif if (((per.l(ad:0x2100000+0x00))&0x4000)==0x4000) rgroup.long 0x2C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 31. " TCF ,Transfer complete flag" "Not complete,Complete" bitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF ,End of queue flag" "Not set,Set" newline bitfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" bitfld.long 0x00 24. " BSYF ,Busy flag" "Idle,Busy" bitfld.long 0x00 23. " CMDTCF ,Command transfer complete flag" "Not completed,Completed" newline bitfld.long 0x00 21. " SPEF ,SPI parity error flag" "No error,Error" bitfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" bitfld.long 0x00 18. " TFIWF ,Transmit FIFO invalid write flag" "Not invalid,Invalid" newline bitfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" bitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,?..." bitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,?..." newline bitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,?..." bitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,?..." else group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not complete,Complete" eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not set,Set" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" rbitfld.long 0x00 24. " BSYF ,Busy flag" "Idle,Busy" eventfld.long 0x00 23. " CMDTCF ,Command transfer complete flag" "Not completed,Completed" newline eventfld.long 0x00 21. " SPEF ,SPI parity error flag" "No error,Error" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 18. " TFIWF ,Transmit FIFO invalid write flag" "Not invalid,Invalid" newline rbitfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,?..." rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,?..." newline rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,?..." rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,?..." endif if (((per.l(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 30. " CMDFFF_RE ,Command FIFO fill flag request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" newline bitfld.long 0x00 23. " CMDTCF_RE ,Command transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPEF_RE ,SPI parity error request enable" "Disabled,Enabled" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " TFIWF_RE ,Transmit FIFO invalid write request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RDFD_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" newline bitfld.long 0x00 15. " CMDFFF_DIRS ,Command FIFO fill DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 30. " CMDFFF_RE ,Command FIFO fill flag request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" newline bitfld.long 0x00 23. " CMDTCF_RE ,Command transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 21. " SPEF_RE ,SPI parity error request enable" "Disabled,Enabled" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " TFIWF_RE ,Transmit FIFO invalid write request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RDFD_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" newline bitfld.long 0x00 15. " CMDFFF_DIRS ,Command FIFO fill DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l(ad:0x2100000+0x00))&0x80000000)==0x80000000) if (((per.l(ad:0x2100000+0x00))&0x04)==0x04) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not last,Last" newline bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not clear,Clear" bitfld.long 0x00 25. " MASC ,Mask T_asc delay in the current frame" "Not masked,Masked" bitfld.long 0x00 24. " MCSC ,Mask T_csc delay in the next frame" "Not masked,Masked" newline bitfld.long 0x00 21. " PCS[5] ,PCS 5 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 20. " [4] ,PCS 4 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 19. " [3] ,PCS 3 asserted for the transfer" "Negated,Asserted" newline bitfld.long 0x00 18. " [2] ,PCS 2 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 17. " [1] ,PCS 1 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 16. " [0] ,PCS 0 asserted for the transfer" "Negated,Asserted" newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not last,Last" newline bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not clear,Clear" bitfld.long 0x00 25. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 24. " PP ,Parity polarity" "Even,Odd" newline bitfld.long 0x00 21. " PCS[5] ,PCS 5 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 20. " [4] ,PCS 4 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 19. " [3] ,PCS 3 asserted for the transfer" "Negated,Asserted" newline bitfld.long 0x00 18. " [2] ,PCS 2 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 17. " [1] ,PCS 1 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 16. " [0] ,PCS 0 asserted for the transfer" "Negated,Asserted" newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else hgroup.long 0x34++0x03 hide.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" endif hgroup.long 0x38++0x03 hide.long 0x00 "POPR,POP RX FIFO Register" in if (((per.l.be(ad:0x2100000+0x00))&0x80000008)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,Transmit FIFO Register" hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,Transmit FIFO Register" hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,Transmit FIFO Register" hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,Transmit FIFO Register" endif rgroup.long 0x7C++0x0F line.long 0x00 "RXFR0,Receive FIFO Register 0" line.long 0x04 "RXFR1,Receive FIFO Register 1" line.long 0x08 "RXFR2,Receive FIFO Register 2" line.long 0x0C "RXFR3,Receive FIFO Register 3" if (((per.l.be(ad:0x2100000+0x00))&0x08)==0x00) group.long 0x11C++0x03 line.long 0x00 "CTARE0,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" group.long 0x120++0x03 line.long 0x00 "CTARE1,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" else hgroup.long 0x11C++0x03 hide.long 0x00 "CTARE0,Clock And Transfer Attributes Register Extended" hgroup.long 0x120++0x03 hide.long 0x00 "CTARE1,Clock And Transfer Attributes Register Extended" endif rgroup.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" bitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endian.le width 0x0B tree.end else tree "SPI (Serial Peripheral Interface)" base ad:0x2100000 width 13. endian.be if (((per.l.be(ad:0x2100000+0x2C))&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" ",Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." newline rbitfld.long 0x00 25. " PCSEE ,Peripheral chip select strobe enable" "CS 5,PCS Strobe" rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Ignored,Overwritten" rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" newline rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Allows clock to be stopped to non-memory mapped logic in module" "Not allowed,Allowed" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Flushes the TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Flushes the RX FIFO" "No effect,Clear" rbitfld.long 0x00 3. " XSPI ,Extended SPI mode" "Normal,Extended" sif !cpuis("LS1012*") newline rbitfld.long 0x00 2. " FCPCS ,Fast continuous PCS mode" "Normal/Slow,Fast" endif newline rbitfld.long 0x00 1. " PES ,Parity error stop" "Continued,Stopped" bitfld.long 0x00 0. " HALT ,Start and stop frame transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" ",Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,SPI configuration" "SPI,?..." newline bitfld.long 0x00 25. " PCSEE ,Peripheral chip select strobe enable" "CS 5,PCS Strobe" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Ignored,Overwritten" bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" newline bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " MDIS ,Allows clock to be stopped to non-memory mapped logic in module" "Not allowed,Allowed" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Flushes the TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Flushes the RX FIFO" "No effect,Clear" bitfld.long 0x00 3. " XSPI ,Extended SPI mode" "Normal,Extended" sif !cpuis("LS1012*") newline bitfld.long 0x00 2. " FCPCS ,Fast continuous PCS mode" "Normal/Slow,Fast" endif newline bitfld.long 0x00 1. " PES ,Parity error stop" "Continued,Stopped" bitfld.long 0x00 0. " HALT ,Start and stop frame transfers" "Started,Stopped" endif if (((per.l.be(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " TCNT ,SPI transfer counter" endif if (((per.l.be(ad:0x2100000+0x00))&0x80000000)==0x80000000) if (((per.l.be(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x00++0x0F line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x04 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x04 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x04 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x04 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x04 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x04 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x04 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x04 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x04 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x04 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x08 "CTAR2,Clock And Transfer Attributes Register 2" bitfld.long 0x08 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x08 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x08 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x08 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x08 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x08 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x08 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x08 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x08 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x08 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x08 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x0C "CTAR3,Clock And Transfer Attributes Register 3" bitfld.long 0x0C 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x0C 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0C 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x0C 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x0C 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x0C 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x0C 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x0C 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x0C 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x0C 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x0C 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x0F line.long 0x00 "CTAR0,Clock And Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x04 "CTAR1,Clock And Transfer Attributes Register 1" bitfld.long 0x04 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x04 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x04 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x04 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x04 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x04 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x04 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x04 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x04 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x04 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x04 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x08 "CTAR2,Clock And Transfer Attributes Register 2" bitfld.long 0x08 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x08 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x08 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x08 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x08 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x08 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x08 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x08 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x08 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x08 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x08 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" line.long 0x0C "CTAR3,Clock And Transfer Attributes Register 3" bitfld.long 0x0C 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x0C 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0C 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" newline bitfld.long 0x0C 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow" bitfld.long 0x0C 24. " LSBFE ,LSB first" "MSB first,LSB first" bitfld.long 0x0C 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" newline bitfld.long 0x0C 20.--21. " PASC ,After SCK delay prescaler" "1,3,5,7" bitfld.long 0x0C 18.--19. " PDT ,Delay after transfer prescaler" "1,3,5,7" bitfld.long 0x0C 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" newline bitfld.long 0x0C 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x0C 8.--11. " ASC ,After SCK delay scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. " DT ,Delay after transfer scaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" endif else if (((per.l.be(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (in Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Active low,Active high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Capt-lead. Chng-follow.,Chng-lead. Capt-follow." newline sif cpuis("LS1012*")||cpuis("LS10?6*") bitfld.long 0x00 24. " LSBFE ,LSB first" "MSB first,LSB first" newline else bitfld.long 0x00 24. " PE ,Parity enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " PP ,Parity polarity" "Even,Odd" endif else hgroup.long 0x0C++0x03 hide.long 0x00 "CTAR0_SLAVE,Clock And Transfer Attributes Register (in Slave Mode)" endif endif if (((per.l.be(ad:0x2100000+0x00))&0x4000)==0x4000) rgroup.long 0x2C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 31. " TCF ,Transfer complete flag" "Not complete,Complete" bitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF ,End of queue flag" "Not set,Set" newline bitfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" bitfld.long 0x00 24. " BSYF ,Busy flag" "Idle,Busy" bitfld.long 0x00 23. " CMDTCF ,Command transfer complete flag" "Not completed,Completed" newline bitfld.long 0x00 21. " SPEF ,SPI parity error flag" "No error,Error" bitfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" bitfld.long 0x00 18. " TFIWF ,Transmit FIFO invalid write flag" "Not invalid,Invalid" newline bitfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" bitfld.long 0x00 16. " CMDFFF ,Command FIFO fill flag" "Full,Not full" bitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,?..." newline bitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,?..." bitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,?..." bitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,?..." else group.long 0x2C++0x03 line.long 0x00 "SR,Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not complete,Complete" rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not set,Set" newline eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" rbitfld.long 0x00 24. " BSYF ,Busy flag" "Idle,Busy" eventfld.long 0x00 23. " CMDTCF ,Command transfer complete flag" "Not completed,Completed" newline eventfld.long 0x00 21. " SPEF ,SPI parity error flag" "No error,Error" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" eventfld.long 0x00 18. " TFIWF ,Transmit FIFO invalid write flag" "Not invalid,Invalid" newline rbitfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" eventfld.long 0x00 16. " CMDFFF ,Command FIFO fill flag" "Full,Not full" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,?..." newline rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,?..." rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,?..." rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,?..." endif if (((per.l.be(ad:0x2100000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 30. " CMDFFF_RE ,Command FIFO fill flag request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 23. " CMDTCF_RE ,Command transmission complete request enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " SPEF_RE ,SPI parity error request enable" "Disabled,Enabled" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 18. " TFIWF_RE ,Transmit FIFO invalid write request enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RDFD_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 15. " CMDFFF_DIRS ,Command FIFO fill DMA or interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DMA/Interrupt Request Select And Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 30. " CMDFFF_RE ,Command FIFO fill flag request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,Finished request enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 23. " CMDTCF_RE ,Command transmission complete request enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " SPEF_RE ,SPI parity error request enable" "Disabled,Enabled" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 18. " TFIWF_RE ,Transmit FIFO invalid write request enable" "Disabled,Enabled" newline bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" bitfld.long 0x00 16. " RDFD_DIRS ,Receive FIFO drain DMA or interrupt request select" "Interrupt,DMA" bitfld.long 0x00 15. " CMDFFF_DIRS ,Command FIFO fill DMA or interrupt request select" "Interrupt,DMA" endif if (((per.l.be(ad:0x2100000+0x00))&0x80000000)==0x80000000) if (((per.l.be(ad:0x2100000+0x00))&0x04)==0x04) group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,CTAR2,CTAR3,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not last,Last" newline bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not clear,Clear" bitfld.long 0x00 25. " MASC ,Mask T_asc delay in the current frame" "Not masked,Masked" bitfld.long 0x00 24. " MCSC ,Mask T_csc delay in the next frame" "Not masked,Masked" newline bitfld.long 0x00 21. " PCS[5] ,PCS 5 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 20. " [4] ,PCS 4 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 19. " [3] ,PCS 3 asserted for the transfer" "Negated,Asserted" newline bitfld.long 0x00 18. " [2] ,PCS 2 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 17. " [1] ,PCS 1 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 16. " [0] ,PCS 0 asserted for the transfer" "Negated,Asserted" newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else group.long 0x34++0x03 line.long 0x00 "PUSHR,PUSH TX FIFO Register In Master Mode" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,CTAR2,CTAR3,?..." bitfld.long 0x00 27. " EOQ ,End of queue" "Not last,Last" newline bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "Not clear,Clear" bitfld.long 0x00 25. " PE ,Parity enable" "Disabled,Enabled" bitfld.long 0x00 24. " PP ,Parity polarity" "Even,Odd" newline bitfld.long 0x00 21. " PCS[5] ,PCS 5 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 20. " [4] ,PCS 4 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 19. " [3] ,PCS 3 asserted for the transfer" "Negated,Asserted" newline bitfld.long 0x00 18. " [2] ,PCS 2 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 17. " [1] ,PCS 1 asserted for the transfer" "Negated,Asserted" bitfld.long 0x00 16. " [0] ,PCS 0 asserted for the transfer" "Negated,Asserted" newline hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif else hgroup.long 0x34++0x03 hide.long 0x00 "PUSHR_SLAVE,PUSH TX FIFO Register In Slave Mode" endif hgroup.long 0x38++0x03 hide.long 0x00 "POPR,POP RX FIFO Register" in if (((per.l.be(ad:0x2100000+0x00))&0x80000008)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x4C++0x03 line.long 0x00 "TXFR4,Transmit FIFO Register 4" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x50++0x03 line.long 0x00 "TXFR5,Transmit FIFO Register 5" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x54++0x03 line.long 0x00 "TXFR6,Transmit FIFO Register 6" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x58++0x03 line.long 0x00 "TXFR7,Transmit FIFO Register 7" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x5C++0x03 line.long 0x00 "TXFR8,Transmit FIFO Register 8" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x60++0x03 line.long 0x00 "TXFR9,Transmit FIFO Register 9" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x64++0x03 line.long 0x00 "TXFR10,Transmit FIFO Register 10" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x68++0x03 line.long 0x00 "TXFR11,Transmit FIFO Register 11" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x6C++0x03 line.long 0x00 "TXFR12,Transmit FIFO Register 12" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x70++0x03 line.long 0x00 "TXFR13,Transmit FIFO Register 13" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x74++0x03 line.long 0x00 "TXFR14,Transmit FIFO Register 14" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x78++0x03 line.long 0x00 "TXFR15,Transmit FIFO Register 15" hexmask.long.word 0x00 16.--31. 1. " TXCMD_TXDATA ,Transmit command or transmit data" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,Transmit FIFO Register" hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,Transmit FIFO Register" hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,Transmit FIFO Register" hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,Transmit FIFO Register" hgroup.long 0x4C++0x03 hide.long 0x00 "TXFR4,Transmit FIFO Register" hgroup.long 0x50++0x03 hide.long 0x00 "TXFR5,Transmit FIFO Register" hgroup.long 0x54++0x03 hide.long 0x00 "TXFR6,Transmit FIFO Register" hgroup.long 0x58++0x03 hide.long 0x00 "TXFR7,Transmit FIFO Register" hgroup.long 0x5C++0x03 hide.long 0x00 "TXFR8,Transmit FIFO Register" hgroup.long 0x60++0x03 hide.long 0x00 "TXFR9,Transmit FIFO Register" hgroup.long 0x64++0x03 hide.long 0x00 "TXFR10,Transmit FIFO Register" hgroup.long 0x68++0x03 hide.long 0x00 "TXFR11,Transmit FIFO Register" hgroup.long 0x6C++0x03 hide.long 0x00 "TXFR12,Transmit FIFO Register" hgroup.long 0x70++0x03 hide.long 0x00 "TXFR13,Transmit FIFO Register" hgroup.long 0x74++0x03 hide.long 0x00 "TXFR14,Transmit FIFO Register" hgroup.long 0x78++0x03 hide.long 0x00 "TXFR15,Transmit FIFO Register" endif rgroup.long 0x7C++0x03 line.long 0x00 "RXFR0,Receive FIFO Register 0" rgroup.long 0x80++0x03 line.long 0x00 "RXFR1,Receive FIFO Register 1" rgroup.long 0x84++0x03 line.long 0x00 "RXFR2,Receive FIFO Register 2" rgroup.long 0x88++0x03 line.long 0x00 "RXFR3,Receive FIFO Register 3" rgroup.long 0x8C++0x03 line.long 0x00 "RXFR4,Receive FIFO Register 4" rgroup.long 0x90++0x03 line.long 0x00 "RXFR5,Receive FIFO Register 5" rgroup.long 0x94++0x03 line.long 0x00 "RXFR6,Receive FIFO Register 6" rgroup.long 0x98++0x03 line.long 0x00 "RXFR7,Receive FIFO Register 7" rgroup.long 0x9C++0x03 line.long 0x00 "RXFR8,Receive FIFO Register 8" rgroup.long 0xA0++0x03 line.long 0x00 "RXFR9,Receive FIFO Register 9" rgroup.long 0xA4++0x03 line.long 0x00 "RXFR10,Receive FIFO Register 10" rgroup.long 0xA8++0x03 line.long 0x00 "RXFR11,Receive FIFO Register 11" rgroup.long 0xAC++0x03 line.long 0x00 "RXFR12,Receive FIFO Register 12" rgroup.long 0xB0++0x03 line.long 0x00 "RXFR13,Receive FIFO Register 13" rgroup.long 0xB4++0x03 line.long 0x00 "RXFR14,Receive FIFO Register 14" rgroup.long 0xB8++0x03 line.long 0x00 "RXFR15,Receive FIFO Register 15" if (((per.l.be(ad:0x2100000+0x00))&0x08)==0x00) group.long 0x11C++0x03 line.long 0x00 "CTARE0,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" group.long 0x120++0x03 line.long 0x00 "CTARE1,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" group.long 0x124++0x03 line.long 0x00 "CTARE2,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" group.long 0x128++0x03 line.long 0x00 "CTARE3,Clock And Transfer Attributes Register Extended" bitfld.long 0x00 16. " FMSZE ,Frame size extended" "16 bit SPI frame,32 bit SPI frame" hexmask.long.word 0x00 0.--10. 1. " DTCP ,Data transfer count preload" else hgroup.long 0x11C++0x03 hide.long 0x00 "CTARE0,Clock And Transfer Attributes Register Extended" hgroup.long 0x120++0x03 hide.long 0x00 "CTARE1,Clock And Transfer Attributes Register Extended" hgroup.long 0x124++0x03 hide.long 0x00 "CTARE2,Clock And Transfer Attributes Register Extended" hgroup.long 0x128++0x03 hide.long 0x00 "CTARE3,Clock And Transfer Attributes Register Extended" endif rgroup.long 0x13C++0x03 line.long 0x00 "SREX,Status Register Extended" bitfld.long 0x00 14. " RXCTR4 ,RX FIFO counter" "0,1" bitfld.long 0x00 11. " TXCTR4 ,TX FIFO counter" "0,1" bitfld.long 0x00 4.--8. " CMDCTR ,CMD FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--3. " CMDNXTPTR ,Command next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endian.le width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "TMU (Thermal Monitoring Unit)" base ad:0x01F80000 width 13. group.long 0x00++0x03 line.long 0x00 "TMR,TMU Mode Register" bitfld.long 0x00 31. " ME ,Monitor mode enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ALPF ,Average low pass filter setting" "1.0,0.5,0.25,0.125" bitfld.long 0x00 15. " MSITE[1] ,Monitoring site select: 1 WRIOP" "Disabled,Enabled" bitfld.long 0x00 14. " [0] ,Monitoring site select: 0 A53 core cluster" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "TSR,TMU Status Register" bitfld.long 0x00 30. " MIE ,Monitoring interval exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 29. " ORL ,Out-of-range low temperature measurement detected" "Not detected,Detected" bitfld.long 0x00 28. " ORH ,Out-of-range high temperature measurement detected" "Not detected,Detected" if (((per.l(ad:0x01F80000+0x00))&0x80000000)==0x00) group.long 0x08++0x03 line.long 0x00 "TMTMIR,TMU Monitor Temperature Measurement Interval Register" bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.02s/0.015s/0.01s,0.04s/0.03s/0.02s,0.08s/0.05s/0.04s,0.17s/0.10s/0.08s,0.34s/0.20s/0.17s,0.67s/0.40s/0.34s,1.34s/0.80s/0.67s,2.7s/1.6s/1.34s,5.4s/3.2s/2.7s,10.7s/6.4s/5.4s,21.5s/12.9s/10.7s,42.9s/25.8s/21.5s,85.9s/51.5s/42.9s,171.8s/103.0s/85.9s,343.6s/206.1s/171.8s,Disabled" else rgroup.long 0x08++0x03 line.long 0x00 "TMTMIR,TMU Monitor Temperature Measurement Interval Register" bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.02s/0.015s/0.01s,0.04s/0.03s/0.02s,0.08s/0.05s/0.04s,0.17s/0.10s/0.08s,0.34s/0.20s/0.17s,0.67s/0.40s/0.34s,1.34s/0.80s/0.67s,2.7s/1.6s/1.34s,5.4s/3.2s/2.7s,10.7s/6.4s/5.4s,21.5s/12.9s/10.7s,42.9s/25.8s/21.5s,85.9s/51.5s/42.9s,171.8s/103.0s/85.9s,343.6s/206.1s/171.8s,Disabled" endif group.long 0x20++0x0F line.long 0x00 "TIER,TMU Interrupt Enable Register" bitfld.long 0x00 31. " ITTEIE ,Immediate temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " ATTEIE ,Average temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " ATCTEIE ,Average temperature critical threshold exceeded interrupt enable" "Disabled,Enabled" line.long 0x04 "TIDR,TMU Interrupt Detect Register" eventfld.long 0x04 31. " ITTE ,Immediate temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 30. " ATTE ,Average temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 29. " ATCTE ,Average temperature critical threshold exceeded interrupt status" "No interrupt,Interrupt" line.long 0x08 "TISCR,TMU Interrupt Site Capture Register" bitfld.long 0x08 31. " ISITE[1] ,Temperature sensor site associated with the setting of TIDR[ITTE]" "Not masked,Masked" bitfld.long 0x08 30. " [0] ,Temperature sensor site associated with the setting of TIDR[ITTE]" "Not masked,Masked" newline bitfld.long 0x08 15. " ASITE[1] ,Temperature sensor site associated with the setting of TIDR[ATTE]" "Not masked,Masked" bitfld.long 0x08 14. " [0] ,Temperature sensor site associated with the setting of TIDR[ATTE]" "Not masked,Masked" line.long 0x0C "TICSCR,TMU Interrupt Critical Site Capture Register" bitfld.long 0x0C 15. " CASITE[1] ,Temperature sensor site associated with the setting of TIDR[ATCTE]" "Not masked,Masked" bitfld.long 0x0C 14. " [0] ,Temperature sensor site associated with the setting of TIDR[ATCTE]" "Not masked,Masked" if (((per.l(ad:0x01F80000+0x40))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TMHTCR,TMU Monitor High Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Highest temperature recorded in degrees Celsius" else rgroup.long 0x40++0x03 line.long 0x00 "TMHTCR,TMU Monitor High Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" endif if (((per.l(ad:0x01F80000+0x44))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TMLTCR,TMU Monitor Low Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Lowest temperature recorded in degrees Celsius" else rgroup.long 0x44++0x03 line.long 0x00 "TMLTCR,TMU Monitor Low Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" endif if (((per.l(ad:0x01F80000+0x50))&0x80000000)==0x02) group.long 0x50++0x03 line.long 0x00 "TMHTITR,TMU Monitor High Temperature Immediate Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,High temperature immediate threshold value" else group.long 0x50++0x03 line.long 0x00 "TMHTITR,TMU Monitor High Temperature Immediate Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" endif if (((per.l(ad:0x01F80000+0x54))&0x80000000)==0x02) group.long 0x54++0x03 line.long 0x00 "TMHTATR,TMU Monitor High Temperature Average Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,High temperature average threshold value" else group.long 0x54++0x03 line.long 0x00 "TMHTATR,TMU Monitor High Temperature Average Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" endif if (((per.l(ad:0x01F80000+0x54))&0x80000000)==0x02) group.long 0x58++0x03 line.long 0x00 "TMHTACTR,TMU Monitor High Temperature Average Critical Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,High temperature average critical threshold value" else group.long 0x58++0x03 line.long 0x00 "TMHTACTR,TMU Monitor High Temperature Average Critical Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" endif group.long 0x80++0x07 line.long 0x00 "TTCFGR,TMU Temperature Configuration Register" line.long 0x04 "TSCFGR,TMU Sensor Configuration Register" rgroup.long (0x100)++0x07 line.long 0x00 "TRITSR0,TMU Report Immediate Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading at site 0" line.long 0x04 "TRATSR0,TMU Report Average Temperature Site Register 0" bitfld.long 0x04 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x04 0.--7. 1. " TEMP ,Average temperature reading at site 0" rgroup.long (0x110)++0x07 line.long 0x00 "TRITSR1,TMU Report Immediate Temperature Site Register 1" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading at site 1" line.long 0x04 "TRATSR1,TMU Report Average Temperature Site Register 1" bitfld.long 0x04 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x04 0.--7. 1. " TEMP ,Average temperature reading at site 1" group.long (0xF10+0x0)++0x03 line.long 0x00 "TTR0CR,TMU Temperature Range 0 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 0" group.long (0xF10+0x4)++0x03 line.long 0x00 "TTR1CR,TMU Temperature Range 1 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 1" group.long (0xF10+0x8)++0x03 line.long 0x00 "TTR2CR,TMU Temperature Range 2 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 2" group.long (0xF10+0xC)++0x03 line.long 0x00 "TTR3CR,TMU Temperature Range 3 Control Register" bitfld.long 0x00 16.--19. " CAL_PTS ,Temperature calibration points" "1 point,2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 3" width 0x0B tree.end elif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") tree "TMU (Thermal Monitoring Unit)" base ad:0x01F00000 endian.be width 10. if (((per.l.be(ad:0x01F00000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "TMR,TMU Mode Register" bitfld.long 0x00 31. " ME ,Monitor mode enable" "Disabled,Enabled" rbitfld.long 0x00 26.--27. " ALPF ,Average low pass filter setting" "1.0,0.5,0.25,0.125" newline sif cpuis("LS1012*") rbitfld.long 0x00 15. " MSITE ,Monitoring site select: Near A53 core" "Disabled,Enabled" else rbitfld.long 0x00 15. " MSITE[0] ,Monitoring site select: Near DDR controller" "Disabled,Enabled" rbitfld.long 0x00 14. " [1] ,Monitoring site select: Near SerDes" "Disabled,Enabled" rbitfld.long 0x00 13. " [2] ,Monitoring site select: Near frame manager" "Disabled,Enabled" newline sif cpuis("LS10?6*") rbitfld.long 0x00 12. " [3] ,Monitoring site select: Near Arm A72 core" "Disabled,Enabled" newline else rbitfld.long 0x00 12. " [3] ,Monitoring site select: Near ARM A53 core" "Disabled,Enabled" newline endif rbitfld.long 0x00 11. " [4] ,Monitoring site select: SEC" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "TMR,TMU Mode Register" bitfld.long 0x00 31. " ME ,Monitor mode enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " ALPF ,Average low pass filter setting" "1.0,0.5,0.25,0.125" newline sif cpuis("LS1012*") bitfld.long 0x00 15. " MSITE ,Monitoring site select: Near A53 core" "Disabled,Enabled" else bitfld.long 0x00 15. " MSITE[0] ,Monitoring site select: Near DDR controller" "Disabled,Enabled" bitfld.long 0x00 14. " [1] ,Monitoring site select: Near SerDes" "Disabled,Enabled" bitfld.long 0x00 13. " [2] ,Monitoring site select: Near frame manager" "Disabled,Enabled" newline sif cpuis("LS10?6*") bitfld.long 0x00 12. " [3] ,Monitoring site select: Near Arm A72 core" "Disabled,Enabled" newline else bitfld.long 0x00 12. " [3] ,Monitoring site select: Near ARM A53 core" "Disabled,Enabled" newline endif bitfld.long 0x00 11. " [4] ,Monitoring site select: SEC" "Disabled,Enabled" endif endif rgroup.long 0x04++0x03 line.long 0x00 "TSR,TMU Status Register" bitfld.long 0x00 30. " MIE ,Monitoring interval exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 29. " ORL ,Out-of-range low temperature measurement detected" "Not detected,Detected" bitfld.long 0x00 28. " ORH ,Out-of-range high temperature measurement detected" "Not detected,Detected" if (((per.l.be(ad:0x01F00000))&0x80000000)==0x00) group.long 0x08++0x03 line.long 0x00 "TMTMIR,TMU Monitor Temperature Measurement Interval Register" sif cpuis("LS1012*") bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.034s,0.067s,0.134s,0.27s,0.54s,1.07s,2.15s,4.3s,8.6s,17s,34s,68s,137s,275s,550 s,Disabled" elif cpuis("LS10?6*") bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.03s/0.025s/0.02s,0.07s/0.05s/0.04s,0.13s/0.1s/0.08s,0.26s/0.2s/0.17s,0.5s/0.4s/0.34s,1s/0.8s/0.67s,2.1s/1.6s/1.34s,4.2s/3.2s/2.7s,8.4s/6.4s/5.4s,16.7s/12.9s/10.7s,33.6s/25.8s/21.5s,67.1s/51.6s/42.9s,134.2s/103.2s/85.9s,268.4s/206.4s/171.8s,536.9s/412.7s/343.6s,Disabled" else bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.02s/0.015s/0.01s,0.04s/0.03s/0.02s,0.08s/0.05s/0.04s,0.17s/0.10s/0.08s,0.34s/0.20s/0.17s,0.67s/0.40s/0.34s,1.34s/0.80s/0.67s,2.7s/1.6s/1.34s,5.4s/3.2s/2.7s,10.7s/6.4s/5.4s,21.5s/12.9s/10.7s,42.9s/25.8s/21.5s,85.9s/51.5s/42.9s,171.8s/103.0s/85.9s,343.6s/206.1s/171.8s,Disabled" endif else rgroup.long 0x08++0x03 line.long 0x00 "TMTMIR,TMU Monitor Temperature Measurement Interval Register" sif cpuis("LS1012*") bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.034s,0.067s,0.134s,0.27s,0.54s,1.07s,2.15s,4.3s,8.6s,17s,34s,68s,137s,275s,550 s,Disabled" elif cpuis("LS10?6*") bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.03s/0.025s/0.02s,0.07s/0.05s/0.04s,0.13s/0.1s/0.08s,0.26s/0.2s/0.17s,0.5s/0.4s/0.34s,1s/0.8s/0.67s,2.1s/1.6s/1.34s,4.2s/3.2s/2.7s,8.4s/6.4s/5.4s,16.7s/12.9s/10.7s,33.6s/25.8s/21.5s,67.1s/51.6s/42.9s,134.2s/103.2s/85.9s,268.4s/206.4s/171.8s,536.9s/412.7s/343.6s,Disabled" else bitfld.long 0x00 0.--3. " TMI ,Temperature monitoring interval in seconds" "0.02s/0.015s/0.01s,0.04s/0.03s/0.02s,0.08s/0.05s/0.04s,0.17s/0.10s/0.08s,0.34s/0.20s/0.17s,0.67s/0.40s/0.34s,1.34s/0.80s/0.67s,2.7s/1.6s/1.34s,5.4s/3.2s/2.7s,10.7s/6.4s/5.4s,21.5s/12.9s/10.7s,42.9s/25.8s/21.5s,85.9s/51.5s/42.9s,171.8s/103.0s/85.9s,343.6s/206.1s/171.8s,Disabled" endif endif group.long 0x20++0x07 line.long 0x00 "TIER,TMU Interrupt Enable Register" bitfld.long 0x00 31. " ITTEIE ,Immediate temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " ATTEIE ,Average temperature threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " ATCTEIE ,Average temperature critical threshold exceeded interrupt enable" "Disabled,Enabled" line.long 0x04 "TIDR,TMU Interrupt Detect Register" eventfld.long 0x04 31. " ITTE ,Immediate temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 30. " ATTE ,Average temperature threshold exceeded interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 29. " ATCTE ,Average temperature critical threshold exceeded interrupt status" "No interrupt,Interrupt" sif cpuis("LS1012*") group.long 0x28++0x07 line.long 0x00 "TISCR,TMU Interrupt Site Capture Register" bitfld.long 0x00 31. " ISITE ,Temperature sensor site (Near A53 core) associated with the setting of TIDR[ITTE]" "Not masked,Masked" bitfld.long 0x00 15. " ASITE ,Temperature sensor site (Near A53 core) associated with the setting of TIDR[ATTE]" "Not masked,Masked" line.long 0x04 "TICSCR,TMU Interrupt Critical Site Capture Register" bitfld.long 0x04 15. " CASITE ,Temperature sensor site (Near A53 core) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" else group.long 0x28++0x07 line.long 0x00 "TISCR,TMU Interrupt Site Capture Register" bitfld.long 0x00 31. " ISITE[0] ,Temperature sensor site (Near DDR controller) associated with the setting of TIDR[ITTE]" "Not masked,Masked" bitfld.long 0x00 30. " [1] ,Temperature sensor site (Near SerDes) associated with the setting of TIDR[ITTE]" "Not masked,Masked" bitfld.long 0x00 29. " [2] ,Temperature sensor site (Near Frame manager) associated with the setting of TIDR[ITTE]" "Not masked,Masked" newline sif cpuis("LS10?3*") bitfld.long 0x00 28. " [3] ,Temperature sensor site (Near ARM A53 core) associated with the setting of TIDR[ITTE]" "Not masked,Masked" newline else bitfld.long 0x00 28. " [3] ,Temperature sensor site (Near Arm A72 core) associated with the setting of TIDR[ITTE]" "Not masked,Masked" newline endif bitfld.long 0x00 27. " [4] ,Temperature sensor site (SEC) associated with the setting of TIDR[ITTE]" "Not masked,Masked" newline bitfld.long 0x00 15. " ASITE[0] ,Temperature sensor site (Near DDR controller) associated with the setting of TIDR[ATTE]" "Not masked,Masked" bitfld.long 0x00 14. " [1] ,Temperature sensor site (Near SerDes) associated with the setting of TIDR[ATTE]" "Not masked,Masked" bitfld.long 0x00 13. " [2] ,Temperature sensor site (Near Frame manager) associated with the setting of TIDR[ATTE]" "Not masked,Masked" newline sif cpuis("LS10?3*") bitfld.long 0x00 12. " [3] ,Temperature sensor site (Near ARM A53 core) associated with the setting of TIDR[ATTE]" "Not masked,Masked" newline else bitfld.long 0x00 12. " [3] ,Temperature sensor site (Near Arm A72 core) associated with the setting of TIDR[ATTE]" "Not masked,Masked" newline endif bitfld.long 0x00 11. " [4] ,Temperature sensor site (SEC) associated with the setting of TIDR[ATTE]" "Not masked,Masked" line.long 0x04 "TICSCR,TMU Interrupt Critical Site Capture Register" bitfld.long 0x04 15. " CASITE[0] ,Temperature sensor site (Near DDR controller) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" bitfld.long 0x04 14. " [1] ,Temperature sensor site (Near SerDes) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" bitfld.long 0x04 13. " [2] ,Temperature sensor site (Near Frame manager) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" newline sif cpuis("LS10?3*") bitfld.long 0x04 12. " [3] ,Temperature sensor site (Near ARM A53 core) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" newline else bitfld.long 0x04 12. " [3] ,Temperature sensor site (Near Arm A72 core) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" newline endif bitfld.long 0x04 11. " [4] ,Temperature sensor site (SEC) associated with the setting of TIDR[ATCTE]" "Not masked,Masked" endif if (((per.l.be(ad:0x01F00000+0x40))&0x80000000)==0x80000000) rgroup.long 0x40++0x03 line.long 0x00 "TMHTCR,TMU Monitor High Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Highest temperature recorded in degrees Celsius" else rgroup.long 0x40++0x03 line.long 0x00 "TMHTCR,TMU Monitor High Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x44))&0x80000000)==0x80000000) rgroup.long 0x44++0x03 line.long 0x00 "TMLTCR,TMU Monitor Low Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Lowest temperature recorded in degrees Celsius" else rgroup.long 0x44++0x03 line.long 0x00 "TMLTCR,TMU Monitor Low Temperature Capture Register" bitfld.long 0x00 31. " V ,Valid reading" "Not valid,Valid" endif group.long 0x50++0x0B line.long 0x00 "TMHTITR,TMU Monitor High Temperature Immediate Threshold Register" bitfld.long 0x00 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,High temperature immediate threshold value" line.long 0x04 "TMHTATR,TMU Monitor High Temperature Average Threshold Register" bitfld.long 0x04 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x04 0.--7. 1. " TEMP ,High temperature average threshold value" line.long 0x08 "TMHTACTR,TMU Monitor High Temperature Average Critical Threshold Register" bitfld.long 0x08 31. " EN ,Enable threshold" "Disabled,Enabled" hexmask.long.byte 0x08 0.--7. 1. " TEMP ,High temperature average critical threshold value" group.long 0x80++0x07 line.long 0x00 "TTCFGR,TMU Temperature Configuration Register" line.long 0x04 "TSCFGR,TMU Sensor Configuration Register" sif cpuis("LS1012*") if (((per.l.be(ad:0x01F00000+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "TRITSR0,TMU Report Immediate Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long 0x100++0x03 line.long 0x00 "TRITSR0,TMU Report Immediate Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x104))&0x80000000)==0x80000000) rgroup.long 0x104++0x03 line.long 0x00 "TRATSR0,TMU Report Average Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long 0x104++0x03 line.long 0x00 "TRATSR0,TMU Report Average Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif else if (((per.l.be(ad:0x01F00000+0x100))&0x80000000)==0x80000000) rgroup.long (0x100)++0x03 line.long 0x00 "TRITSR0,TMU Report Immediate Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long (0x100)++0x03 line.long 0x00 "TRITSR0,TMU Report Immediate Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x100+0x04))&0x80000000)==0x80000000) rgroup.long (0x100+0x04)++0x03 line.long 0x00 "TRATSR0,TMU Report Average Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long (0x100+0x04)++0x03 line.long 0x00 "TRATSR0,TMU Report Average Temperature Site Register 0" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x110))&0x80000000)==0x80000000) rgroup.long (0x110)++0x03 line.long 0x00 "TRITSR1,TMU Report Immediate Temperature Site Register 1" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long (0x110)++0x03 line.long 0x00 "TRITSR1,TMU Report Immediate Temperature Site Register 1" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x110+0x04))&0x80000000)==0x80000000) rgroup.long (0x110+0x04)++0x03 line.long 0x00 "TRATSR1,TMU Report Average Temperature Site Register 1" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long (0x110+0x04)++0x03 line.long 0x00 "TRATSR1,TMU Report Average Temperature Site Register 1" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x120))&0x80000000)==0x80000000) rgroup.long (0x120)++0x03 line.long 0x00 "TRITSR2,TMU Report Immediate Temperature Site Register 2" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long (0x120)++0x03 line.long 0x00 "TRITSR2,TMU Report Immediate Temperature Site Register 2" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x120+0x04))&0x80000000)==0x80000000) rgroup.long (0x120+0x04)++0x03 line.long 0x00 "TRATSR2,TMU Report Average Temperature Site Register 2" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long (0x120+0x04)++0x03 line.long 0x00 "TRATSR2,TMU Report Average Temperature Site Register 2" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x130))&0x80000000)==0x80000000) rgroup.long (0x130)++0x03 line.long 0x00 "TRITSR3,TMU Report Immediate Temperature Site Register 3" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long (0x130)++0x03 line.long 0x00 "TRITSR3,TMU Report Immediate Temperature Site Register 3" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x130+0x04))&0x80000000)==0x80000000) rgroup.long (0x130+0x04)++0x03 line.long 0x00 "TRATSR3,TMU Report Average Temperature Site Register 3" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long (0x130+0x04)++0x03 line.long 0x00 "TRATSR3,TMU Report Average Temperature Site Register 3" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x140))&0x80000000)==0x80000000) rgroup.long (0x140)++0x03 line.long 0x00 "TRITSR4,TMU Report Immediate Temperature Site Register 4" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Last temperature reading" else rgroup.long (0x140)++0x03 line.long 0x00 "TRITSR4,TMU Report Immediate Temperature Site Register 4" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif if (((per.l.be(ad:0x01F00000+0x140+0x04))&0x80000000)==0x80000000) rgroup.long (0x140+0x04)++0x03 line.long 0x00 "TRATSR4,TMU Report Average Temperature Site Register 4" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Average temperature reading" else rgroup.long (0x140+0x04)++0x03 line.long 0x00 "TRATSR4,TMU Report Average Temperature Site Register 4" bitfld.long 0x00 31. " V ,Valid measured temperature" "Not valid,Valid" endif endif rgroup.long 0xBF8++0x03 line.long 0x00 "IPBRR0,IP Block Revision Register 0" hexmask.long.word 0x00 16.--31. 1. " IP_ID ,IP block ID" hexmask.long.byte 0x00 8.--15. 1. " IP_MJ ,Major revision" hexmask.long.byte 0x00 0.--7. 1. " IP_MN ,Minor revision" group.long (0xF10+0x0)++0x03 line.long 0x00 "TTR0CR,TMU Temperature Range 0 Control Register" bitfld.long 0x00 16.--19. " CAL_PTR ,Temperature calibration points" ",2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 0" group.long (0xF10+0x4)++0x03 line.long 0x00 "TTR1CR,TMU Temperature Range 1 Control Register" bitfld.long 0x00 16.--19. " CAL_PTR ,Temperature calibration points" ",2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 1" group.long (0xF10+0x8)++0x03 line.long 0x00 "TTR2CR,TMU Temperature Range 2 Control Register" bitfld.long 0x00 16.--19. " CAL_PTR ,Temperature calibration points" ",2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 2" group.long (0xF10+0xC)++0x03 line.long 0x00 "TTR3CR,TMU Temperature Range 3 Control Register" bitfld.long 0x00 16.--19. " CAL_PTR ,Temperature calibration points" ",2 points,3 points,4 points,5 points,6 points,7 points,8 points,9 points,10 points,11 points,12 points,13 points,14 points,15 points,16 points" hexmask.long.byte 0x00 0.--7. 1. " TEMP ,Starting temperature in Celsius for range 3" endian.le width 0x0B tree.end endif sif cpuis("LS1012*") tree "USB 2.0 (Universal Serial Bus Interface 2.0)" base ad:0x8600000 width 21. rgroup.long 0x00++0x03 line.long 0x00 "ID,Identification Register" bitfld.long 0x00 26.--31. " ID ,Configuration number" ",,,,,5,?..." bitfld.long 0x00 18.--23. " NID ,Configuration number ones complement" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11.--15. " TAG ,USB core tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--10. " REVISION ,Module revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3.--6. " VERSION ,Module version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x07 line.long 0x00 "GPTIMER0LD,General Purpose Timer Load 0" hexmask.long.tbyte 0x00 8.--31. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER0CTRL,General Purpose Timer Control 0" hexmask.long.tbyte 0x04 8.--31. 1. " GPTCNT ,General purpose timer counter" bitfld.long 0x04 7. " GPTMODE ,General purpose timer mode" "One-shot,Repeat" newline bitfld.long 0x04 1. " GPTRST ,General purpose timer reset" "No reset,Reset" bitfld.long 0x04 0. " GPTRUN ,General purpose timer run" "Stop,Run" group.long 0x88++0x07 line.long 0x00 "GPTIMER1LD,General Purpose Timer Load 1" hexmask.long.tbyte 0x00 8.--31. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER1CTRL,General Purpose Timer Control 1" hexmask.long.tbyte 0x04 8.--31. 1. " GPTCNT ,General purpose timer counter" bitfld.long 0x04 7. " GPTMODE ,General purpose timer mode" "One-shot,Repeat" newline bitfld.long 0x04 1. " GPTRST ,General purpose timer reset" "No reset,Reset" bitfld.long 0x04 0. " GPTRUN ,General purpose timer run" "Stop,Run" rgroup.byte 0x100++0x00 line.byte 0x00 "CAPLENGTH,Capability Register Length" rgroup.word 0x102++0x01 line.word 0x00 "HCIVERSION,Host Controller Interface Version Number" rgroup.long 0x104++0x07 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 28.--31. " N_PORTS ,Number of ports" ",1,?..." bitfld.long 0x00 27. " PPC ,Power port control" "Drive 0,Drive 1" bitfld.long 0x00 20.--23. " N_PCC ,Number ports per CC" "0,?..." newline bitfld.long 0x00 16.--19. " N_CC ,Number of companion controllers associated with the DR controller" "0,?..." bitfld.long 0x00 15. " PI ,Port indicators" "Not supported,Supported" bitfld.long 0x00 8.--11. " N_PTT ,Ports per transaction translator" ",1,?..." newline bitfld.long 0x00 4.--7. " N_TT ,Number of transaction translators" ",1,?..." line.long 0x04 "HCCPARAMS,Host Controller Capability Parameters" bitfld.long 0x04 31. " ADC ,64-bit addressing capability (Not supported)" "32-bit address,?..." bitfld.long 0x04 30. " PFL ,Programmable frame list flag" ",Set" bitfld.long 0x04 29. " ASP ,Asynchronous schedule park capability support" ",Supported" newline bitfld.long 0x04 24.--27. " IST ,Isochronous scheduling threshold" "0,?..." hexmask.long.byte 0x04 16.--23. 0x01 " EECP ,EHCI extended capabilities pointer" rgroup.word 0x120++0x01 line.word 0x00 "DCIVERSION,Device Controller Interface Version Number" rgroup.long 0x124++0x03 line.long 0x00 "DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 27.--31. " DEN ,Device endpoint number" ",,,,,,6,?..." bitfld.long 0x00 24. " DC ,Device capable" ",Capable" bitfld.long 0x00 23. " HC ,Host capable" ",Capable" if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0xC0000000) group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command" bitfld.long 0x00 31. " RS ,Run/Stop" "Stop,Run" bitfld.long 0x00 30. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 28.--29. 16. " FS ,Frame list size" "4096 bytes,2048 bytes,1024 bytes,512 bytes,256 bytes,128 bytes,64 bytes,32 bytes" newline bitfld.long 0x00 27. " PSE ,Periodic schedule enable" "Disabled,Enabled" bitfld.long 0x00 26. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 25. " IAA ,Interrupt on async advance doorbell" "No interrupt,Interrupt" newline bitfld.long 0x00 22.--23. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 20. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " SUTW ,Setup tripwire" "Not set,Set" newline bitfld.long 0x00 17. " ATDTW ,Add dTD TripWire" "Not added,Added" hexmask.long.byte 0x00 8.--15. 1. " ITC ,Interrupt threshold control" else group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command" bitfld.long 0x00 31. " RS ,Run/Stop" "Stop,Run" bitfld.long 0x00 30. " RST ,Controller reset" "No effect,Reset" bitfld.long 0x00 22.--23. " ASP ,Asynchronous schedule park mode count" ",1,2,3" newline bitfld.long 0x00 20. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" bitfld.long 0x00 18. " SUTW ,Setup tripwire" "Not set,Set" bitfld.long 0x00 17. " ATDTW ,Add dTD TripWire" "Not added,Added" newline hexmask.long.byte 0x00 8.--15. 1. " ITC ,Interrupt threshold control" endif if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0xC0000000) group.long 0x144++0x0B line.long 0x00 "USBSTS,USB Status" eventfld.long 0x00 31. " UI ,USB interrupt (USBINT)" "No interrupt,Interrupt" eventfld.long 0x00 30. " UEI ,USB error interrupt (USBERRINT)" "No error,Error" eventfld.long 0x00 29. " PCI ,The controller sets this bit when a connect status occurs on any port" "Not occurred,Occurred" newline eventfld.long 0x00 28. " FRI ,Frame list rollover" "No effect,Rolled over" eventfld.long 0x00 27. " SEI ,System error" "No error,Error" eventfld.long 0x00 26. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" newline eventfld.long 0x00 24. " SRI ,Set every 125us provided the PHY clock is present and running" "Stopped,Running" rbitfld.long 0x00 21. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 19. " HCH ,HC halted" "Running,Halted" newline rbitfld.long 0x00 18. " RCL ,Reclamation used to detect an empty asynchronous schedule" "Not empty,Empty" rbitfld.long 0x00 17. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x00 16. " AS ,Asynchronous schedule status" "Disabled,Enabled" line.long 0x04 "USBINTR,USB Interrupt Enable" bitfld.long 0x04 31. " UE ,USB interrupt enable" "Disabled,Enabled" bitfld.long 0x04 26. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x04 29. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " FRE ,Frame list rollover enable" "Disabled,Enabled" bitfld.long 0x04 27. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x04 30. " UEE ,USB error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x04 24. " SRE ,SOF received enable" "Disabled,Enabled" bitfld.long 0x04 21. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" line.long 0x08 "FRINDEX,USB Frame Index" hexmask.long.word 0x08 18.--31. 1. " FRINDEX ,Frame index" elif (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0x80000000) group.long 0x144++0x07 line.long 0x00 "USBSTS,USB Status" eventfld.long 0x00 31. " UI ,USB interrupt (USBINT)" "No interrupt,Interrupt" eventfld.long 0x00 30. " UEI ,USB error interrupt (USBERRINT)" "No error,Error" eventfld.long 0x00 29. " PCI ,Sets this bit when it enters the full or high-speed operational state" "LS,FS/HS" newline eventfld.long 0x00 27. " SEI ,System error" "No error,Error" eventfld.long 0x00 25. " URI ,USB reset received" "No reset,Reset" eventfld.long 0x00 24. " SRI ,SOF received" "Not set,Set" newline eventfld.long 0x00 23. " SLI ,DC suspend" "Active,Suspended" rbitfld.long 0x00 21. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" line.long 0x04 "USBINTR,USB Interrupt Enable" bitfld.long 0x04 31. " UE ,USB interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 29. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x04 27. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x04 25. " URE ,USB reset enable" "Disabled,Enabled" bitfld.long 0x04 24. " SRE ,SOF received enable" "Disabled,Enabled" newline bitfld.long 0x04 23. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x04 21. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x03 line.long 0x00 "FRINDEX,USB Frame Index" hexmask.long.word 0x00 18.--31. 1. " FRINDEX ,Current frame number of the last frame transmitted" else group.long 0x144++0x0B line.long 0x00 "USBSTS,USB Status" eventfld.long 0x00 31. " UI ,USB interrupt (USBINT)" "No interrupt,Interrupt" eventfld.long 0x00 30. " UEI ,USB error interrupt (USBERRINT)" "No error,Error" eventfld.long 0x00 27. " SEI ,System error" "No error,Error" newline eventfld.long 0x00 24. " SRI ,SOF received" "Not set,Set" rbitfld.long 0x00 21. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" line.long 0x04 "USBINTR,USB Interrupt Enable" bitfld.long 0x04 31. " UE ,USB interrupt enable" "Disabled,Enabled" bitfld.long 0x04 30. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x04 29. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x04 27. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x04 24. " SRE ,SOF received enable" "Disabled,Enabled" bitfld.long 0x04 21. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" line.long 0x08 "FRINDEX,USB Frame Index" hexmask.long.word 0x08 18.--31. 1. " FRINDEX ,Frame index" endif if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0xC0000000) group.long 0x154++0x07 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address" hexmask.long.tbyte 0x00 0.--19. 0x01 " PERBASE ,Base address" line.long 0x04 "ASYNCLISTADDR,Next Asynchronous List Addr" hexmask.long 0x04 0.--26. 0x01 " ASYBASE ,Link pointer low (LPL)" elif (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0x80000000) group.long 0x154++0x07 line.long 0x00 "DEVICEADDR,USB Device Address" hexmask.long.byte 0x00 0.--6. 0x01 " USBADR ,Device address" line.long 0x04 "ENDPOINTLISTADDR,Address At Endpoint List" hexmask.long.tbyte 0x04 0.--20. 0x01 " EPBASE ,Endpoint list address" else hgroup.long 0x154++0x03 hide.long 0x00 "DEVICEADDR,USB Device Address" hgroup.long 0x158++0x03 hide.long 0x00 "ENDPOINTLISTADDR,Address At Endpoint List" endif group.long 0x160++0x03 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size" hexmask.long.byte 0x00 24.--31. 1. " RXPBURST ,Programmable RX burst length" hexmask.long.byte 0x00 16.--23. 1. " TXPBURST ,Programmable TX burst length" if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0xC0000000) rgroup.long 0x164++0x03 line.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls" hexmask.long.byte 0x00 24.--31. 1. " TXSCHOH ,Scheduler overhead" bitfld.long 0x00 19.--23. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--15. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long 0x164++0x03 hide.long 0x00 "TXFILLTUNING,Transmit FIFO Tuning Controls" endif group.long 0x170++0x03 line.long 0x00 "ULPI_VIEWPORT,ULPI Register Access" hexmask.long.byte 0x00 24.--31. 1. " ULPIDTWR ,When a write operation is commanded the data to be sent is written to this field" hexmask.long.byte 0x00 16.--23. 1. " ULPIDATRD ,After a read operation completes the result is placed in this field" hexmask.long.byte 0x00 8.--15. 0x01 " ULPIADDR ,When a read or write operation is commanded the address of the operation is written to this field" newline bitfld.long 0x00 5.--7. " ULPIPORT ,For wakeup or read/write operations this value selects the port number to which the ULPI PHY is attached" "0,1,?..." rbitfld.long 0x00 4. " ULPISS ,This bit represents the state of the ULPI interface" "Carkit/Serial/Low Power,Normal sync state" bitfld.long 0x00 2. " ULPIRW ,Selects between running a read or write operation to the ULPI" "Read,Write" newline bitfld.long 0x00 1. " ULPIRUN ,ULPI run (begin a read/write operation)" "No effect,Begin R/W" bitfld.long 0x00 0. " ULPIWU ,ULPI wake up" "No effect,Wake up" if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0x80000000) group.long 0x178++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK Indication Register" bitfld.long 0x00 31. " EPRN[5] ,RX endpoint 0 NAK" "0,1" bitfld.long 0x00 30. " [4] ,RX endpoint 1 NAK" "0,1" bitfld.long 0x00 29. " [3] ,RX endpoint 2 NAK" "0,1" newline bitfld.long 0x00 28. " [2] ,RX endpoint 3 NAK" "0,1" bitfld.long 0x00 27. " [1] ,RX endpoint 4 NAK" "0,1" bitfld.long 0x00 26. " [0] ,RX endpoint 5 NAK" "0,1" newline bitfld.long 0x00 15. " EPTN[5] ,TX endpoint 0 NAK" "0,1" bitfld.long 0x00 14. " [4] ,TX endpoint 1 NAK" "0,1" bitfld.long 0x00 13. " [3] ,TX endpoint 2 NAK" "0,1" newline bitfld.long 0x00 12. " [2] ,TX endpoint 3 NAK" "0,1" bitfld.long 0x00 11. " [1] ,TX endpoint 4 NAK" "0,1" bitfld.long 0x00 10. " [0] ,TX endpoint 5 NAK" "0,1" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Indication Enable Register" bitfld.long 0x04 31. " EPRNE[5] ,RX endpoint 0 NAK enable" "Disabled,Enabled" bitfld.long 0x04 30. " [4] ,RX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 29. " [3] ,RX endpoint 2 NAK enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " [2] ,RX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 27. " [1] ,RX endpoint 4 NAK enable" "Disabled,Enabled" bitfld.long 0x04 26. " [0] ,RX endpoint 5 NAK enable" "Disabled,Enabled" newline bitfld.long 0x04 15. " EPTNE[5] ,TX endpoint 0 NAK enable" "Disabled,Enabled" bitfld.long 0x04 14. " [4] ,TX endpoint 1 NAK enable" "Disabled,Enabled" bitfld.long 0x04 13. " [3] ,TX endpoint 2 NAK enable" "Disabled,Enabled" newline bitfld.long 0x04 12. " [2] ,TX endpoint 3 NAK enable" "Disabled,Enabled" bitfld.long 0x04 11. " [1] ,TX endpoint 4 NAK enable" "Disabled,Enabled" bitfld.long 0x04 10. " [0] ,TX endpoint 5 NAK enable" "Disabled,Enabled" else hgroup.long 0x178++0x03 hide.long 0x00 "ENDPTNAK,Endpoint NAK Indication Register" hgroup.long 0x17C++0x03 hide.long 0x00 "ENDPTNAKEN,Endpoint NAK Indication Enable Register" endif rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configured Flag Register" bitfld.long 0x00 31. " CF ,Configure flag" "0,1" if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0x80000000) group.long 0x184++0x03 line.long 0x00 "PORTSC,Port Status/Control" rbitfld.long 0x00 31. " CCS ,Current connect status" "Not attached,Attached" bitfld.long 0x00 29. " PE ,Port enabled/disabled" ",Enabled" eventfld.long 0x00 28. " PEC ,Port disable change" "No,Yes" newline rbitfld.long 0x00 27. " OCA ,Over-current active" "Not active,?..." eventfld.long 0x00 26. " OCC ,Over-current change" "Not changed,?..." bitfld.long 0x00 25. " FPR ,Force port resume" "No resume,Resume" newline rbitfld.long 0x00 24. " SUSP ,Suspend" "Not suspended,Suspended" rbitfld.long 0x00 23. " PR ,Port reset" "No reset,Reset" rbitfld.long 0x00 20.--21. " LS ,Line status" "SE0,J-state,K-state,Undefined" newline bitfld.long 0x00 19. " PP ,Port power" "Off,?..." bitfld.long 0x00 18. " PO ,Port owner release ownership of the port to a selected module" "0,1" bitfld.long 0x00 12.--15. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,?..." newline bitfld.long 0x00 8. " PHCD ,PHY low power suspend" "Normal PHY,Low power PHY" bitfld.long 0x00 7. " PFSC ,Port force full-speed connect" "Allow high-speed,Force full-speed" rbitfld.long 0x00 4.--5. " PSPD ,Port speed" "Full-speed,Low-speed,High-speed,Undefined" newline bitfld.long 0x00 0.--1. " PTS ,Port transceiver select" ",,ULPI,?..." elif (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0xC0000000) group.long 0x184++0x03 line.long 0x00 "PORTSC,Port Status/Control" rbitfld.long 0x00 31. " CCS ,Current connect status" "Not present,Present" eventfld.long 0x00 30. " CSC ,Connect change status" "Not changed,Changed" bitfld.long 0x00 29. " PE ,Port enabled/disabled" "Disabled,Enabled" newline eventfld.long 0x00 28. " PEC ,Port disable change" "No,Yes" rbitfld.long 0x00 27. " OCA ,Over-current active" "Not active,Active" eventfld.long 0x00 26. " OCC ,Over-current change" "Not changed,Changed" newline bitfld.long 0x00 25. " FPR ,Force port resume" "No resume,Resume" bitfld.long 0x00 24. " SUSP ,Suspend" "Not suspended,Suspended" rbitfld.long 0x00 23. " PR ,Port reset" "No reset,Reset" newline rbitfld.long 0x00 20.--21. " LS ,Line status" "SE0,J-state,K-state,Undefined" bitfld.long 0x00 19. " PP ,Port power" "Off,On" bitfld.long 0x00 18. " PO ,Port owner release ownership of the port to a selected module" "0,1" newline bitfld.long 0x00 16.--17. " PIC ,Port indicator control" "OFF,Amber,Green,Undefined" bitfld.long 0x00 12.--15. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE,?..." bitfld.long 0x00 11. " WKCN ,Wake on connect enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " WKDS ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 9. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 8. " PHCD ,PHY low power suspend" "Normal PHY,Low power PHY" newline bitfld.long 0x00 7. " PFSC ,Port force full-speed connect" "Allow high-speed,Force full-speed" rbitfld.long 0x00 4.--5. " PSPD ,Port speed" "Full-speed,Low-speed,High-speed,Undefined" bitfld.long 0x00 0.--1. " PTS ,Port transceiver select" ",,ULPI,?..." endif group.long 0x1A8++0x03 line.long 0x00 "USBMODE,USB Device Mode" bitfld.long 0x00 30.--31. " CM ,Controller mode" "Idle,,Device,Host" bitfld.long 0x00 29. " ES ,Endian select" "Little,Big" bitfld.long 0x00 28. " SLOM ,Setup lockout mode" "Lockouts off,Lockouts on" newline bitfld.long 0x00 27. " SDIS ,Stream disable" "No,Yes" bitfld.long 0x00 17.--19. " TXHSD ,Tx to Tx HS delay delay(8-bit 60MHz)---delay(16-bit 30MHz)" "10---5,11---5,12---6,13---6,14---7,15---7,16---8,17---8" bitfld.long 0x00 15. " ALP ,Auto low power enable" "Disabled,Enabled" if (((per.l(ad:0x8600000+0x1A8))&0xC0000000)==0x80000000) group.long 0x1AC++0x03 line.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status" eventfld.long 0x00 31. " ENDPTSETUPSTAT[5] ,Setup endpoint status 0" "0,1" eventfld.long 0x00 30. " [4] ,Setup endpoint status 1" "0,1" eventfld.long 0x00 29. " [3] ,Setup endpoint status 2" "0,1" newline eventfld.long 0x00 28. " [2] ,Setup endpoint status 3" "0,1" eventfld.long 0x00 27. " [1] ,Setup endpoint status 4" "0,1" eventfld.long 0x00 26. " [0] ,Setup endpoint status 5" "0,1" group.long 0x1B8++0x07 line.long 0x00 "ENDPTSTATUS_SET/CLR,Endpoint Set/Clear Status" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " ERBR[5] ,Endpoint receive buffer ready 0" "Cleared,Set" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [4] ,Endpoint receive buffer ready 1" "Cleared,Set" setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [3] ,Endpoint receive buffer ready 2" "Cleared,Set" newline setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [2] ,Endpoint receive buffer ready 3" "Cleared,Set" setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [1] ,Endpoint receive buffer ready 4" "Cleared,Set" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [0] ,Endpoint receive buffer ready 5" "Cleared,Set" newline setclrfld.long 0x00 15. -0x08 15. -0x04 15. " ETBR[5] ,Endpoint transmit buffer ready 0" "Cleared,Set" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [4] ,Endpoint transmit buffer ready 1" "Cleared,Set" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [3] ,Endpoint transmit buffer ready 2" "Cleared,Set" newline setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [2] ,Endpoint transmit buffer ready 3" "Cleared,Set" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [1] ,Endpoint transmit buffer ready 4" "Cleared,Set" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [0] ,Endpoint transmit buffer ready 5" "Cleared,Set" line.long 0x04 "ENDPTCOMPLETE,Endpoint Complete" eventfld.long 0x04 31. " ERCE[5] ,Endpoint receive complete event 0" "Not occurred,Occurred" eventfld.long 0x04 30. " [4] ,Endpoint receive complete event 1" "Not occurred,Occurred" eventfld.long 0x04 29. " [3] ,Endpoint receive complete event 2" "Not occurred,Occurred" newline eventfld.long 0x04 28. " [2] ,Endpoint receive complete event 3" "Not occurred,Occurred" eventfld.long 0x04 27. " [1] ,Endpoint receive complete event 4" "Not occurred,Occurred" eventfld.long 0x04 26. " [0] ,Endpoint receive complete event 5" "Not occurred,Occurred" newline eventfld.long 0x04 15. " ETCE[5] ,Endpoint transmit complete event 0" "Not occurred,Occurred" eventfld.long 0x04 14. " [4] ,Endpoint transmit complete event 1" "Not occurred,Occurred" eventfld.long 0x04 13. " [3] ,Endpoint transmit complete event 2" "Not occurred,Occurred" newline eventfld.long 0x04 12. " [2] ,Endpoint transmit complete event 3" "Not occurred,Occurred" eventfld.long 0x04 11. " [1] ,Endpoint transmit complete event 4" "Not occurred,Occurred" eventfld.long 0x04 10. " [0] ,Endpoint transmit complete event 5" "Not occurred,Occurred" else hgroup.long 0x1AC++0x03 hide.long 0x00 "ENDPTSETUPSTAT,Endpoint Setup Status" hgroup.long 0x1B8++0x03 hide.long 0x00 "ENDPTSTATUS,Endpoint Status" hgroup.long 0x1BC++0x03 hide.long 0x00 "ENDPTCOMPLETE,Endpoint Complete" endif group.long 0x1C0++0x03 line.long 0x00 "ENDPTCTRL0,Endpoint Control 0" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" rbitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,?..." rbitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "Not stalled,Stalled" rbitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,?..." rbitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x1C4++0x03 line.long 0x00 "ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" bitfld.long 0x00 30. " RXD ,RX endpoint data sink" "Dual port mem / DMA engine,?..." bitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 26. " RXI ,RX data toggle inhibit" "PID enabled,PID disabled" bitfld.long 0x00 25. " RXR ,RX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 14. " TXD ,TX endpoint data source" "DPM,DMA" bitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 10. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 9. " TXR ,TX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x1C8++0x03 line.long 0x00 "ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" bitfld.long 0x00 30. " RXD ,RX endpoint data sink" "Dual port mem / DMA engine,?..." bitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 26. " RXI ,RX data toggle inhibit" "PID enabled,PID disabled" bitfld.long 0x00 25. " RXR ,RX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 14. " TXD ,TX endpoint data source" "DPM,DMA" bitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 10. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 9. " TXR ,TX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x1CC++0x03 line.long 0x00 "ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" bitfld.long 0x00 30. " RXD ,RX endpoint data sink" "Dual port mem / DMA engine,?..." bitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 26. " RXI ,RX data toggle inhibit" "PID enabled,PID disabled" bitfld.long 0x00 25. " RXR ,RX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 14. " TXD ,TX endpoint data source" "DPM,DMA" bitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 10. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 9. " TXR ,TX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x1D0++0x03 line.long 0x00 "ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" bitfld.long 0x00 30. " RXD ,RX endpoint data sink" "Dual port mem / DMA engine,?..." bitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 26. " RXI ,RX data toggle inhibit" "PID enabled,PID disabled" bitfld.long 0x00 25. " RXR ,RX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 14. " TXD ,TX endpoint data source" "DPM,DMA" bitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 10. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 9. " TXR ,TX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x1D4++0x03 line.long 0x00 "ENDPTCTRL5,Endpoint Control 5" bitfld.long 0x00 31. " RXS ,RX endpoint stall" "Not stalled,Stalled" bitfld.long 0x00 30. " RXD ,RX endpoint data sink" "Dual port mem / DMA engine,?..." bitfld.long 0x00 28.--29. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 26. " RXI ,RX data toggle inhibit" "PID enabled,PID disabled" bitfld.long 0x00 25. " RXR ,RX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 24. " RXE ,RX endpoint enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " TXS ,TX endpoint stall" "OK,Stalled" bitfld.long 0x00 14. " TXD ,TX endpoint data source" "DPM,DMA" bitfld.long 0x00 12.--13. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" newline bitfld.long 0x00 10. " TXI ,TX data toggle inhibit" "Not inhibited,Inhibited" bitfld.long 0x00 9. " TXR ,TX data toggle reset" "No effect,Synchronized" bitfld.long 0x00 8. " TXE ,TX endpoint enable" "Disabled,Enabled" group.long 0x400++0x13 line.long 0x00 "SNOOP1,Snoop 1" bitfld.long 0x00 27.--31. " SNOOP_ENABLES ,Snoop_Enables. xKB/MB/GB snoop range starting at the value defined by SNOOP 1" "Disabled,,,,,,,,,,,4KB[0-19],8KB[0-18],16KB[0-17],32KB[0-16],64KB[0-15],128KB[0-14],256KB[0-13],512KB[0-12],1MB[0-11],2MB[0-10],4MB[0-9],8MB[0-8],16MB[0-7],32MB[0-6],64MB[0-5],128MB[0-4],256MB[0-3],512MB[0-2],1GB[0-1],2GB[0],?..." hexmask.long.tbyte 0x00 0.--19. 0x01 " SNOOP_ADDRESS ,The starting base address for which transactions are snooped" line.long 0x04 "SNOOP2,Snoop 2" bitfld.long 0x04 27.--31. " SNOOP_ENABLES ,Snoop_Enables. xKB/MB/GB snoop range starting at the value defined by SNOOP 2" "Disabled,,,,,,,,,,,4KB[0-19],8KB[0-18],16KB[0-17],32KB[0-16],64KB[0-15],128KB[0-14],256KB[0-13],512KB[0-12],1MB[0-11],2MB[0-10],4MB[0-9],8MB[0-8],16MB[0-7],32MB[0-6],64MB[0-5],128MB[0-4],256MB[0-3],512MB[0-2],1GB[0-1],2GB[0],?..." hexmask.long.tbyte 0x04 0.--19. 0x01 " SNOOP_ADDRESS ,The starting base address for which transactions are snooped" line.long 0x08 "AGE_CNT_THRESH,Age Count Threshold" hexmask.long.word 0x08 0.--13. 1. " THRESHOLD ,Aging counter threshold value" line.long 0x0C "PRI_CTRL,Priority Control" bitfld.long 0x0C 2.--3. " PRI_LVL1 ,Priority level for priority state 1" "0,1,2,3" bitfld.long 0x0C 0.--1. " PRI_LVL0 ,Priority level for priority state 0" "0,1,2,3" line.long 0x10 "SI_CTRL,System Interface Control" bitfld.long 0x10 4. " ERR_DISABLE ,Ignore system bus errors" "No,Yes" bitfld.long 0x10 0. " RD_PREFETCH_VAL ,Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system interface" "64 byte,?..." group.long 0x500++0x03 line.long 0x00 "CONTROL,Control" bitfld.long 0x00 31. " ULPI_INT_EN ,Used to enable the ULPI low power wakeup interrupt from the PHY when the PHY is in low power mode only" "Disabled,Enabled" bitfld.long 0x00 30. " WU_INT_EN ,This bit is used to mask/unmask the system wakeup interrupt signal" "Disabled,Enabled" bitfld.long 0x00 29. " USB_EN ,ULPI mode" "Safe mode,Normal" newline rbitfld.long 0x00 15. " WU_INT ,Reflects the state of the wake up interrupt" "Wait for wake up event,Wake up event" width 0x0B tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "USB 3.0 (Universal Serial Bus Interface 3.0)" tree "USB 1" base ad:0x03100000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability Registers Length And HC Interface Version Number Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters Register 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" newline hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters Register 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad bufs lo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" newline bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS_HI ,Max scratchpad bufs hi" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVICE_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVICE_EXIT_LAT ,U1 device exit latency" newline line.long 0x10 "HCCPARAMS1,Capability Parameters" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "0,1" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "0,1" newline bitfld.long 0x10 9. " SPC ,Short packet capability" "0,1" bitfld.long 0x10 8. " PAE ,Parse all event data" "0,1" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "0,1" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "0,1" newline bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "0,1" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" newline bitfld.long 0x10 1. " BNC ,BW negotiation capability" "0,1" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "0,1" line.long 0x14 "DBOFF,Doorbell Offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELLARRAYOFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime Register Space Offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPACE_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS2,Capability Parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "0,1" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "0,1" newline bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "0,1" bitfld.long 0x1C 2. " FSC ,Force save context capability" "0,1" newline bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "0,1" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "0,1" newline group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " DATWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " INCR256BRSTENA ,NCR256 burst type enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,NCR128 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " INCR64BRSTENA ,NCR64 burst type enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,NCR32 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " INCR16BRSTENA ,NCR16 burst type enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,NCR8 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " INCR4BRSTENA ,NCR4 burst type enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "INCRX,INCR" line.long 0x04 "GSBUSCFG1,Global SoC Bus Configuration Register 1" bitfld.long 0x04 12. " EN1KPAGE ,1k page boundary enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--11. " PIPETRANSLIMIT ,AXI pipelined transfers burst request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) if (((per.l(ad:0x03100000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBURSTSIZE ,USB maximum TX burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x03100000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x03100000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global Status Register" sif !cpuis("LS108*")&&!cpuis("LS1044*")&&!cpuis("LS1048*") rbitfld.long 0x00 10. " OTG_IP ,OTG interrupt pending" "Not pending,Pending" newline endif rbitfld.long 0x00 7. " HOST_IP ,HOST interrupt pending" "Not pending,Pending" rbitfld.long 0x00 6. " DEVICE_IP ,Device interrupt pending" "Not pending,Pending" newline bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "No timeout,Timeout" bitfld.long 0x00 4. " BUSERRADDRVLD ,Bus error address valid" "Invalid,Valid" newline rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device,Host,?..." sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) ; if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global User ID Register" newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 21. " NOEXTRDL ,No extra delay between SOF and the first packet" "Waits 2 us,Doesn't wait" newline bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" bitfld.long 0x00 16. " RESBWHSEPS ,Indicates whether reserve 80% or 85% of bandwidth for HS periodic EPs" "80%,85%" newline bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot ID,Increment address" bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" newline bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" bitfld.long 0x00 9.--10. " DTCT ,Device timeout coarse tuning" "DTFT,500 us,1.5 ms,6.5 ms" newline hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" newline bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" else hgroup.long 0xC12C++0x03 hide.long 0x00 "GUCTL,Global User Control Register" endif newline if (((per.l(ad:0x03100000+0xC118))&0x10)==0x01) rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" line.long 0x04 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" else hgroup.long 0xC130++0x03 hide.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" hgroup.long 0xC134++0x03 hide.long 0x00 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" endif group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,SuperSpeed Port To Bus Instance Mapping" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,High-Speed Port To Bus Instance Mapping" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus (register access bus) data bus width" newline hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus (DMA bus) data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus (register access bus) interface type" "AHB,?..." newline bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus (DMA bus) interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global Hardware Parameters Register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "Disabled,Enabled" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Optional features removal enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,Specifies whether the RAM clock and the Bus clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 27. " DWC_USB3_MAC_RAM_CLKS_SYNC ,Specifies whether the MAC clock and the RAM clock are synchronous to each other" "Asynchronous,Synchronous" newline bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,Specifies whether the MAC clock and the PHY clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Specifies the power optimization mode" "No power optimization,Clock gating only,?..." newline bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Selects the FIFO synchronous static RAM type" "2-Port-RAM,SPRAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,Selects the number of RAMs" ",1,2,3" newline bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Selects the number of event buffers in device mode" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,Selects the address space port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,Selects the Request/Response info port width of the master and slave bus interfaces" ",,,,4,5,6,?..." bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Selects the data info port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 3.--5. " DWC_USB3_BURSTWIDTH ,Selects the burst port width of the master and slave bus interfaces - 1" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global Hardware Parameters Register 2" line.long 0x0C "GHWPARAMS3,Global Hardware Parameters Register 3" hexmask.long.word 0x0C 23.--30. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Selects the maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Specifies the maximum number of device mode IN endpoints active at any time" ",,,,4,?..." newline bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Specifies the number of device mode single directional endpoints" ",,,,,,,,8,?..." bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERFACE ,Enables the UTMI+ PHY vendor control interface" "Disabled,Enabled" newline bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Specifies the data width of the UTMI+ PHY interface" ",,8/16-bits,?..." bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,Specifies the high-speed PHY interface" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,Specifies the superSpeed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global Hardware Parameters Register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,Specifies the depth of the BMU-LSP status buffer" ",,,,4,?..." bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,Specifies the depth of the BMU-PTL source/sink buffers-1" ",,,,,,,,8,?..." newline bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enables isochronous endpoint capability" "Disabled,Enabled" bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Specifies the number of SuperSpeed USB bus instances" ",1,?..." newline bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Selects the number of transfer request blocks" ",,,,4,?..." line.long 0x14 "GHWPARAMS5,Global Hardware Parameters Register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor fetch request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor write queue" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,?..." newline bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPTH ,Specifies the size of the BMU Tx request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPTH ,Specifies the size of the BMU Rx request queue" ",,,,,,,,,,,,,,,,16,?..." newline bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Specifies the depth of the BMU-BUSGM source/sink buffer" ",,,,,,,,8,?..." line.long 0x18 "GHWPARAMS6,Global Hardware Parameters Register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Specifies the depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Specifies whether to add a filter for VBUS and ID related control inputs from the PHY" "Not added,Added" newline bitfld.long 0x18 13. " OTG3_0SUPEN ,OTG 3.0 Support Enabled" "Disabled,Enabled" newline bitfld.long 0x18 12. " ADPSUPPORT ,Enables internal ADP capability of the USB 3.0 core" "Disabled,Enabled" newline bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" newline sif !cpuis("LS1088*")&&!cpuis("LS1084A")&&!cpuis("LS1048A")&&!cpuis("LS1044A") bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" newline endif bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" newline bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,Used for FPGA hardware validation of the core" "Not used,Used" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFO_DEPTH ,Specifies the size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global Hardware Parameters Register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Specifies the depth of RAM2" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Specifies the depth of RAM1" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port To Bus Instance Mapping Low Register" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global High-Speed Port To Bus Instance Mapping High Register" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline if (((per.l(ad:0x03100000+0xC118))&0x03)==0x01) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" bitfld.long 0x00 19.--21. " LSIPD ,LS inter-packet time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPHY ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" endif newline group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL0,Global USB 3.0 PIPE Control Register 0" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No reset,Reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSInactive" "P2,P3" newline bitfld.long 0x00 28. " DISRXDETP3 ,Receiver detection in P3 state" "Stays in P3,Goes to P2 then back P3" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,Selects transition from U1/U2 to recovery or SS inactive when U1/U2 LFPS handshake fails" "No effect,Failed" newline sif !cpuis("LS10?3*") bitfld.long 0x00 17. " SUSPENDENABLE ,Suspend USB3.0 SS PHY" "Not suspended,Suspended" newline endif bitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8 bits,?..." bitfld.long 0x00 6. " TXSWING ,TXSWING field" "0,1" newline bitfld.long 0x00 3.--5. " TXMARGIN ,TXMARGIN field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " TXDEEMPHASIS ,Value driven to the PHY is controlled by LTSSM during USB3 compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. " ELASTICBUFFERMODE ,Elastic buffer mode" "0,1" newline group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Transmit FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,TXFIFO 0 depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Transmit FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,TXFIFO 1 depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Transmit FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,TXFIFO 2 depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Transmit FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,TXFIFO 3 depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Receive FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,RXFIFO 0 depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Receive FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,RXFIFO 1 depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Receive FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,RXFIFO 2 depth" group.long 0xC3B0++0x03 line.long 0x00 "GRXFIFOSIZ_3,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Receive FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,RXFIFO 3 depth" group.long 0xC400++0x0B line.long 0x00 "GEVNTADRLO,Global Event Buffer Address Register Low" line.long 0x04 "GEVNTADRHI,Global Event Buffer Address Register High" line.long 0x08 "GEVNTSIZ,Global Event Buffer Size Register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 1. " EVNTSIZ ,Event buffer size in bytes" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*")||cpuis("LS1088A") group.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" else rgroup.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" endif rgroup.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register" bitfld.long 0x00 3. " GTXFIFOPRIDEV[3] ,Device TXFIFO 3 priority" "Low,High" bitfld.long 0x00 2. " [2] ,Device TXFIFO 2 priority" "Low,High" newline bitfld.long 0x00 1. " [1] ,Device TXFIFO 1 priority" "Low,High" bitfld.long 0x00 0. " [0] ,Device TXFIFO 0 priority" "Low,High" group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register" bitfld.long 0x00 2. " GTXFIFOPRIHST[2] ,Host TXFIFO 2 priority" "Low,High" bitfld.long 0x00 1. " [1] ,Host TXFIFO 1 priority" "Low,High" newline bitfld.long 0x00 0. " [0] ,Host TXFIFO 0 priority" "Low,High" line.long 0x04 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register" bitfld.long 0x04 2. " GRXFIFOPRIHST[2] ,Host RXFIFO 2 priority" "Low,High" bitfld.long 0x04 1. " [1] ,Host RXFIFO 1 priority" "Low,High" newline bitfld.long 0x04 0. " [0] ,Host RXFIFO 0 priority" "Low,High" if (((per.l.le(ad:0x03100000+0xC110))&0x3000)==0x1000) group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0xC624++0x03 hide.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" endif newline group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,Indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,Selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP" "32,GFLADJ.GFLADJ_30MHZ" newline bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,Value used for frame length adjustment" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496" if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000)&&(((per.l(ad:0x03100000+0xC144))&0x80000000)==0x80000000) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" newline bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,?..." newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS.Disabled,Rx.Detect,SS.Inactive,,Recovery,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" ",,,,,,,,Remote wakeup request,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device Event Enable Register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LMP received event enable" "Disabled,Enabled" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" newline if (((per.l(ad:0x03100000+0xC70C))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in SS mode" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/Reset" bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in HS/FS/LS mode" "On state,,Sleep,Suspend,Disconnected,?..." bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." endif group.long 0xC710++0x07 line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register" line.long 0x04 "DGCMD,Device Generic Command Register" rbitfld.long 0x04 15. " CMDSTATUS[3] ,Command status 3" "Success,Error" rbitfld.long 0x04 14. " [2] ,Command status 2" "Success,Error" newline rbitfld.long 0x04 13. " [1] ,Command status 1" "Success,Error" rbitfld.long 0x04 12. " [0] ,Command status 0" "Success,Error" newline bitfld.long 0x04 10. " CMDACT ,Command active" "Not active,Active" bitfld.long 0x04 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" newline hexmask.long.byte 0x04 0.--7. 1. " CMDTYP ,Command type" group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register" bitfld.long 0x00 7. " USBACTEP[7] ,USB EP3-IN" "Not active,Active" bitfld.long 0x00 6. " [6] ,USB EP3-OUT" "Not active,Active" newline bitfld.long 0x00 5. " [5] ,USB EP2-IN" "Not active,Active" bitfld.long 0x00 4. " [4] ,USB EP2-OUT" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,USB EP1-IN" "Not active,Active" bitfld.long 0x00 2. " [2] ,USB EP1-OUT" "Not active,Active" newline bitfld.long 0x00 1. " [1] ,USB EP0-IN" "Not active,Active" bitfld.long 0x00 0. " [0] ,USB EP0-OUT" "Not active,Active" newline group.long (0xC800+0x0)++0x0F line.long 0x00 "DEPCMDPAR2_0,Device Physical Endpoint-0 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_0,Device Physical Endpoint-0 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_0,Device Physical Endpoint-0 Command Parameter 0 Register" line.long 0x0C "DEPCMD_0,Device Physical Endpoint-0 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x10)++0x0F line.long 0x00 "DEPCMDPAR2_1,Device Physical Endpoint-1 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_1,Device Physical Endpoint-1 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_1,Device Physical Endpoint-1 Command Parameter 0 Register" line.long 0x0C "DEPCMD_1,Device Physical Endpoint-1 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x20)++0x0F line.long 0x00 "DEPCMDPAR2_2,Device Physical Endpoint-2 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_2,Device Physical Endpoint-2 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_2,Device Physical Endpoint-2 Command Parameter 0 Register" line.long 0x0C "DEPCMD_2,Device Physical Endpoint-2 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x30)++0x0F line.long 0x00 "DEPCMDPAR2_3,Device Physical Endpoint-3 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_3,Device Physical Endpoint-3 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_3,Device Physical Endpoint-3 Command Parameter 0 Register" line.long 0x0C "DEPCMD_3,Device Physical Endpoint-3 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x40)++0x0F line.long 0x00 "DEPCMDPAR2_4,Device Physical Endpoint-4 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_4,Device Physical Endpoint-4 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_4,Device Physical Endpoint-4 Command Parameter 0 Register" line.long 0x0C "DEPCMD_4,Device Physical Endpoint-4 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x50)++0x0F line.long 0x00 "DEPCMDPAR2_5,Device Physical Endpoint-5 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_5,Device Physical Endpoint-5 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_5,Device Physical Endpoint-5 Command Parameter 0 Register" line.long 0x0C "DEPCMD_5,Device Physical Endpoint-5 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x60)++0x0F line.long 0x00 "DEPCMDPAR2_6,Device Physical Endpoint-6 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_6,Device Physical Endpoint-6 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_6,Device Physical Endpoint-6 Command Parameter 0 Register" line.long 0x0C "DEPCMD_6,Device Physical Endpoint-6 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x70)++0x0F line.long 0x00 "DEPCMDPAR2_7,Device Physical Endpoint-7 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_7,Device Physical Endpoint-7 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_7,Device Physical Endpoint-7 Command Parameter 0 Register" line.long 0x0C "DEPCMD_7,Device Physical Endpoint-7 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." newline sif !cpuis("LS10?8*")&&!cpuis("LS10?4*") if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x3000) group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,Not masked" newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" else group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,?..." newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" endif group.long 0xCC04++0x03 line.long 0x00 "OCTL,OTG Control Register" bitfld.long 0x00 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x00 5. " PRTPWRCTL ,Port power control" "B-device,A-device" newline bitfld.long 0x00 4. " HNPREQ ,HNP request" "Not requested,Requested" bitfld.long 0x00 3. " SESREQ ,Session request" "Not requested,Requested" newline bitfld.long 0x00 2. " TERMSELDLPULSE ,TermSel dLine pulsing selection" "UTMI_TXVALID,UTMI_TERMSEL" bitfld.long 0x00 1. " DEVSETHNPEN ,Device set RSP/HNP enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HSTSETHNPEN ,Host set RSP/HNP enable" "Disabled,Enabled" if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x3000) if (((per.l(ad:0x03100000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNT ,A-device B-Host end event" "Not set,Set" newline bitfld.long 0x00 19. " OTGADEVHOSTEVNT ,A-device host event" "Not set,Set" bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNT ,A-Dev HNP change event" "Not set,Set" newline bitfld.long 0x00 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not set,Set" bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNT ,B-Device B-Host end event" "Not set,Set" bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNT ,B-device HNP change event" "Not set,Set" newline bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not set,Set" bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif else if (((per.l(ad:0x03100000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" newline rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif endif group.long 0xCC0C++0x03 line.long 0x00 "OEVTEN,OTG Events Enable Register" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x00 23. " HRRCONFNOTIFEVNTEN ,HRRConfNotif event enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " HRRINITNOTIFEVNTEN ,HRRInitNotif event enable" "Disabled,Enabled" bitfld.long 0x00 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-Host end event enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGADEVHOSTEVNTEN ,A-device host event enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNTEN ,A-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-Host end event enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNTEN ,B-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG Status Register" bitfld.long 0x00 13. " DEVRUNSTP ,Reflects the status of the device Run/Stop bit in the DCTL device register" "Stopped,Started" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 4. " PERIPHERALSTATE ,Indicates whether the core is acting as a peripheral or host" "Host,Peripheral" bitfld.long 0x00 3. " XHCIPRTPOWER ,Reflects the PORTSC.PP bit in the xHCI register" "Low,High" newline bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" bitfld.long 0x00 1. " ASESVLD ,VBUS valid" "Not valid,Valid" newline bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" endif group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP Configuration Register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period/Scale down probe period" "0.775 s/12.5 ms,1.55 s/18.75 ms,2.275 s/25 ms,-/31.25 ms" bitfld.long 0x00 28.--29. " PRBDELTA ,Sets the resolution for RTIM value" "1 cycle,2 cycles,3 cycles,4 cycles" newline bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge/Scale down probe discharge" "4 ms/62.5 us,8 ms/125 us,16 ms/250 us,32 ms/500 us" line.long 0x04 "ADPCTL,ADP Control Register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" newline bitfld.long 0x04 26. " ADPEN ,ADP enable" "Disabled,Enabled" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" newline rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP Event Register" eventfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" eventfld.long 0x08 27. " ADPSNSEVNT ,ADP sense event" "Not occurred,Occurred" newline eventfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" eventfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" newline hexmask.long.word 0x08 0.--15. 1. " RTIM ,Captures the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB" line.long 0x0C "ADPEVTEN,ADP Event Enable Register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPSNSEVNTEN ,ADP sense event enable" "Disabled,Enabled" newline bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end tree "USB 2" base ad:0x03110000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability Registers Length And HC Interface Version Number Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters Register 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" newline hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters Register 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad bufs lo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" newline bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS_HI ,Max scratchpad bufs hi" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVICE_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVICE_EXIT_LAT ,U1 device exit latency" newline line.long 0x10 "HCCPARAMS1,Capability Parameters" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "0,1" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "0,1" newline bitfld.long 0x10 9. " SPC ,Short packet capability" "0,1" bitfld.long 0x10 8. " PAE ,Parse all event data" "0,1" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "0,1" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "0,1" newline bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "0,1" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" newline bitfld.long 0x10 1. " BNC ,BW negotiation capability" "0,1" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "0,1" line.long 0x14 "DBOFF,Doorbell Offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELLARRAYOFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime Register Space Offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPACE_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS2,Capability Parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "0,1" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "0,1" newline bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "0,1" bitfld.long 0x1C 2. " FSC ,Force save context capability" "0,1" newline bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "0,1" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "0,1" newline group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " DATWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " INCR256BRSTENA ,NCR256 burst type enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,NCR128 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " INCR64BRSTENA ,NCR64 burst type enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,NCR32 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " INCR16BRSTENA ,NCR16 burst type enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,NCR8 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " INCR4BRSTENA ,NCR4 burst type enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "INCRX,INCR" line.long 0x04 "GSBUSCFG1,Global SoC Bus Configuration Register 1" bitfld.long 0x04 12. " EN1KPAGE ,1k page boundary enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--11. " PIPETRANSLIMIT ,AXI pipelined transfers burst request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" newline if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) if (((per.l(ad:0x03110000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBURSTSIZE ,USB maximum TX burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x03110000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif elif (((per.l(ad:0x03110000+0xC110))&0x3000)==0x2000) hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" if (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif newline if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03110000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x03110000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global Status Register" sif !cpuis("LS108*")&&!cpuis("LS1044*")&&!cpuis("LS1048*") rbitfld.long 0x00 10. " OTG_IP ,OTG interrupt pending" "Not pending,Pending" newline endif rbitfld.long 0x00 7. " HOST_IP ,HOST interrupt pending" "Not pending,Pending" rbitfld.long 0x00 6. " DEVICE_IP ,Device interrupt pending" "Not pending,Pending" newline bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "No timeout,Timeout" bitfld.long 0x00 4. " BUSERRADDRVLD ,Bus error address valid" "Invalid,Valid" newline rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device,Host,?..." sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000) ; if (((per.l(ad:0x03110000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03110000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03110000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03110000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03110000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03110000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global User ID Register" newline if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 21. " NOEXTRDL ,No extra delay between SOF and the first packet" "Waits 2 us,Doesn't wait" newline bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" bitfld.long 0x00 16. " RESBWHSEPS ,Indicates whether reserve 80% or 85% of bandwidth for HS periodic EPs" "80%,85%" newline bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot ID,Increment address" bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" newline bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" bitfld.long 0x00 9.--10. " DTCT ,Device timeout coarse tuning" "DTFT,500 us,1.5 ms,6.5 ms" newline hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" elif (((per.l(ad:0x03110000+0xC110))&0x3000)==0x2000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" newline bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" else hgroup.long 0xC12C++0x03 hide.long 0x00 "GUCTL,Global User Control Register" endif newline if (((per.l(ad:0x03110000+0xC118))&0x10)==0x01) rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" line.long 0x04 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" else hgroup.long 0xC130++0x03 hide.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" hgroup.long 0xC134++0x03 hide.long 0x00 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" endif group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,SuperSpeed Port To Bus Instance Mapping" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,High-Speed Port To Bus Instance Mapping" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus (register access bus) data bus width" newline hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus (DMA bus) data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus (register access bus) interface type" "AHB,?..." newline bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus (DMA bus) interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global Hardware Parameters Register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "Disabled,Enabled" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Optional features removal enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,Specifies whether the RAM clock and the Bus clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 27. " DWC_USB3_MAC_RAM_CLKS_SYNC ,Specifies whether the MAC clock and the RAM clock are synchronous to each other" "Asynchronous,Synchronous" newline bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,Specifies whether the MAC clock and the PHY clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Specifies the power optimization mode" "No power optimization,Clock gating only,?..." newline bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Selects the FIFO synchronous static RAM type" "2-Port-RAM,SPRAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,Selects the number of RAMs" ",1,2,3" newline bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Selects the number of event buffers in device mode" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,Selects the address space port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,Selects the Request/Response info port width of the master and slave bus interfaces" ",,,,4,5,6,?..." bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Selects the data info port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 3.--5. " DWC_USB3_BURSTWIDTH ,Selects the burst port width of the master and slave bus interfaces - 1" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global Hardware Parameters Register 2" line.long 0x0C "GHWPARAMS3,Global Hardware Parameters Register 3" hexmask.long.word 0x0C 23.--30. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Selects the maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Specifies the maximum number of device mode IN endpoints active at any time" ",,,,4,?..." newline bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Specifies the number of device mode single directional endpoints" ",,,,,,,,8,?..." bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERFACE ,Enables the UTMI+ PHY vendor control interface" "Disabled,Enabled" newline bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Specifies the data width of the UTMI+ PHY interface" ",,8/16-bits,?..." bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,Specifies the high-speed PHY interface" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,Specifies the superSpeed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global Hardware Parameters Register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,Specifies the depth of the BMU-LSP status buffer" ",,,,4,?..." bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,Specifies the depth of the BMU-PTL source/sink buffers-1" ",,,,,,,,8,?..." newline bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enables isochronous endpoint capability" "Disabled,Enabled" bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Specifies the number of SuperSpeed USB bus instances" ",1,?..." newline bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Selects the number of transfer request blocks" ",,,,4,?..." line.long 0x14 "GHWPARAMS5,Global Hardware Parameters Register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor fetch request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor write queue" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,?..." newline bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPTH ,Specifies the size of the BMU Tx request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPTH ,Specifies the size of the BMU Rx request queue" ",,,,,,,,,,,,,,,,16,?..." newline bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Specifies the depth of the BMU-BUSGM source/sink buffer" ",,,,,,,,8,?..." line.long 0x18 "GHWPARAMS6,Global Hardware Parameters Register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Specifies the depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Specifies whether to add a filter for VBUS and ID related control inputs from the PHY" "Not added,Added" newline bitfld.long 0x18 13. " OTG3_0SUPEN ,OTG 3.0 Support Enabled" "Disabled,Enabled" newline bitfld.long 0x18 12. " ADPSUPPORT ,Enables internal ADP capability of the USB 3.0 core" "Disabled,Enabled" newline bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" newline sif !cpuis("LS1088*")&&!cpuis("LS1084A")&&!cpuis("LS1048A")&&!cpuis("LS1044A") bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" newline endif bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" newline bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,Used for FPGA hardware validation of the core" "Not used,Used" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFO_DEPTH ,Specifies the size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global Hardware Parameters Register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Specifies the depth of RAM2" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Specifies the depth of RAM1" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port To Bus Instance Mapping Low Register" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global High-Speed Port To Bus Instance Mapping High Register" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline if (((per.l(ad:0x03110000+0xC118))&0x03)==0x01) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" bitfld.long 0x00 19.--21. " LSIPD ,LS inter-packet time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPHY ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" endif newline group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL0,Global USB 3.0 PIPE Control Register 0" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No reset,Reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSInactive" "P2,P3" newline bitfld.long 0x00 28. " DISRXDETP3 ,Receiver detection in P3 state" "Stays in P3,Goes to P2 then back P3" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,Selects transition from U1/U2 to recovery or SS inactive when U1/U2 LFPS handshake fails" "No effect,Failed" newline sif !cpuis("LS10?3*") bitfld.long 0x00 17. " SUSPENDENABLE ,Suspend USB3.0 SS PHY" "Not suspended,Suspended" newline endif bitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8 bits,?..." bitfld.long 0x00 6. " TXSWING ,TXSWING field" "0,1" newline bitfld.long 0x00 3.--5. " TXMARGIN ,TXMARGIN field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " TXDEEMPHASIS ,Value driven to the PHY is controlled by LTSSM during USB3 compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. " ELASTICBUFFERMODE ,Elastic buffer mode" "0,1" newline group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Transmit FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,TXFIFO 0 depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Transmit FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,TXFIFO 1 depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Transmit FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,TXFIFO 2 depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Transmit FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,TXFIFO 3 depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Receive FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,RXFIFO 0 depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Receive FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,RXFIFO 1 depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Receive FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,RXFIFO 2 depth" group.long 0xC3B0++0x03 line.long 0x00 "GRXFIFOSIZ_3,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Receive FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,RXFIFO 3 depth" group.long 0xC400++0x0B line.long 0x00 "GEVNTADRLO,Global Event Buffer Address Register Low" line.long 0x04 "GEVNTADRHI,Global Event Buffer Address Register High" line.long 0x08 "GEVNTSIZ,Global Event Buffer Size Register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 1. " EVNTSIZ ,Event buffer size in bytes" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*")||cpuis("LS1088A") group.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" else rgroup.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" endif rgroup.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register" bitfld.long 0x00 3. " GTXFIFOPRIDEV[3] ,Device TXFIFO 3 priority" "Low,High" bitfld.long 0x00 2. " [2] ,Device TXFIFO 2 priority" "Low,High" newline bitfld.long 0x00 1. " [1] ,Device TXFIFO 1 priority" "Low,High" bitfld.long 0x00 0. " [0] ,Device TXFIFO 0 priority" "Low,High" group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register" bitfld.long 0x00 2. " GTXFIFOPRIHST[2] ,Host TXFIFO 2 priority" "Low,High" bitfld.long 0x00 1. " [1] ,Host TXFIFO 1 priority" "Low,High" newline bitfld.long 0x00 0. " [0] ,Host TXFIFO 0 priority" "Low,High" line.long 0x04 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register" bitfld.long 0x04 2. " GRXFIFOPRIHST[2] ,Host RXFIFO 2 priority" "Low,High" bitfld.long 0x04 1. " [1] ,Host RXFIFO 1 priority" "Low,High" newline bitfld.long 0x04 0. " [0] ,Host RXFIFO 0 priority" "Low,High" if (((per.l.le(ad:0x03110000+0xC110))&0x3000)==0x1000) group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0xC624++0x03 hide.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" endif newline group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,Indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,Selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP" "32,GFLADJ.GFLADJ_30MHZ" newline bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,Value used for frame length adjustment" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496" if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x1000)&&(((per.l(ad:0x03110000+0xC144))&0x80000000)==0x80000000) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" newline bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x03110000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,?..." newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS.Disabled,Rx.Detect,SS.Inactive,,Recovery,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" ",,,,,,,,Remote wakeup request,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device Event Enable Register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LMP received event enable" "Disabled,Enabled" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" newline if (((per.l(ad:0x03110000+0xC70C))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in SS mode" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/Reset" bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in HS/FS/LS mode" "On state,,Sleep,Suspend,Disconnected,?..." bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." endif group.long 0xC710++0x07 line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register" line.long 0x04 "DGCMD,Device Generic Command Register" rbitfld.long 0x04 15. " CMDSTATUS[3] ,Command status 3" "Success,Error" rbitfld.long 0x04 14. " [2] ,Command status 2" "Success,Error" newline rbitfld.long 0x04 13. " [1] ,Command status 1" "Success,Error" rbitfld.long 0x04 12. " [0] ,Command status 0" "Success,Error" newline bitfld.long 0x04 10. " CMDACT ,Command active" "Not active,Active" bitfld.long 0x04 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" newline hexmask.long.byte 0x04 0.--7. 1. " CMDTYP ,Command type" group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register" bitfld.long 0x00 7. " USBACTEP[7] ,USB EP3-IN" "Not active,Active" bitfld.long 0x00 6. " [6] ,USB EP3-OUT" "Not active,Active" newline bitfld.long 0x00 5. " [5] ,USB EP2-IN" "Not active,Active" bitfld.long 0x00 4. " [4] ,USB EP2-OUT" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,USB EP1-IN" "Not active,Active" bitfld.long 0x00 2. " [2] ,USB EP1-OUT" "Not active,Active" newline bitfld.long 0x00 1. " [1] ,USB EP0-IN" "Not active,Active" bitfld.long 0x00 0. " [0] ,USB EP0-OUT" "Not active,Active" newline group.long (0xC800+0x0)++0x0F line.long 0x00 "DEPCMDPAR2_0,Device Physical Endpoint-0 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_0,Device Physical Endpoint-0 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_0,Device Physical Endpoint-0 Command Parameter 0 Register" line.long 0x0C "DEPCMD_0,Device Physical Endpoint-0 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x10)++0x0F line.long 0x00 "DEPCMDPAR2_1,Device Physical Endpoint-1 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_1,Device Physical Endpoint-1 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_1,Device Physical Endpoint-1 Command Parameter 0 Register" line.long 0x0C "DEPCMD_1,Device Physical Endpoint-1 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x20)++0x0F line.long 0x00 "DEPCMDPAR2_2,Device Physical Endpoint-2 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_2,Device Physical Endpoint-2 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_2,Device Physical Endpoint-2 Command Parameter 0 Register" line.long 0x0C "DEPCMD_2,Device Physical Endpoint-2 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x30)++0x0F line.long 0x00 "DEPCMDPAR2_3,Device Physical Endpoint-3 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_3,Device Physical Endpoint-3 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_3,Device Physical Endpoint-3 Command Parameter 0 Register" line.long 0x0C "DEPCMD_3,Device Physical Endpoint-3 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x40)++0x0F line.long 0x00 "DEPCMDPAR2_4,Device Physical Endpoint-4 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_4,Device Physical Endpoint-4 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_4,Device Physical Endpoint-4 Command Parameter 0 Register" line.long 0x0C "DEPCMD_4,Device Physical Endpoint-4 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x50)++0x0F line.long 0x00 "DEPCMDPAR2_5,Device Physical Endpoint-5 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_5,Device Physical Endpoint-5 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_5,Device Physical Endpoint-5 Command Parameter 0 Register" line.long 0x0C "DEPCMD_5,Device Physical Endpoint-5 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x60)++0x0F line.long 0x00 "DEPCMDPAR2_6,Device Physical Endpoint-6 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_6,Device Physical Endpoint-6 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_6,Device Physical Endpoint-6 Command Parameter 0 Register" line.long 0x0C "DEPCMD_6,Device Physical Endpoint-6 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x70)++0x0F line.long 0x00 "DEPCMDPAR2_7,Device Physical Endpoint-7 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_7,Device Physical Endpoint-7 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_7,Device Physical Endpoint-7 Command Parameter 0 Register" line.long 0x0C "DEPCMD_7,Device Physical Endpoint-7 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." newline sif !cpuis("LS10?8*")&&!cpuis("LS10?4*") if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x3000) group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,Not masked" newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" else group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,?..." newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" endif group.long 0xCC04++0x03 line.long 0x00 "OCTL,OTG Control Register" bitfld.long 0x00 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x00 5. " PRTPWRCTL ,Port power control" "B-device,A-device" newline bitfld.long 0x00 4. " HNPREQ ,HNP request" "Not requested,Requested" bitfld.long 0x00 3. " SESREQ ,Session request" "Not requested,Requested" newline bitfld.long 0x00 2. " TERMSELDLPULSE ,TermSel dLine pulsing selection" "UTMI_TXVALID,UTMI_TERMSEL" bitfld.long 0x00 1. " DEVSETHNPEN ,Device set RSP/HNP enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HSTSETHNPEN ,Host set RSP/HNP enable" "Disabled,Enabled" if (((per.l(ad:0x03110000+0xC110))&0x3000)==0x3000) if (((per.l(ad:0x03110000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNT ,A-device B-Host end event" "Not set,Set" newline bitfld.long 0x00 19. " OTGADEVHOSTEVNT ,A-device host event" "Not set,Set" bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNT ,A-Dev HNP change event" "Not set,Set" newline bitfld.long 0x00 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not set,Set" bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNT ,B-Device B-Host end event" "Not set,Set" bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNT ,B-device HNP change event" "Not set,Set" newline bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not set,Set" bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif else if (((per.l(ad:0x03110000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" newline rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif endif group.long 0xCC0C++0x03 line.long 0x00 "OEVTEN,OTG Events Enable Register" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x00 23. " HRRCONFNOTIFEVNTEN ,HRRConfNotif event enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " HRRINITNOTIFEVNTEN ,HRRInitNotif event enable" "Disabled,Enabled" bitfld.long 0x00 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-Host end event enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGADEVHOSTEVNTEN ,A-device host event enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNTEN ,A-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-Host end event enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNTEN ,B-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG Status Register" bitfld.long 0x00 13. " DEVRUNSTP ,Reflects the status of the device Run/Stop bit in the DCTL device register" "Stopped,Started" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 4. " PERIPHERALSTATE ,Indicates whether the core is acting as a peripheral or host" "Host,Peripheral" bitfld.long 0x00 3. " XHCIPRTPOWER ,Reflects the PORTSC.PP bit in the xHCI register" "Low,High" newline bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" bitfld.long 0x00 1. " ASESVLD ,VBUS valid" "Not valid,Valid" newline bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" endif group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP Configuration Register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period/Scale down probe period" "0.775 s/12.5 ms,1.55 s/18.75 ms,2.275 s/25 ms,-/31.25 ms" bitfld.long 0x00 28.--29. " PRBDELTA ,Sets the resolution for RTIM value" "1 cycle,2 cycles,3 cycles,4 cycles" newline bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge/Scale down probe discharge" "4 ms/62.5 us,8 ms/125 us,16 ms/250 us,32 ms/500 us" line.long 0x04 "ADPCTL,ADP Control Register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" newline bitfld.long 0x04 26. " ADPEN ,ADP enable" "Disabled,Enabled" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" newline rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP Event Register" eventfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" eventfld.long 0x08 27. " ADPSNSEVNT ,ADP sense event" "Not occurred,Occurred" newline eventfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" eventfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" newline hexmask.long.word 0x08 0.--15. 1. " RTIM ,Captures the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB" line.long 0x0C "ADPEVTEN,ADP Event Enable Register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPSNSEVNTEN ,ADP sense event enable" "Disabled,Enabled" newline bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end tree.end elif cpuis("LS10?3*")||cpuis("LS1012*")||cpuis("LS10?6*") tree "USB 3.0 (Universal Serial Bus Interface 3.0)" tree "USB 1" base ad:0x02F00000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability Registers Length And HC Interface Version Number Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters Register 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" newline hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters Register 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad bufs lo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" newline bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS_HI ,Max scratchpad bufs hi" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVICE_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVICE_EXIT_LAT ,U1 device exit latency" newline line.long 0x10 "HCCPARAMS1,Capability Parameters" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "0,1" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "0,1" newline bitfld.long 0x10 9. " SPC ,Short packet capability" "0,1" bitfld.long 0x10 8. " PAE ,Parse all event data" "0,1" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "0,1" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "0,1" newline bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "0,1" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" newline bitfld.long 0x10 1. " BNC ,BW negotiation capability" "0,1" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "0,1" line.long 0x14 "DBOFF,Doorbell Offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELLARRAYOFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime Register Space Offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPACE_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS2,Capability Parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "0,1" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "0,1" newline bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "0,1" bitfld.long 0x1C 2. " FSC ,Force save context capability" "0,1" newline bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "0,1" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "0,1" newline group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " DATWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " INCR256BRSTENA ,NCR256 burst type enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,NCR128 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " INCR64BRSTENA ,NCR64 burst type enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,NCR32 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " INCR16BRSTENA ,NCR16 burst type enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,NCR8 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " INCR4BRSTENA ,NCR4 burst type enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "INCRX,INCR" line.long 0x04 "GSBUSCFG1,Global SoC Bus Configuration Register 1" bitfld.long 0x04 12. " EN1KPAGE ,1k page boundary enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--11. " PIPETRANSLIMIT ,AXI pipelined transfers burst request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" newline if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) if (((per.l(ad:0x02F00000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBURSTSIZE ,USB maximum TX burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x02F00000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif elif (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x2000) hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif newline if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x02F00000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x02F00000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global Status Register" sif !cpuis("LS108*")&&!cpuis("LS1044*")&&!cpuis("LS1048*") rbitfld.long 0x00 10. " OTG_IP ,OTG interrupt pending" "Not pending,Pending" newline endif rbitfld.long 0x00 7. " HOST_IP ,HOST interrupt pending" "Not pending,Pending" rbitfld.long 0x00 6. " DEVICE_IP ,Device interrupt pending" "Not pending,Pending" newline bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "No timeout,Timeout" bitfld.long 0x00 4. " BUSERRADDRVLD ,Bus error address valid" "Invalid,Valid" newline rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device,Host,?..." sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000) ; if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global User ID Register" newline if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 21. " NOEXTRDL ,No extra delay between SOF and the first packet" "Waits 2 us,Doesn't wait" newline bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" bitfld.long 0x00 16. " RESBWHSEPS ,Indicates whether reserve 80% or 85% of bandwidth for HS periodic EPs" "80%,85%" newline bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot ID,Increment address" bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" newline bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" bitfld.long 0x00 9.--10. " DTCT ,Device timeout coarse tuning" "DTFT,500 us,1.5 ms,6.5 ms" newline hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" elif (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x2000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" newline bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" else hgroup.long 0xC12C++0x03 hide.long 0x00 "GUCTL,Global User Control Register" endif newline if (((per.l(ad:0x02F00000+0xC118))&0x10)==0x01) rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" line.long 0x04 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" else hgroup.long 0xC130++0x03 hide.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" hgroup.long 0xC134++0x03 hide.long 0x00 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" endif group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,SuperSpeed Port To Bus Instance Mapping" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,High-Speed Port To Bus Instance Mapping" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus (register access bus) data bus width" newline hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus (DMA bus) data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus (register access bus) interface type" "AHB,?..." newline bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus (DMA bus) interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global Hardware Parameters Register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "Disabled,Enabled" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Optional features removal enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,Specifies whether the RAM clock and the Bus clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 27. " DWC_USB3_MAC_RAM_CLKS_SYNC ,Specifies whether the MAC clock and the RAM clock are synchronous to each other" "Asynchronous,Synchronous" newline bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,Specifies whether the MAC clock and the PHY clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Specifies the power optimization mode" "No power optimization,Clock gating only,?..." newline bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Selects the FIFO synchronous static RAM type" "2-Port-RAM,SPRAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,Selects the number of RAMs" ",1,2,3" newline bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Selects the number of event buffers in device mode" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,Selects the address space port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,Selects the Request/Response info port width of the master and slave bus interfaces" ",,,,4,5,6,?..." bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Selects the data info port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 3.--5. " DWC_USB3_BURSTWIDTH ,Selects the burst port width of the master and slave bus interfaces - 1" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global Hardware Parameters Register 2" line.long 0x0C "GHWPARAMS3,Global Hardware Parameters Register 3" hexmask.long.word 0x0C 23.--30. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Selects the maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Specifies the maximum number of device mode IN endpoints active at any time" ",,,,4,?..." newline bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Specifies the number of device mode single directional endpoints" ",,,,,,,,8,?..." bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERFACE ,Enables the UTMI+ PHY vendor control interface" "Disabled,Enabled" newline bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Specifies the data width of the UTMI+ PHY interface" ",,8/16-bits,?..." bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,Specifies the high-speed PHY interface" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,Specifies the superSpeed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global Hardware Parameters Register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,Specifies the depth of the BMU-LSP status buffer" ",,,,4,?..." bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,Specifies the depth of the BMU-PTL source/sink buffers-1" ",,,,,,,,8,?..." newline bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enables isochronous endpoint capability" "Disabled,Enabled" bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Specifies the number of SuperSpeed USB bus instances" ",1,?..." newline bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Selects the number of transfer request blocks" ",,,,4,?..." line.long 0x14 "GHWPARAMS5,Global Hardware Parameters Register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor fetch request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor write queue" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,?..." newline bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPTH ,Specifies the size of the BMU Tx request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPTH ,Specifies the size of the BMU Rx request queue" ",,,,,,,,,,,,,,,,16,?..." newline bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Specifies the depth of the BMU-BUSGM source/sink buffer" ",,,,,,,,8,?..." line.long 0x18 "GHWPARAMS6,Global Hardware Parameters Register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Specifies the depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Specifies whether to add a filter for VBUS and ID related control inputs from the PHY" "Not added,Added" newline bitfld.long 0x18 13. " OTG3_0SUPEN ,OTG 3.0 Support Enabled" "Disabled,Enabled" newline bitfld.long 0x18 12. " ADPSUPPORT ,Enables internal ADP capability of the USB 3.0 core" "Disabled,Enabled" newline bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" newline sif !cpuis("LS1088*")&&!cpuis("LS1084A")&&!cpuis("LS1048A")&&!cpuis("LS1044A") bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" newline endif bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" newline bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,Used for FPGA hardware validation of the core" "Not used,Used" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFO_DEPTH ,Specifies the size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global Hardware Parameters Register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Specifies the depth of RAM2" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Specifies the depth of RAM1" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port To Bus Instance Mapping Low Register" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global High-Speed Port To Bus Instance Mapping High Register" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline if (((per.l(ad:0x02F00000+0xC118))&0x03)==0x01) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" bitfld.long 0x00 19.--21. " LSIPD ,LS inter-packet time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPHY ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" endif newline group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL0,Global USB 3.0 PIPE Control Register 0" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No reset,Reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSInactive" "P2,P3" newline bitfld.long 0x00 28. " DISRXDETP3 ,Receiver detection in P3 state" "Stays in P3,Goes to P2 then back P3" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,Selects transition from U1/U2 to recovery or SS inactive when U1/U2 LFPS handshake fails" "No effect,Failed" newline sif !cpuis("LS10?3*") bitfld.long 0x00 17. " SUSPENDENABLE ,Suspend USB3.0 SS PHY" "Not suspended,Suspended" newline endif bitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8 bits,?..." bitfld.long 0x00 6. " TXSWING ,TXSWING field" "0,1" newline bitfld.long 0x00 3.--5. " TXMARGIN ,TXMARGIN field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " TXDEEMPHASIS ,Value driven to the PHY is controlled by LTSSM during USB3 compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. " ELASTICBUFFERMODE ,Elastic buffer mode" "0,1" newline group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Transmit FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,TXFIFO 0 depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Transmit FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,TXFIFO 1 depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Transmit FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,TXFIFO 2 depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Transmit FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,TXFIFO 3 depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Receive FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,RXFIFO 0 depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Receive FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,RXFIFO 1 depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Receive FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,RXFIFO 2 depth" group.long 0xC3B0++0x03 line.long 0x00 "GRXFIFOSIZ_3,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Receive FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,RXFIFO 3 depth" group.long 0xC400++0x0B line.long 0x00 "GEVNTADRLO,Global Event Buffer Address Register Low" line.long 0x04 "GEVNTADRHI,Global Event Buffer Address Register High" line.long 0x08 "GEVNTSIZ,Global Event Buffer Size Register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 1. " EVNTSIZ ,Event buffer size in bytes" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*")||cpuis("LS1088A") group.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" else rgroup.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" endif rgroup.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register" bitfld.long 0x00 3. " GTXFIFOPRIDEV[3] ,Device TXFIFO 3 priority" "Low,High" bitfld.long 0x00 2. " [2] ,Device TXFIFO 2 priority" "Low,High" newline bitfld.long 0x00 1. " [1] ,Device TXFIFO 1 priority" "Low,High" bitfld.long 0x00 0. " [0] ,Device TXFIFO 0 priority" "Low,High" group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register" bitfld.long 0x00 2. " GTXFIFOPRIHST[2] ,Host TXFIFO 2 priority" "Low,High" bitfld.long 0x00 1. " [1] ,Host TXFIFO 1 priority" "Low,High" newline bitfld.long 0x00 0. " [0] ,Host TXFIFO 0 priority" "Low,High" line.long 0x04 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register" bitfld.long 0x04 2. " GRXFIFOPRIHST[2] ,Host RXFIFO 2 priority" "Low,High" bitfld.long 0x04 1. " [1] ,Host RXFIFO 1 priority" "Low,High" newline bitfld.long 0x04 0. " [0] ,Host RXFIFO 0 priority" "Low,High" if (((per.l.le(ad:0x02F00000+0xC110))&0x3000)==0x1000) group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0xC624++0x03 hide.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" endif newline group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,Indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,Selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP" "32,GFLADJ.GFLADJ_30MHZ" newline bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,Value used for frame length adjustment" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496" if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x1000)&&(((per.l(ad:0x02F00000+0xC144))&0x80000000)==0x80000000) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" newline bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x02F00000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,?..." newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS.Disabled,Rx.Detect,SS.Inactive,,Recovery,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" ",,,,,,,,Remote wakeup request,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device Event Enable Register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LMP received event enable" "Disabled,Enabled" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" newline if (((per.l(ad:0x02F00000+0xC70C))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in SS mode" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/Reset" bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in HS/FS/LS mode" "On state,,Sleep,Suspend,Disconnected,?..." bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." endif group.long 0xC710++0x07 line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register" line.long 0x04 "DGCMD,Device Generic Command Register" rbitfld.long 0x04 15. " CMDSTATUS[3] ,Command status 3" "Success,Error" rbitfld.long 0x04 14. " [2] ,Command status 2" "Success,Error" newline rbitfld.long 0x04 13. " [1] ,Command status 1" "Success,Error" rbitfld.long 0x04 12. " [0] ,Command status 0" "Success,Error" newline bitfld.long 0x04 10. " CMDACT ,Command active" "Not active,Active" bitfld.long 0x04 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" newline hexmask.long.byte 0x04 0.--7. 1. " CMDTYP ,Command type" group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register" bitfld.long 0x00 7. " USBACTEP[7] ,USB EP3-IN" "Not active,Active" bitfld.long 0x00 6. " [6] ,USB EP3-OUT" "Not active,Active" newline bitfld.long 0x00 5. " [5] ,USB EP2-IN" "Not active,Active" bitfld.long 0x00 4. " [4] ,USB EP2-OUT" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,USB EP1-IN" "Not active,Active" bitfld.long 0x00 2. " [2] ,USB EP1-OUT" "Not active,Active" newline bitfld.long 0x00 1. " [1] ,USB EP0-IN" "Not active,Active" bitfld.long 0x00 0. " [0] ,USB EP0-OUT" "Not active,Active" newline group.long (0xC800+0x0)++0x0F line.long 0x00 "DEPCMDPAR2_0,Device Physical Endpoint-0 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_0,Device Physical Endpoint-0 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_0,Device Physical Endpoint-0 Command Parameter 0 Register" line.long 0x0C "DEPCMD_0,Device Physical Endpoint-0 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x10)++0x0F line.long 0x00 "DEPCMDPAR2_1,Device Physical Endpoint-1 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_1,Device Physical Endpoint-1 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_1,Device Physical Endpoint-1 Command Parameter 0 Register" line.long 0x0C "DEPCMD_1,Device Physical Endpoint-1 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x20)++0x0F line.long 0x00 "DEPCMDPAR2_2,Device Physical Endpoint-2 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_2,Device Physical Endpoint-2 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_2,Device Physical Endpoint-2 Command Parameter 0 Register" line.long 0x0C "DEPCMD_2,Device Physical Endpoint-2 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x30)++0x0F line.long 0x00 "DEPCMDPAR2_3,Device Physical Endpoint-3 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_3,Device Physical Endpoint-3 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_3,Device Physical Endpoint-3 Command Parameter 0 Register" line.long 0x0C "DEPCMD_3,Device Physical Endpoint-3 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x40)++0x0F line.long 0x00 "DEPCMDPAR2_4,Device Physical Endpoint-4 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_4,Device Physical Endpoint-4 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_4,Device Physical Endpoint-4 Command Parameter 0 Register" line.long 0x0C "DEPCMD_4,Device Physical Endpoint-4 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x50)++0x0F line.long 0x00 "DEPCMDPAR2_5,Device Physical Endpoint-5 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_5,Device Physical Endpoint-5 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_5,Device Physical Endpoint-5 Command Parameter 0 Register" line.long 0x0C "DEPCMD_5,Device Physical Endpoint-5 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x60)++0x0F line.long 0x00 "DEPCMDPAR2_6,Device Physical Endpoint-6 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_6,Device Physical Endpoint-6 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_6,Device Physical Endpoint-6 Command Parameter 0 Register" line.long 0x0C "DEPCMD_6,Device Physical Endpoint-6 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x70)++0x0F line.long 0x00 "DEPCMDPAR2_7,Device Physical Endpoint-7 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_7,Device Physical Endpoint-7 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_7,Device Physical Endpoint-7 Command Parameter 0 Register" line.long 0x0C "DEPCMD_7,Device Physical Endpoint-7 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." newline sif !cpuis("LS10?8*")&&!cpuis("LS10?4*") if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x3000) group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,Not masked" newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" else group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,?..." newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" endif group.long 0xCC04++0x03 line.long 0x00 "OCTL,OTG Control Register" bitfld.long 0x00 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x00 5. " PRTPWRCTL ,Port power control" "B-device,A-device" newline bitfld.long 0x00 4. " HNPREQ ,HNP request" "Not requested,Requested" bitfld.long 0x00 3. " SESREQ ,Session request" "Not requested,Requested" newline bitfld.long 0x00 2. " TERMSELDLPULSE ,TermSel dLine pulsing selection" "UTMI_TXVALID,UTMI_TERMSEL" bitfld.long 0x00 1. " DEVSETHNPEN ,Device set RSP/HNP enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HSTSETHNPEN ,Host set RSP/HNP enable" "Disabled,Enabled" if (((per.l(ad:0x02F00000+0xC110))&0x3000)==0x3000) if (((per.l(ad:0x02F00000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNT ,A-device B-Host end event" "Not set,Set" newline bitfld.long 0x00 19. " OTGADEVHOSTEVNT ,A-device host event" "Not set,Set" bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNT ,A-Dev HNP change event" "Not set,Set" newline bitfld.long 0x00 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not set,Set" bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNT ,B-Device B-Host end event" "Not set,Set" bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNT ,B-device HNP change event" "Not set,Set" newline bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not set,Set" bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif else if (((per.l(ad:0x02F00000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" newline rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif endif group.long 0xCC0C++0x03 line.long 0x00 "OEVTEN,OTG Events Enable Register" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x00 23. " HRRCONFNOTIFEVNTEN ,HRRConfNotif event enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " HRRINITNOTIFEVNTEN ,HRRInitNotif event enable" "Disabled,Enabled" bitfld.long 0x00 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-Host end event enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGADEVHOSTEVNTEN ,A-device host event enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNTEN ,A-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-Host end event enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNTEN ,B-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG Status Register" bitfld.long 0x00 13. " DEVRUNSTP ,Reflects the status of the device Run/Stop bit in the DCTL device register" "Stopped,Started" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 4. " PERIPHERALSTATE ,Indicates whether the core is acting as a peripheral or host" "Host,Peripheral" bitfld.long 0x00 3. " XHCIPRTPOWER ,Reflects the PORTSC.PP bit in the xHCI register" "Low,High" newline bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" bitfld.long 0x00 1. " ASESVLD ,VBUS valid" "Not valid,Valid" newline bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" endif group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP Configuration Register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period/Scale down probe period" "0.775 s/12.5 ms,1.55 s/18.75 ms,2.275 s/25 ms,-/31.25 ms" bitfld.long 0x00 28.--29. " PRBDELTA ,Sets the resolution for RTIM value" "1 cycle,2 cycles,3 cycles,4 cycles" newline bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge/Scale down probe discharge" "4 ms/62.5 us,8 ms/125 us,16 ms/250 us,32 ms/500 us" line.long 0x04 "ADPCTL,ADP Control Register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" newline bitfld.long 0x04 26. " ADPEN ,ADP enable" "Disabled,Enabled" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" newline rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP Event Register" eventfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" eventfld.long 0x08 27. " ADPSNSEVNT ,ADP sense event" "Not occurred,Occurred" newline eventfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" eventfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" newline hexmask.long.word 0x08 0.--15. 1. " RTIM ,Captures the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB" line.long 0x0C "ADPEVTEN,ADP Event Enable Register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPSNSEVNTEN ,ADP sense event enable" "Disabled,Enabled" newline bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end sif cpuis("LS10?3*") tree "USB 2" base ad:0x03000000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability Registers Length And HC Interface Version Number Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters Register 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" newline hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters Register 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad bufs lo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" newline bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS_HI ,Max scratchpad bufs hi" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVICE_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVICE_EXIT_LAT ,U1 device exit latency" newline line.long 0x10 "HCCPARAMS1,Capability Parameters" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "0,1" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "0,1" newline bitfld.long 0x10 9. " SPC ,Short packet capability" "0,1" bitfld.long 0x10 8. " PAE ,Parse all event data" "0,1" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "0,1" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "0,1" newline bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "0,1" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" newline bitfld.long 0x10 1. " BNC ,BW negotiation capability" "0,1" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "0,1" line.long 0x14 "DBOFF,Doorbell Offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELLARRAYOFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime Register Space Offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPACE_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS2,Capability Parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "0,1" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "0,1" newline bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "0,1" bitfld.long 0x1C 2. " FSC ,Force save context capability" "0,1" newline bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "0,1" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "0,1" newline group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " DATWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " INCR256BRSTENA ,NCR256 burst type enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,NCR128 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " INCR64BRSTENA ,NCR64 burst type enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,NCR32 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " INCR16BRSTENA ,NCR16 burst type enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,NCR8 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " INCR4BRSTENA ,NCR4 burst type enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "INCRX,INCR" line.long 0x04 "GSBUSCFG1,Global SoC Bus Configuration Register 1" bitfld.long 0x04 12. " EN1KPAGE ,1k page boundary enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--11. " PIPETRANSLIMIT ,AXI pipelined transfers burst request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" newline if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) if (((per.l(ad:0x03000000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBURSTSIZE ,USB maximum TX burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x03000000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif elif (((per.l(ad:0x03000000+0xC110))&0x3000)==0x2000) hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" if (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif newline if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03000000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x03000000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global Status Register" sif !cpuis("LS108*")&&!cpuis("LS1044*")&&!cpuis("LS1048*") rbitfld.long 0x00 10. " OTG_IP ,OTG interrupt pending" "Not pending,Pending" newline endif rbitfld.long 0x00 7. " HOST_IP ,HOST interrupt pending" "Not pending,Pending" rbitfld.long 0x00 6. " DEVICE_IP ,Device interrupt pending" "Not pending,Pending" newline bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "No timeout,Timeout" bitfld.long 0x00 4. " BUSERRADDRVLD ,Bus error address valid" "Invalid,Valid" newline rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device,Host,?..." sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000) ; if (((per.l(ad:0x03000000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03000000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03000000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03000000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03000000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03000000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global User ID Register" newline if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 21. " NOEXTRDL ,No extra delay between SOF and the first packet" "Waits 2 us,Doesn't wait" newline bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" bitfld.long 0x00 16. " RESBWHSEPS ,Indicates whether reserve 80% or 85% of bandwidth for HS periodic EPs" "80%,85%" newline bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot ID,Increment address" bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" newline bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" bitfld.long 0x00 9.--10. " DTCT ,Device timeout coarse tuning" "DTFT,500 us,1.5 ms,6.5 ms" newline hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" elif (((per.l(ad:0x03000000+0xC110))&0x3000)==0x2000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" newline bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" else hgroup.long 0xC12C++0x03 hide.long 0x00 "GUCTL,Global User Control Register" endif newline if (((per.l(ad:0x03000000+0xC118))&0x10)==0x01) rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" line.long 0x04 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" else hgroup.long 0xC130++0x03 hide.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" hgroup.long 0xC134++0x03 hide.long 0x00 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" endif group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,SuperSpeed Port To Bus Instance Mapping" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,High-Speed Port To Bus Instance Mapping" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus (register access bus) data bus width" newline hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus (DMA bus) data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus (register access bus) interface type" "AHB,?..." newline bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus (DMA bus) interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global Hardware Parameters Register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "Disabled,Enabled" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Optional features removal enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,Specifies whether the RAM clock and the Bus clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 27. " DWC_USB3_MAC_RAM_CLKS_SYNC ,Specifies whether the MAC clock and the RAM clock are synchronous to each other" "Asynchronous,Synchronous" newline bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,Specifies whether the MAC clock and the PHY clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Specifies the power optimization mode" "No power optimization,Clock gating only,?..." newline bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Selects the FIFO synchronous static RAM type" "2-Port-RAM,SPRAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,Selects the number of RAMs" ",1,2,3" newline bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Selects the number of event buffers in device mode" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,Selects the address space port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,Selects the Request/Response info port width of the master and slave bus interfaces" ",,,,4,5,6,?..." bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Selects the data info port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 3.--5. " DWC_USB3_BURSTWIDTH ,Selects the burst port width of the master and slave bus interfaces - 1" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global Hardware Parameters Register 2" line.long 0x0C "GHWPARAMS3,Global Hardware Parameters Register 3" hexmask.long.word 0x0C 23.--30. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Selects the maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Specifies the maximum number of device mode IN endpoints active at any time" ",,,,4,?..." newline bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Specifies the number of device mode single directional endpoints" ",,,,,,,,8,?..." bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERFACE ,Enables the UTMI+ PHY vendor control interface" "Disabled,Enabled" newline bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Specifies the data width of the UTMI+ PHY interface" ",,8/16-bits,?..." bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,Specifies the high-speed PHY interface" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,Specifies the superSpeed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global Hardware Parameters Register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,Specifies the depth of the BMU-LSP status buffer" ",,,,4,?..." bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,Specifies the depth of the BMU-PTL source/sink buffers-1" ",,,,,,,,8,?..." newline bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enables isochronous endpoint capability" "Disabled,Enabled" bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Specifies the number of SuperSpeed USB bus instances" ",1,?..." newline bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Selects the number of transfer request blocks" ",,,,4,?..." line.long 0x14 "GHWPARAMS5,Global Hardware Parameters Register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor fetch request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor write queue" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,?..." newline bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPTH ,Specifies the size of the BMU Tx request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPTH ,Specifies the size of the BMU Rx request queue" ",,,,,,,,,,,,,,,,16,?..." newline bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Specifies the depth of the BMU-BUSGM source/sink buffer" ",,,,,,,,8,?..." line.long 0x18 "GHWPARAMS6,Global Hardware Parameters Register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Specifies the depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Specifies whether to add a filter for VBUS and ID related control inputs from the PHY" "Not added,Added" newline bitfld.long 0x18 13. " OTG3_0SUPEN ,OTG 3.0 Support Enabled" "Disabled,Enabled" newline bitfld.long 0x18 12. " ADPSUPPORT ,Enables internal ADP capability of the USB 3.0 core" "Disabled,Enabled" newline bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" newline sif !cpuis("LS1088*")&&!cpuis("LS1084A")&&!cpuis("LS1048A")&&!cpuis("LS1044A") bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" newline endif bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" newline bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,Used for FPGA hardware validation of the core" "Not used,Used" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFO_DEPTH ,Specifies the size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global Hardware Parameters Register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Specifies the depth of RAM2" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Specifies the depth of RAM1" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port To Bus Instance Mapping Low Register" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global High-Speed Port To Bus Instance Mapping High Register" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline if (((per.l(ad:0x03000000+0xC118))&0x03)==0x01) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" bitfld.long 0x00 19.--21. " LSIPD ,LS inter-packet time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPHY ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" endif newline group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL0,Global USB 3.0 PIPE Control Register 0" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No reset,Reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSInactive" "P2,P3" newline bitfld.long 0x00 28. " DISRXDETP3 ,Receiver detection in P3 state" "Stays in P3,Goes to P2 then back P3" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,Selects transition from U1/U2 to recovery or SS inactive when U1/U2 LFPS handshake fails" "No effect,Failed" newline sif !cpuis("LS10?3*") bitfld.long 0x00 17. " SUSPENDENABLE ,Suspend USB3.0 SS PHY" "Not suspended,Suspended" newline endif bitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8 bits,?..." bitfld.long 0x00 6. " TXSWING ,TXSWING field" "0,1" newline bitfld.long 0x00 3.--5. " TXMARGIN ,TXMARGIN field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " TXDEEMPHASIS ,Value driven to the PHY is controlled by LTSSM during USB3 compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. " ELASTICBUFFERMODE ,Elastic buffer mode" "0,1" newline group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Transmit FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,TXFIFO 0 depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Transmit FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,TXFIFO 1 depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Transmit FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,TXFIFO 2 depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Transmit FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,TXFIFO 3 depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Receive FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,RXFIFO 0 depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Receive FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,RXFIFO 1 depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Receive FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,RXFIFO 2 depth" group.long 0xC3B0++0x03 line.long 0x00 "GRXFIFOSIZ_3,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Receive FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,RXFIFO 3 depth" group.long 0xC400++0x0B line.long 0x00 "GEVNTADRLO,Global Event Buffer Address Register Low" line.long 0x04 "GEVNTADRHI,Global Event Buffer Address Register High" line.long 0x08 "GEVNTSIZ,Global Event Buffer Size Register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 1. " EVNTSIZ ,Event buffer size in bytes" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*")||cpuis("LS1088A") group.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" else rgroup.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" endif rgroup.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register" bitfld.long 0x00 3. " GTXFIFOPRIDEV[3] ,Device TXFIFO 3 priority" "Low,High" bitfld.long 0x00 2. " [2] ,Device TXFIFO 2 priority" "Low,High" newline bitfld.long 0x00 1. " [1] ,Device TXFIFO 1 priority" "Low,High" bitfld.long 0x00 0. " [0] ,Device TXFIFO 0 priority" "Low,High" group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register" bitfld.long 0x00 2. " GTXFIFOPRIHST[2] ,Host TXFIFO 2 priority" "Low,High" bitfld.long 0x00 1. " [1] ,Host TXFIFO 1 priority" "Low,High" newline bitfld.long 0x00 0. " [0] ,Host TXFIFO 0 priority" "Low,High" line.long 0x04 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register" bitfld.long 0x04 2. " GRXFIFOPRIHST[2] ,Host RXFIFO 2 priority" "Low,High" bitfld.long 0x04 1. " [1] ,Host RXFIFO 1 priority" "Low,High" newline bitfld.long 0x04 0. " [0] ,Host RXFIFO 0 priority" "Low,High" if (((per.l.le(ad:0x03000000+0xC110))&0x3000)==0x1000) group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0xC624++0x03 hide.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" endif newline group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,Indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,Selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP" "32,GFLADJ.GFLADJ_30MHZ" newline bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,Value used for frame length adjustment" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496" if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x1000)&&(((per.l(ad:0x03000000+0xC144))&0x80000000)==0x80000000) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" newline bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x03000000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,?..." newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS.Disabled,Rx.Detect,SS.Inactive,,Recovery,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" ",,,,,,,,Remote wakeup request,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device Event Enable Register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LMP received event enable" "Disabled,Enabled" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" newline if (((per.l(ad:0x03000000+0xC70C))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in SS mode" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/Reset" bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in HS/FS/LS mode" "On state,,Sleep,Suspend,Disconnected,?..." bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." endif group.long 0xC710++0x07 line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register" line.long 0x04 "DGCMD,Device Generic Command Register" rbitfld.long 0x04 15. " CMDSTATUS[3] ,Command status 3" "Success,Error" rbitfld.long 0x04 14. " [2] ,Command status 2" "Success,Error" newline rbitfld.long 0x04 13. " [1] ,Command status 1" "Success,Error" rbitfld.long 0x04 12. " [0] ,Command status 0" "Success,Error" newline bitfld.long 0x04 10. " CMDACT ,Command active" "Not active,Active" bitfld.long 0x04 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" newline hexmask.long.byte 0x04 0.--7. 1. " CMDTYP ,Command type" group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register" bitfld.long 0x00 7. " USBACTEP[7] ,USB EP3-IN" "Not active,Active" bitfld.long 0x00 6. " [6] ,USB EP3-OUT" "Not active,Active" newline bitfld.long 0x00 5. " [5] ,USB EP2-IN" "Not active,Active" bitfld.long 0x00 4. " [4] ,USB EP2-OUT" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,USB EP1-IN" "Not active,Active" bitfld.long 0x00 2. " [2] ,USB EP1-OUT" "Not active,Active" newline bitfld.long 0x00 1. " [1] ,USB EP0-IN" "Not active,Active" bitfld.long 0x00 0. " [0] ,USB EP0-OUT" "Not active,Active" newline group.long (0xC800+0x0)++0x0F line.long 0x00 "DEPCMDPAR2_0,Device Physical Endpoint-0 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_0,Device Physical Endpoint-0 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_0,Device Physical Endpoint-0 Command Parameter 0 Register" line.long 0x0C "DEPCMD_0,Device Physical Endpoint-0 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x10)++0x0F line.long 0x00 "DEPCMDPAR2_1,Device Physical Endpoint-1 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_1,Device Physical Endpoint-1 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_1,Device Physical Endpoint-1 Command Parameter 0 Register" line.long 0x0C "DEPCMD_1,Device Physical Endpoint-1 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x20)++0x0F line.long 0x00 "DEPCMDPAR2_2,Device Physical Endpoint-2 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_2,Device Physical Endpoint-2 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_2,Device Physical Endpoint-2 Command Parameter 0 Register" line.long 0x0C "DEPCMD_2,Device Physical Endpoint-2 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x30)++0x0F line.long 0x00 "DEPCMDPAR2_3,Device Physical Endpoint-3 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_3,Device Physical Endpoint-3 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_3,Device Physical Endpoint-3 Command Parameter 0 Register" line.long 0x0C "DEPCMD_3,Device Physical Endpoint-3 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x40)++0x0F line.long 0x00 "DEPCMDPAR2_4,Device Physical Endpoint-4 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_4,Device Physical Endpoint-4 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_4,Device Physical Endpoint-4 Command Parameter 0 Register" line.long 0x0C "DEPCMD_4,Device Physical Endpoint-4 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x50)++0x0F line.long 0x00 "DEPCMDPAR2_5,Device Physical Endpoint-5 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_5,Device Physical Endpoint-5 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_5,Device Physical Endpoint-5 Command Parameter 0 Register" line.long 0x0C "DEPCMD_5,Device Physical Endpoint-5 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x60)++0x0F line.long 0x00 "DEPCMDPAR2_6,Device Physical Endpoint-6 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_6,Device Physical Endpoint-6 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_6,Device Physical Endpoint-6 Command Parameter 0 Register" line.long 0x0C "DEPCMD_6,Device Physical Endpoint-6 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x70)++0x0F line.long 0x00 "DEPCMDPAR2_7,Device Physical Endpoint-7 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_7,Device Physical Endpoint-7 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_7,Device Physical Endpoint-7 Command Parameter 0 Register" line.long 0x0C "DEPCMD_7,Device Physical Endpoint-7 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." newline sif !cpuis("LS10?8*")&&!cpuis("LS10?4*") if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x3000) group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,Not masked" newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" else group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,?..." newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" endif group.long 0xCC04++0x03 line.long 0x00 "OCTL,OTG Control Register" bitfld.long 0x00 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x00 5. " PRTPWRCTL ,Port power control" "B-device,A-device" newline bitfld.long 0x00 4. " HNPREQ ,HNP request" "Not requested,Requested" bitfld.long 0x00 3. " SESREQ ,Session request" "Not requested,Requested" newline bitfld.long 0x00 2. " TERMSELDLPULSE ,TermSel dLine pulsing selection" "UTMI_TXVALID,UTMI_TERMSEL" bitfld.long 0x00 1. " DEVSETHNPEN ,Device set RSP/HNP enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HSTSETHNPEN ,Host set RSP/HNP enable" "Disabled,Enabled" if (((per.l(ad:0x03000000+0xC110))&0x3000)==0x3000) if (((per.l(ad:0x03000000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNT ,A-device B-Host end event" "Not set,Set" newline bitfld.long 0x00 19. " OTGADEVHOSTEVNT ,A-device host event" "Not set,Set" bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNT ,A-Dev HNP change event" "Not set,Set" newline bitfld.long 0x00 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not set,Set" bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNT ,B-Device B-Host end event" "Not set,Set" bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNT ,B-device HNP change event" "Not set,Set" newline bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not set,Set" bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif else if (((per.l(ad:0x03000000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" newline rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif endif group.long 0xCC0C++0x03 line.long 0x00 "OEVTEN,OTG Events Enable Register" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x00 23. " HRRCONFNOTIFEVNTEN ,HRRConfNotif event enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " HRRINITNOTIFEVNTEN ,HRRInitNotif event enable" "Disabled,Enabled" bitfld.long 0x00 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-Host end event enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGADEVHOSTEVNTEN ,A-device host event enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNTEN ,A-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-Host end event enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNTEN ,B-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG Status Register" bitfld.long 0x00 13. " DEVRUNSTP ,Reflects the status of the device Run/Stop bit in the DCTL device register" "Stopped,Started" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 4. " PERIPHERALSTATE ,Indicates whether the core is acting as a peripheral or host" "Host,Peripheral" bitfld.long 0x00 3. " XHCIPRTPOWER ,Reflects the PORTSC.PP bit in the xHCI register" "Low,High" newline bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" bitfld.long 0x00 1. " ASESVLD ,VBUS valid" "Not valid,Valid" newline bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" endif group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP Configuration Register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period/Scale down probe period" "0.775 s/12.5 ms,1.55 s/18.75 ms,2.275 s/25 ms,-/31.25 ms" bitfld.long 0x00 28.--29. " PRBDELTA ,Sets the resolution for RTIM value" "1 cycle,2 cycles,3 cycles,4 cycles" newline bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge/Scale down probe discharge" "4 ms/62.5 us,8 ms/125 us,16 ms/250 us,32 ms/500 us" line.long 0x04 "ADPCTL,ADP Control Register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" newline bitfld.long 0x04 26. " ADPEN ,ADP enable" "Disabled,Enabled" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" newline rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP Event Register" eventfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" eventfld.long 0x08 27. " ADPSNSEVNT ,ADP sense event" "Not occurred,Occurred" newline eventfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" eventfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" newline hexmask.long.word 0x08 0.--15. 1. " RTIM ,Captures the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB" line.long 0x0C "ADPEVTEN,ADP Event Enable Register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPSNSEVNTEN ,ADP sense event enable" "Disabled,Enabled" newline bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end tree "USB 3" base ad:0x03100000 width 16. rgroup.long 0x00++0x1F line.long 0x00 "CAPLENGTH,Capability Registers Length And HC Interface Version Number Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HC interface version number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS1,Structural Parameters Register 1" hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,Number of ports" hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,Number of interrupters" newline hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,Number of device slots" line.long 0x08 "HCSPARAMS2,Structural Parameters Register 2" bitfld.long 0x08 27.--31. " MAXSCRATCHPADBUFS ,Max scratchpad bufs lo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 26. " SPR ,Scratchpad restore" "0,1" newline bitfld.long 0x08 21.--25. " MAXSCRATCHPADBUFS_HI ,Max scratchpad bufs hi" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--7. " ERSTMAX ,Event ring segment table max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "HCSPARAMS3,Structural Parameters 3" hexmask.long.word 0x0C 16.--31. 1. " U2_DEVICE_EXIT_LAT ,U2 device exit latency" hexmask.long.byte 0x0C 0.--7. 1. " U1_DEVICE_EXIT_LAT ,U1 device exit latency" newline line.long 0x10 "HCCPARAMS1,Capability Parameters" hexmask.long.word 0x10 16.--31. 0x01 " XECP ,XHCI extended capabilities pointer" bitfld.long 0x10 12.--15. " MAXPSASIZE ,Maximum primary stream array size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. " CFC ,Contiguous frame ID capability" "0,1" bitfld.long 0x10 10. " SEC ,Stopped EDLTA capability" "0,1" newline bitfld.long 0x10 9. " SPC ,Short packet capability" "0,1" bitfld.long 0x10 8. " PAE ,Parse all event data" "0,1" newline bitfld.long 0x10 7. " NSS ,No secondary SID support" "0,1" bitfld.long 0x10 6. " LTC ,Latency tolerance messaging capability" "0,1" newline bitfld.long 0x10 5. " LHRC ,Light HC reset capability" "0,1" bitfld.long 0x10 4. " PIND ,Port indicators" "0,1" newline bitfld.long 0x10 3. " PPC ,Port power control" "0,1" bitfld.long 0x10 2. " CSZ ,Context size" "0,1" newline bitfld.long 0x10 1. " BNC ,BW negotiation capability" "0,1" bitfld.long 0x10 0. " AC64 ,64-bit addressing capability" "0,1" line.long 0x14 "DBOFF,Doorbell Offset" hexmask.long 0x14 2.--31. 0x04 " DOORBELLARRAYOFFSET ,Doorbell array offset" line.long 0x18 "RTSOFF,Runtime Register Space Offset" hexmask.long 0x18 5.--31. 0x20 " RUNTIME_REG_SPACE_OFFSET ,Runtime register space offset" line.long 0x1C "HCCPARAMS2,Capability Parameters 2" bitfld.long 0x1C 5. " CIC ,Configuration information capability" "0,1" bitfld.long 0x1C 4. " LEC ,Large ESIT payload capability" "0,1" newline bitfld.long 0x1C 3. " CTC ,Compliance transition capability" "0,1" bitfld.long 0x1C 2. " FSC ,Force save context capability" "0,1" newline bitfld.long 0x1C 1. " CMC ,Configure endpoint command max exit latency too large capability" "0,1" bitfld.long 0x1C 0. " U3C ,U3 entry capability" "0,1" newline group.long 0xC100++0x07 line.long 0x00 "GSBUSCFG0,Global SoC Bus Configuration Register 0" bitfld.long 0x00 28.--31. " DATRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " DESRDREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. " DATWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for data write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DESWRREQINFO ,AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " INCR256BRSTENA ,NCR256 burst type enable" "Disabled,Enabled" bitfld.long 0x00 6. " INCR128BRSTENA ,NCR128 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " INCR64BRSTENA ,NCR64 burst type enable" "Disabled,Enabled" bitfld.long 0x00 4. " INCR32BRSTENA ,NCR32 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " INCR16BRSTENA ,NCR16 burst type enable" "Disabled,Enabled" bitfld.long 0x00 2. " INCR8BRSTENA ,NCR8 burst type enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " INCR4BRSTENA ,NCR4 burst type enable" "Disabled,Enabled" bitfld.long 0x00 0. " INCRBRSTENA ,Undefined length INCR burst type enable" "INCRX,INCR" line.long 0x04 "GSBUSCFG1,Global SoC Bus Configuration Register 1" bitfld.long 0x04 12. " EN1KPAGE ,1k page boundary enable" "Disabled,Enabled" newline bitfld.long 0x04 8.--11. " PIPETRANSLIMIT ,AXI pipelined transfers burst request limit" "1 request,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests,9 requests,10 requests,11 requests,12 requests,13 requests,14 requests,15 requests,16 requests" newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) if (((per.l(ad:0x03100000+0xC108))&0x20000000)==0x20000000) group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBTXPKTCNT ,USB transmit packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 16.--23. 1. " USBMAXTXBURSTSIZE ,USB maximum TX burst size" else group.long 0xC108++0x03 line.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" bitfld.long 0x00 29. " USBTXPKTCNTSEL ,USB transmit packet count enable" "Disabled,Enabled" endif if (((per.l(ad:0x03100000+0xC10C))&0x20000000)==0x20000000) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC10C++0x03 line.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" bitfld.long 0x00 29. " USBRXPKTCNTSEL ,USB receive packet count enable" "Disabled,Enabled" bitfld.long 0x00 24.--27. " USBRXPKTCNT ,USB receive packet count" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19.--23. " USBMAXRXBURSTSIZE ,USB maximum receive burst size" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif else hgroup.long 0xC108++0x03 hide.long 0x00 "GTXTHRCFG,Global Tx Threshold Control Register" hgroup.long 0xC10C++0x03 hide.long 0x00 "GRXTHRCFG,Global Rx Threshold Control Register" endif newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 10. " SOFITPSYNC ,SOFITPSYNC" "SS not in Rx.Det SS.Dis and U3,Non-SS not in a susp state" newline bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,?..." bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" newline bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif else if (((per.l(ad:0x03100000+0xC700))&0x07)==(0x00||0x04)) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "125 us,62.5 us,31.25 us,15.625 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "1000 us,500 us,250 us,125 us" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" else group.long 0xC110++0x03 line.long 0x00 "GCTL,Global Core Control Register" hexmask.long.word 0x00 19.--31. 1. " PWRDNSCALE ,Power down scale" bitfld.long 0x00 18. " MASTERFILTBYPASS ,Master filter bypass" "Not bypassed,Bypassed" newline bitfld.long 0x00 17. " BYPSSETADDR ,Bypass set address in device mode" "Not bypassed,Bypassed" bitfld.long 0x00 16. " U2RSTECN ,If super speed connection fails during POLL or LMP the device connects at non-SS mode 3 more times when bit is set" "0,3 more times" newline bitfld.long 0x00 14.--15. " FRMSCLDWN ,Scales down device view of SOF/USOF/ITP duration and MaxPacketSize (for xHCI debug capability enabled)" "0,1,2,3" newline sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,OTG" newline else bitfld.long 0x00 12.--13. " PRTCAPDIR ,Port capability direction" ",Host,Device,?..." newline endif bitfld.long 0x00 11. " CORESOFTRESET ,Core software reset" "No reset,Reset" bitfld.long 0x00 6.--7. " RAMCLKSEL ,RAM clock select" "Bus clock,Pipe clock,Pipe/2 clock,?..." newline bitfld.long 0x00 3. " DISSCRAMBLE ,Disable scrambling" "No,Yes" bitfld.long 0x00 2. " U2EXIT_LFPS ,Sets LFPS filter for dealing with LFPS glitches" "248ns LFPS valid,Waits for 8us" newline bitfld.long 0x00 0. " DSBLCLKGTNG ,Disable clock gating" "No,Yes" endif endif group.long 0xC118++0x03 line.long 0x00 "GSTS,Global Status Register" sif !cpuis("LS108*")&&!cpuis("LS1044*")&&!cpuis("LS1048*") rbitfld.long 0x00 10. " OTG_IP ,OTG interrupt pending" "Not pending,Pending" newline endif rbitfld.long 0x00 7. " HOST_IP ,HOST interrupt pending" "Not pending,Pending" rbitfld.long 0x00 6. " DEVICE_IP ,Device interrupt pending" "Not pending,Pending" newline bitfld.long 0x00 5. " CSRTIMEOUT ,CSR timeout" "No timeout,Timeout" bitfld.long 0x00 4. " BUSERRADDRVLD ,Bus error address valid" "Invalid,Valid" newline rbitfld.long 0x00 0.--1. " CURMOD ,Current mode of operation" "Device,Host,?..." sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) ; if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1_SUSP_THRLD_EN_FOR_HOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1_SUSP_THRLD_FOR_HOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HC_ERRATA_ENABLE ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 2. " HC_PARCHK_DISABLE ,Host parameter check disable" "No,Yes" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 16. " PARKMODE_DISABLE_HS ,Park mode disable" "No,Yes" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) if (((per.l(ad:0x03100000+0xC700))&0x07)==0x00) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" newline bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" newline bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" newline bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x01) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 29. " FILTER_SE0_FSLS_EOP ,SE0 filter enable for FS/LS" "Disabled,Enabled" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" newline bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" bitfld.long 0x00 26. " DEV_FORCE_20_CLK_FOR_30_CLK ,Force 2.0 clk as 3.0 clk enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" elif (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC11C++0x03 line.long 0x00 "GUCTL1,Global User Control Register 1" bitfld.long 0x00 28. " TX_IPGAP_LINECHECK_DIS ,Line check disable" "No,Yes" bitfld.long 0x00 27. " DEV_TRB_OUT_SPR_IND ,OUT TRB short packet indication enable" "Disabled,Enabled" newline bitfld.long 0x00 25. " P3_IN_U2 ,P3 power state when the SuperSpeed link is in U2 enable" "Disabled,Enabled" bitfld.long 0x00 24. " DEV_L1_EXIT_BY_HW ,Remote wakeup for L1 enable" "Disabled,Enabled" newline bitfld.long 0x00 21.--23. " IP_GAP_ADD_ON ,Adds on to the default inter packet gap setting in the USB 2.0 MAC" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " DEV_LSP_TAIL_LOCK_DIS ,Bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode disable" "No,Yes" newline bitfld.long 0x00 19. " NAK_PER_ENH_FS ,Enables performance enhancement for FS async endpoints in the presence of NAKs" "Disabled,Enabled" bitfld.long 0x00 18. " NAK_PER_ENH_HS ,Enables performance enhancement for HS async endpoints in the presence of NAKs" "Disabled,Enabled" newline bitfld.long 0x00 8. " L1SUSPTHRLDENFORHOST ,L1 suspend threshold for host enable" "Disabled,Enabled" bitfld.long 0x00 4.--7. " L1SUSPTHRLDFORHOST ,L1 suspend threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. " HELDEN ,Host ELD enable" "No,Yes" bitfld.long 0x00 2. " HPARCHKDISABLE ,Host parameter check disable" "Enabled,Disabled" newline bitfld.long 0x00 1. " OVRLD_L1_SUSP_COM ,Overloads utmi_l1_suspend_com_n with the utmi_sleep_n signal" "Not set,Set" bitfld.long 0x00 0. " LOA_FILTER_EN ,Enables checking USB 2.0 port babble at least three consecutive times before port is disabled" "Disabled,Enabled" else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif else hgroup.long 0xC11C++0x03 hide.long 0x00 "GUCTL1,Global User Control Register 1" endif endif group.long 0xC128++0x03 line.long 0x00 "GUID,Global User ID Register" newline if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 21. " NOEXTRDL ,No extra delay between SOF and the first packet" "Waits 2 us,Doesn't wait" newline bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" bitfld.long 0x00 16. " RESBWHSEPS ,Indicates whether reserve 80% or 85% of bandwidth for HS periodic EPs" "80%,85%" newline bitfld.long 0x00 15. " CMDEVADDR ,Compliance mode for device address" "Equal to Slot ID,Increment address" bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" newline bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" bitfld.long 0x00 9.--10. " DTCT ,Device timeout coarse tuning" "DTFT,500 us,1.5 ms,6.5 ms" newline hexmask.long.word 0x00 0.--8. 1. " DTFT ,Device timeout fine tuning" elif (((per.l(ad:0x03100000+0xC110))&0x3000)==0x2000) group.long 0xC12C++0x03 line.long 0x00 "GUCTL,Global User Control Register" hexmask.long.word 0x00 22.--31. 1. " REFCLKPER ,Period of ref_clk in ns" bitfld.long 0x00 17. " SPRSCTRLTRANSEN ,Sparse control transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USBHSTINAUTORETRYEN ,Host IN auto retry" "Disabled,Enabled" bitfld.long 0x00 13. " ENOVERLAPCHK ,Enable check for LFPS overlap during remote Ux exit" "Disabled,Enabled" newline bitfld.long 0x00 12. " EXTCAPSUPTEN ,External extended capability support enable" "Disabled,Enabled" bitfld.long 0x00 11. " INSRTEXTRFSBODL ,Insert extra delay between FS bulk OUT transactions" "Not inserted,Inserted" else hgroup.long 0xC12C++0x03 hide.long 0x00 "GUCTL,Global User Control Register" endif newline if (((per.l(ad:0x03100000+0xC118))&0x10)==0x01) rgroup.long 0xC130++0x07 line.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" line.long 0x04 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" else hgroup.long 0xC130++0x03 hide.long 0x00 "GBUSERRADDRLO,Global SoC Bus Error Address Register Low" hgroup.long 0xC134++0x03 hide.long 0x00 "GBUSERRADDRHI,Global SoC Bus Error Address Register High" endif group.long 0xC138++0x07 line.long 0x00 "GPRTBIMAPLO,SuperSpeed Port To Bus Instance Mapping" bitfld.long 0x00 0.--3. " BINUM1 ,SS USB instance number for port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAPHI,High-Speed Port To Bus Instance Mapping" bitfld.long 0x04 0.--3. " BINUM9 ,SS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rgroup.long 0xC140++0x1F line.long 0x00 "GHWPARAMS0,Global Hardware Parameters Register 0" hexmask.long.byte 0x00 24.--31. 1. " DWC_USB3_AWIDTH ,Master/slave address bus width" hexmask.long.byte 0x00 16.--23. 1. " DWC_USB3_SDWIDTH ,Slave bus (register access bus) data bus width" newline hexmask.long.byte 0x00 8.--15. 1. " DWC_USB3_MDWIDTH ,Master bus (DMA bus) data bus width" bitfld.long 0x00 6.--7. " DWC_USB3_SBUS_TYPE ,Slave bus (register access bus) interface type" "AHB,?..." newline bitfld.long 0x00 3.--5. " DWC_USB3_MBUS_TYPE ,Master bus (DMA bus) interface type" ",AXI,?..." bitfld.long 0x00 0.--2. " DWC_USB3_MODE ,Mode of operation" ",,DRD,?..." line.long 0x04 "GHWPARAMS1,Global Hardware Parameters Register 1" bitfld.long 0x04 31. " DWC_USB3_EN_DBC ,Enables xHCI debug capability" "Disabled,Enabled" bitfld.long 0x04 30. " DWC_USB3_RM_OPT_FEATURES ,Optional features removal enable" "Disabled,Enabled" newline bitfld.long 0x04 28. " DWC_USB3_RAM_BUS_CLKS_SYNC ,Specifies whether the RAM clock and the Bus clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 27. " DWC_USB3_MAC_RAM_CLKS_SYNC ,Specifies whether the MAC clock and the RAM clock are synchronous to each other" "Asynchronous,Synchronous" newline bitfld.long 0x04 26. " DWC_USB3_MAC_PHY_CLKS_SYNC ,Specifies whether the MAC clock and the PHY clock are synchronous to each other" "Asynchronous,Synchronous" bitfld.long 0x04 24.--25. " DWC_USB3_EN_PWROPT ,Specifies the power optimization mode" "No power optimization,Clock gating only,?..." newline bitfld.long 0x04 23. " DWC_USB3_SPRAM_TYP ,Selects the FIFO synchronous static RAM type" "2-Port-RAM,SPRAM" bitfld.long 0x04 21.--22. " DWC_USB3_NUM_RAMS ,Selects the number of RAMs" ",1,2,3" newline bitfld.long 0x04 15.--20. " DWC_USB3_DEVICE_NUM_INT ,Selects the number of event buffers in device mode" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." bitfld.long 0x04 12.--14. " DWC_USB3_ASPACEWIDTH ,Selects the address space port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 9.--11. " DWC_USB3_REQINFOWIDTH ,Selects the Request/Response info port width of the master and slave bus interfaces" ",,,,4,5,6,?..." bitfld.long 0x04 6.--8. " DWC_USB3_DATAINFOWIDTH ,Selects the data info port width of the master and slave bus interfaces" ",1,2,3,4,5,6,?..." newline bitfld.long 0x04 3.--5. " DWC_USB3_BURSTWIDTH ,Selects the burst port width of the master and slave bus interfaces - 1" "1,2,3,4,5,6,7,8" bitfld.long 0x04 0.--2. " DWC_USB3_IDWIDTH1 ,Master ID port width" ",,,4,5,6,7,8" line.long 0x08 "GHWPARAMS2,Global Hardware Parameters Register 2" line.long 0x0C "GHWPARAMS3,Global Hardware Parameters Register 3" hexmask.long.word 0x0C 23.--30. 1. " DWC_USB3_CACHE_TOTAL_XFER_RESOURCES ,Selects the maximum number of transfer resources in the core" bitfld.long 0x0C 18.--22. " DWC_USB3_NUM_IN_EPS ,Specifies the maximum number of device mode IN endpoints active at any time" ",,,,4,?..." newline bitfld.long 0x0C 12.--17. " DWC_USB3_NUM_EPS ,Specifies the number of device mode single directional endpoints" ",,,,,,,,8,?..." bitfld.long 0x0C 10. " DWC_USB3_VENDOR_CTL_INTERFACE ,Enables the UTMI+ PHY vendor control interface" "Disabled,Enabled" newline bitfld.long 0x0C 6.--7. " DWC_USB3_HSPHY_DWIDTH ,Specifies the data width of the UTMI+ PHY interface" ",,8/16-bits,?..." bitfld.long 0x0C 2.--3. " DWC_USB3_HSPHY_INTERFACE ,Specifies the high-speed PHY interface" "0,1,2,3" newline bitfld.long 0x0C 0.--1. " DWC_USB3_SSPHY_INTERFACE ,Specifies the superSpeed PHY interface" "0,1,2,3" line.long 0x10 "GHWPARAMS4,Global Hardware Parameters Register 4" bitfld.long 0x10 28.--31. " DWC_USB3_BMU_LSP_DEPTH ,Specifies the depth of the BMU-LSP status buffer" ",,,,4,?..." bitfld.long 0x10 24.--27. " DWC_USB3_BMU_PTL_DEPTH ,Specifies the depth of the BMU-PTL source/sink buffers-1" ",,,,,,,,8,?..." newline bitfld.long 0x10 23. " DWC_USB3_EN_ISOC_SUPT ,Enables isochronous endpoint capability" "Disabled,Enabled" bitfld.long 0x10 17.--20. " DWC_USB3_NUM_SS_USB_INSTANCES ,Specifies the number of SuperSpeed USB bus instances" ",1,?..." newline bitfld.long 0x10 0.--5. " DWC_USB3_CACHE_TRBS_PER_TRANSFER ,Selects the number of transfer request blocks" ",,,,4,?..." line.long 0x14 "GHWPARAMS5,Global Hardware Parameters Register 5" bitfld.long 0x14 22.--27. " DWC_USB3_DFQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor fetch request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 16.--21. " DWC_USB3_DWQ_FIFO_DEPTH ,Specifies the size of the BMU descriptor write queue" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32,?..." newline bitfld.long 0x14 10.--15. " DWC_USB3_TXQ_FIFO_DEPTH ,Specifies the size of the BMU Tx request queue" ",,,,,,,,,,,,,,,,16,?..." bitfld.long 0x14 4.--9. " DWC_USB3_RXQ_FIFO_DEPTH ,Specifies the size of the BMU Rx request queue" ",,,,,,,,,,,,,,,,16,?..." newline bitfld.long 0x14 0.--3. " DWC_USB3_BMU_BUSGM_DEPTH ,Specifies the depth of the BMU-BUSGM source/sink buffer" ",,,,,,,,8,?..." line.long 0x18 "GHWPARAMS6,Global Hardware Parameters Register 6" hexmask.long.word 0x18 16.--31. 1. " DWC_USB3_RAM0_DEPTH ,Specifies the depth of RAM0" bitfld.long 0x18 15. " BUSFLTRSSUPPORT ,Specifies whether to add a filter for VBUS and ID related control inputs from the PHY" "Not added,Added" newline bitfld.long 0x18 13. " OTG3_0SUPEN ,OTG 3.0 Support Enabled" "Disabled,Enabled" newline bitfld.long 0x18 12. " ADPSUPPORT ,Enables internal ADP capability of the USB 3.0 core" "Disabled,Enabled" newline bitfld.long 0x18 11. " HNPSUPPORT ,HNP support enabled" "Disabled,Enabled" newline sif !cpuis("LS1088*")&&!cpuis("LS1084A")&&!cpuis("LS1048A")&&!cpuis("LS1044A") bitfld.long 0x18 10. " SRPSUPPORT ,SRP support enabled" "Disabled,Enabled" newline endif bitfld.long 0x18 7. " DWC_USB3_EN_FPGA ,Hardware validation/driver development with an FPGA platform" "No,Yes" newline bitfld.long 0x18 6. " DWC_USB3_EN_DBG_PORTS ,Used for FPGA hardware validation of the core" "Not used,Used" bitfld.long 0x18 0.--5. " DWC_USB3_PSQ_FIFO_DEPTH ,Specifies the size of the BMU protocol status queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "GHWPARAMS7,Global Hardware Parameters Register 7" hexmask.long.word 0x1C 16.--31. 1. " DWC_USB3_RAM2_DEPTH ,Specifies the depth of RAM2" hexmask.long.word 0x1C 0.--15. 1. " DWC_USB3_RAM1_DEPTH ,Specifies the depth of RAM1" group.long 0xC180++0x07 line.long 0x00 "GPRTBIMAP_HSLO,Global High-Speed Port To Bus Instance Mapping Low Register" bitfld.long 0x00 0.--3. " BINUM1 ,HS USB instance number for port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "GPRTBIMAP_HSHI,Global High-Speed Port To Bus Instance Mapping High Register" bitfld.long 0x04 0.--3. " BINUM9 ,HS USB instance number for port 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline if (((per.l(ad:0x03100000+0xC118))&0x03)==0x01) group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 22.--24. " LSTRD ,LS turnaround time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" bitfld.long 0x00 19.--21. " LSIPD ,LS inter-packet time" "2 bit times,2.5 bit times,3 bit times,3.5 bit times,4 bit times,4.5 bit times,5 bit times,5.5 bit times" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPENDUSB20 ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" else group.long 0xC200++0x03 line.long 0x00 "GUSB2PHYCFGN,Global USB2 PHY Configuration Register" bitfld.long 0x00 31. " UTMI_PHYSOFTRST ,UTMI PHY soft reset" "No reset,Reset" rbitfld.long 0x00 30. " U2_FREECLK_EXISTS ,Specifies whether USB 2.0 PHY provides free-running PHY clock" "No,Yes" newline bitfld.long 0x00 8. " ENBLSLPM ,Enables utmi_sleep_n and utmi_l1_suspend_n" "Disabled,Enabled" bitfld.long 0x00 6. " SUSPHY ,Suspend USB 2.0 HS/FS/LS PHY" "Not suspended,Suspended" newline bitfld.long 0x00 3. " PHYIF ,Uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface" "8-bits,16-bits" endif newline group.long 0xC2C0++0x03 line.long 0x00 "GUSB3PIPECTL0,Global USB 3.0 PIPE Control Register 0" bitfld.long 0x00 31. " PHYSOFTRST ,USB3 PHY soft reset" "No reset,Reset" bitfld.long 0x00 29. " U2SSINACTP3OK ,P3 OK for U2/SSInactive" "P2,P3" newline bitfld.long 0x00 28. " DISRXDETP3 ,Receiver detection in P3 state" "Stays in P3,Goes to P2 then back P3" bitfld.long 0x00 25. " U1U2EXITFAIL_TO_RECOV ,Selects transition from U1/U2 to recovery or SS inactive when U1/U2 LFPS handshake fails" "No effect,Failed" newline sif !cpuis("LS10?3*") bitfld.long 0x00 17. " SUSPENDENABLE ,Suspend USB3.0 SS PHY" "Not suspended,Suspended" newline endif bitfld.long 0x00 15.--16. " DATWIDTH ,PIPE data width" "32 bits,16 bits,8 bits,?..." bitfld.long 0x00 6. " TXSWING ,TXSWING field" "0,1" newline bitfld.long 0x00 3.--5. " TXMARGIN ,TXMARGIN field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " TXDEEMPHASIS ,Value driven to the PHY is controlled by LTSSM during USB3 compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. " ELASTICBUFFERMODE ,Elastic buffer mode" "0,1" newline group.long 0xC300++0x03 line.long 0x00 "GTXFIFOSIZ_0,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Transmit FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,TXFIFO 0 depth" group.long 0xC310++0x03 line.long 0x00 "GTXFIFOSIZ_1,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Transmit FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,TXFIFO 1 depth" group.long 0xC320++0x03 line.long 0x00 "GTXFIFOSIZ_2,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Transmit FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,TXFIFO 2 depth" group.long 0xC330++0x03 line.long 0x00 "GTXFIFOSIZ_3,Global Transmit FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Transmit FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,TXFIFO 3 depth" group.long 0xC380++0x03 line.long 0x00 "GRXFIFOSIZ_0,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_0 ,Receive FIFO_0 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_0 ,RXFIFO 0 depth" group.long 0xC390++0x03 line.long 0x00 "GRXFIFOSIZ_1,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_1 ,Receive FIFO_1 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_1 ,RXFIFO 1 depth" group.long 0xC3A0++0x03 line.long 0x00 "GRXFIFOSIZ_2,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_2 ,Receive FIFO_2 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_2 ,RXFIFO 2 depth" group.long 0xC3B0++0x03 line.long 0x00 "GRXFIFOSIZ_3,Global Receive FIFO Size Register 0" hexmask.long.word 0x00 16.--31. 0x01 " TXFSTADDR_3 ,Receive FIFO_3 RAM start address" hexmask.long.word 0x00 0.--15. 0x01 " TXFDEP_3 ,RXFIFO 3 depth" group.long 0xC400++0x0B line.long 0x00 "GEVNTADRLO,Global Event Buffer Address Register Low" line.long 0x04 "GEVNTADRHI,Global Event Buffer Address Register High" line.long 0x08 "GEVNTSIZ,Global Event Buffer Size Register" bitfld.long 0x08 31. " EVNTINTRPTMASK ,Event interrupt mask" "Not masked,Masked" hexmask.long.word 0x08 0.--15. 1. " EVNTSIZ ,Event buffer size in bytes" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*")||cpuis("LS1088A") group.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" else rgroup.long 0xC40C++0x03 line.long 0x00 "GEVNTCOUNT,Global Event Buffer Count Register" hexmask.long.word 0x00 0.--15. 1. " EVNTCOUNT ,Event count" endif rgroup.long 0xC600++0x03 line.long 0x00 "GHWPARAMS8,Global Hardware Parameters Register 8" group.long 0xC610++0x03 line.long 0x00 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register" bitfld.long 0x00 3. " GTXFIFOPRIDEV[3] ,Device TXFIFO 3 priority" "Low,High" bitfld.long 0x00 2. " [2] ,Device TXFIFO 2 priority" "Low,High" newline bitfld.long 0x00 1. " [1] ,Device TXFIFO 1 priority" "Low,High" bitfld.long 0x00 0. " [0] ,Device TXFIFO 0 priority" "Low,High" group.long 0xC618++0x07 line.long 0x00 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register" bitfld.long 0x00 2. " GTXFIFOPRIHST[2] ,Host TXFIFO 2 priority" "Low,High" bitfld.long 0x00 1. " [1] ,Host TXFIFO 1 priority" "Low,High" newline bitfld.long 0x00 0. " [0] ,Host TXFIFO 0 priority" "Low,High" line.long 0x04 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register" bitfld.long 0x04 2. " GRXFIFOPRIHST[2] ,Host RXFIFO 2 priority" "Low,High" bitfld.long 0x04 1. " [1] ,Host RXFIFO 1 priority" "Low,High" newline bitfld.long 0x04 0. " [0] ,Host RXFIFO 0 priority" "Low,High" if (((per.l.le(ad:0x03100000+0xC110))&0x3000)==0x1000) group.long 0xC624++0x03 line.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" bitfld.long 0x00 8.--12. " HSTRXFIFO ,Host RXFIFO DMA high-low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " HSTTXFIFO ,Host TXFIFO DMA high-low priority ratio reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hgroup.long 0xC624++0x03 hide.long 0x00 "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register" endif newline group.long 0xC630++0x03 line.long 0x00 "GFLADJ,Global Frame Length Adjustment Register" hexmask.long.word 0x00 8.--21. 1. " GFLADJ_REFCLK_FLADJ ,Indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk" bitfld.long 0x00 7. " GFLADJ_30MHZ_REG_SEL ,Selects whether to use a hard-coded value of 20h (32 decimal) or the value in GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP" "32,GFLADJ.GFLADJ_30MHZ" newline bitfld.long 0x00 0.--5. " GFLADJ_30MHZ ,Value used for frame length adjustment" "59488,59504,59520,59536,59552,59568,59584,59600,59616,59632,59648,59664,59680,59696,59712,59728,59744,59760,59776,59792,59808,59824,59840,59856,59872,59888,59904,59920,59936,59952,59968,59984,60000,60016,60032,60048,60064,60080,60096,60112,60128,60144,60160,60176,60192,60208,60224,60240,60256,60272,60288,60304,60320,60336,60352,60368,60384,60400,60416,60432,60448,60464,60480,60496" if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x1000)&&(((per.l(ad:0x03100000+0xC144))&0x80000000)==0x80000000) group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 17.--21. " NUMP ,Number of receive buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." else group.long 0xC700++0x03 line.long 0x00 "DCFG,Device Configuration Register" bitfld.long 0x00 23. " IGNORESTREAMPP ,Receive or ignore PP bit" "Received,Ignored" bitfld.long 0x00 22. " LPMCAP ,LPM capability enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--16. " INTRNUM ,Interrupt number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 3.--9. 0x08 " DEVADDR ,Device address" newline bitfld.long 0x00 0.--2. " DEVSPD ,Device speed" "High-speed,Full-speed,,,SuperSpeed,?..." endif if (((per.l(ad:0x03100000+0xC700))&0x07)==0x04) group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,?..." newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" "No action,,,,SS.Disabled,Rx.Detect,SS.Inactive,,Recovery,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." else group.long 0xC704++0x03 line.long 0x00 "DCTL,Device Control Register" bitfld.long 0x00 31. " RUN_STOP ,Run/Stop" "Stopped,Started" eventfld.long 0x00 30. " CSFTRST ,Core soft reset" "No reset,Reset" newline bitfld.long 0x00 24.--28. " HIRD_THRES ,HIRD threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--23. " LMP_NYET_THRES ,LPM NYET response threshold handshake response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17. " CRS ,Controller restore state" "Not restored,Restored" newline bitfld.long 0x00 16. " CSS ,Controller save state" "Not saved,Saved" bitfld.long 0x00 12. " INITU2ENA ,Initiate U2 enable" "Disabled,Enabled" newline bitfld.long 0x00 11. " ACCEPTU2ENA ,Accept U2 enable" "Disabled,Enabled" bitfld.long 0x00 10. " INITU1ENA ,Initiate U1 enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " ACCEPTU1ENA ,Accept U1 enable" "Disabled,Enabled" bitfld.long 0x00 5.--8. " ULSTCHNGREQ ,USB/Link state change request" ",,,,,,,,Remote wakeup request,?..." newline bitfld.long 0x00 1.--4. " TSTCTL ,Test control mode" "Disabled,Test_J,Test_K,Test_SE0_NAK,Test_Packet,Test_Force_Enable,?..." endif group.long 0xC708++0x03 line.long 0x00 "DEVTEN,Device Event Enable Register" bitfld.long 0x00 12. " VENDEVTSTRCVDEN ,Vendor device test LMP received event enable" "Disabled,Enabled" bitfld.long 0x00 9. " ERRTICERREVTEN ,Erratic error event enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SOFTEVTEN ,Start of frame enable" "Disabled,Enabled" bitfld.long 0x00 6. " U3L2L1SUSPEN ,U3/L2-L1 suspend event enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " WKUPEVTEN ,Resume/Remote wakeup detected event enable" "Disabled,Enabled" bitfld.long 0x00 3. " ULSTCNGEN ,USB/Link state change event enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CONNECTDONEEVTEN ,Connection done enable" "Disabled,Enabled" bitfld.long 0x00 1. " USBRSTEVTEN ,USB reset enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DISSCONNEVTEN ,Disconnect detected event enable" "Disabled,Enabled" newline if (((per.l(ad:0x03100000+0xC70C))&0x07)==0x04) rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in SS mode" "U0,U1,U2,U3,SS_DIS,RX_DET,SS_INACT,POLL,RECOV,HRESET,CMPLY,LPBK,,,,Resume/Reset" bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." else rgroup.long 0xC70C++0x03 line.long 0x00 "DSTS,Device Status Register" bitfld.long 0x00 25. " RSS ,Restore state status" "Completed,Not completed" bitfld.long 0x00 24. " SSS ,Save state status" "Completed,Not completed" newline bitfld.long 0x00 23. " COREIDLE ,Core idle" "Busy,Idle" bitfld.long 0x00 22. " DEVCTRLHLT ,Device controller halted" "Not halted,Halted" newline bitfld.long 0x00 18.--21. " USBLNKST ,USB/Link state in HS/FS/LS mode" "On state,,Sleep,Suspend,Disconnected,?..." bitfld.long 0x00 17. " RXFIFOEMPTY ,RxFIFO empty" "Not empty,Empty" newline hexmask.long.tbyte 0x00 3.--16. 1. " SOFFN ,Frame/Microframe number of the received SOF" bitfld.long 0x00 0.--2. " CONNECTSPD ,Connected speed" "High-speed,Full-speed,Low-speed,Full-speed,SuperSpeed,?..." endif group.long 0xC710++0x07 line.long 0x00 "DGCMDPAR,Device Generic Command Parameter Register" line.long 0x04 "DGCMD,Device Generic Command Register" rbitfld.long 0x04 15. " CMDSTATUS[3] ,Command status 3" "Success,Error" rbitfld.long 0x04 14. " [2] ,Command status 2" "Success,Error" newline rbitfld.long 0x04 13. " [1] ,Command status 1" "Success,Error" rbitfld.long 0x04 12. " [0] ,Command status 0" "Success,Error" newline bitfld.long 0x04 10. " CMDACT ,Command active" "Not active,Active" bitfld.long 0x04 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" newline hexmask.long.byte 0x04 0.--7. 1. " CMDTYP ,Command type" group.long 0xC720++0x03 line.long 0x00 "DALEPENA,Device Active USB Endpoint Enable Register" bitfld.long 0x00 7. " USBACTEP[7] ,USB EP3-IN" "Not active,Active" bitfld.long 0x00 6. " [6] ,USB EP3-OUT" "Not active,Active" newline bitfld.long 0x00 5. " [5] ,USB EP2-IN" "Not active,Active" bitfld.long 0x00 4. " [4] ,USB EP2-OUT" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,USB EP1-IN" "Not active,Active" bitfld.long 0x00 2. " [2] ,USB EP1-OUT" "Not active,Active" newline bitfld.long 0x00 1. " [1] ,USB EP0-IN" "Not active,Active" bitfld.long 0x00 0. " [0] ,USB EP0-OUT" "Not active,Active" newline group.long (0xC800+0x0)++0x0F line.long 0x00 "DEPCMDPAR2_0,Device Physical Endpoint-0 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_0,Device Physical Endpoint-0 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_0,Device Physical Endpoint-0 Command Parameter 0 Register" line.long 0x0C "DEPCMD_0,Device Physical Endpoint-0 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x10)++0x0F line.long 0x00 "DEPCMDPAR2_1,Device Physical Endpoint-1 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_1,Device Physical Endpoint-1 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_1,Device Physical Endpoint-1 Command Parameter 0 Register" line.long 0x0C "DEPCMD_1,Device Physical Endpoint-1 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x20)++0x0F line.long 0x00 "DEPCMDPAR2_2,Device Physical Endpoint-2 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_2,Device Physical Endpoint-2 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_2,Device Physical Endpoint-2 Command Parameter 0 Register" line.long 0x0C "DEPCMD_2,Device Physical Endpoint-2 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x30)++0x0F line.long 0x00 "DEPCMDPAR2_3,Device Physical Endpoint-3 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_3,Device Physical Endpoint-3 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_3,Device Physical Endpoint-3 Command Parameter 0 Register" line.long 0x0C "DEPCMD_3,Device Physical Endpoint-3 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x40)++0x0F line.long 0x00 "DEPCMDPAR2_4,Device Physical Endpoint-4 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_4,Device Physical Endpoint-4 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_4,Device Physical Endpoint-4 Command Parameter 0 Register" line.long 0x0C "DEPCMD_4,Device Physical Endpoint-4 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x50)++0x0F line.long 0x00 "DEPCMDPAR2_5,Device Physical Endpoint-5 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_5,Device Physical Endpoint-5 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_5,Device Physical Endpoint-5 Command Parameter 0 Register" line.long 0x0C "DEPCMD_5,Device Physical Endpoint-5 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x60)++0x0F line.long 0x00 "DEPCMDPAR2_6,Device Physical Endpoint-6 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_6,Device Physical Endpoint-6 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_6,Device Physical Endpoint-6 Command Parameter 0 Register" line.long 0x0C "DEPCMD_6,Device Physical Endpoint-6 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." group.long (0xC800+0x70)++0x0F line.long 0x00 "DEPCMDPAR2_7,Device Physical Endpoint-7 Command Parameter 2 Register" line.long 0x04 "DEPCMDPAR1_7,Device Physical Endpoint-7 Command Parameter 1 Register" line.long 0x08 "DEPCMDPAR0_7,Device Physical Endpoint-7 Command Parameter 0 Register" line.long 0x0C "DEPCMD_7,Device Physical Endpoint-7 Command Register" hexmask.long.word 0x0C 16.--31. 1. " COMMANDPARAM ,Command parameters" bitfld.long 0x0C 12.--15. " CMDSTATUS ,Command completion status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. " HIPRI_FORCERM ,HighPriority/ForceRM" "0,1" bitfld.long 0x0C 10. " CMDACT ,Enables device endpoint controller to execute generic command" "No effect,Execute" newline bitfld.long 0x0C 8. " CMDIOC ,Command interrupt on complete" "Masked,Not masked" bitfld.long 0x0C 0.--3. " CMDTYPE ,Command type" ",Set EP conf.,Set EP transfer res. conf.,Get EP state,Set stall,Clear stall,Start transfer,Update transfer,End transfer,Start new conf.,?..." newline sif !cpuis("LS10?8*")&&!cpuis("LS10?4*") if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x3000) group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,Not masked" newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" else group.long 0xCC00++0x03 line.long 0x00 "OCFG,OTG Configuration Register" bitfld.long 0x00 5. " DISPRTPWRCUTOFF ,OTG disable port power cut off" "No,Yes" bitfld.long 0x00 3. " OTGSFTRSTMSK ,OTG soft reset mask" "Masked,?..." newline bitfld.long 0x00 1. " HNPCAP ,HNP capability enable" "Disabled,Enabled" bitfld.long 0x00 0. " SRPCAP ,SRP capability enable" "Disabled,Enabled" endif group.long 0xCC04++0x03 line.long 0x00 "OCTL,OTG Control Register" bitfld.long 0x00 6. " PERIMODE ,Peripheral mode" "Host,Peripheral" bitfld.long 0x00 5. " PRTPWRCTL ,Port power control" "B-device,A-device" newline bitfld.long 0x00 4. " HNPREQ ,HNP request" "Not requested,Requested" bitfld.long 0x00 3. " SESREQ ,Session request" "Not requested,Requested" newline bitfld.long 0x00 2. " TERMSELDLPULSE ,TermSel dLine pulsing selection" "UTMI_TXVALID,UTMI_TERMSEL" bitfld.long 0x00 1. " DEVSETHNPEN ,Device set RSP/HNP enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " HSTSETHNPEN ,Host set RSP/HNP enable" "Disabled,Enabled" if (((per.l(ad:0x03100000+0xC110))&0x3000)==0x3000) if (((per.l(ad:0x03100000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNT ,A-device B-Host end event" "Not set,Set" newline bitfld.long 0x00 19. " OTGADEVHOSTEVNT ,A-device host event" "Not set,Set" bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNT ,A-Dev HNP change event" "Not set,Set" newline bitfld.long 0x00 17. " OTGADEVSRPDETEVNT ,SRP detect event" "Not set,Set" bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNT ,Session end detected event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNT ,B-Device B-Host end event" "Not set,Set" bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNT ,B-device HNP change event" "Not set,Set" newline bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNT ,Session valid detected event" "Not set,Set" bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNT ,VBUS change event" "Not set,Set" newline rbitfld.long 0x00 3. " BSESVLD ,B-Session valid" "Not valid,Valid" rbitfld.long 0x00 2. " HSTNEGSTS ,Host negotiation status" "Failure,Success" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif else if (((per.l(ad:0x03100000+0xCC08))&0x80000000)==0x00) group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline bitfld.long 0x00 21. " OTGADEVIDLEEVNT ,A-device A-IDLE event" "Not set,Set" rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" newline rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" else group.long 0xCC08++0x03 line.long 0x00 "OEVT,OTG Events Register" rbitfld.long 0x00 31. " DEVICEMODE ,Device mode" "A-Device,B-Device" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNT ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNT ,OTG device run stop set event" "Not set,Set" bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNT ,Connector ID status change event" "Not set,Set" newline rbitfld.long 0x00 1. " SESREQSTS ,Session request status" "Not requested,Requested" rbitfld.long 0x00 0. " OEVTERROR ,OTG event error" "No error,Error" endif endif group.long 0xCC0C++0x03 line.long 0x00 "OEVTEN,OTG Events Enable Register" bitfld.long 0x00 27. " OTGXHCIRUNSTPSETEVNTEN ,OTG host run stop set event enable" "Disabled,Enabled" bitfld.long 0x00 26. " OTGDEVRUNSTPSETEVNTEN ,OTG device run stop set event enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " OTGCONIDSTSCHNGEVNTEN ,Connector ID status change event enable" "Disabled,Enabled" bitfld.long 0x00 23. " HRRCONFNOTIFEVNTEN ,HRRConfNotif event enable" "Disabled,Enabled" newline bitfld.long 0x00 22. " HRRINITNOTIFEVNTEN ,HRRInitNotif event enable" "Disabled,Enabled" bitfld.long 0x00 21. " OTGADEVIDLEEVNTEN ,A-device A-IDLE event enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " OTGADEVBHOSTENDEVNTEN ,A-device B-Host end event enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGADEVHOSTEVNTEN ,A-device host event enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " OTGADEVHNPCHNGEVNTEN ,A-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 17. " OTGADEVSRPDETEVNTEN ,SRP detect event enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " OTGADEVSESSENDDETEVNTEN ,Session end detected event enable" "Disabled,Enabled" bitfld.long 0x00 11. " OTGBDEVBHOSTENDEVNTEN ,B-device B-Host end event enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " OTGBDEVHNPCHNGEVNTEN ,B-Dev HNP change event enable" "Disabled,Enabled" bitfld.long 0x00 9. " OTGBDEVSESSVLDDETEVNTEN ,Session valid detected event enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " OTGBDEVVBUSCHNGEVNTEN ,VBUS change event enable" "Disabled,Enabled" rgroup.long 0xCC10++0x03 line.long 0x00 "OSTS,OTG Status Register" bitfld.long 0x00 13. " DEVRUNSTP ,Reflects the status of the device Run/Stop bit in the DCTL device register" "Stopped,Started" bitfld.long 0x00 12. " XHCIRUNSTP ,OTG host run stop set event" "Not set,Set" newline bitfld.long 0x00 4. " PERIPHERALSTATE ,Indicates whether the core is acting as a peripheral or host" "Host,Peripheral" bitfld.long 0x00 3. " XHCIPRTPOWER ,Reflects the PORTSC.PP bit in the xHCI register" "Low,High" newline bitfld.long 0x00 2. " BSESVLD ,B-session valid" "Not valid,Valid" bitfld.long 0x00 1. " ASESVLD ,VBUS valid" "Not valid,Valid" newline bitfld.long 0x00 0. " CONIDSTS ,Connector ID status" "A-device,B-device" endif group.long 0xCC20++0x0F line.long 0x00 "ADPCFG,ADP Configuration Register" bitfld.long 0x00 30.--31. " PRBPER ,Probe period/Scale down probe period" "0.775 s/12.5 ms,1.55 s/18.75 ms,2.275 s/25 ms,-/31.25 ms" bitfld.long 0x00 28.--29. " PRBDELTA ,Sets the resolution for RTIM value" "1 cycle,2 cycles,3 cycles,4 cycles" newline bitfld.long 0x00 26.--27. " PRBDSCHG ,Probe discharge/Scale down probe discharge" "4 ms/62.5 us,8 ms/125 us,16 ms/250 us,32 ms/500 us" line.long 0x04 "ADPCTL,ADP Control Register" bitfld.long 0x04 28. " ENAPRB ,Enable probe" "Disabled,Enabled" bitfld.long 0x04 27. " ENASNS ,Enable sense" "Disabled,Enabled" newline bitfld.long 0x04 26. " ADPEN ,ADP enable" "Disabled,Enabled" bitfld.long 0x04 25. " ADPRES ,ADP reset" "No reset,Reset" newline rbitfld.long 0x04 24. " WB ,Write busy" "Completed,In progress" line.long 0x08 "ADPEVT,ADP Event Register" eventfld.long 0x08 28. " ADPPRBEVNT ,ADP probe event" "Not occurred,Occurred" eventfld.long 0x08 27. " ADPSNSEVNT ,ADP sense event" "Not occurred,Occurred" newline eventfld.long 0x08 26. " ADPTMOUTEVNT ,ADP timeout event" "Not occurred,Occurred" eventfld.long 0x08 25. " ADPRSTCMPLTEVNT ,ADP reset complete event" "Not occurred,Occurred" newline hexmask.long.word 0x08 0.--15. 1. " RTIM ,Captures the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB" line.long 0x0C "ADPEVTEN,ADP Event Enable Register" bitfld.long 0x0C 28. " ADPPRBEVNTEN ,ADP probe event enable" "Disabled,Enabled" bitfld.long 0x0C 27. " ADPSNSEVNTEN ,ADP sense event enable" "Disabled,Enabled" newline bitfld.long 0x0C 26. " ADPTMOUTEVNTEN ,ADP timeout event enable" "Disabled,Enabled" bitfld.long 0x0C 25. " ADPRSTCMPLTEVNTEN ,ADP reset complete event enable" "Disabled,Enabled" width 0x0B tree.end endif tree.end endif sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "USB PHY SuperSpeed" sif !cpuis("LS1088A")&&!cpuis("LS1084A")&&!cpuis("LS1044A")&&!cpuis("LS1048A") tree "USB3 PHY 1" base ad:0x04600000 endian.le width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x06++0x07 line.word 0x00 "RTUNE_DEBUG,RTUNE_DEBUG" bitfld.word 0x00 3.--4. " TYPE ,Type of manual tuning or register read/write to execute" "ADC or read/write rt_value,Rx tune or read/write rx_cal_val,Tx tune or read/write tx_cal_val,Resref detect" newline bitfld.word 0x00 2. " SET_VAL ,Sets to 1 to manually write the register specified by the TYPE bit to the value in the VALUE bit" "To,Set" bitfld.word 0x00 1. " MAN_TUNE ,Writes to a 1 to do a manual tuning specified by the TYPE bit" "No effect,Tune" bitfld.word 0x00 0. " FLIP_COMP ,Inverts analog comparator output" "Not inverted,Inverted" line.word 0x02 "RTUNE_STAT,RTUNE_STAT" hexmask.word 0x02 0.--8. 1. " STAT ,STAT" line.word 0x04 "SUP_SS_PHASE,SUP_SS_PHASE" bitfld.word 0x04 13.--15. " REF_SEL_DIV ,Reference divisor to achieve better resolution and less ppm errors" "1,2,3,4,5,6,7,8" bitfld.word 0x04 12. " PH_SEL ,Phase mixer clock select" "0,1" newline bitfld.word 0x04 11. " ZERO_FREQ ,Zero frequency" "0,1" hexmask.word 0x04 2.--10. 1. " VAL ,Phase value from zero reference" bitfld.word 0x04 0.--1. " DTHR ,Bits below the useful resolution" "0,1,2,3" line.word 0x06 "SS_FREQ,SS_FREQ" bitfld.word 0x06 14. " FREQ_OVRD ,Frequency register override" "Not overridden,Overridden" hexmask.word.byte 0x06 7.--13. 1. " FREQ_PK ,Peak frequency value (for changing direction)" hexmask.word.byte 0x06 0.--6. 1. " FREQ_CNT_INIT ,Initial frequency counter value" group.word 0x20++0x01 line.word 0x00 "ATEOVRD,ATEOVRD" bitfld.word 0x00 2. " ATEOVRD_EN ,Override enable for ATE signals" "0,1" bitfld.word 0x00 1. " REF_USB2_EN ,Override value for USB 2.0 high-speed PHY ref_clk enable" "0,1" bitfld.word 0x00 0. " REF_CLKDIV2 ,Override value for SS function ref_clk prescaler" "0,1" group.word 0x22++0x01 line.word 0x00 "MPLL_OVRD_IN_LO,MPLL_OVRD_IN_LO" bitfld.word 0x00 15. " RES_ACK_IN_OVRD ,Override enable for res_ack_in" "Disabled,Enabled" bitfld.word 0x00 14. " RES_ACK_IN ,Override value for res_ack_in" "0,1" newline bitfld.word 0x00 13. " RES_REQ_IN_OVRD ,Override enable for res_req_in" "Disabled,Enabled" bitfld.word 0x00 12. " RES_REQ_IN ,Override value for res_req_in" "0,1" newline bitfld.word 0x00 11. " RTUNE_REQ_OVRD ,Override enable for rtune_req" "Disabled,Enabled" bitfld.word 0x00 10. " RTUNE_REQ ,Override value for rtune_req" "0,1" newline bitfld.word 0x00 9. " MPLL_MULTIPLIER_OVRD ,Override enable for mpll_multipler" "Disabled,Enabled" hexmask.word.byte 0x00 2.--8. 1. " MPLL_MULTIPLIER ,Override value for mpll_multipler" newline bitfld.word 0x00 1. " MPLL_EN_OVRD ,Override enable for mpll_en" "Disabled,Enabled" bitfld.word 0x00 0. " MPLL_EN ,Override value for mpll_en" "0,1" group.word 0x30++0x01 line.word 0x00 "LEVEL_OVRD_IN,LEVEL_OVRD_IN" bitfld.word 0x00 13.--15. " LOS_BIAS ,Override value for los_bias" "Invalid,45,60,75,90,105,120,135" bitfld.word 0x00 12. " MPLL_HALF_RATE_OVRD ,Enable override value for mpll_half_rate" "Disabled,Enabled" bitfld.word 0x00 11. " MPLL_HALF_RATE ,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x00 10. " LEVEL_EN ,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs" "Disabled,Enabled" bitfld.word 0x00 5.--9. " LOS_LEVEL_A ,Override value for acjt_level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--4. " LOS_LEVEL ,Override value for los_level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x44++0x01 line.word 0x00 "SCOPE_COUNT,SCOPE_COUNT" group.word 0x48++0x01 line.word 0x00 "MPLL_OVRD_IN_HI,MPLL_OVRD_IN_HI" bitfld.word 0x00 13.--15. " TX_VBOOST_LVL ,Override value for tx_vboost_lvl" "0,1,2,3,4,5,6,7" bitfld.word 0x00 12. " MPLL_REFSSC_CLK_EN_OVRD ,Override enable for mpll_refssc_clk_en" "0,1" bitfld.word 0x00 11. " MPLL_REFSSC_CLK_EN ,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x00 10. " MPLL_RST ,Resets the MPLL state machine" "0,1" bitfld.word 0x00 9. " FSEL_OVRD ,Override enable for fsel[2:0]" "0,1" bitfld.word 0x00 6.--8. " FSEL ,Override value for fsel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 5. " MPLL_WORD_CLK_EN_OVRD ,Override enable for mpll_word_clk_en" "0,1" bitfld.word 0x00 4. " MPLL_WORD_CLK_EN ,Override value for mpll_word_clk_en" "0,1" bitfld.word 0x00 3. " MPLL_DWORD_CLK_EN_OVRD ,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x00 2. " MPLL_DWORD_CLK_EN ,Override value for mpll_dword_clk_en" "0,1" bitfld.word 0x00 1. " MPLL_QWORD_CLK_EN_OVRD ,Override enable for mpll_qword_clk_en" "0,1" bitfld.word 0x00 0. " MPLL_QWORD_CLK_EN ,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x01 line.word 0x00 "SSC_OVRD_IN,SSC_OVRD_IN" bitfld.word 0x00 13. " SSC_OVRD_IN_EN ,Override enable for spread spectrum generator" "Disabled,Enabled" newline bitfld.word 0x00 12. " SSC_EN ,Override value for SSC enable" "0,1" bitfld.word 0x00 9.--11. " SSC_RANGE ,Override value for SSC modulation range" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--8. 1. " SSC_REF_CLK_SEL ,Override value for reference clock scaling" group.word 0x66++0x01 line.word 0x00 "MPLL_OVRD_IN_LO,MPLL_OVRD_IN_LO" bitfld.word 0x00 15. " RES_ACK_IN_OVRD ,Override enable for res_ack_in" "Disabled,Enabled" bitfld.word 0x00 14. " RES_ACK_IN ,Override value for res_ack_in" "0,1" newline bitfld.word 0x00 13. " RES_REQ_IN_OVRD ,Override enable for res_req_in" "Disabled,Enabled" bitfld.word 0x00 12. " RES_REQ_IN ,Override value for res_req_in" "0,1" newline bitfld.word 0x00 11. " RTUNE_REQ_OVRD ,Override enable for rtune_req" "Disabled,Enabled" bitfld.word 0x00 10. " RTUNE_REQ ,Override value for rtune_req" "0,1" newline bitfld.word 0x00 9. " MPLL_MULTIPLIER_OVRD ,Override enable for mpll_multipler" "Disabled,Enabled" hexmask.word.byte 0x00 2.--8. 1. " MPLL_MULTIPLIER ,Override value for mpll_multipler" newline bitfld.word 0x00 1. " MPLL_EN_OVRD ,Override enable for mpll_en" "Disabled,Enabled" bitfld.word 0x00 0. " MPLL_EN ,Override value for mpll_en" "0,1" group.word 0xA2++0x01 line.word 0x00 "SSC_CLK_CNTRL,SSC_CLK_CNTRL" hexmask.word.byte 0x00 0.--6. 1. " SSC_CLK_DIV1 ,Sets SSC reference clock to 20 MHz" group.word 0x1006++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0_RX_OVRD_IN_HI" bitfld.word 0x00 13. " RX_RESET_OVRD ,RX_RESET_OVRD" "0,1" bitfld.word 0x00 12. " RX_RESET ,Override value for rx_reset" "0,1" newline bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 6. " RX_EQ_EN ,Override value for rx_eq_en" "0,1" bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" newline bitfld.word 0x00 5. " RX_LOS_FILTER_OVRD ,Override enable for rx_los_filter" "Disabled,Enabled" bitfld.word 0x00 3.--4. " RX_LOS_FILTER ,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x00 0.--1. " RX_RATE ,Override value for rx_rate" "0,1,2,3" bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" group.word 0x2002++0x01 line.word 0x00 "LANE0_TX_OVRD_IN_HI,LANE0_TX_OVRD_IN_HI" bitfld.word 0x00 9. " TX_VBOOST_EN_OVRD ,Override enable for tx_vboost_en" "Disabled,Enabled" bitfld.word 0x00 8. " TX_VBOOST_EN ,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x00 7. " TX_RESET_OVRD ,Override enable for tx_reset" "Disabled,Enabled" bitfld.word 0x00 6. " TX_RESET ,Override value for tx_reset" "0,1" newline bitfld.word 0x00 5. " TX_NYQUIST_DATA ,Overrides incoming data to nyquist" "0,1" bitfld.word 0x00 4. " TX_CLK_OUT_EN_OVRD ,Override enable for tx_clk_out_en" "Disabled,Enabled" newline bitfld.word 0x00 3. " TX_CLK_OUT_EN ,Overrides incoming tx_clk_out_en" "0,1" bitfld.word 0x00 2. " TX_RATE_OVRD ,Override enable for tx_rate" "Disabled,Enabled" newline bitfld.word 0x00 0.--1. " TX_RATE ,Overrides incoming Tx lane rate" "0,1,2,3" group.word 0x2004++0x01 line.word 0x00 "LANE0_TX_OVRD_DRV_LO,LANE0_TX_OVRD_DRV_LO" bitfld.word 0x00 14. " EN ,Enables override values for all inputs controlled by this register" "Disabled,Enabled" hexmask.word.byte 0x00 7.--13. 1. " PREEMPH ,Override value for transmit pre-emphasis" hexmask.word.byte 0x00 0.--6. 1. " AMPLITUDE ,Override value for transmit amplitude" group.word 0x2022++0x01 line.word 0x00 "LANE0_TX_CM_WAIT_TIME_OVRD,LANE0_TX_CM_WAIT_TIME_OVRD" bitfld.word 0x00 10. " CM_TIME_OVRD_EN ,Override enable for common mode charging wait time" "Disabled,Enabled" hexmask.word 0x00 0.--9. 1. " CM_TIME_OVRD ,Time to wait, in reference clock cycles, for LFPS common mode charging" group.word 0x202A++0x01 line.word 0x00 "LANE0_TX_LBERT_CTL,LANE0_TX_LBERT_CTL" hexmask.word 0x00 5.--14. 1. " PAT0 ,10-bit pattern for modes using PAT0 (5-7)" bitfld.word 0x00 4. " TRIGGER_ERR ,Single shot inversion of the LSB of the current symbol" "No effect,Trigger" bitfld.word 0x00 0.--3. " MODE ,Pattern to generate" "Disabled,lfsr31. X^31 + X^28 + 1,lfsr23. X^23 + X^18 + 1,lfsr15. X^15 + X^14 + 1,lfsr7. X^7 + X^6 + ,Fixed word (PAT0),DC-balanced word,Word pattern (20-bit),?..." group.word 0x202C++0x01 line.word 0x00 "LANE0_RX_LBERT_CTL,LANE0_RX_LBERT_CTL" bitfld.word 0x00 4. " SYNC ,Synchronizes pattern matcher with incoming data" "No effect,Sync" bitfld.word 0x00 0.--3. " MODE ,Pattern to match" "Disabled,lfsr31: X^31 + X^28 + 1,lfsr23: X^23 + X^18 + 1,lfsr15: X^15 + X^14 + 1,lfsr7 : X^7 + X^6 + 1,d[n] = d[n-10],d[n] = !d[n-10],d[n] = !d[n-20],?..." hgroup.word 0x202E++0x01 hide.word 0x00 "LANE0_RX_LBERT_ERR,LANE0_RX_LBERT_ERR" in group.word 0x205A++0x01 line.word 0x00 "LANE0_TX_ALT_BLOCK,LANE0_TX_ALT_BLOCK" bitfld.word 0x00 7. " EN_ALT_BUS ,Enables the Tx for alt bus mode, powers up the pmos_bias block, and so on" "Disabled,Enabled" newline bitfld.word 0x00 5.--6. " DRV_SOURCE_REG ,Value to use for tx_data_source" "0,1,2,3" bitfld.word 0x00 4. " JTAG_DATA_REG ,Value to use for jtag_data when OVRD_ALT_BUS is 1" "0,1" newline bitfld.word 0x00 3. " ALT_OSC_VP ,Enables and connects the vp oscillator to the transmit pins" "Disabled,Enabled" bitfld.word 0x00 2. " ALT_OSC_VPH ,Enables and connects the vph oscillator to the transmit pins" "Disabled,Enabled" newline bitfld.word 0x00 1. " ALT_OSC_VPHREG ,Enables and connects the vphreg oscillator to the transmit pins" "Disabled,Enabled" bitfld.word 0x00 0. " OVRD_ALT_BUS ,Enables local overrides for alt-bus control signals, DRV_SOURCE_REG and JTAG_DATA_REG" "Disabled,Enabled" width 0x0B tree.end tree "USB3 PHY 2" base ad:0x04610000 endian.le width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x06++0x07 line.word 0x00 "RTUNE_DEBUG,RTUNE_DEBUG" bitfld.word 0x00 3.--4. " TYPE ,Type of manual tuning or register read/write to execute" "ADC or read/write rt_value,Rx tune or read/write rx_cal_val,Tx tune or read/write tx_cal_val,Resref detect" newline bitfld.word 0x00 2. " SET_VAL ,Sets to 1 to manually write the register specified by the TYPE bit to the value in the VALUE bit" "To,Set" bitfld.word 0x00 1. " MAN_TUNE ,Writes to a 1 to do a manual tuning specified by the TYPE bit" "No effect,Tune" bitfld.word 0x00 0. " FLIP_COMP ,Inverts analog comparator output" "Not inverted,Inverted" line.word 0x02 "RTUNE_STAT,RTUNE_STAT" hexmask.word 0x02 0.--8. 1. " STAT ,STAT" line.word 0x04 "SUP_SS_PHASE,SUP_SS_PHASE" bitfld.word 0x04 13.--15. " REF_SEL_DIV ,Reference divisor to achieve better resolution and less ppm errors" "1,2,3,4,5,6,7,8" bitfld.word 0x04 12. " PH_SEL ,Phase mixer clock select" "0,1" newline bitfld.word 0x04 11. " ZERO_FREQ ,Zero frequency" "0,1" hexmask.word 0x04 2.--10. 1. " VAL ,Phase value from zero reference" bitfld.word 0x04 0.--1. " DTHR ,Bits below the useful resolution" "0,1,2,3" line.word 0x06 "SS_FREQ,SS_FREQ" bitfld.word 0x06 14. " FREQ_OVRD ,Frequency register override" "Not overridden,Overridden" hexmask.word.byte 0x06 7.--13. 1. " FREQ_PK ,Peak frequency value (for changing direction)" hexmask.word.byte 0x06 0.--6. 1. " FREQ_CNT_INIT ,Initial frequency counter value" group.word 0x20++0x01 line.word 0x00 "ATEOVRD,ATEOVRD" bitfld.word 0x00 2. " ATEOVRD_EN ,Override enable for ATE signals" "0,1" bitfld.word 0x00 1. " REF_USB2_EN ,Override value for USB 2.0 high-speed PHY ref_clk enable" "0,1" bitfld.word 0x00 0. " REF_CLKDIV2 ,Override value for SS function ref_clk prescaler" "0,1" group.word 0x22++0x01 line.word 0x00 "MPLL_OVRD_IN_LO,MPLL_OVRD_IN_LO" bitfld.word 0x00 15. " RES_ACK_IN_OVRD ,Override enable for res_ack_in" "Disabled,Enabled" bitfld.word 0x00 14. " RES_ACK_IN ,Override value for res_ack_in" "0,1" newline bitfld.word 0x00 13. " RES_REQ_IN_OVRD ,Override enable for res_req_in" "Disabled,Enabled" bitfld.word 0x00 12. " RES_REQ_IN ,Override value for res_req_in" "0,1" newline bitfld.word 0x00 11. " RTUNE_REQ_OVRD ,Override enable for rtune_req" "Disabled,Enabled" bitfld.word 0x00 10. " RTUNE_REQ ,Override value for rtune_req" "0,1" newline bitfld.word 0x00 9. " MPLL_MULTIPLIER_OVRD ,Override enable for mpll_multipler" "Disabled,Enabled" hexmask.word.byte 0x00 2.--8. 1. " MPLL_MULTIPLIER ,Override value for mpll_multipler" newline bitfld.word 0x00 1. " MPLL_EN_OVRD ,Override enable for mpll_en" "Disabled,Enabled" bitfld.word 0x00 0. " MPLL_EN ,Override value for mpll_en" "0,1" group.word 0x30++0x01 line.word 0x00 "LEVEL_OVRD_IN,LEVEL_OVRD_IN" bitfld.word 0x00 13.--15. " LOS_BIAS ,Override value for los_bias" "Invalid,45,60,75,90,105,120,135" bitfld.word 0x00 12. " MPLL_HALF_RATE_OVRD ,Enable override value for mpll_half_rate" "Disabled,Enabled" bitfld.word 0x00 11. " MPLL_HALF_RATE ,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x00 10. " LEVEL_EN ,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs" "Disabled,Enabled" bitfld.word 0x00 5.--9. " LOS_LEVEL_A ,Override value for acjt_level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--4. " LOS_LEVEL ,Override value for los_level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x44++0x01 line.word 0x00 "SCOPE_COUNT,SCOPE_COUNT" group.word 0x48++0x01 line.word 0x00 "MPLL_OVRD_IN_HI,MPLL_OVRD_IN_HI" bitfld.word 0x00 13.--15. " TX_VBOOST_LVL ,Override value for tx_vboost_lvl" "0,1,2,3,4,5,6,7" bitfld.word 0x00 12. " MPLL_REFSSC_CLK_EN_OVRD ,Override enable for mpll_refssc_clk_en" "0,1" bitfld.word 0x00 11. " MPLL_REFSSC_CLK_EN ,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x00 10. " MPLL_RST ,Resets the MPLL state machine" "0,1" bitfld.word 0x00 9. " FSEL_OVRD ,Override enable for fsel[2:0]" "0,1" bitfld.word 0x00 6.--8. " FSEL ,Override value for fsel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 5. " MPLL_WORD_CLK_EN_OVRD ,Override enable for mpll_word_clk_en" "0,1" bitfld.word 0x00 4. " MPLL_WORD_CLK_EN ,Override value for mpll_word_clk_en" "0,1" bitfld.word 0x00 3. " MPLL_DWORD_CLK_EN_OVRD ,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x00 2. " MPLL_DWORD_CLK_EN ,Override value for mpll_dword_clk_en" "0,1" bitfld.word 0x00 1. " MPLL_QWORD_CLK_EN_OVRD ,Override enable for mpll_qword_clk_en" "0,1" bitfld.word 0x00 0. " MPLL_QWORD_CLK_EN ,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x01 line.word 0x00 "SSC_OVRD_IN,SSC_OVRD_IN" bitfld.word 0x00 13. " SSC_OVRD_IN_EN ,Override enable for spread spectrum generator" "Disabled,Enabled" newline bitfld.word 0x00 12. " SSC_EN ,Override value for SSC enable" "0,1" bitfld.word 0x00 9.--11. " SSC_RANGE ,Override value for SSC modulation range" "0,1,2,3,4,5,6,7" hexmask.word 0x00 0.--8. 1. " SSC_REF_CLK_SEL ,Override value for reference clock scaling" group.word 0x66++0x01 line.word 0x00 "MPLL_OVRD_IN_LO,MPLL_OVRD_IN_LO" bitfld.word 0x00 15. " RES_ACK_IN_OVRD ,Override enable for res_ack_in" "Disabled,Enabled" bitfld.word 0x00 14. " RES_ACK_IN ,Override value for res_ack_in" "0,1" newline bitfld.word 0x00 13. " RES_REQ_IN_OVRD ,Override enable for res_req_in" "Disabled,Enabled" bitfld.word 0x00 12. " RES_REQ_IN ,Override value for res_req_in" "0,1" newline bitfld.word 0x00 11. " RTUNE_REQ_OVRD ,Override enable for rtune_req" "Disabled,Enabled" bitfld.word 0x00 10. " RTUNE_REQ ,Override value for rtune_req" "0,1" newline bitfld.word 0x00 9. " MPLL_MULTIPLIER_OVRD ,Override enable for mpll_multipler" "Disabled,Enabled" hexmask.word.byte 0x00 2.--8. 1. " MPLL_MULTIPLIER ,Override value for mpll_multipler" newline bitfld.word 0x00 1. " MPLL_EN_OVRD ,Override enable for mpll_en" "Disabled,Enabled" bitfld.word 0x00 0. " MPLL_EN ,Override value for mpll_en" "0,1" group.word 0xA2++0x01 line.word 0x00 "SSC_CLK_CNTRL,SSC_CLK_CNTRL" hexmask.word.byte 0x00 0.--6. 1. " SSC_CLK_DIV1 ,Sets SSC reference clock to 20 MHz" group.word 0x1006++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0_RX_OVRD_IN_HI" bitfld.word 0x00 13. " RX_RESET_OVRD ,RX_RESET_OVRD" "0,1" bitfld.word 0x00 12. " RX_RESET ,Override value for rx_reset" "0,1" newline bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 6. " RX_EQ_EN ,Override value for rx_eq_en" "0,1" bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" newline bitfld.word 0x00 5. " RX_LOS_FILTER_OVRD ,Override enable for rx_los_filter" "Disabled,Enabled" bitfld.word 0x00 3.--4. " RX_LOS_FILTER ,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x00 0.--1. " RX_RATE ,Override value for rx_rate" "0,1,2,3" bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" group.word 0x2002++0x01 line.word 0x00 "LANE0_TX_OVRD_IN_HI,LANE0_TX_OVRD_IN_HI" bitfld.word 0x00 9. " TX_VBOOST_EN_OVRD ,Override enable for tx_vboost_en" "Disabled,Enabled" bitfld.word 0x00 8. " TX_VBOOST_EN ,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x00 7. " TX_RESET_OVRD ,Override enable for tx_reset" "Disabled,Enabled" bitfld.word 0x00 6. " TX_RESET ,Override value for tx_reset" "0,1" newline bitfld.word 0x00 5. " TX_NYQUIST_DATA ,Overrides incoming data to nyquist" "0,1" bitfld.word 0x00 4. " TX_CLK_OUT_EN_OVRD ,Override enable for tx_clk_out_en" "Disabled,Enabled" newline bitfld.word 0x00 3. " TX_CLK_OUT_EN ,Overrides incoming tx_clk_out_en" "0,1" bitfld.word 0x00 2. " TX_RATE_OVRD ,Override enable for tx_rate" "Disabled,Enabled" newline bitfld.word 0x00 0.--1. " TX_RATE ,Overrides incoming Tx lane rate" "0,1,2,3" group.word 0x2004++0x01 line.word 0x00 "LANE0_TX_OVRD_DRV_LO,LANE0_TX_OVRD_DRV_LO" bitfld.word 0x00 14. " EN ,Enables override values for all inputs controlled by this register" "Disabled,Enabled" hexmask.word.byte 0x00 7.--13. 1. " PREEMPH ,Override value for transmit pre-emphasis" hexmask.word.byte 0x00 0.--6. 1. " AMPLITUDE ,Override value for transmit amplitude" group.word 0x2022++0x01 line.word 0x00 "LANE0_TX_CM_WAIT_TIME_OVRD,LANE0_TX_CM_WAIT_TIME_OVRD" bitfld.word 0x00 10. " CM_TIME_OVRD_EN ,Override enable for common mode charging wait time" "Disabled,Enabled" hexmask.word 0x00 0.--9. 1. " CM_TIME_OVRD ,Time to wait, in reference clock cycles, for LFPS common mode charging" group.word 0x202A++0x01 line.word 0x00 "LANE0_TX_LBERT_CTL,LANE0_TX_LBERT_CTL" hexmask.word 0x00 5.--14. 1. " PAT0 ,10-bit pattern for modes using PAT0 (5-7)" bitfld.word 0x00 4. " TRIGGER_ERR ,Single shot inversion of the LSB of the current symbol" "No effect,Trigger" bitfld.word 0x00 0.--3. " MODE ,Pattern to generate" "Disabled,lfsr31. X^31 + X^28 + 1,lfsr23. X^23 + X^18 + 1,lfsr15. X^15 + X^14 + 1,lfsr7. X^7 + X^6 + ,Fixed word (PAT0),DC-balanced word,Word pattern (20-bit),?..." group.word 0x202C++0x01 line.word 0x00 "LANE0_RX_LBERT_CTL,LANE0_RX_LBERT_CTL" bitfld.word 0x00 4. " SYNC ,Synchronizes pattern matcher with incoming data" "No effect,Sync" bitfld.word 0x00 0.--3. " MODE ,Pattern to match" "Disabled,lfsr31: X^31 + X^28 + 1,lfsr23: X^23 + X^18 + 1,lfsr15: X^15 + X^14 + 1,lfsr7 : X^7 + X^6 + 1,d[n] = d[n-10],d[n] = !d[n-10],d[n] = !d[n-20],?..." hgroup.word 0x202E++0x01 hide.word 0x00 "LANE0_RX_LBERT_ERR,LANE0_RX_LBERT_ERR" in group.word 0x205A++0x01 line.word 0x00 "LANE0_TX_ALT_BLOCK,LANE0_TX_ALT_BLOCK" bitfld.word 0x00 7. " EN_ALT_BUS ,Enables the Tx for alt bus mode, powers up the pmos_bias block, and so on" "Disabled,Enabled" newline bitfld.word 0x00 5.--6. " DRV_SOURCE_REG ,Value to use for tx_data_source" "0,1,2,3" bitfld.word 0x00 4. " JTAG_DATA_REG ,Value to use for jtag_data when OVRD_ALT_BUS is 1" "0,1" newline bitfld.word 0x00 3. " ALT_OSC_VP ,Enables and connects the vp oscillator to the transmit pins" "Disabled,Enabled" bitfld.word 0x00 2. " ALT_OSC_VPH ,Enables and connects the vph oscillator to the transmit pins" "Disabled,Enabled" newline bitfld.word 0x00 1. " ALT_OSC_VPHREG ,Enables and connects the vphreg oscillator to the transmit pins" "Disabled,Enabled" bitfld.word 0x00 0. " OVRD_ALT_BUS ,Enables local overrides for alt-bus control signals, DRV_SOURCE_REG and JTAG_DATA_REG" "Disabled,Enabled" width 0x0B tree.end else tree "USB3 PHY 1" base ad:0x084F0000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end tree "USB3 PHY 2" base ad:0x08500000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end endif tree.end elif cpuis("LS10?3*") tree "USB PHY SuperSpeed" tree "USB3 PHY 1" base ad:0x084F0000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end tree "USB3 PHY 2" base ad:0x08500000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end tree "USB3 PHY 3" base ad:0x08510000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end tree.end elif cpuis("LS1012*")||cpuis("LS10?6*") tree "USB PHY SuperSpeed" tree "USB3 PHY 1" base ad:0x084F0000 width 28. rgroup.word 0x00++0x03 line.word 0x00 "IP_IDCODE_LO,SUP_IDCODE_LO" line.word 0x02 "IP_IDCODE_HI,SUP_IDCODE_HI" group.word 0x60++0x01 line.word 0x00 "MPLL_LOOP_CTL,MPLL Loop Control" bitfld.word 0x00 4.--7. " PROP_CNTRL ,Charge pump proportional current setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x200C++0x01 line.word 0x00 "LANE0_RX_OVRD_IN_HI,LANE0 RX Override IN HI" bitfld.word 0x00 11. " RX_EQ_OVRD ,Override value for rx_eq" "0,1" bitfld.word 0x00 8.--10. " RX_EQ ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 7. " RX_EQ_EN_OVRD ,Override enable for rx_eq_en" "Disabled,Enabled" bitfld.word 0x00 6. " RX_EQ_EN ,Override enable for rx_eq_en" "0,1" sif cpuis("LS10?3*") newline bitfld.word 0x00 2. " RX_RATE_OVRD ,Override enable for rx_rate" "Disabled,Enabled" endif width 0x0B tree.end tree.end endif tree.open "WDOG (Watchdog Timer)" sif cpuis("LS1088*")||cpuis("LS1084*")||cpuis("LS1048*")||cpuis("LS1044*") tree "WDOG_1" base ad:0xC000000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_2" base ad:0xC010000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_3" base ad:0xC020000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_4" base ad:0xC030000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_5" base ad:0xC100000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_6" base ad:0xC110000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_7" base ad:0xC120000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end tree "WDOG_8" base ad:0xC130000 width 11. hgroup.long 0x00++0x03 hide.long 0x00 "LOAD,Watchdog Load Register" hgroup.long 0x04++0x03 hide.long 0x00 "VALUE,Watchdog Value Register" group.long 0x08++0x03 line.long 0x00 "CONTROL,Watchdog Control Register" bitfld.long 0x00 1. " RESEN ,Enable watchdog reset output" "Disabled,Enabled" bitfld.long 0x00 0. " INTEN ,Enable the interrupt event" "Disabled,Enabled" wgroup.long 0x0C++0x03 line.long 0x00 "INTCLR,Watchdog Clear Interrupt Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,A write of any value clears the watchdog interrupt" "Clear,Clear" rgroup.long 0x10++0x07 line.long 0x00 "RIS,Watchdog Raw Interrupt Status Register" bitfld.long 0x00 0. " RAW_WATCHDOG_INTERRUPT ,Raw interrupt status from the counter" "No interrupt,Interrupt" line.long 0x04 "MIS,Watchdog Interrupt Status Register" bitfld.long 0x04 0. " WATCHDOG_INTERRUPT ,Enabled interrupt status from the counter" "No interrupt,Interrupt" group.long 0xC00++0x03 line.long 0x00 "LOCK,Watchdog Lock Register" hexmask.long 0x00 1.--31. 1. " ENABLE_REGISTER_WRITES ,Enable write access to all other registers by writing 0x1ACCE551" bitfld.long 0x00 0. " REGISTER_WRITE_ENABLE_STATUS ,Registers write access enable" "Enabled,Disabled" group.long 0xF00++0x03 line.long 0x00 "ITCR,Watchdog Integration Test Control Register" bitfld.long 0x00 0. " INTEGRATION_TEST_MODE_ENABLE ,Watchdog integration test mode enable" "Disabled,Enabled" wgroup.long 0xF04++0x03 line.long 0x00 "ITOP,Watchdog Integration Test Output Set Register" bitfld.long 0x00 1. " INTEGRATION_TEST_WDOGINT_VALUE ,Value output on WDOGINT when in integration test mode" "0,1" bitfld.long 0x00 0. " INTEGRATION_TEST_WDOGRES_VALUE ,Value output on WDOGRES when in integration test mode" "0,1" rgroup.long 0xFE0++0x1F line.long 0x00 "PERIPHID0,Peripheral Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " PARTNUMBER0 ,PARTNUMBER 0 field" line.long 0x04 "PERIPHID1,Peripheral Identification Register 1" bitfld.long 0x04 4.--7. " DESIGNER0 ,DESIGNER 0 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PARTNUMBER1 ,PARTNUMBER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHID2,Peripheral Identification Register 2" bitfld.long 0x08 4.--7. " REVISION ,Peripheral revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " DESIGNER1 ,DESIGNER 1 field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "PERIPHID3,Peripheral Identification Register 3" hexmask.long.byte 0x0C 0.--7. 1. " CONFIGURATION ,CONFIGURATION field" line.long 0x10 "PCELLID0,PrimeCell Identification Register 0" hexmask.long.byte 0x10 0.--7. 1. " WDOGPCELLID0 ,Watchdog primecell identification 0" line.long 0x14 "PCELLID1,PrimeCell Identification Register 1" hexmask.long.byte 0x14 0.--7. 1. " WDOGPCELLID1 ,Watchdog primecell identification 1" line.long 0x18 "PCELLID2,PrimeCell Identification Register 2" hexmask.long.byte 0x18 0.--7. 1. " WDOGPCELLID2 ,Watchdog primecell identification 2" line.long 0x1C "PCELLID3,PrimeCell Identification Register 3" hexmask.long.byte 0x1C 0.--7. 1. " WDOGPCELLID3 ,Watchdog primecell identification 3" width 0x0B tree.end elif cpuis("LS10?6*")||cpuis("LS10?3*")||cpuis("LS1012*") tree "WDOG_1" base ad:0x2AD0000 width 6. endian.be group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog time-out field" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.word 0x00 0. " WDZST ,Operation of the WDOG during low-power modes" "Continued,Suspended" endif line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 1. " TOUT ,Timeout" "Not occurred,Occurred" bitfld.word 0x00 0. " SFTW ,Software reset" "Not occurred,Occurred" group.word 0x06++0x01 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count time-out" endian.le width 0x0B tree.end sif !cpuis("LS1012*")&&!cpuis("LS10?6*") tree "WDOG_2" base ad:0x2AE0000 width 6. endian.be group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog time-out field" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.word 0x00 0. " WDZST ,Operation of the WDOG during low-power modes" "Continued,Suspended" endif line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 1. " TOUT ,Timeout" "Not occurred,Occurred" bitfld.word 0x00 0. " SFTW ,Software reset" "Not occurred,Occurred" group.word 0x06++0x01 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count time-out" endian.le width 0x0B tree.end tree "WDOG_3" base ad:0x2A70000 width 6. endian.be group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog time-out field" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.word 0x00 0. " WDZST ,Operation of the WDOG during low-power modes" "Continued,Suspended" endif line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 1. " TOUT ,Timeout" "Not occurred,Occurred" bitfld.word 0x00 0. " SFTW ,Software reset" "Not occurred,Occurred" group.word 0x06++0x01 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count time-out" endian.le width 0x0B tree.end tree "WDOG_4" base ad:0x2A80000 width 6. endian.be group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog time-out field" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.word 0x00 0. " WDZST ,Operation of the WDOG during low-power modes" "Continued,Suspended" endif line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 1. " TOUT ,Timeout" "Not occurred,Occurred" bitfld.word 0x00 0. " SFTW ,Software reset" "Not occurred,Occurred" group.word 0x06++0x01 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count time-out" endian.le width 0x0B tree.end tree "WDOG_5" base ad:0x2A90000 width 6. endian.be group.word 0x00++0x03 line.word 0x00 "WCR,Watchdog Control Register" hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog time-out field" bitfld.word 0x00 4. " SRS ,Software reset signal" "Reset,No effect" bitfld.word 0x00 2. " WDE ,Watchdog enable" "Disabled,Enabled" sif cpuis("LS1012*")||cpuis("LS10?3*")||cpuis("LS10?6*") newline bitfld.word 0x00 0. " WDZST ,Operation of the WDOG during low-power modes" "Continued,Suspended" endif line.word 0x02 "WSR,Watchdog Service Register" rgroup.word 0x04++0x01 line.word 0x00 "WRSR,Watchdog Reset Status Register" bitfld.word 0x00 1. " TOUT ,Timeout" "Not occurred,Occurred" bitfld.word 0x00 0. " SFTW ,Software reset" "Not occurred,Occurred" group.word 0x06++0x01 line.word 0x00 "WICR,Watchdog Interrupt Control Register" bitfld.word 0x00 15. " WIE ,Watchdog timer interrupt enable bit" "Disabled,Enabled" eventfld.word 0x00 14. " WTIS ,Watchdog timer interrupt" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog interrupt count time-out" endian.le width 0x0B tree.end endif endif tree.end newline